Adaptive network architecture for implicit neural representation

Abstract

A method for encoding comprising: obtaining (604) a current partition representing a subpart of a picture; determining (605) an architecture of an implicit neural representation network adapted to the current partition; learning (606) parameters of the implicit neural representation network with the determined architecture for the current partition, and, signaling (607) information representing the learned parameters and the determined architecture in video data.

Description

[0001]2023PF00618 ADAPTIVE NETWORK ARCHITECTURE FOR IMPLICIT NEURAL REPRESENTATION 1. CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to European Application No.23306323.9, filed August 2, 2023, which is incorporated herein by reference in its entirety. 2. TECHNICAL FIELD At least one of the present embodiments generally relates to a method and a device for encoding picture or video data based on an Implicit Neural Representation. 3. BACKGROUND Implicit Neural Representation (INR) based compression techniques are relatively new compression techniques that can be applied to 2D picture, video, 3D scenes or objects. These techniques have a far lower computational complexity than end-to-end neural network based compression approaches. An INR network is typically a neural network, composed of multiple neural layers, such as fully connected layers. Each neural layer can be described as a function that first multiplies an input signal by a tensor, adds a vector called the bias and then applies a nonlinear function on the resulting values. The shape (and other characteristics) of the tensor and the type of non-linear functions are called the architecture of the network. The input signal may be modified by a transformation before being used as input for the neural network. This transformation can be a Fourier mapping, coordinate transformation, normalization etc. Using a single INR network for a whole input signal is often suboptimal. Therefore, the input signal is preferably partitioned. This partitioning can take any form, such as fixed-sized partitions, coding-tree, etc. Then, the signal is encoded using a collection of INRs sharing a same architecture. There is typically a bijection between the INRs of the collection and the partitions of the signal. Each partition of the signal is encoded by its associated INR and thus this associated INR is trained on that part of 2023PF00618 the signal. Finally, the signal is encoded into a bitstream by encoding the partitioning (if necessary) and parameters of the different INRs. Partitions of a signal may have different complexity. The difference in complexity between the partitions can have at least two origins: 1) partitions of the signal with similar complexity / quantity of details and with different sizes or 2) partitions with the same size but different quantity of details. Fig. 8A illustrates a picture partitioned in regions homogeneous in terms of complexity. Fig. 8B illustrates the complexity of the regions of the picture of Fig.8A, the darkest regions being the more complex. Using INRs having the same architecture on partitions having different complexities leads to a suboptimal encoding of the signal in terms of rate / distortion performances but also in terms of computation complexity. Indeed, the common architecture is either too powerful for partitions showing a low complexity or not powerful enough for partitions showing a high complexity. It is desirable to propose solutions allowing to overcome the above issues. In particular, it is desirable to propose solutions improving INR based encoding of a signal when the signal is partitioned in terms of rate / distortion performance but also, in terms of computation complexity of the encoding and decoding process. 4. BRIEF SUMMARY In a first aspect, one or more of the present embodiments provide a method for encoding comprising: obtaining a current partition representing a subpart of a signal; determining an architecture of an implicit neural representation network adapted to the current partition; learning parameters of the implicit neural representation network with the determined architecture for the current partition, and, signaling information representing the learned parameters and the determined architecture in video data. In an embodiment, information representing the learned parameters and the determined architecture result from an application of at least one of a quantization 2023PF00618 process or an entropy coding process onto the learned parameters and the determined architecture. In an embodiment, the learning of the parameters of the implicit neural representation network comprises determining the parameters of the implicit neural representation network minimizing of a loss function depending on the parameters of the implicit neural representation and of the determined architecture. In an embodiment, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the parameters of the implicit neural representation and of the architecture. In an embodiment, the current partition results from an application of a partitioning to the signal and wherein the partitioning, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the partitioning, the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the partitioning and for each partition resulting from the partitioning, of the parameters of the implicit neural representation and of the architecture associated to this partition. In an embodiment, the information representative of the architecture is an index on an architecture of a set of architectures. In an embodiment, the set of architectures is signaled in the video data. In a second aspect, one or more of the present embodiments provide a method for decoding comprising: decoding from video data an information representing a partitioning of at least a portion of a signal in a plurality of partitions; for each partition of at least a subset of partitions resulting from the partitioning; decoding from the video data information representative of an architecture of an implicit neural representation and of parameters of the implicit neural representation for the partition; applying the implicit neural representation with the decoded architecture and parameters to samples coordinates of the partitions to reconstruct the partition. 2023PF00618 In an embodiment, the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation are quantized or entropy coded version or quantized and entropy coded versions of the architecture and of the parameters, the architecture and the parameters applied to reconstruct the partition result from respectively an inverse quantization or an entropy decoding or an entropy decoding and an inverse quantization of the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation. In an embodiment, the information representative of the architecture is an index on an architecture of a set of architectures. In an embodiment, the set of architectures is signaled in the video data. In a third aspect, one or more of the present embodiments provide a device for encoding comprising electronic circuitry configured for: obtaining a current partition representing a subpart of a signal; determining an architecture of an implicit neural representation network adapted to the current partition; learning parameters of the implicit neural representation network with the determined architecture for the current partition, and, signaling information representing the learned parameters and the determined architecture in video data. In an embodiment, information representing the learned parameters and the determined architecture result from an application of at least one of a quantization process or an entropy coding process onto the learned parameters and the determined architecture. In an embodiment, the learning of the parameters of the implicit neural representation network comprises determining the parameters of the implicit neural representation network minimizing of a loss function depending on the parameters of the implicit neural representation and of the determined architecture. In an embodiment, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the parameters of the implicit neural representation network and the architecture minimizing of a loss 2023PF00618 function depending on the parameters of the implicit neural representation and of the architecture. In an embodiment, the current partition results from an application of a partitioning to the signal and wherein the partitioning, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the partitioning, the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the partitioning and for each partition resulting from the partitioning, of the parameters of the implicit neural representation and of the architecture associated to this partition. In an embodiment, the information representative of the architecture is an index on an architecture of a set of architectures. In an embodiment, the set of architectures is signaled in the video data. In a fourth aspect, one or more of the present embodiments provide device for decoding comprising electronic circuitry configured for: decoding from video data an information representing a partitioning of at least a portion of a signal in a plurality of partitions; for each partition of at least a subset of partitions resulting from the partitioning; decoding from the video data information representative of an architecture of an implicit neural representation and of parameters of the implicit neural representation for the partition; applying the implicit neural representation with the decoded architecture and parameters to samples coordinates of the partitions to reconstruct the partition. In an embodiment, the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation are quantized or entropy coded version or quantized and entropy coded versions of the architecture and of the parameters, the architecture and the parameters applied to reconstruct the partition result from respectively an inverse quantization or an entropy decoding or an entropy decoding and an inverse quantization of the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation. In an embodiment, the information representative of the architecture is an index on an architecture of a set of architectures. 2023PF00618 In an embodiment, the set of architectures is signaled in the video data. In a fifth aspect, one or more of the present embodiments provide a non- transitory information storage medium storing program code instructions for implementing the method according to the first or the second aspect. In a sixth aspect, one or more of the present embodiments provide a computer program comprising program code instructions for implementing the method according to the first or the second aspect. In a seventh aspect, one or more of the present embodiments provide an output signal generated by the method of the first aspect or by the device of the third aspect. 5. BRIEF SUMMARY OF THE DRAWINGS Fig. 1 illustrates an example of context in which various embodiments may be implemented; Fig. 2A illustrates schematically an example of hardware architecture of a processing module able to implement an encoding module or a decoding module in which various aspects and embodiments are implemented; Fig. 2B illustrates a block diagram of an example of a first system in which various aspects and embodiments are implemented; Fig.2C illustrates a block diagram of an example of a second system in which various aspects and embodiments are implemented; Fig.3 illustrates a simple neural network used for implicit neural representation; Fig. 4A illustrates a typical process to encode a signal using an implicit neural representation; Fig. 4B illustrates a typical process to decode a signal using an implicit neural representation; Fig. 5 illustrates an example of partitioning undergone by a picture of pixels of an original video sequence; Fig.6 illustrates schematically a process to encode according to various embodiments; 2023PF00618 Fig.7 illustrates schematically a process to decode according to various embodiments; and, Fig.8A and 8B illustrates a picture comprising regions with various complexities. 6. DETAILED DESCRIPTION In the following, various embodiments are applied to a 2D signal such as picture or video data. One can note that these various embodiments can also be applied identically to other types of signals such as 3D signals representing 3D scenes or objects. In case of a 3D signal, a partition may be a cube. Fig.1 describes an example of a context in which following embodiments can be implemented. In Fig. 1, a system 11, that could be a camera, a storage device, a computer, a server or any device capable of delivering a video stream, transmits a video stream to a system 13 using a communication channel 12. The video stream is either encoded and transmitted by the system 11 or received and / or stored by the system 11 and then transmitted. The communication channel 12 is a wired (for example Internet or Ethernet) or a wireless (for example WiFi, 3G, 4G or 5G) network link. The system 13, that could be for example a set top box, receives and decodes the video stream to generate a sequence of decoded pictures. The obtained sequence of decoded pictures is then transmitted to a display system 15 using a communication channel 14, that could be a wired or wireless network. The display system 15 then displays said pictures. In an embodiment, the system 13 is comprised in the display system 15. In that case, the system 13 and display system 15 are comprised in a TV, a computer, a tablet, a smartphone, a head-mounted display, etc. Fig. 2A illustrates schematically an example of hardware architecture of a processing module 200 able to implement an encoding module or a decoding module capable of implementing respectively a method for encoding of Fig.6 and a method for decoding of Fig. 7. The encoding module is for example comprised in the system 11 when this apparatus is in charge of encoding the video stream. The decoding module is for example comprised in the system 13. The processing module 200 comprises, connected by a communication bus 2005: a processor or CPU (central processing unit) 2023PF00618 2000 encompassing one or more microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as non-limiting examples; a random access memory (RAM) 2001; a read only memory (ROM) 2002; a storage unit 2003, which can include non-volatile memory and / or volatile memory, including, but not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, magnetic disk drive, and / or optical disk drive, or a storage medium reader, such as a SD (secure digital) card reader and / or a hard disc drive (HDD) and / or a network accessible storage device; at least one communication interface 2004 for exchanging data with other modules, devices or equipment. The communication interface 2004 can include, but is not limited to, a transceiver configured to transmit and to receive data over a communication channel. The communication interface 2004 can include, but is not limited to, a modem or network card. If the processing module 200 implements a decoding module, the communication interface 2004 enables for instance the processing module 200 to receive encoded video streams and to provide a sequence of decoded pictures. If the processing module 200 implements an encoding module, the communication interface 2004 enables for instance the processing module 200 to receive a sequence of original picture data to encode and to provide an encoded video stream. The processor 2000 is capable of executing instructions loaded into the RAM 2001 from the ROM 2002, from an external memory (not shown), from a storage medium, or from a communication network. When the processing module 200 is powered up, the processor 2000 is capable of reading instructions from the RAM 2001 and executing them. These instructions form a computer program causing, for example, the implementation by the processor 2000 of a decoding method as described in relation with Fig. 7, an encoding method described in relation to Fig. 6, these methods comprising various aspects and embodiments described below in this document. All or some of the algorithms and steps of the methods of Figs.6 and 7 may be implemented in software form by the execution of a set of instructions by a programmable machine such as a DSP (digital signal processor) or a microcontroller, or be implemented in hardware form by a machine or a dedicated component such as a 2023PF00618 FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). As can be seen, microprocessors, general purpose computers, special purpose computers, processors based or not on a multi-core architecture, DSP, microcontroller, FPGA and ASIC are electronic circuitry adapted to implement (i.e., configured for implementing) at least partially the methods of Figs.6 and 7. Fig. 2C illustrates a block diagram of an example of the system 13 in which various aspects and embodiments are implemented. The system 13 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects and embodiments described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances and head mounted display. Elements of system 13, singly or in combination, can be embodied in a single integrated circuit (IC), multiple ICs, and / or discrete components. For example, in at least one embodiment, the system 13 comprises one processing module 200 that implements a decoding module. In various embodiments, the system 13 is communicatively coupled to one or more other systems, or other electronic devices, via, for example, a communications bus or through dedicated input and / or output ports. In various embodiments, the system 13 is configured to implement one or more of the aspects described in this document. The input to the processing module 200 can be provided through various input modules as indicated in block 231. Such input modules include, but are not limited to, (i) a radio frequency (RF) module that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a component (COMP) input module (or a set of COMP input modules), (iii) a Universal Serial Bus (USB) input module, and / or (iv) a High Definition Multimedia Interface (HDMI) input module. Other examples, not shown in FIG.2C, include composite video. In various embodiments, the input modules of block 231 have associated respective input processing elements as known in the art. For example, the RF module can be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) down-converting the selected signal, (iii) band-limiting again to a narrower band of 2023PF00618 frequencies to select (for example) a signal frequency band which can be referred to as a channel in certain embodiments, (iv) demodulating the down-converted and band- limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets. The RF module of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band-limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers. The RF portion can include a tuner that performs various of these functions, including, for example, down-converting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband. In one set-top box embodiment, the RF module and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, down- converting, and filtering again to a desired frequency band. Various embodiments rearrange the order of the above-described (and other) elements, remove some of these elements, and / or add other elements performing similar or different functions. Adding elements can include inserting elements in between existing elements, such as, for example, inserting amplifiers and an analog-to-digital converter. In various embodiments, the RF module includes an antenna. Additionally, the USB and / or HDMI modules can include respective interface processors for connecting system 13 to other electronic devices across USB and / or HDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, can be implemented, for example, within a separate input processing IC or within the processing module 200 as necessary. Similarly, aspects of USB or HDMI interface processing can be implemented within separate interface ICs or within the processing module 200 as necessary. The demodulated, error corrected, and demultiplexed stream is provided to the processing module 200. Various elements of system 13 can be provided within an integrated housing. Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangements, for example, an internal bus as known in the art, including the Inter-IC (I2C) bus, wiring, and printed circuit boards. For example, in the system 13, the processing module 200 is interconnected to other elements of said system 13 by the bus 2005. 2023PF00618 The communication interface 2004 of the processing module 200 allows the system 13 to communicate on the communication channel 12. As already mentioned above, the communication channel 12 can be implemented, for example, within a wired and / or a wireless medium. Data is streamed, or otherwise provided, to the system 13, in various embodiments, using a wireless network such as a Wi-Fi network, for example IEEE 802.11 (IEEE refers to the Institute of Electrical and Electronics Engineers). The Wi- Fi signal of these embodiments is received over the communications channel 12 and the communications interface 2004 which are adapted for Wi-Fi communications. The communications channel 12 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 13 using the RF connection of the input block 231. As indicated above, various embodiments provide data in a non- streaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network. The system 13 can provide an output signal to various output devices, including the display system 15, speakers 26, and other peripheral devices 27. The display system 15 of various embodiments includes one or more of, for example, a touchscreen display, an organic light-emitting diode (OLED) display, a curved display, and / or a foldable display. The display system 15 can be for a television, a tablet, a laptop, a cell phone (mobile phone), a head mounted display or other devices. The display system 15 can also be integrated with other components (for example, as in a smart phone), or separate (for example, an external monitor for a laptop). The other peripheral devices 27 include, in various examples of embodiments, one or more of a stand-alone digital video disc (or digital versatile disc) (DVR, for both terms), a disk player, a stereo system, and / or a lighting system. Various embodiments use one or more peripheral devices 27 that provide a function based on the output of the system 13. For example, a disk player performs the function of playing an output of the system 13. In various embodiments, control signals are communicated between the system 13 and the display system 15, speakers 26, or other peripheral devices 27 using signaling such as AV.Link, Consumer Electronics Control (CEC), or other communications protocols that enable device-to-device control with or without user 2023PF00618 intervention. The output devices can be communicatively coupled to system 13 via dedicated connections through respective interfaces 232, 233, and 234. Alternatively, the output devices can be connected to system 13 using the communications channel 12 via the communications interface 2004 or a dedicated communication channel corresponding to the communication channel 14 in Fig. 2A via the communication interface 2004. The display system 15 and speakers 26 can be integrated in a single unit with the other components of system 13 in an electronic device such as, for example, a television. In various embodiments, the display interface 232 includes a display driver, such as, for example, a timing controller (T Con) chip. The display system 15 and speaker 26 can alternatively be separate from one or more of the other components. In various embodiments in which the display system 15 and speakers 26 are external components, the output signal can be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs. Fig. 2B illustrates a block diagram of an example of the system 11 in which various aspects and embodiments are implemented. System 11 is very similar to system 13. The system 11 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects and embodiments described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, a camera and a server. Elements of system 11, singly or in combination, can be embodied in a single integrated circuit (IC), multiple ICs, and / or discrete components. For example, in at least one embodiment, the system 11 comprises one processing module 200 that implements an encoding module. In various embodiments, the system 11 is communicatively coupled to one or more other systems, or other electronic devices, via, for example, a communications bus or through dedicated input and / or output ports. In various embodiments, the system 11 is configured to implement one or more of the aspects described in this document. The input to the processing module 200 can be provided through various input modules as indicated in block 231 already described in relation to Fig.2C. Various elements of system 11 can be provided within an integrated housing. Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangements, for example, an internal bus 2023PF00618 as known in the art, including the Inter-IC (I2C) bus, wiring, and printed circuit boards. For example, in the system 11, the processing module 200 is interconnected to other elements of said system 11 by the bus 2005. The communication interface 2004 of the processing module 200 allows the system 200 to communicate on the communication channel 12. Data is streamed, or otherwise provided, to the system 11, in various embodiments, using a wireless network such as a Wi-Fi network, for example IEEE 802.11 (IEEE refers to the Institute of Electrical and Electronics Engineers). The Wi- Fi signal of these embodiments is received over the communications channel 12 and the communications interface 2004 which are adapted for Wi-Fi communications. The communications channel 12 of these embodiments is typically connected to an access point or router that provides access to external networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 11 using the RF connection of the input block 231. As indicated above, various embodiments provide data in a non-streaming manner. Additionally, various embodiments use wireless networks other than Wi-Fi, for example a cellular network or a Bluetooth network. The data provided to the system 11 can be provided in different format. In various embodiments, these data are raw data provided for example by a picture acquisition module connected to the system 11 or comprised in the system 11. In that case, the processing module take in charge the encoding of these data. The system 11 can provide an output signal to various output devices capable of storing and / or decoding the output signal such as the system 13. Various implementations involve decoding. “Decoding”, as used in this application, can encompass all or part of the processes performed, for example, on a received encoded video stream (i.e., received video data) in order to produce a final output suitable for display. In various embodiments, such processes include processes performed by a decoder of various implementations described in this application in relation to Fig.7. Various implementations involve encoding. In an analogous way to the above discussion about “decoding”, “encoding” as used in this application can encompass all or part of the processes performed, for example, on an input video sequence in order to 2023PF00618 produce an encoded video stream. In various embodiments, such processes include processes performed by an encoder of various implementations described in this application in relation to Fig.6. When a figure is presented as a flow diagram, it should be understood that it also provides a block diagram of a corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow diagram of a corresponding method / process. The implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program). An apparatus can be implemented in, for example, appropriate hardware, software, and firmware. The methods can be implemented, for example, in a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable / personal digital assistants ("PDAs"), and other devices that facilitate communication of information between end-users. Reference to “one embodiment” or “an embodiment” or “one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” or “in one implementation” or “in an implementation”, as well any other variations, appearing in various places throughout this application are not necessarily all referring to the same embodiment. Additionally, this application may refer to “determining” various pieces of information. Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, retrieving the information from memory or obtaining the information for example from another device, module or from user. Further, this application may refer to “accessing” various pieces of information. Accessing the information can include one or more of, for example, receiving the 2023PF00618 information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information. Additionally, this application may refer to “receiving” various pieces of information. Receiving is, as with “accessing”, intended to be a broad term. Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory). Further, “receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information. It is to be appreciated that the use of any of the following “ / ”, “and / or”, and “at least one of”, “one or more of” for example, in the cases of “A and / or B” and “at least one of A and B”, “one or more of A and B” is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, “one or more of A, B and C” such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are listed. Also, as used herein, the word “signal” refers to, among other things, indicating something to a corresponding decoder. For example, in certain embodiments the encoder signals a use of some INR parameters. In this way, in an embodiment the same parameters can be used at both the encoder side and the decoder side. Thus, for example, an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as others, then signaling can be used without 2023PF00618 transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter. By avoiding transmission of any actual functions, a bit savings is realized in various embodiments. It is to be appreciated that signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word “signal”, the word “signal” can also be used herein as a noun. As will be evident to one of ordinary skill in the art, implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted. The information can include, for example, instructions for performing a method, or data produced by one of the described implementations. For example, a signal can be formatted to carry the encoded video stream (i.e. encoded data). Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting can include, for example, encoding an encoded video stream and modulating a carrier with the encoded video stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium. Fig.3 illustrates a simple neural network used for implicit neural representation (INR). Such a neural network used for INR can be referred to as an INR network. For clarity, we use for illustration a 2D signal such as a picture, but, as already mentioned above, INR can be used for signals of any dimension. INR parameterizes a signal as a function (300), which takes coordinates (310) as input and outputs potentially approximated signal values (320) at these coordinates. When the signal processed by the INR is a picture, the inputs (310) can be sample coordinates (x,y) of picture samples and the INR outputs (320) are the picture sample values. Picture samples values can be original sample values of an original picture or residual values representative of a difference between predictor samples and the original samples. A picture sample can be a single component signal (such as a grey scale picture) or a multi-component signal comprising a plurality of components such as for example a RGB, YUV or YUV+d picture where d represents a depth component. In the video case, the output is similar, but the input can include a picture index t in addition to the sample coordinates. The 2023PF00618 INR can be used to reconstruct a signal by computing picture sample values for some or each sample coordinates (x,y). An INR network is typically a neural network composed of multiple neural layers, such as fully connected layers. In Fig. 3, the network has four neural layers. Intermediate outputs are represented by circles. Each neural layer can be described as a function that first multiplies the input by a tensor, adds a vector called the bias and then applies a nonlinear function on the resulting values. In the present document, we may also refer to a neural layer simply as a layer. Tensors shapes (and other characteristics of the tensors) and non-linear functions types of the neural network defines an architecture of the neural network. In the following, tensor values and bias values are denoted by the term weights. The weights and, if applicable, the parameters of the non-linear functions, are called parameters ^^ of the neural network. The architecture and the parameters ^^ define a model. In the following we use ^^ఏto denote an INR function parameterized by ^^. Fig.4A illustrates a typical process to encode a signal using an INR. The process of Fig. 4A is executed for example by the processing module 200 of the system 11. In a step 401, the processing module 200 obtains an input signal and applies a learning phase during which the INR parameters ^^ (or a subset of them) of the INR network allowing reconstructing the input signal from the samples coordinates are learned. In an embodiment, the INR parameters ^^ are learned by minimizing a loss function such as for example, the loss function of equation eq.1 below: ^^ ^^ ^^ ^^ ൌ ^^^ ^^, ^^^^^ ^ ^^ ^^^ ^^^ (eq.1) where ^^ is a distortion which quantifies a difference between a reconstructed version of the signal obtained by applying the INR function ^^ఏto input coordinate and the original signal ^^, ^^ is a bitrate of the encoded INR parameters ^^ and ^^ is a trade-off parameter representing a trade-off between the distortion ^^ and the bitrate ^^. ^^ could be any distortion measure, such as mean squared error as in equation eq.2. ^^ெௌா ൌ^ெே∑௫,௬^^^^^^, ^^^െ ^^ ^^^ ^^, ^^^^ଶ(eq. 2) 2023PF00618 M and N are a width and a height of a picture when the signal is a picture. Other metrics such as LPIPS (Learned Perceptual Image Patch Similarity) can also be used in this case. The optimization of the INR parameters (or weights) ^^ is typically performed by a machine learning approach such as a batch gradient descent method. In a step 402, the processing module 200 encodes the INR parameters ^^ (or a subset of them) in an output bitstream (i.e., in output data). When the signal is a picture, the processing module 200 also adds information representative of the picture such as the width and the height of the picture. Fig.4B illustrates a typical process to decode data using INR. The process of Fig. 4B is executed for example by the processing module 200 of the system 13. In a step 411, the processing module 200 obtains input data, for instance, corresponding to the output data generated by the processing module 200 of the system 11 when applying the method of Fig. 4A. The input data comprises encoded INR parameters ^^. During step 411, the processing module 200 decodes the INR parameters ^^ from the input data and regenerates the INR network applying the INR function ^^ఏ. When the signal is a picture, the processing module 200 also decodes the information representative of the picture. In a step 412, the processing module 200 applies the regenerated INR network (i.e., the processing module 200 applies the INR function ^^ఏ) to samples coordinates to generate a reconstructed version of the input signal obtained by the system 11 in step 401. If the input signal is a picture, the processing module 200 applies the regenerated INR network to at least a sub-part of the samples coordinates (x,y) of the picture. As an example, for a 256x256 samples picture, these coordinates could be all pairs (x,y) for all x∈{0,1,…,255} and y∈{0,1,…,255}. Other choices are possible, for example to generate an up-sampled, down-sampled or extended version of the input picture. Using one INR network globally for a whole signal makes learning difficult, as all parameters contribute to all values and lead to a large network as it must encode all details of the signal. A solution to address this issue is to divide the signal in partitions and to define a local INR network for each partition. When the signal is a picture, the partition of a picture could be a slice, a tile, a coding unit, etc. Fig.5 illustrates an example of partitioning undergone by a picture of pixels 51 2023PF00618 of an original video sequence 20. A picture is divided into a plurality of coding entities. First, as represented by reference 53 in Fig. 5, a picture is divided in a grid of blocks called coding tree units (CTU). A CTU consists for example of an ^^ ൈ ^^ block of luminance samples together with two corresponding blocks of chrominance samples. V is generally a power of two. Second, a picture is divided into one or more groups of CTU. For example, it can be divided into one or more tile rows and tile columns, a tile being a sequence of CTU covering a rectangular region of a picture. In some cases, a tile could be divided into one or more bricks, each of which consisting of at least one row of CTU within the tile. Above the concept of tiles and bricks, another encoding entity, called slice, exists, that can contain at least one tile of a picture or at least one brick of a tile. In the example in Fig.5, as represented by reference 52, the picture 51 is divided into three slices S1, S2 and S3 of the raster-scan slice mode, each comprising a plurality of tiles (not represented), each tile comprising only one brick. As represented by reference 54 in Fig. 5, a CTU may be partitioned into the form of a hierarchical tree of one or more sub-blocks called coding units (CU). The CTU is the root (i.e., the parent node) of the hierarchical tree and can be partitioned in a plurality of CU (i.e. child nodes). Each CU becomes a leaf of the hierarchical tree if it is not further partitioned in smaller CU or becomes a parent node of smaller CU (i.e., child nodes) if it is further partitioned. In the example of Fig.5, the CTU 54 is first partitioned in “4” square CU using a quadtree type partitioning. The upper left CU is a leaf of the hierarchical tree since it is not further partitioned, i.e., it is not a parent node of any other CU. The upper right CU is further partitioned in “4” smaller square CU using again a quadtree type partitioning. The bottom right CU is vertically partitioned in “2” rectangular CU using a binary tree type partitioning. The bottom left CU is vertically partitioned in “3” rectangular CU using a ternary tree type partitioning. During the coding of a picture, the partitioning is adaptive, each CTU being partitioned so as to optimize a criterion such as a criterion of homogeneity of samples in a partition (based on characteristics of the CUs, such as pixel mean, variance, texture and / or any other statistics of the signal within a considered CUs) or compression efficiency of the CTU criterion. In the present application, the term “block” or “picture block” can be used to 2023PF00618 refer to any one of a CTU and a CU. In the present application, the terms “reconstructed” and “decoded” may be used interchangeably, the terms “pixel” and “sample” may be used interchangeably, the terms “image,” “picture”, “sub-picture”, “slice” and “frame” may be used interchangeably. Usually, but not necessarily, the term “reconstructed” is used at the encoder side while “decoded” is used at the decoder side. In the following, it is considered that the processing module 200 of the system 11 obtains a picture divided in coding units (CU) and that the encoding process of Fig. 4 is applied to each coding unit independently. An INR network is therefore obtained for each CU with INR parameters ^^ adapted to this CU. The bitstream outputted by the encoding process of Fig. 4A represents therefore a plurality of sets of INR parameters ^^, one for each CU. As already mentioned in introduction, using INR networks with the same architecture for each CU of a picture is generally suboptimal in terms of rate / distortion performances (i.e., in terms of coding efficiency) but also in terms of computation complexity. In the following embodiments, it is proposed to allow using different INR architectures (with different capacities / number of parameters) for each partition of an encoded signal (i.e., for each CU of a picture). A process is described to choose an optimal architecture for each INR. In an example embodiment, supposing that a signal is partitioned in L partitions, for each partition i of the signal, an architecture ^^^of an INR and parameters ^^^of the INR are learned jointly by minimizing the loss function of equation Eq.1 involving the following distortion D: ^^ ൌ ^ m^^∈in^^ ଶ^^ ^ ^ ^^^^^, ^^^െ ^^ ^^ ^^ ^ ^^, ^^^^Where A is of samples of the partition i and^^ ^^represents the INR function with architecture ^^^and parameters ^^^. encoding procedure, the rate ^^ in equation eq. 1 may include a rate for encoding information representing the architecture ^^^and a rate for encoding information representing the partition i (i.e., size, shape, etc). Fig. 6 illustrates schematically a process to encode a picture according to various embodiments. 2023PF00618 The process of Fig.6 is executed for example by the processing module 200 of the system 11. In the example of Fig. 6, the process is applied to partitions corresponding to coding units (CUs) resulting from a partitioning obtained by the partitioning method illustrated by Fig. 5. However, the same process could be applied identically to other types of portions of a picture such as slices, tiles, CTU, homogeneous regions in terms of complexity, etc. In the example of Fig.6, the partitions comprise original samples of a picture. However, the process of Fig.6 could be also applied to partitions comprising residuals resulting from a prediction of partitions of original samples by a predictor. In a step 600, the processing module 200 applies a partitioning process on the picture. In an embodiment, the partitioning process of Fig. 5 is applied to the picture using an adaptive partitioning wherein the picture is first partitioned in CTU of the same size and then each CTU is partitioned so as to optimize a criterion of homogeneity of samples in a CU. Homogeneity of samples in a CU could be captured for example by measuring a variance of samples in the CU. When the variance of samples in a CU is above a threshold, the CU is further split. The threshold may evolve in function of a depth of a CU in the CTU (i.e., in function of the number of splits that were needed to obtain the CU). The CTUs and CUs are split until finding a variance below the threshold or until a minimum size. In this embodiment, this adaptive partitioning process allows partitioning the picture before determining the architecture ^^^and the parameters ^^^of the INR of each partition. In a step 601, the processing module 200 signals information representative of the partitioning of the picture in a video stream (i.e., in video data). This information provides an information representing a shape, a size and a position of each partition of the picture. In case of the process of the process of Fig. 5, the partitions are CUs in CTUs. In a step 602, the processing module 200 determines if all partitions of the picture were processed. If yes, the process to encode the picture is stopped in a step 603. Otherwise, the processing module 200 applies a step 604 during which a next partition to encode is obtained by the processing module 200. This next partition becomes the current partition i to encode. In a step 605, the processing module 200 determines an architecture ^^^of an 2023PF00618 INR adapted to the current partition. The determination of the architecture may involve evaluating performances of different possible architectures comprised in a set of architectures A on the current partition i based on characteristics of the current partition i. For instance, each architecture of the set of architectures A can be associated to average characteristics of partitions. The architecture ^^^of the set of architectures A that is associated to the average characteristics the closest to the characteristics of the current partition i is selected for the current partition i. In an embodiment, the average characteristics associated to each architecture of the set A were determined by applying each architecture of the set A on a large set of partitions of pictures of a training sequence of pictures. Then, these average characteristics could be updated during the encoding of the partitions of the picture. In an embodiment of step 605, the determination of the architecture could be based on encoding results of previous partitions using for example a reinforcement learning or an active learning algorithm. In a step 606, the processing module 200 learns the parameters ^^^of the INR to apply to the current partition i, the architecture of the INR being the architecture ^^^determined in step 605. In an example embodiment, for the partition i and the architecture ^^^, the parameters ^^^of the INR are learned by minimizing the loss function of equation Eq.1 involving the following distortion D1 below: ^^1 ൌ min ^ ^^^^^, ^^^െ ^^^^^ ^^, ^^^ଶ^^ ^^ ^ ^^ ^^ ^The gradient descent process applying gradient descent of the loss function D1. At each iteration ^^ of a recursive process, the parameters of the INR ^^^are updated as: Θ௧ା^ൌ Θ௧െ λ∇^^^1, where Θ௧represents the INR parameters ^^ at the iteration t. In this optimization, the parameter λ is denoted the learning rate. The learning phase results in a set of INR parameters ^^^^௧^ optimized for the current partition i. In a step 607, the processing module 200 encodes information representative of the architecture ^^^^௧^ and of the parameters ^^^of the INR in the video data. In an embodiment the parameters ^^^^௧^ are encoded in the video data using existing codec such as MPEG-NNC (ISO / IEC 15938-17:2022). In another embodiment, the parameters ^^^^௧^ are quantized and entropy coded in the video data. Regarding the 2023PF00618 architecture ^^^, several encoding method are possible. In a first example, the architectures of the set A are supposed not known by the decoder. In this first example, the architectures of the set A are transmitted to the decoder using a SEI (supplemental enhancement information) message attached to the video data. A SEI message, as defined for example in standards such as VVC (ISO / IEC 23090-3 – MPEG-I : Versatile Video Coding (VVC) / ITU-T H.266), HEVC (ISO / IEC 23008-2 – MPEG-H Part 2, High Efficiency Video Coding / ITU-T H.265)) and AVC ((ISO / CEI 14496-10), is a data container associated to video data and comprising metadata providing information relative to the video data. In a variant of the first example, the architectures of the set A are transmitted using high level syntax per sequence in a sequence parameter set (SPS), per picture in a picture parameter set (PPS) or a picture header or per slices in a slice header. Then, when encoding the current partition i, a syntax element representing an index identifying the architecture ^^^selected for the current partition i is signaled in the video data with the information representative of the parameters ^^^^௧^ of the INR to apply to the current partition i. In a second example, the architectures of the set A are supposed known by the decoder. In that case, there is no need to transmit the architectures of the set A to the decoder. Only the syntax element representing the index identifying the architecture ^^^selected for the current partition i is signaled in the video data with the information representative of the parameters ^^^^௧^ of the INR to apply to the current partition i. Step 606 is followed by step 602 already described. In the embodiment described until now in relation to Fig.6, the partitions of the picture, the architecture of the INR of each partition and the parameters of the INR of each partition are determined independently and sequentially. There are many possible variants of this embodiment. For example, the partitioning of the picture, the architecture of the INR of each partition, the parameters of the INR of each partition could be optimized jointly using any optimization algorithm such as greedy search, gradient descent of a specific loss function, genetic algorithms, the use of machine learning algorithms, etc. In a first variant, steps 605 and 606 are combined in a joint learning process of determining the architecture ^^^and the parameters ^^^for the current partition i. In this first variant, for each partition i of the picture, an architecture ^^^of an INR and parameters ^^^of the INR are learned jointly by minimizing the loss function of equation 2023PF00618 Eq.1 involving the following distortion D2 below: ^^2 ൌଶ^m^∈ ^i^n , ^^ ^^ ^ ^ ^^^^^, ^^^െ ^^^^^^^^ ^ ^^, ^^^^The descent process applying gradient descent of the loss function D2. At each iteration ^^ of the recursive process, at least one of the parameters of the INR ^^^and the architecture ^^^are updated as: Θ௧ା^ൌ Θ௧െ λ∇^^^2, where Θ௧represents the INR parameters ^^^and the architecture ^^^at the iteration t. The learning phase results in a set of INR parameters ^^^^௧^ and an architecture ^^^^௧^ optimized for the current partition i. In that case, the rate term R of equation eq. 1 that may be included in the loss function used for the gradient descent process takes into account the rate used for encoding information representative of the architecture ^^^^௧^ and of the parameters ^^^^௧. If the information representative of the architectur^^௧^ e ^^^and of the parameters ^^^^௧^ is quantized and entropy coded, the rate term R may take into account the result of the quantization and / or of the entropy coding of the information representative of the architecture ^^^^௧and o^^௧^ f the parameters ^^^. In a second variant, the process of Fig. 6 is replaced by a global optimization process wherein the partitioning of the picture, the architecture ^^^and the parameters ^^^of each partition are optimized jointly. In this second variant, the partitions used for partitioning the picture are selected in a set of partitions P. For instance, the set of partitions P comprises CTUs of fixed size as represented by reference 53 in Fig.5, and all possible subdivisions of CTUs in CUs as represented by reference 54 and 541 in Fig.5. This set of partitions P allows defining a finite set of possible partitioning Π of the picture in CTUs and CUs. A partitioning π of the set of possible partitioning Π of the picture and, for each partition ^^గresulting from the partitioning π of the picture, an architecture ^^^ഏof an INR and parameters ^^^ഏof the INR are learned jointly by minimizing the loss function of equation Eq. 1 involving the following distortion D3 below: ଶ ^^3 ൌ min ^^^ ^^, ^^^ െ ^^^ഏ^∈ஈ,^^ ∈ ^^, ^^^ ^ ^ ^^^^ഏ^ ^^, ^^^^ 2023PF00618 where ∑^ഏ∈గ^ adds the distortions of all partitions ^^గresulting from the partitioning picture. The minimization uses for example a recursive gradient descent process applying gradient descent of the loss function D3. At each iteration ^^ of the recursive process, the parameters of the INR ^^^, the architecture ^^^, and the partitioning π are updated as: Θ௧ା^ൌ Θ௧െ λ∇^^^3, where Θ௧represents the INR parameters ^^^, the architecture ^^^and the partitioning π at the iteration t. The learning phase results in a set of INR parameters ^^^^௧ ^^௧^ , a set of architectures ^^^and a partitioning π^^௧optimized for the picture, all these information being in video data. In that case, the rate term R of equation eq.1 takes into account for all partitions ^^గof the partitioning π^^௧the rate used for encoding information representative of the architecture ^^^^௧and of the parameters ^^^௧^ ^^, but also the rate for encoding the partitioning π^^௧of the picture. If the information representative of the architecture ^^^^௧^ , of the parameters ^^^^௧^ and of the partitioning π^^௧are quantized and / or entropy coded, the rate term R may take into account the result of the quantization and / or of the entropy coding of the information representative of the architecture ^^^^௧^ , of the parameters ^^^^௧^ and of the partitioning π^^௧. One can note that until now, we have considered that all partitions of the picture were encoded using an INR. In a variant, only a subset of partitions is encoded using an INR. Remaining partitions are encoded by other means such an Intra prediction, an inter prediction or skipped. Fig. 7 illustrates schematically a process to decode a picture according to various embodiments. The process of Fig.7 is executed for example by the processing module 200 of the system 13 on video data produced by the method of Fig.6. In a step 700, the processing module 200 decodes an information representative of the partitions of the partitioned picture. In a step 701, the processing module determines if all partitions of the picture were processed. If yes, the processing module 200 stop the decoding process in step 702. Otherwise, step 702 is followed by step 703. In step 703, the processing module 2023PF00618 200 obtains data representing a partition i from the video data. In a step 704, the processing module 200 decodes an information representing an architecture ^^^and of parameters ^^^of an INR to apply to reconstruct the partition i. In a step 705, the processing module 200 applies the INR defined by the architecture ^^^and the parameters ^^^on sample coordinates of the partition i. Step 705 is followed by step 701 already described. Variants of the above embodiments are possible, such as constructing the INR networks all at once and then generating the values; constructing the INR networks and computing the values per partition sequentially, one at a time; modifying the order of the input coordinates within a partition; using batches of coordinates as input to perform parallel computation of values; grouping partitions by architectures, initializing one INR network per architecture (sequentially, in parallel or a mix of both) and, for each partition using this architecture, setting the parameters of the INR network to the value associated to this partition and performing inference to recover the values of the pixels of this partition. Experimental results show that the proposed method for encoding of Fig.6 and its variants leads to better rate / distortion performances than using a single identical architecture of INR for all partitions of a picture. We described above a number of embodiments. Features of these embodiments can be provided alone or in any combination. Further, embodiments can include one or more of the following features, devices, or aspects, alone or in any combination, across various claim categories and types: ^ A bitstream or signal or video data that includes information representative of one or more of the described INR parameters, INR architecture or of a partitioning of a picture, or variations thereof. ^ Creating and / or transmitting and / or receiving and / or decoding a bitstream or signal that includes information representative of one or more of the described INR parameters, INR architecture or of a partitioning of a picture, or variations thereof. 2023PF00618 ^ A TV, set-top box, cell phone, tablet, or other electronic device that performs at least one of the embodiments described. ^ A TV, set-top box, cell phone, tablet, or other electronic device that performs at least one of the embodiments described, and that displays (e.g. using a monitor, screen, or other type of display) a resulting picture. ^ A TV, set-top box, cell phone, tablet, or other electronic device that tunes (e.g. using a tuner) a channel to receive a signal including an encoded video stream, and performs at least one of the embodiments described. ^ A TV, set-top box, cell phone, tablet, or other electronic device that receives (e.g. using an antenna) a signal over the air that includes an encoded video stream, and performs at least one of the embodiments described. ^ A server, camera, cell phone, tablet or other electronic device that transmits (e.g. using an antenna) a signal over the air that includes an encoded video stream, and performs at least one of the embodiments described. ^ A server, camera, cell phone, tablet or other electronic device that tunes (e.g. using a tuner) a channel to transmit a signal including an encoded video stream, and performs at least one of the embodiments described.

Claims

2023PF00618 Claims 1. A method for encoding comprising: obtaining (604) a current partition representing a subpart of a signal; determining (605) an architecture of an implicit neural representation network adapted to the current partition; learning (606) parameters of the implicit neural representation network with the determined architecture for the current partition; and, signaling (607) information representing the learned parameters and the determined architecture in video data.

2. The method of claim 1 wherein information representing the learned parameters and the determined architecture result from an application of at least one of a quantization process or an entropy coding process onto the learned parameters and the determined architecture.

3. The method of claim 1 or 2 wherein the learning of the parameters of the implicit neural representation network comprises determining the parameters of the implicit neural representation network minimizing of a loss function depending on the parameters of the implicit neural representation and of the determined architecture.

4. The method of claim 1 or 2 wherein the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the parameters of the implicit neural representation and of the architecture.

5. The method of claim 1 or 2 wherein the current partition results from an application of a partitioning to the signal and wherein the partitioning, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the partitioning, the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on2023PF00618 the partitioning and for each partition resulting from the partitioning, of the parameters of the implicit neural representation and of the architecture associated to this partition.

6. The method of any previous claim wherein, the information representing the architecture is an index on an architecture of a set of architectures.

7. The method of claim 6 wherein, the set of architectures is signaled in the video data.

8. A method for decoding comprising: decoding from video data an information representing a partitioning of at least a portion of a signal in a plurality of partitions; for each partition of at least a subset of partitions resulting from the partitioning; decoding (704) from the video data information representative of an architecture of an implicit neural representation and of parameters of the implicit neural representation for the partition; and, applying (705) the implicit neural representation with the decoded architecture and parameters to samples coordinates of the partitions to reconstruct the partition.

9. The method according to claim 8 wherein, the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation are quantized or entropy coded version or quantized and entropy coded versions of the architecture and of the parameters, the architecture and the parameters applied to reconstruct the partition result from respectively an inverse quantization or an entropy decoding or an entropy decoding and an inverse quantization of the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation.

10. The method of claim 8 or 9 wherein the information representative of the architecture is an index on an architecture of a set of architectures.

11. The method of claim 10 wherein, the set of architectures is signaled in the video data.2023PF00618 12. A device for encoding comprising electronic circuitry configured for : obtaining (604) a current partition representing a subpart of a signal; determining (605) an architecture of an implicit neural representation network adapted to the current partition; learning (606) parameters of the implicit neural representation network with the determined architecture for the current partition; and, signaling (607) information representing the learned parameters and the determined architecture in video data.

13. The device of claim 12 wherein information representing the learned parameters and the determined architecture result from an application of at least one of a quantization process or an entropy coding process onto the learned parameters and the determined architecture.

14. The device of claim 12 or 13 wherein the learning of the parameters of the implicit neural representation network comprises determining the parameters of the implicit neural representation network minimizing of a loss function depending on the parameters of the implicit neural representation and of the determined architecture.

15. The device of claim 12 or 13 wherein the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the parameters of the implicit neural representation and of the architecture.

16. The device of claim 12 or 13 wherein the current partition results from an application of a partitioning to the signal and wherein the partitioning, the learned parameters and the determined architecture are obtained by applying a joint learning process comprising determining the partitioning, the parameters of the implicit neural representation network and the architecture minimizing of a loss function depending on the partitioning and for each partition resulting from the partitioning, of the parameters of the implicit neural representation and of the architecture associated to this partition.2023PF00618 17. The device of any previous claim from claim 12 to 16 wherein the information representing of the architecture is an index on an architecture of a set of architectures.

18. The device of claim 17 wherein, the set of architectures is signaled in the video data.

19. A device for decoding comprising electronic circuitry configured for: decoding from video data an information representing a partitioning of at least a portion of a signal in a plurality of partitions; for each partition of at least a subset of partitions resulting from the partitioning; decoding (704) from the video data information representative of an architecture of an implicit neural representation and of parameters of the implicit neural representation for the partition; and, applying (705) the implicit neural representation with the decoded architecture and parameters to samples coordinates of the partitions to reconstruct the partition.

20. The device according to claim 19 wherein the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation are quantized or entropy coded version or quantized and entropy coded versions of the architecture and of the parameters, the architecture and the parameters applied to reconstruct the partition result from respectively an inverse quantization or an entropy decoding or an entropy decoding and an inverse quantization of the information representative of the architecture of the implicit neural representation and of the parameters of the implicit neural representation.

21. The device of claim 19 or 20 wherein the information representative of the architecture is an index on an architecture of a set of architectures.

22. The device of claim 21 wherein, the set of architectures is signaled in the video data.2023PF00618 23. Non-transitory information storage medium storing program code instructions for implementing the method according to any previous claims from claim 1 to 11.

24. A computer program comprising program code instructions for implementing the method according to any previous claims from claim 1 to 11.

25. An output signal generated by the method of claim 1 to 7 or by the device of claim 12 to 18.

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