Method for implementing a quantum parity circuit

Abstract

The invention relates to a method for implementing a quantum parity circuit (1) for N qubits (qb1…5) by means of at most 2N global entangling gates (3), comprising the steps of: a) implementing the quantum parity circuit (1) by means of at most N fan-in gates (21) or fan-out gates (22); b) converting each of the fan-in gates (21) or fan-out gates (22) into individual qubit gates (4) and at most two global entangling gates (3). The invention also relates to a computer program, a computer-readable storage medium, and a quantum computer.

Description

[0001] P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 1 - Description Method for representing a quantum parity circuit. A method for representing a quantum parity circuit is specified. One object of various embodiments is to specify a method for representing a quantum parity circuit in which the number of required entanglement gates is as small as possible. This object is achieved by a method having the steps of patent claim 1. Advantageous embodiments and developments of the method for representing a quantum parity circuit are specified in the dependent claims.According to one embodiment, the method for representing a quantum parity circuit for N quantum bits (short: qubits) by at most 2N global entanglement gates comprises a step in which the quantum parity circuit is represented by at most N input fan-out gates or output fan-out gates. Here and below, quantum parity circuits are a special subclass of general quantum circuits in which output states of the qubits correspond, in particular, to parities of one or more input states of the qubits. A qubit is a quantum mechanical two-state system with two linearly independent basis states, which are referred to below as "|0>" and "|1>". The states |0> and |1> form a calculation state basis (English: measurement P2023,0537 WO N August 13, 2024 FOKUS - 2023P66160 WO - 2 - basis). For example, the parity of the qubits corresponds to a parity in the computational state basis.In particular, a quantum parity circuit is a quantum mechanical generalization of a classical parity circuit. In the classical parity circuit, the value of an output bit corresponds to the parity of one or more input bits. For example, the output bit of the classical parity circuit takes the value "1" if an odd number of input bits has the value "1", while the output bit takes the value "0" if an even number of input bits has the value "1". For example, a classical parity circuit can be constructed by sequentially connecting the input bits using exclusive-OR gates (XOR gates for short). In the quantum parity circuit, for example, an output state of at least one qubit corresponds to a parity of input states of one or more qubits.For example, the parity of two qubits can be determined by applying a controlled not gate (CNOT gate) to the two qubits. For example, the CNOT gate has inputs and outputs for exactly one control qubit and exactly one target qubit. Specifically, the CNOT gate negates an output state of the target qubit in the computational state basis if the input state of the control qubit is |1>. In other words, an input state |0> of the target qubit is mapped to the output state |1> of the target qubit, while the input state |1> of the target qubit is mapped to the output state |0> of the target qubit if the input state of the control qubit is |1>. In particular, when the input state of the P2023,0537 WO N 13 August 2024 FOCUS - 2023P66160 WO - 3 - control qubit is |0>, the CNOT gate acts as an identity operation on the target qubit.Thus, the output state of the target qubit after the action of the CNOT gate corresponds to a parity of the input states of the control qubit and the target qubit. Here and in the following, the input state refers to the state of the qubit at the input of a quantum gate or a quantum circuit, while the output state refers to the state of the qubit at the output of a quantum gate or a quantum circuit. With the method described here, in particular, arbitrary quantum parity circuits or general quantum parity circuits for N qubits can be represented by at most 2N or at most N global entanglement gates. For an arbitrary or general quantum parity circuit for N qubits, the output states of one, two, several, or all of the N qubits correspond to the parities of at least two, three, or more of the input states of the N qubits.For example, the quantum parity circuit is a translation of a general classical parity circuit into a quantum circuit. A fan-in gate, for example, consists of one or more CNOT gates. In particular, the fan-in gate can be represented exclusively by paired CNOT gates. For example, the fan-in gate comprises inputs and outputs for exactly one target qubit and at least one or more control qubits, where the target qubit is linked to each of the control qubits via exactly one CNOT gate. After the operation of the fan-in gate, the output state of the target qubit in the computational state basis thus corresponds to the parity of the input states of the target qubit and all control qubits in the computational state basis.A fan-out gate, for example, consists of one or more CNOT gates. In particular, the fan-out gate can be represented exclusively by pairs of CNOT gates. For example, the fan-out gate comprises inputs and outputs for exactly one control qubit and at least one or more target qubits, where each of the target qubits is connected to the control qubit via exactly one CNOT gate. In particular, any fan-out gate can be converted into an input fan-out gate by applying a Hadamard gate to each target qubit of the fan-out gate before each input and after each output of the fan-out gate.Likewise, any input fanout gate can be converted into an output fanout gate by applying a Hadamard gate to the target qubit of the input fanout gate before the corresponding input and after the corresponding output of the input fanout gate. Thus, an input fanout gate can be converted into an output fanout gate, and vice versa. The Hadamard gate H is represented in the computational state basis, in particular, by the unitary 2×2 matrix. by matrix multiplication. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 5 - Embodiments relating to fan-out input gates or fan-out output gates can be directly converted into one another by the conversion described above. The quantum parity circuit is thus represented, for example, by at most N fan-out input gates, or at most N fan-out output gates, or at most N fan-out input gates and fan-out output gates. In other words, the quantum parity circuit is represented by N1 fan-out input gates and N2 fan-out output gates, where 0≤N1≤N, 0≤N2≤N, and N1+N2=N. When the quantum parity circuit is represented by at most N input fan-out gates or output fan-out gates, the input fan-out gates or output fan-out gates act in particular sequentially, i.e. one after the other in time, on the N qubits.For example, it is possible for the output state of the target qubit or a control qubit of a first input fan-out gate or a first output fan-out gate to be an input state of a control qubit or the target qubit of a subsequent second input fan-out gate or a second output fan-out gate. It should be noted that, unlike a classical bit, the state of a qubit cannot be copied and / or cloned for physical reasons. For example, a classical parity circuit constructed from XOR gates cannot generally be directly translated into a corresponding quantum parity circuit by simply replacing each classical XOR gate with a CNOT quantum gate.This is especially true when inputs of at least two different XOR gates of the classical parity circuit are linked to the same input bit, i.e. when a classical bit is linked to two or more XOR gates via at least two lines. According to a further embodiment, the method comprises a step in which each of the input fan-out gates or output fan-out gates is converted into single-qubit gates and at most two global entanglement gates. Alternatively, the method comprises a step in which each of the input fan-out gates is converted into single-qubit gates and at most one global entanglement gate. In this case, a single-qubit gate acts in particular only on a single qubit. In other words, a single-qubit gate has exactly one input and exactly one output for each qubit.For example, the single-qubit gates comprise Hadamard gates and / or phase gates or are Hadamard gates and / or phase gates. A global entanglement gate is, in particular, an entanglement gate that can act on all qubits of the quantum parity circuit. For example, the global entanglement gate acts simultaneously on all pairwise combinations of qubits, or on selected pairs of qubits. By using global entanglement gates, the total number of quantum gates required to represent the quantum parity circuit can be reduced compared to the use of simple entanglement gates, each of which acts only on a single pair of qubits. Thus, when implementing the quantum parity circuit with a quantum computer, for example, an error rate is reduced. Preferably, the global entanglement gate is a native quantum gate.Here and in the following, a native quantum gate is a quantum gate that can be directly physically implemented on a quantum computer. In particular, a native quantum gate does not need to be translated into a sequence of further quantum gates in order to be implemented on a given quantum computer. Native quantum gates are determined, for example, by the hardware platform of the quantum computer, i.e., by the specific physical realization of the qubits. For example, the native quantum gates for superconducting qubits differ from the native quantum gates for ion-based qubits. In particular, the method described here requires at most 2N global entanglement gates to represent a quantum parity circuit for N qubits, if the global entanglement gates act uniformly on all pairs of qubits participating in the respective global entanglement gate.In the case of non-uniform global entanglement gates, which, for example, act differently on pairs of qubits participating in the respective global entanglement gate, a representation of the quantum parity circuit for N qubits with at most N global entanglement gates is also possible. Depending on the specific physical implementation of the qubits, uniform global entanglement gates and / or non-uniform global entanglement gates can be applied to the qubits as native quantum gates in a quantum computer. In some quantum computers, for example, non-uniform global entanglement gates cannot be implemented as native quantum gates.According to a preferred embodiment, the method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates or by at most N global entanglement gates comprises the following steps: a) representing the quantum parity circuit by at most N input fan-out gates or output fan-out gates; b) converting each of the input fan-out gates or output fan-out gates into single-qubit gates and at most two global entanglement gates, or converting each of the input fan-out gates or output fan-out gates into single-qubit gates and at most one global entanglement gate. Preferably, the steps of the method are carried out in the order specified above. In particular, in the method described here, at most 2N global entanglement gates and no further simple entanglement gates are necessary to represent the quantum parity circuit for N qubits.The method described here is based on the idea of ​​representing a quantum parity circuit using as few native entanglement gates as possible. When implementing entanglement gates in a quantum computer, errors can occur that can severely limit the usability of the quantum computer. In particular, every concrete realization of a quantum gate with a quantum computer is error-prone, and the total error of a quantum circuit increases with the number of quantum gates. By reducing the number of required entanglement gates, the error rate of the quantum computer can be advantageously reduced when implementing the quantum parity circuit.Alternatively or additionally, the method described here can advantageously be used to implement a quantum parity circuit for a larger number of qubits, given a given maximum permissible error rate of the quantum computer. Quantum circuits for N qubits can be designed as unitary 2nd order circuits. N ×2 NMatrices. The unitary matrix of a general CNOT quantum circuit for N qubits, which is composed exclusively of CNOT gates, can, for example, be decomposed into a lower triangular matrix and an upper triangular matrix using an LU decomposition of the unitary matrix, which in turn can be represented by N-1 input fan-out gates and N-1 output fan-out gates. Each of these input and output fan-out gates can be represented by 2N-3 global entanglement gates. Thus, for example, 4N-6 global entanglement gates are required to represent a general CNOT quantum circuit for N qubits. The publication by D. Masolv and Y.Nam, "Use of global interactions in efficient quantum circuit constructions," New Journal of Physics 20, 033018 (2018), the disclosure of which is hereby incorporated by reference, describes, for example, the representation of general CNOT circuits for N qubits using 4N-6 uniform global entanglement gates. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 10 - Quantum parity circuits represent a special case of general CNOT quantum circuits, which can also be constructed exclusively from CNOT gates. In contrast to general CNOT circuits, however, the method described here allows a representation of quantum parity circuits with a comparatively smaller number of at most 2N or at most N global entanglement gates. Thus, by implementing the quantum parity circuit on a quantum computer according to the method described here, the error rate in particular can be reduced.Furthermore, Clifford circuits, which are important for quantum error correction, for example, can be converted into a H+S+CZ+Parity+H+CZ+S+H normal form. Here, "Parity" denotes a quantum parity circuit, while H, S, and CZ represent layers of Hadamard gates (H), phase gates (S), and controlled Z gates (CZ), respectively. The method described here thus also enables the simplification of Clifford circuits by reducing the necessary entanglement gates in the quantum parity circuit of the corresponding normal form. The above-mentioned normal form of Clifford circuits is described, for example, in the paper R. Duncan, A. Kissinger, S. Perdrix, and Jvd Wetering, “Graph-theoretic Simplification of Quantum Circuits with the ZX-calculus”, Quantum 4, 279 (2020), the disclosure content of which is hereby incorporated by reference.According to a further embodiment of the method, the quantum parity circuit has inputs and outputs for N qubits each. In particular, the quantum parity circuit has inputs and outputs for exactly N qubits each. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 11 - According to a further embodiment of the method, output states of the N qubits of the quantum parity circuit each correspond to parities of one or more input states of the N qubits of the quantum parity circuit. For example, each output of the quantum parity circuit has one or more associated inputs. For example, the output state of a qubit is set to |1> if the input states of an odd number of associated qubits are set to |1>, while the output state of that qubit is set to |0> if the input states of an even number of associated qubits are set to |1>.This also applies, for example, to superposition states of qubits. According to a further embodiment of the method, each fan-out input gate has inputs and outputs for exactly one target qubit and at least one control qubit. The output state of the target qubit depends in particular on the input states of the target qubit and all control qubits. For example, the output state of the target qubit in the computational state basis corresponds to the parity of all input states of the fan-out input gate in the computational state basis. According to a further embodiment of the method, the target qubit of the fan-out input gate is connected to each control qubit of the fan-out input gate via a CNOT gate. In particular, the target qubit of the fan-out input gate is the target qubit of each CNOT gate of the fan-out input gate. P2023,0537 WO N 13.August 2024 FOCUS - 2023P66160 WO - 12 - According to a further embodiment of the method, each output fan-out gate has inputs and outputs for exactly one control qubit and at least one target qubit. The output states of the target qubits depend in particular on the input states of the target qubits as well as on the input state of the control qubit. According to a further embodiment of the method, the control qubit of the output fan-out gate is connected to each target qubit of the output fan-out gate via a CNOT gate. In particular, each target qubit of the output fan-out gate is the target qubit of the corresponding CNOT gate of the output fan-out gate. According to a further embodiment of the method, in step b), ieIn the step of converting each of the input fan-out gates or output fan-out gates into single-qubit gates and at most two global entanglement gates, at least one of the input fan-out gates or output fan-out gates is converted into single-qubit gates and one or exactly one non-uniform, generalized Mølmer-Sørensen gate. For example, the conversion of an input fan-out gate into single-qubit gates and exactly one non-uniform, generalized Mølmer-Sørensen gate is described in connection with Figure 5. For example, the conversion of an output fan-out gate into single-qubit gates and exactly one non-uniform, generalized Mølmer-Sørensen gate is described in connection with Figure 13. The generalized Mølmer-Sørensen gate (short: GMS gate) is also called global Mølmer-Sørensen gate and is a P2023,0537 WO N 13.August 2024 FOCUS - 2023P66160 WO - 13 - Native entanglement gate for ion-based quantum computers. In ion-based quantum computers, qubits are realized by the electronic states of ions trapped in ion traps using electric and / or magnetic fields. The effect of the GMS gate on N qubits can be described by the following unitary operator or the following unitary second order. N ×2 N Matrix can be described: Here ^^ ^ denotes ^ ∈ { ^, ^, ^ } one of the three 2×2 Pauli matrices ^ ^ , ^ ^ , or ^ ^ , which acts on the i-th qubit. Products of Pauli matrices that act on different qubits are to be understood as tensor products. The GMS gate thus acts on all pairs of qubits. For example, the GMS gate can be realized for ^ = ^ = ^ for all ^ and ^. Furthermore, a real phase that can be set when implementing the GMS gate. If ^ ^^ is different for at least two pairs of qubits, the gate is called a non-uniform GMS gate. For non-uniform GMS gates, it is also possible that the phase for certain pairs of qubits is set to ^ ^^ = 0, while the phase for other pairs of qubits is different from zero. If the phase ^ ^^= ^ is identical for all pairs of qubits, the gate is referred to as a uniform GMS gate. Otherwise, it is a non-uniform GMS gate. According to a further embodiment of the method, in step b), ie in the step of converting each of the input fan-out gates or output fan-out gates into single-qubit gates and at most two global entanglement gates, at least one of the P2023,0537 WO N August 13, 2024 FOKUS - 2023P66160 WO - 14 - input fan-out gates or output fan-out gates is converted into single-qubit gates and two or exactly two uniform, generalized Mølmer-Sørensen gates. For example, the conversion of an input fan-out gate into single-qubit gates and exactly two uniform, generalized Mølmer-Sørensen gates is described in the above-mentioned paper D. Masolv and Y. Nam, “Use of global interactions in efficient quantum circuit constructions”, New Journal of Physics 20, 033018 (2018).According to a further embodiment of the method, the quantum parity circuit has a first fan-out input gate and a second fan-out input gate following the first fan-out input gate. In particular, the subsequent second fan-out input gate acts on the qubits after the first fan-out input gate has already acted on the qubits. According to a further embodiment of the method, the second fan-out input gate is modified to compensate for the effect of the first fan-out input gate on the target qubit of the first fan-out input gate if the target qubit of the first fan-out input gate is a control qubit of the second fan-out input gate. For example, after the execution of the first fan-out input gate, the initial state of the target qubit of the first fan-out input gate is the value y. i = x i ⊕x k1 ⊕…⊕x kn , where y idenotes the initial state of the target qubit, x i denotes the input state of the target qubit and x k1 up to x kn the input states of the n P2023,0537 WO N 13 August 2024 FOCUS - 2023P66160 WO - 15 - control qubits, while the symbol the classical XOR or the quantum mechanical CNOT operation. If the second input fan-out gate also depends on the input state x i of the i-th qubit, which, however, is already set to y by the first input fan-out gate. i has been changed, then the second input fan-out gate is modified, for example, in such a way that in the second input fan-out gate all occurrences of x i by the following, from y i dependent expression x i = y i ⊕x k1 ⊕…⊕x kn This expression is based on the fact that x k ⊕x k = 0 and x i ⊕0 = x iIn this way, any subsequent dependencies on the input x itaken into account and no additional global entanglement gates are added in this step. According to a further embodiment of the method, the second input fan-out gate is modified such that all control qubits of the first input fan-out gate are used as further control qubits of the second input fan-out gate. In particular, for each control qubit of the first input fan-out gate, a CNOT gate with this control qubit is added to the second input fan-out gate. This is illustrated below using an example. For example, the quantum parity circuit should map the N qubit state |x1, x2, x3,…> to the state |x1⊕x3, x1⊕x2, x3,…>, where x1, x2, and x3 denote arbitrary input states of the first, second, and third qubits, while the symbol “⊕” denotes the classical XOR or quantum mechanical CNOT operation for calculating the parity.In this case, the quantum parity circuit can be represented by a first P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 16 - input fan-out gate and a second input fan-out gate. For example, the first input fan-out gate consists of a CNOT gate, where the first qubit x1 is the target qubit and the third qubit x3 is the control qubit of the first input fan-out gate. The first input fan-out gate changes the state of the first qubit to |x1⊕x3>. Thus, the second fan-out gate following the first fan-out gate cannot be exclusively represented by a single CNOT gate with the second qubit x2 as the target qubit and the first qubit x1 as the control qubit, since the output state of the second qubit x2 would then be |x1⊕x2⊕x3> instead of |x1⊕x2>.To compensate for the effect of the first input fan-out gate on the first qubit, the third qubit x3 can be added to the second input fan-out gate as an additional control qubit. Thus, the output state of the second qubit x2 at the second input fan-out gate is |x1⊕x2⊕x3⊕x3> = |x1⊕x2>, because x3⊕x3 = 0 and an XOR or CNOT operation with the state |0> acts like an identity operation. According to a further embodiment of the method, the quantum parity circuit has a first output fan-out gate and a second output fan-out gate following the first output fan-out gate. In particular, the subsequent second output fan-out gate acts on the qubits after the first output fan-out gate has already acted on the qubits. According to a further embodiment of the method, the second output fan-out gate is modified to achieve the effect P2023,0537 WO N 13.August 2024 FOCUS - 2023P66160 WO - 17 - of the first fan-out output gate to a target qubit of the first fan-out output gate if this target qubit of the first fan-out output gate is a control qubit of the second fan-out output gate. For example, after the execution of the first fan-out output gate, the value y is in the initial state of a target qubit of the first fan-out output gate. i = x i ⊕x c , where y i denotes the initial state of this target qubit, x i denotes the input state of this target qubit and x C denotes the input state of the control qubit, while the symbol the classical XOR or the quantum mechanical CNOT operation. If the second output fan-out gate is also dependent on the input state x i of the i-th qubit, which, however, is already set to y by the first output fan-out gate. ihas been changed, then the second output fan-out gate is modified, for example, in such a way that in the second output fan-out gate all occurrences of x i by the following, from y i dependent expression x i = y i ⊕x C This expression is based on the fact that x C ⊕x C = 0 and x i ⊕0 = x i In this way, any subsequent dependencies on the input x itaken into account. According to a further embodiment of the method, the second output fan-out gate is modified such that each target qubit of the second output fan-out gate is connected to the control qubit of the first output fan-out gate via a corresponding CNOT gate. According to a further embodiment of the method, inputs or outputs of the quantum parity circuit of a first qubit and a second qubit are virtually swapped if an output state of the first qubit depends on the input state of the second qubit and does not depend on the input state of the first qubit. The virtual swap consists, for example, in renumbering the inputs or outputs of the quantum parity circuit. In particular, no additional swap gates are necessary when implementing the quantum parity circuit with a quantum computer. This is described inThe following is illustrated by an example. For example, the quantum parity circuit is intended to map the N qubit state |x1, x2, x3,…> to the state |x2⊕x3, x1, x3,…>. In particular, the output state of the first qubit x1 does not depend on the input state of the first qubit x1. In this case, the quantum parity circuit can be represented by a single input fan-out gate or output fan-out gate. For example, the input fan-out gate or the output fan-out gate consists of a CNOT gate with the second qubit x2 as the target qubit and the third qubit x3 as the control qubit. After applying the input fan-out gate, the qubits are thus in the state |x1, x2⊕x3, x3,…>. Compared to the desired output state, the states of the qubits x1 and x2 must be swapped. This can be done by renumbering the output states without requiring a swap gate for the implementation of theQuantum parity circuit is necessary. Alternatively, the input states of the first and second qubits can be swapped, so that the input state corresponds to |x2, x1, x3,…>. In this case, no swapping of states is required in the output state P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 19 - |x1, x2⊕x3, x3,…> after applying the CNOT gate. The swapping of the input states can also be achieved by renumbering the input states, without requiring a swapping gate for the implementation of the quantum parity circuit. According to a further embodiment of the method, in step a), ie in the step of representing the quantum parity circuit by at most N input fan-out gates or output fan-out gates, the quantum parity circuit is represented by a ZX diagram with an input layer and an output layer directly linked thereto, wherein the input layer has aZ-spider for each input of the quantum parity circuit, and the output layer has an X-spider for each output of the quantum parity circuit. ZX diagrams and the so-called ZX calculus are described, for example, in the aforementioned publication by R. Duncan, A. Kissinger, S. Perdrix, and Jvd Wetering, "Graph-theoretic Simplification of Quantum Circuits with the ZX-calculus," Quantum 4, 279 (2020). According to a further embodiment of the method, each X-spider of the output layer, which has at least two connections to Z-spiders of the input layer, is assigned an input fan-out gate. According to a further embodiment of the method, the input fan-out gates each have a CNOT gate for each connection of the corresponding X-spider to one of the Z-spiders of the input layer. P2023,0537 WO N 13 August 2024 FOCUS - 2023P66160 WO - 20 - According to a furtherIn an embodiment of the method, step b), i.e. the step of converting each of the input fan-out gates into single-qubit gates and at most two global entanglement gates, comprises the following substeps: b1) numbering the inputs and outputs of the quantum parity circuit from 1 to N; b2) executing a loop over all outputs j from 1 to N, with the following substeps: - if the X-spider at output j is not connected to the Z-spider at input j, swapping the X-spiders of the output layer so that the X-spider at output j is connected to the Z-spider at input j and storing the swap; - forming an input fan-out gate by adding a CNOT gate for each connection of the X-spider at output j to a Z-spider at an input different from j, wherein the qubit at output j is the target qubit of the CNOT gate; - Compensate for the effect of the input fan-out gate on the target qubit, if the target qubit is also acontrol qubit of a following input fan-out gate; b3) changing the numbering of the outputs according to the stored swap. The effect of the input fan-out gate on the target qubit is compensated for, for example, as described above by adding all control qubits of the input fan-out gate as further control qubits of the following input fan-out gate. According to a further embodiment, the method can be represented by the following pseudocode: P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 21 - i = 0; n = number of qubits; while i < nj = i; while j < n if output j is connected to input i then if i is not equal to j then note swap operation for output i and j; j++; k = 0; while k < n if input i is connected to output k then add CNOT gate with k as control qubit to input fan-out gate; k++; convert input fan-out gate to GMS gate; m = i; while m < n if output m is connected to input ithen Add output i to output m; m++; i++; Execute the swap operations internally. The step "Add output i to output m" in the pseudocode represents the above-described step of modifying an input fan-out gate to compensate for the effect of a previous input fan-out gate on the associated target qubit. According to a further embodiment of the method, each Z-spider of the input layer that has at least two connections to X-spiders of the output layer is assigned an output fan-out gate. According to a further embodiment of the method, the output fan-out gates each have a CNOT gate for each connection of the corresponding Z-spider to one of the X-spiders of the output layer. According to a further embodiment of the method, step b), ie the step of converting each of the output fan-out gates into single-qubit gates andat most two global entanglement gates, the following substeps: b1) numbering the inputs and outputs of the quantum parity circuit from 1 to N; b2) executing a loop over all inputs j from 1 to N, with the following substeps: - if the Z-spider at input j is not connected to the X-spider at output j, swapping the Z-spiders of the input layer so that the Z-spider at input j is connected to the X-spider at output j and storing the swap; - forming an output fan-out gate by adding a CNOT gate for each connection of the Z-spider at input j to an X-spider at an output different from j, where the qubit at input j is a control qubit of the CNOT gate; P2023,0537 WO N 13 August 2024 FOCUS - 2023P66160 WO - 23 - - compensating the effect of the output fan-out gate on a target qubit if this target qubit is also a control qubit of a following output fan-out gate; b3) changingthe numbering of the inputs according to the stored swap. In particular, the output fan-out gates obtained in this way are converted into global entanglement gates, wherein the global entanglement gates are arranged in a backward order, i.e. starting from the output of the quantum parity circuit towards the input of the quantum parity circuit. For example, the first of the output fan-out gates is the one in which the last qubit acts as a control qubit. According to a further embodiment, the method can be represented by the following pseudocode: i = 0; n = number of qubits; while i < nj = i; while j < n if input j connected to output i then if i not equal to j then note swap operation for input i and j; j++; k = 0; while k < n if output i is connected to input k then P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 24 - add CNOT gate with k as target qubit to output fan-out gate; k++; convertConvert the fan-out output gate into a GMS gate and remember the gate; m = i; while m < n if input m is connected to output i then add input i to input m; m++; i++; perform the swap operations internally; execute the GMS gates in reverse order. The step "add input i to input m" in the pseudocode represents the step described above of modifying a fan-out output gate to compensate for the effect of a previous fan-out output gate on a corresponding target qubit. The step "execute the GMS gates in reverse order" in the pseudocode represents the arrangement of the global entanglement gates from back to front, i.e., from the output of the quantum parity circuit to the input of the quantum parity circuit, as described above. A computer program is also given. All features of the method for representing a quantum parity circuit for N qubits by at most 2N globalEntanglement gates are also disclosed for the computer program, and vice versa. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 25 - According to one embodiment, the computer program comprises instructions which, when the computer program is executed by a computer, cause the computer to carry out the method described here. Furthermore, a computer-readable storage medium is specified. All features of the computer program are also disclosed for the computer-readable storage medium, and vice versa. According to one embodiment, the computer program described here is stored on the computer-readable storage medium. Furthermore, a quantum computer is specified. All features of the method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates are also disclosed for the quantum computer, and vice versa. According to one embodiment of the quantum computer, the quantum computer implements aQuantum parity circuit obtained by the method described here. For example, the quantum computer is an ion-based quantum computer. In an ion-based quantum computer, the basis states of a qubit are realized, for example, by two electronic states of an ion trapped in an ion trap by electric fields and / or magnetic fields. The method described here for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates can run, for example, on a computer, in particular a control computer for the quantum computer. Likewise, the control computer can cause the quantum computer to perform quantum calculations. The quantum calculations comprise in particular the operations of a representation of the quantum parity circuit, where the representation of the quantum parity circuit is represented by theThe method described here is obtained. Further advantageous embodiments and developments of the method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates emerge from the exemplary embodiments described below in conjunction with the figures. Figures 1 and 2 show an input fan-out gate of a quantum parity circuit according to an exemplary embodiment. Figures 3 to 6 show steps of a method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates according to an exemplary embodiment. Figure 7 shows a schematic representation of a computer program according to an exemplary embodiment. Figure 8 shows a schematic representation of a computer-readable storage medium according to an exemplary embodiment. Figure 9 shows a schematic representation of a quantum computer according to an exemplary embodiment. P2023,0537 WO N August 13, 2024FOKUS - 2023P66160 WO - 27 - Figures 10 and 11 show an output fan-out gate of a quantum parity circuit according to an embodiment. Figures 12 to 14 show steps of a method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates according to an embodiment. Figure 15 shows a flowchart of a method for representing a quantum parity circuit for N qubits by at most 2N global entanglement gates according to an embodiment. Identical, similar, or similarly acting elements are provided with the same reference numerals in the figures. The figures and the relative sizes of the elements shown in the figures are not to be considered to scale. Rather, individual elements, in particular layer thicknesses, may be exaggerated for better representation and / or better understanding. Figure 1 shows an example of aInput fan-out gate 21 for N=5 qubits, which has inputs E and outputs A for a target qubit qb T and four control qubits qb C1 , qb C2 , qb C3 , qb C4 has. Generalizations for more or fewer control qubits are obvious. The input fan-out gate 21 consists of four consecutive CNOT gates, where each CNOT gate contains one of the four control qubits qb C1 , qb C2 , qb C3 , qb C4 with the target qubit qb T The order of the CNOT gates is arbitrary. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 28 - An input state |x T , x C1 , x C2 , x C3 , x C4 > of the five qubits is fanned out by the input fan-out gate 21, for example, to the output state |x T ⊕x C1 ⊕x C2 ⊕x C3 ⊕x C4 , x C1 , x C2 , x C3 , x C4> shown, where which describes the classical XOR or quantum mechanical CNOT operation. Thus, the initial state of the target qubit corresponds to qb T the parity of all five qubits at the inputs E of the input fan-out gate 21. The input fan-out gate 21 in Figure 1 is thus an example of a quantum parity circuit 1. Figure 2 shows a ZX diagram 5 of the input fan-out gate 21 according to the example in Figure 1. The XZ diagram 5 has an input layer ES with a Z-spider Z for each input E and an output layer AS with an X-spider X for each output A. Z-spiders Z are represented by white circles, while X-spiders X are represented by black circles. A Z-spider Z with one input (left side) and multiple outputs (right side) represents the mapping |0,0,…><0|+|1,1,…><1|, while an X-spider X with multiple inputs (left side) and one output (right side) represents the mapping ,-,…|, where |±> = (|0>±|1>) / √2 represents rotated basis states obtained by applying a Hadamard gate H. The ZX diagram 5 in Figure 2 thus corresponds to the input fan-out gate from Figure 1. Figure 3 shows a ZX diagram 5 of a quantum parity circuit 1 for N=5 qubits qb1, qb2, qb3, qb4, qb5 according to a further embodiment, which can be represented by three consecutive input fan-out gates 21 or four consecutive output fan-out gates 22. Subsequently, each of these P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 29 - input fan-out gates 21 or output fan-out gates 22 can be represented by single-qubit gates 4 and a global entanglement gate 3, as described below in connection with Figures 4 to 6 and 12 to 14. Figure 4 shows a first step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3.Starting from the first output A in Figure 3, a check is made to see whether it is connected to the first input E. If the first output A is connected to the first input E, the next step is to construct the input fan-out gate 21 for the first output A and then translate it into a global entanglement gate 3. If the first output A is not connected to the first input E, as shown in the example in Figure 3, the outputs A are traversed one after the other until an output A is connected to the first input E. This output A is internally swapped with the first output A, and the swap is stored. What is important about this step is that no gates are added to the quantum parity circuit 1 here, but that the outputs A are only virtually swapped.The stored exchanges are implemented in the final step of the method, whereby the internal numbering of the qubits at the outputs A of the quantum parity circuit 1 is changed according to the stored exchange. In the example of Figure 4, the outputs A of the qubits qb1 and qb3 were exchanged according to the method described above. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 30 - Figure 5 shows a second step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3, whereby the input fan-out gate 21 is constructed to the first output A (qb3 in Figure 4). For this purpose, for each connection of the X-spider X at the output A of the qubit qb3 with a Z-spider Z of the input layer ES (see Figure 4), a CNOT gate is added to the input fan-out gate 21, where the qubit at the output qb3 is the target qubit qb. Tof the input fan-out gate 21, while the qubits qb1, qb2, qb4, qb5 in the example of Figure 4 are control qubits qb C1 , qb C2 , qb C3 , qb C4 of the input fan-out gate 21 to the output of the qubit qb3. Thus, the input fan-out gate 21 described in connection with Figure 1 is constructed. The input fan-out gate 21 described in Figure 1 is subsequently represented by single-qubit gate 4 and exactly one global entanglement gate 3, as shown in detail in Figure 5. The global entanglement gate 3 is here a uniform GMS gate that only ^ ^ Pauli matrices and is therefore called a GZZ gate. The target qubit of the input fan-out gate 21 is marked with "0" in the GZZ gate. Furthermore, "H" denotes a Hadamard gate, which is represented by the unitary 2×2 matrix while P(φ) denotes a phase gate which is represented by the unitary 2×2 matrix P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 31 - is shown. Figure 6 shows a third step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3, wherein the first two steps described in connection with Figures 4 and 5 are repeated for each output A. In this case, it is additionally checked whether the input fan-out gate 21 to the respective output A depends on a qubit whose state was changed by a preceding input fan-out gate 21. This change of state by the preceding input fan-out gate 21 is compensated by the control qubits qb C of the previous input fan-out gate 21 as further control qubits qb Cof the input fan-out gate 21 to the respective output A. In this step, no further quantum gates are added to the quantum parity circuit 1, but only the global entanglement gate 3 is modified. After performing the above-mentioned steps of the method, the outputs A of the quantum parity circuit 1 are renumbered according to the stored permutations from the first step. Figure 6 shows the representation of the quantum parity circuit from Figure 3 by three non-uniform, global entanglement gates 3, which was obtained by the method described above. The global entanglement gates 3 are, in particular, non-uniform because they only act on selected qubits qb. Alternatively, each input fan-out gate 21 can be represented by two uniform global entanglement gates 3.The computer program 10 according to the embodiment in Figure 7 causes a computer to execute the method described here for representing a quantum parity circuit 1 for N qubits by at most 2N global entanglement gates 3. For example, the computer program 10 executes the instructions from the pseudocode described above. The computer program described in connection with Figure 7 is stored on the computer-readable storage medium 11 according to the embodiment in Figure 8. The computer-readable storage medium is, for example, an electronic storage medium, e.g., a flash memory, a magnetic storage medium, e.g., a hard disk, or an optical storage medium, e.g., a DVD (digital versatile disc, or DVD for short).The quantum computer 100 according to the embodiment in Figure 9 comprises an ion trap 101, for example, a Penning trap or a Paul trap, which generates electric and / or magnetic fields for confining one or more electrically charged ions 104. Electronic states of the trapped ions 104 are used for the physical realization of qubits. Quantum gates are implemented, in particular, by laser pulses generated by a laser 102 and / or by microwave pulses, which act on the electronic states of one or more trapped ions 104. The electronic states of the trapped ions 104 are read out, for example, by detecting fluorescence of the trapped ions 104 with a photodetector 103 P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 33 -. The quantum computer 100 implements the quantum parity circuit 1 obtained by the method described here.Figure 10 shows an example of an output fan-out gate 22 for N=3 qubits, which has inputs E and outputs A for two target qubits qb. T1 , qb T2 and a control qubit qb C has. Generalizations for more or fewer target qubits are obvious. The output fan-out gate 22 consists of two consecutive CNOT gates, each CNOT gate containing one of the two target qubits qb T1 , qb T2 with the control qubit qb C The order of the CNOT gates is arbitrary. An input state |x C , x T1 , x T2 , x4, x5> of the five qubits is fanned out by the output fan-out gate, for example, to the initial state |x C , x T1 ⊕x C , x T2 ⊕x C , x4, x5>, where the classical XOR or quantum mechanical CNOT operation describes the initial states of the target qubits qb T1 , qb T2the parities of the control qubit qb C with the respective target qubits qb T1 , qb T2at the inputs E of the output fan-out gate 22. The output fan-out gate 22 in Figure 10 is thus an example of a quantum parity circuit 1. Figure 11 shows a ZX diagram 5 of the output fan-out gate 22 according to the example in Figure 10. The XZ diagram 5 has an input layer ES with a Z-spider Z for each input E and an output layer AS with an X-spider X for each output A. The representations and the meanings of the Z-spiders Z and the X-spiders X correspond to those in Figure 2. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 34 - Figure 12 shows a first step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3. Starting from the first input E in Figure 3, it is checked whether this is connected to the first output A.If the first input E is connected to the first output A, the next step is used, in which the output fan-out gate 22 is constructed for the first input E and subsequently translated into a global entanglement gate 3. If the first input E is not connected to the first output A, as shown in the example in Figure 3, the inputs E are sequentially cycled through until an input E is connected to the first output A. This input E is internally swapped with the first input E, and the swap is stored. What is important about this step is that no gates are added to the quantum parity circuit 1 here; rather, the inputs E are only virtually swapped. The stored swaps are implemented in the last step of the method, where the internal numbering of the qubits at the inputs E of the quantum parity circuit 1 is changed according to the stored swap.In the example of Figure 12, the inputs of qubits qb1 and qb2 were swapped according to the method described above. Figure 13 shows a second step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3, where the output fan-out gate 2 is constructed to the first input E (qb2 in Figure 12). For this purpose, for each connection of the Z-spider Z at the input E of the qubit qb2 to an X-spider X of the output layer AS (see Figure 12), a CNOT gate is added to the output fan-out gate 22, where the qubit at the input qb2 is the control qubit qb. C of the output fan-out gate 22, while the qubits qb1 and qb3 in the example of Figure 12 are target qubits qb T1 , qb T2of the output fan-out gate 22 to the input of the qubit qb2. Thus, the output fan-out gate 22 described in connection with Figure 10 is constructed. The input fan-out gate 2 described in Figure 10 is subsequently represented by single-qubit gates 4 and exactly one global entanglement gate 3, as shown in detail in Figure 13. The global entanglement gate 3 is here a GZZ gate as described in connection with Figure 5. The single-qubit gates 4 are Hadamard gates H and phase gate P, as described in connection with Figure 5. Figure 14 shows a third step of the method for representing the quantum parity circuit 1 for N=5 qubits from Figure 3 by at most N=5 global entanglement gates 3, wherein the first two steps described in connection with Figures 12 and 13 are repeated for each input E.In addition, it is checked whether the output fan-out gate 22 for the respective input E depends on a qubit whose state was changed by a previous output fan-out gate 22. This change of state by the previous output fan-out gate 22 is compensated by the control qubit qb. Cof the previous output fan-out gate 22 is added to each target qubit of the output fan-out gate 22 modulo 2. After performing the above-mentioned steps of the method P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 36 -, the inputs E of the quantum parity circuit 1 are renumbered according to the stored permutations from the first step. Figure 14 shows the representation of the quantum parity circuit from Figure 3 by four non-uniform, global entanglement gates obtained by the method described above. The global entanglement gates are notably non-uniform because they only act on selected qubits. Alternatively, each input fan-out gate can be represented by two uniform global entanglement gates.In step S1 of the method according to the embodiment in Figure 15, starting with the first qubit n=1, it is first checked whether the output state of the nth qubit depends on the input state of the nth qubit. For example, the quantum parity circuit should map the input state |x1, x2,…, xN> to the state |xj1⊕xj2⊕…⊕xjm, xk1⊕xk2⊕…⊕xkm,…, xl1⊕xl2⊕…⊕xlm>. Thus, in step S1, for example, it is checked for the first qubit whether one of the states xj1…xjm corresponds to the state x1. If so, step S2 of the method follows. If not, the output states are cycled through until an output state is present that depends on the input state of the first qubit. This output is internally swapped with the first output, and the swap is stored. This is followed by step S2 of the procedure.In step S2, a fan-out input gate is constructed to the nth output after step S1 such that the qubit at the nth output is the target qubit of the fan-out input gate, and all further qubits on which the output state of the nth qubit depends are control qubits of the fan-out input gate. This fan-out input gate is subsequently represented by a global, non-uniform entanglement gate, in particular a GZZ gate, with additional single-qubit gates. In step S3, it is checked whether an input state of the fan-out input gate just constructed in step S2 has been altered by a preceding fan-out input gate. If so, the fan-out input gate is modified to compensate for the effect of the preceding fan-out input gate.For this purpose, in particular, all control qubits of the previous input fan-out gate are added as additional control qubits to the input fan-out gate constructed in step S2. If not, the input fan-out gate is not modified. Steps S1 to S3 are then repeated for all further qubits from n=2 to n=N. In step S4, the exchanges stored in step S1 are performed virtually. For this purpose, the qubits at the output of the quantum parity circuit are renumbered according to the stored exchanges. This patent application claims priority from German patent application DE 102023122374.7, the disclosure of which is hereby incorporated by reference. The invention is not limited to the exemplary embodiments by the description based on these embodiments. Rather, the invention encompasses any new feature and any combination of features, which in particular includes any combination of features in P2023,0537 WO N 13.August 2024 FOCUS - 2023P66160 WO - 38 - the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.

[0002] P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 39 - List of reference symbols 1 quantum parity circuit 21 input fan-out gate 22 output fan-out gate 3 global entanglement gate 4 single-qubit gate 5 ZX diagram 10 computer program 11 computer-readable storage medium 100 quantum computer 101 ion trap 102 laser 103 detector 104 ion E input ES input layer A output AS output layer H Hadamard gate P phase gate CNOT CNOT gate GZZ global Mølmer-Sørensen gate qb 1…5 qubit qb T , qb T1…T2 Target qubit qb C , qb C1…C4 Control qubit X X-spider Z Z-spider S1…S4 first to fourth step of the procedure

Claims

P2023,0537 WO N 13 August 2024 FOKUS - 2023P66160 WO - 40 - Patent claims 1. Method for representing a quantum parity circuit (1) for N qubits (qb 1…5 ), where the initial states of the qubits (qb 1…5 ) Parities of several input states of the qubits (qb 1…5 ), by at most 2N global entanglement gates (3), comprising the steps of: a) representing the quantum parity circuit (1) by at most N input fan-out gates (21) or output fan-out gates (22); b) converting each of the input fan-out gates (2) or output fan-out gates (22) into single-qubit gates (4) and at most two global entanglement gates (3).

2. Method according to the preceding claim, wherein - the quantum parity circuit (1) has inputs (E) and outputs (A) for each N qubits (qb 1…5 ), and - initial states of the N qubits (qb 1…5) of the quantum parity circuit (1) each represent parities of one or more input states of the N qubits (qb 1…5 ) of the quantum parity circuit (1).

3. Method according to one of the preceding claims, wherein - each input fan-out gate (21) has inputs (E) and outputs (A) for exactly one target qubit (qb T ) and at least one control qubit (qb C1 ,…, qb C4 ), and - the target qubit (qb T ) with each control qubit (qb C1 ,…, qb C4 ) of the input fan-out gate (21) via a CNOT gate. P2023,0537 WO N 13 August 2024 FOKUS - 2023P66160 WO - 41 - 4. Method according to one of the preceding claims, wherein - each output fan-out gate (22) has inputs (E) and outputs (A) for exactly one control qubit (qb C ) and at least one target qubit (qb T1 , qb T2 ), and - the control qubit (qb C ) with each target qubit (qb T1 , qbT2 ) of the output fan-out gate (22) via a CNOT gate.

5. The method according to one of the preceding claims, wherein in step b) at least one of the input fan-out gates (21) or output fan-out gates (22) is converted into single-qubit gates (4) and one non-uniform, generalized Mølmer-Sørensen gate (GZZ).

6. The method according to one of the preceding claims, wherein in step b) at least one of the input fan-out gates (21) or output fan-out gates (22) is converted into single-qubit gates (4) and two uniform, generalized Mølmer-Sørensen gates.

7. Method according to one of the preceding claims, wherein - the quantum parity circuit (1) has a first input fan-out gate (21) and a second input fan-out gate (21) following the first input fan-out gate, and - the second input fan-out gate (21) is modified in order to influence the effect of the first input fan-out gate (21) on a target qubit (qbT ) of the first input fan-out gate (21) if the target qubit (qb T ) of the first input fan-out gate (21) a control qubit (qb C1 ,…, qb C4 ) of the second input fan-out gate (21). P2023,0537 WO N 13 August 2024 FOKUS - 2023P66160 WO - 42 - 8. Method according to the preceding claim, wherein the second input fan-out gate (21) is modified such that all control qubits (qb C1 ,…, qb C4 ) of the first input fan-out gate (21) as further control qubits (qb C1 ,…, qb C4) of the second input fan-out gate (21).

9. Method according to one of the preceding claims, wherein - the quantum parity circuit (1) has a first output fan-out gate (22) and a second output fan-out gate (22) following the first output fan-out gate, and - the second output fan-out gate (22) is modified to modify the effect of the first output fan-out gate (22) on a target qubit (qb T1 , qb T2 ) of the first output fan-out gate (22) if this target qubit (qb T1 , qb T2 ) of the first output fan-out gate (22) a control qubit (qb C ) of the second output fan-out gate (22).

10. The method according to the preceding claim, wherein the second output fan-out gate (22) is modified such that each target qubit (qb T ) of the second output fan-out gate via a corresponding CNOT gate with the control qubit (qb C) of the first output fan-out gate (22).

11. Method according to one of the preceding claims, wherein inputs or outputs of the quantum parity circuit (1) of a first qubit (qb1) and a second qubit (qb3) are virtually swapped when an output state of the first qubit (qb1) differs from the input state of the second qubit P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 43 - (qb3) and does not depend on the input state of the first qubit (qb1).

12. The method according to one of the preceding claims, wherein in step a), the quantum parity circuit (1) is represented by a ZX diagram (5) with an input layer (ES) and an output layer (AS) directly linked thereto, wherein the input layer (ES) has a Z-spider (Z) for each input (E) of the quantum parity circuit (1) and the output layer (AS) has an X-spider (X) for each output (A) of the quantum parity circuit (1). 13.Method according to the preceding claim, wherein - each X-spider (X) of the output layer (AS), which has at least two connections to Z-spiders (Z) of the input layer (ES), is assigned a respective input fan-out gate (21), and - the input fan-out gates (21) each have a CNOT gate for each connection of the corresponding X-spider (X) to one of the Z-spiders (Z) of the input layer (ES).

14. Method according to one of claims 12 or 13, wherein step b) comprises the following substeps: b1) numbering the inputs (E) and outputs (A) of the quantum parity circuit (1) from 1 to N; b2) Executing a loop over all outputs j from 1 to N, with the following substeps: - if the X-spider (X) at output j is not connected to the Z-spider (Z) at input j, swapping the X-spiders (X) of the output layer (AS) so that the X-spider (X) at output j is connected to the Z-spider (Z) at input j and storing the swap;. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 44 - - forming an input fan-out gate (21) by adding a CNOT gate for each connection of the X-spider (X) at output j to a Z-spider (Z) at an input different from j, wherein the qubit at output j is a target qubit (qb T ) of the CNOT gate; - compensating the effect of the input fan-out gate (21) on the target qubit (qb T ) if the target qubit (qb T ) also a control qubit (qb C1 ,…, qb C4) of a subsequent input fan-out gate (21); b3) changing the numbering of the outputs (A) according to the stored exchange.

15. The method according to claim 12, wherein - each Z-spider (Z) of the input layer (ES) that has at least two connections to X-spiders (X) of the output layer (AS) is assigned a respective output fan-out gate (22), and - the output fan-out gates (22) each have a CNOT gate for each connection of the corresponding Z-spider (Z) to one of the X-spiders (X) of the output layer (AS). 16.Method according to one of claims 12 or 15, in which step b) has the following sub-steps: b1) numbering the inputs (E) and outputs (A) of the quantum parity circuit (1) from 1 to N; b2) executing a loop over all inputs j from 1 to N, with the following sub-steps: - if the Z-spider (Z) at input j is not connected to the X-spider (X) at output j, swapping the Z-spiders (Z) of the input layer (ES) so that the Z-spider (Z) at input j is connected to the X-spider (Z) at output j and storing the swap;. P2023,0537 WO N August 13, 2024 FOCUS - 2023P66160 WO - 45 - - Forming an output fan-out gate (22) by adding a CNOT gate for each connection of the Z-spider (Z) at input j to an X-spider (X) at an output different from j, wherein the qubit at input j is a control qubit (qb T) of the CNOT gate; - compensating the effect of the output fan-out gate (22) on a target qubit (qb T1 ,…, qb T4 ), if this target qubit (qb T1 ,…, qb T4 ) also a control qubit (qb C ) of a following output fan-out gate (22); b3) changing the numbering of the inputs (E) according to the stored permutation.

17. A computer program (10) comprising instructions which, when the computer program is executed by a computer, cause the computer to carry out the method according to one of claims 1 to 16.

18. A computer-readable storage medium (11) on which the computer program according to claim 17 is stored.

19. A quantum computer (100) implementing a quantum parity circuit (1) obtained by the method according to one of claims 1 to 16.

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