Quantum box device(s) containing dopants localized in a thin semiconducting layer

Abstract

A method for realizing a quantum device with a quantum island structure, comprising the formation of a stack including a first semiconductor layer based on undoped semiconductor material on which at least one second doped semiconductor layer is grown by epitaxy, the doping being carried out during the epitaxial growth, a first region (212a) belonging to the first semiconductor layer and a second region (214a) belonging to the second semiconductor layer being capable of forming a quantum island. Figure for the abstract: 7G

Description

Title of the invention: QUANTUM BOX(ES) DEVICE(S) CONTAINING DOPANTS LOCALIZED IN A THIN SEMI-CONDUCTIVE LAYER TECHNICAL FIELD AND PREVIOUS ART

[0001] The present application relates to quantum devices with one or more quantum islands and in particular to those implementing the Coulomb blockage phenomenon.

[0002] Quantum islands, also called "quantum dots" or "quantum dots" (in Anglo-Saxon terminology), are semiconductor structures fabricated at the submicron scale in which free electrons are present. In these structures, the free electrons are confined as an electron gas. The islands or quantum dots are coupled to regions forming electron reservoirs, commonly called source and drain regions, via tunnel barriers.

[0003] The principle of electron transport in these structures is essentially based on Coulomb blockade. An electron can only be added to a quantum dot containing another electron if it has enough energy to overcome the Coulomb repulsion between two electrons.

[0004] Quantum boxes (or islands) can be implemented using a heterostructure formed from a stack of two IILV semiconductor materials: GaAs and AlGaAs. In such a structure, free electrons are tightly confined at the interface between the GaAs and the AlGaAs, thus forming an electron gas capable of moving in two dimensions. Confinement in the other two dimensions is then achieved by depleting the electron gas using polarized metallic electrodes.

[0005] Such a type of structure is described for example in the paper by Hanson et al. “Spins in few-electron quantum dots”, Rev. Mod. Phys. 79, 1217, October 2007.

[0006] Other quantum dot structures are described in the document Quantum computation: “Silicon dots back”, Schreiber et al., Nature Nanotechnology Volume:9, Pages: 966-968, 2014. Some implement electron trapping in a Si / SiGe heterostructure while others achieve electron confinement at the interface between a layer of semiconductor material and an A12O3 oxide.

[0007] According to another approach, a structure with a quantum island is implemented in which the electron spin is linked to a phosphorus dopant present in a material semiconductor, in particular purified Si Si2x. Implementing such a structure is problematic because the number of dopants must be small (ideally only one dopant) and their positioning very well controlled.

[0008] The document "Controlled shallow single-ion implantation in Silicon using an active substrate for sub-20-keV ions," by Jamieson et al., Appl. Phys. Lett. 86, 202101 (2005), describes the implementation of a quantum device with a quantum island structure in phosphorus-doped silicon. The dopants are generated by ion implantation. With such a method, the risk of incorrect dopant localization remains.

[0009] The problem arises of an implementation of a new quantum device, improved with regard to the disadvantages given above. Description of the invention

[0010] An object of the present invention is to realize a quantum device having at least one quantum island structure comprising a doped region whose dopants are located in a very precise manner.

[0011] Thus, an embodiment of the present invention relates to a method for making a quantum device comprising the formation of a stack comprising a first semiconductor layer based on undoped semiconductor material on which at least a second doped semiconductor layer is grown by epitaxy, the doping being carried out during the growth by epitaxy, a first region belonging to the first semiconductor layer and a second region belonging to the second semiconductor layer being able to form a quantum island.

[0012] By creating the doped region through simultaneous growth and doping, precise localization of the dopant(s) and a precisely defined interface between the doped and undoped regions of the quantum island are achieved. Furthermore, such epitaxial doping allows for the implementation of a very thin doped semiconductor region, preferably on the order of several nanometers, typically between 2 nm and 5 nm.

[0013] The semiconductor region is advantageously encapsulated on both sides by spacers positioned on the flanks of an electrostatic control grid.

[0014] The quantum islands of the device have a perfectly controlled position and geometry defined by the grid dimension

[0015] After the formation of the doped region, at least one electrostatic control grid of the quantum island can be made on said stacking, the grid being arranged opposite the first region and the second region.

[0016] The formation of said stack may include the growth of a third semiconductor layer based on undoped semiconductor material on the second semiconductor layer.

[0017] Such a layer makes it possible to avoid putting the dopants of the second doped semiconductor layer directly in contact with the gate dielectric (or oxide).

[0018] According to a first possible implementation of the process, after the grid has formed, the following steps are planned:

[0019] - thinning portions of said stacking located on either side of said regions and of the grid, the thinning being carried out so as to reveal lateral edges of said second region, a thickness e' i of the first semiconductor layer being preserved, then

[0020] - formation of insulating spacers on either side of the grid, the spacers covering the lateral edges of said second region. Thus, thinned areas of the first semiconductor layer are created to form tunnel junctions and spacers are formed ensuring lateral isolation of the doped region.

[0021] The stack formation may include the growth of another layer on the first semiconductor layer, based on undoped semiconductor material, prior to the epitaxial growth of the second semiconductor layer. This other layer may be semiconductor and include a sacrificial region. The process may then further include, after grid formation and prior to the formation of the insulating spacers, steps consisting of:

[0022] - remove the sacrificial area so as to form an empty space between said first region and said second region, then

[0023] - fill said empty space with a dielectric material. This empty space may The gap is advantageously filled during the formation of the spacers by the dielectric material used to form the spacers. This creates insulation all around the doped region, preventing both vertical and horizontal diffusion of dopants.

[0024] After the spacers have formed, it is possible to grow source and drain semiconductor regions on thinned areas of the stack.

[0025] According to one embodiment, the process comprises the formation of the stack and, prior to the formation of the gate, the etching of the stack to form a semiconductor block. This semiconductor block may be in the form of a nanowire.

[0026] According to a second possible implementation of the process, prior to the formation of the stack, the following steps can be envisaged:

[0027] - formation on the first semiconductor layer of a sacrificial gate block,

[0028] - formation of a masking around the sacrificial grid block, then

[0029] - removal of the sacrificial grid block so as to form a cavity, the cavity revealing the first region of the first semiconductor layer, the growth of the second semiconductor layer by epitaxy being carried out in the cavity, the electrostatic control grid then being carried out in the cavity on the second semiconductor layer.

[0030] The first semiconductor layer can be a surface layer of a semiconductor-on-insulator type substrate, the surface layer resting on an insulating layer of the substrate.

[0031] Advantageously, the second semiconductor layer with the dopants is positioned between the gate dielectric and the insulating layer of the substrate, for example in the form of a buried oxide.

[0032] The method according to the invention is compatible with a co-integration of the quantum device with one or more transistors in CMOS technology, in particular for which the thickness of semiconductor material of the channel and the gate length are of small dimensions.

[0033] According to another aspect, the present application relates to a quantum effect semiconductor device comprising:

[0034] - at least one quantum island structure formed of a first semi-region conductive, and a second semiconductor region, the first semiconductor region being undoped while the second semiconductor region is doped and located opposite said first semiconductor region,

[0035] - an electrostatic control grid arranged opposite the first semi-region conductive and the second semiconducting region.

[0036] The device may be provided with insulating spacers arranged on either side of the grid and extending against lateral edges of said second region.

[0037] The first region belongs to a first semiconductor layer on which the spacers are arranged, the first layer comprising a first tunnel junction under a first spacer of said spacers and a second tunnel junction under a second spacer among said spacers, the device further comprising a source semiconductor region and a drain semiconductor region on either side of the gate and the spacers.

[0038] According to one possible implementation of the quantum device, the first semiconductor region and the second semiconductor region are arranged one on top of the other, with a region of dielectric material intercalated between the first semiconductor region and the second semiconductor region.

[0039] According to one possible implementation of the quantum device, the first region belongs to a first semiconductor layer, at least one other quantum island structure being formed from another undoped semiconductor region of the first semiconductor layer and another doped semiconductor region disposed on the other undoped semiconductor region, the device comprising another electrostatic control grid arranged opposite said other semiconductor regions.

[0040] The first region may belong to a superficial semiconductor layer of a semiconductor-on-insulator substrate comprising an insulating layer on and in contact with which the superficial layer is disposed and a semiconductor support layer on and in contact with which the insulating layer is disposed, the insulating layer being provided with a material and thickness so as to allow electrostatic coupling between the quantum island and the semiconductor support layer. Brief description of the drawings

[0041] The present invention will be better understood upon reading the description of the exemplary embodiments given, by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0042] - Figures IA and IB illustrate a first example of a quantum device such as implemented according to an embodiment of the present invention, the device having at least one quantum island structure formed in a semiconductor structure having a doped region formed by epitaxy on an undoped region.

[0043] - Figures 2A and 2B illustrate a variant embodiment of the quantum device in which the doped region and the undoped region are separated by an insulating region.

[0044] - Figures 3A and 3B illustrate another embodiment of the device quantum with several quantum islands between a source region and a drain region, the electrostatic control of the islands being ensured by means of several grid electrodes.

[0045] - Figures 4A and 4B illustrate another example of an embodiment of the quantum device with several doped regions completely surrounded by dielectric material.

[0046] - Figures 5A to 5F illustrate a first example of a method for making a quantum device, in which, to implement a quantum island structure, a semiconductor region doped by epitaxial growth is formed with concomitant doping.

[0047] - Figures 6A to 6G illustrate an alternative embodiment in which the region doped semiconductor is formed by growth on a sacrificial semiconductor region.

[0048] - Figures 7A to 7K illustrate an example of the implementation of a quantum device in which a doped region and an electrostatic control grid are formed in a cavity.

[0049] In addition, in the description below, terms which depend on the orientation of the device, such as "superior", "inferior", "lateral", apply considering that the structure is oriented in the manner illustrated in the figures.

[0050] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0051] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0052] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0053] Reference is now made to Figures 1A-1B illustrating a quantum effect device as implemented according to an embodiment of the present invention.

[0054] This device, based on the Coulomb block principle, comprises a semiconductor structure called a quantum island or quantum dot, which is isolated from the rest of the device by two tunneling junctions. The electrostatic energy required for an electron from a first electrode or region, called the "source" 26, to tunnel through the quantum island and reach a second electrode or region, called the "drain" 27, depends on the polarization of a third electrode, called the "gate" 22.

[0055] The device is fabricated on a semiconductor substrate such as a semiconductor-on-insulator substrate having a surface semiconductor layer 12, for example silicon, itself resting on an insulating layer 11 of BOX (for "Buried Oxide"). The island structure comprises a so-called "channel" region 12a of the surface semiconductor layer 12. The channel region 12a extends between a first semiconductor region 26 forming the source region and a second semiconductor region 27 forming the drain region. In this example, the channel region 12a is undoped and covered by and in contact with an N-doped semiconductor region 14a, the doping species typically being phosphorus. In this island structure, the spin of electrons whose state can be modified is linked to the Phosphorus dopant present in the doped 14a semiconductor region.

[0056] The doped semiconductor region 14a is a layer produced by epitaxy in order to define a low and precisely controlled level of doping. In this device, the interface between the doped and undoped regions is precisely defined at the contact zone between the semiconductor regions 12a and 14a, which allows for precise positioning of the free electron(s) generated by the doping.

[0057] The undoped semiconductor region 12a and the N-doped semiconductor region 14a stacked together form a semiconductor block typically in parallelepiped shape with a height or thickness ranging from several nanometers to several tens of nanometers and a width, for example, between 5 nm and 10 nm

[0058] The gate 22 is arranged on this semiconductor block 12a-14a and is separated from it by means of a gate dielectric 19. The gate 22 is thus coupled to the quantum island via a capacitor. To allow for better electrostatic control of the quantum pilot, the gate 22 can be partially enclosing and extend, as illustrated in [Fig. 1B], around several faces of the semiconductor block, and in particular opposite the top face 13' and lateral faces 13" of the semiconductor block 12a-14a.

[0059] Insulating spacers 24 are provided against lateral flanks of the gate 22 in order to isolate the quantum pilot from the source and drain regions 16, 27. The insulating spacers 24 extend against lateral faces of the semiconductor block 14a-12a and, in particular, cover lateral edges of the doped semiconductor region 14a. By "lateral edges" are meant edges extending between a top face and a bottom face of the doped semiconductor region 14a. The top face is the one opposite the gate, while the bottom face is the one opposite the surface layer of the substrate.

[0060] The insulating spacers 24 also extend partially in relation to lateral edges of the undoped semiconductor region 12a.

[0061] The junctions or tunnel barrier are formed in regions 12b and 12c of the semiconductor layer 12 arranged on either side of the channel region 12a and located below the spacers 24. These regions 12b, 12c have a small thickness, in particular less than that of the channel region 12a. Preferably, the thickness of regions 12b, 12c is less than 5 nm.

[0062] An alternative embodiment provides for a thin insulating layer 11, for example less than 25 nm thick, to enable coupling between the channel semiconductor region 12 and the substrate support layer. This allows for biasing of the surface layer 12 from its back face, i.e., the face opposite to that on which the gate rests.

[0063] Another embodiment of the device is shown in Figures 2A-2B and involves interposing an insulating region 25 between the doped semiconductor region 14a and the undoped semiconductor region 12a. The thickness and material of the insulating region 25 are designed so that electrostatic coupling can be established between the doped semiconductor region 14a and the undoped semiconductor region 12a. This insulating region 25, when made of an oxide or nitride, for example, has a thickness that can be, for example, between 2 nm and 10 nm. Thus, the insulating region 25 is positioned against the lower face of the doped semiconductor region 14a and the upper face of the undoped semiconductor region 12a.

[0064] For this variant, the doped semiconductor region 14a is thus entirely surrounded by dielectric material in order to achieve better control of electrons and to prevent diffusion of dopants.

[0065] The examples of quantum effect devices just given provide for an electrostatic control grid of a quantum island. Alternatively, as illustrated in the embodiment shown in Figures 3A-3B or Figures 4A-4B, it is possible to implement a device in which several quantum islands 1a, 1b are arranged in series, each island 1a (resp. 1b) being controllable via a grid electrode 22a (resp. 22b).

[0066] In the embodiment example of Figures 3A-3B, a first block formed of a doped semiconductor region 14a arranged on and in contact with an undoped semiconductor region 12a is connected via a semiconductor portion of the surface layer 12 to a second block formed of a doped semiconductor region 14b arranged on and in contact with an undoped semiconductor region 12b.

[0067] In the embodiment example of Figures 4A-4B, a first quantum island having an arrangement of the type described previously in connection with [Fig.2A]-2B is arranged in series with a second quantum island 1b having an arrangement of the same type.

[0068] A quantum dot or island device as described above can be made to form a quantum bit (qubit) and can be integrated, for example, into a logic circuit adapted to implement quantum information processing or a spintronics circuit, or even into a circuit used in a quantum computer. Such a circuit can be associated with or comprise one or more transistors, in particular transistors made using CMOS technology, and more specifically thin-film transistors made using FDSOI technology. A quantum dot or island device as described above is particularly well-suited to co-integration with a channel-structure transistor formed from one or more nanowires and with a partially enclosing gate of the type commonly called "Tri-Gate" or "Omega-Gate," that is, a gate that extends over three different faces of the nanowire to facilitate channel control.

[0069] An example of a method for realizing a quantum device will now be given in connection with Figures 5A-5F.

[0070] The starting material for this process is a semiconductor-on-insulator substrate comprising a semiconductor support layer 10, for example, made of silicon. The support layer 10 is coated with an insulating layer 11, which is itself coated with a so-called "surface" semiconductor layer 12. In particular, a SOI (Silicon on Insulator) substrate is used in which the surface semiconductor layer 12 is silicon-based. The surface layer The semiconductor layer 12 has a thickness ei that can range from 7 nm to 15 nm, for example, on the order of 10 nm. The insulating layer 11, commonly called the BOX layer (BOX for "Buried Oxide"), is typically SiO2-based and has a thickness e0 that can range from 25 nm to 145 nm, for example, on the order of 145 nm (the thicknesses ei and e0 being dimensions measured parallel to a z-axis of an orthogonal coordinate system [O; x; y; z] shown in [Fig. 5A]). In a case where polarization of the surface layer 12 from the back side, i.e., from the support layer 10, is desired, an insulating layer 11 with a smaller thickness e0 can be used, ranging from 10 to 25 nm, for example, on the order of 15 nm.

[0071] A doped semiconductor layer 14 is formed on the surface layer 12, for example, based on phosphorus-doped Si to obtain Si:P. The doped semiconductor layer 14 is produced by epitaxy using in-situ doping, which allows for precise doping and the creation of a precisely located interface between the undoped and doped areas. This process also allows for the creation of a thin doped layer, for example, less than 5 nm.

[0072] The thickness eEP1 of the doped semiconductor layer 14 can be, for example, on the order of 5 nm.

[0073] Another undoped semiconductor layer 16 can be formed on the doped semiconductor layer 14. This undoped semiconductor layer 16 isolates the doped layer from the gate dielectric layer. This other semiconductor layer 16 can be Si-based and have a thickness e2, for example, on the order of 3 nm.

[0074] Next ([Fig.5B]), the stack of semiconductor layers 12, 14, 16 is etched in order to define one or more distinct blocks 18 of oblong or elongated shape.

[0075] The distinct blocks 18 can in particular be parallelepiped-shaped nanowires. The distinct blocks 18 can be provided with a width WNW or critical dimension of, for example, between 5 nm and 20 nm (the width WNW being a dimension measured parallel to the principal plane of the substrate and in particular to the x-axis of the plane [O; x; y], the principal plane of the substrate being defined as a plane passing through the substrate and parallel to the plane [O; x; y]).

[0076] A grid 22 is then formed on the semiconductor block(s) 18 ([Fig. 5C] showing a cross-sectional view along a cutting plane orthogonal to the cutting plane of [Fig. 5B]). The grid 22 may be partially enveloping and extend over the semiconductor blocks 18 as well as over lateral faces of the grid 22. This grid 22 is typically produced by forming a grid stack and then etching this stack, with the exception of at least one block protected by a mask. The hard 21 mask can be formed from a silicon oxide layer topped with a silicon nitride layer. The gate stack consists of a dielectric layer 19 and a conductive or semiconducting layer 20. Layer 19 can, for example, be based on a high-k dielectric material such as HfO2, while layer 20 is metal-based, such as tungsten, or has a metal thickness. As another example, layer 19 can also be SiO2-based, while layer 20 is a semiconducting material such as polysilicon. The gate is designed with a critical dimension, also called the width WD, which is preferably small, i.e., between 1 nm and 30 nm, for example, on the order of 7 nm. Throughout this description, the critical dimension refers to the dimension of a motif, excluding its thickness. A small grid width WD allows for a high island charging energy.

[0077] Preferably, the doped thickness Tdop of the doped semiconductor layer 14 (Tdop can be equal to eEP1 when the layer 14 is fully doped) with phosphorus (Si:P) is fixed according to the dimensions WNW and WD so as to have one or two dopants in a volume V, such that V= WNW * WD *Tdop.

[0078] The table below lists different examples of doping levels (m3) depending on the dimensions of the doped region 12a and the number of dopants that one wishes to obtain near the island. nb dopant {nmj WB (nm} T»(nmj Box volume (nm^ 5 5 2 sa 1 2.00E+25 2 4.G0E+25 3. 6.OOF+?5 4 8.00E+25 Si channel doping:P nb dopant Wc [nm] ! a >K (mm} Box volume (nmb 7 7 2 93 1 1.02E+23 2. 2.O4E+25 3 3.G6E+25 4 4C3E+J5 Si channel doping: P nb dopant Ws [nm] Wlnmj Box volume jnm'} 20 10 2 200 1 5.00E+24 2. l,GOE+25 3- l,50E+25 4 2,S0E+25 Si channel doping: P nb dopant WKiÿ jnm) Ws [nm} U (nmj Box volume (rf) 10 10 3 300 I 3,33E+24 2 fi,67E+24 3 î,GOE+25 4 Î33E+25 Si Channel Doping

[0079] A partial removal of portions of the semiconductor block(s) 18 that are not protected by the hard mask 21 and that are located on either side of the gate 22 is then carried out ([Fig. 5D]). This partial etching is performed so as to remove portions of the semiconductor layer 16 and the doped semiconductor layer 14 that are not protected by the hard mask 21, at least until the surface semiconductor layer 12 is reached. The etching is preferably extended so as to also remove a thickness of the surface semiconductor layer 12 that is not protected by the hard mask 21.

[0080] It allows for the thinning of certain portions of the semiconductor blocks 18, thereby exposing lateral edges of an etched region 16a from the undoped semiconductor layer 16 and of an etched region 14a from the doped semiconductor layer 14a. By extending the etching to a level below the lower face of the doped region 14a, lateral areas of a region 12a of the undoped surface semiconductor layer located opposite the gate are exposed. In this way, the entire surface of the lateral edges of the doped region 14a can subsequently be encapsulated.

[0081] After etching, a thickness e'i of the surface layer 12 is retained on either side of the gate 22 to allow for re-epitaxial growth. This remaining thickness e'i is, however, kept small to facilitate tunnel junctions. Preferably, the remaining thickness e'i is at least less than 5 nm and can be, for example, on the order of 3 to 5 nm. Etching portions of the stack of semiconductor layers 12, 14, 16 is carried out, for example, by plasma etching.

[0082] Once the surface semiconductor layer 12 has been etched, spacers 24 are formed against the lateral flanks of the gate 22 ([Fig. 5E]). The spacers 24 are made of a dielectric material, for example silicon nitride, silicon dioxide, or SiBCN, and cover the lateral edges of the undoped region 16a, the doped region 14a, and part of the region 12a. The spacers 24 can be formed with a thickness Ts, for example, between 10 nm and 50 nm, for example, on the order of 15 nm. The thickness Ts (dimension measured parallel to the plane [O; x; y]) of the spacers 24 is designed so as to allow the electrons present in the quantum island to be shielded by the source and drain regions intended to be formed subsequently.Thinned regions 12c, 12d of the surface semiconductor layer 12 and located under the spacers 24 are intended to form respectively a first tunnel junction and a second tunnel junction.

[0083] Semiconductor regions 26, 27 are then formed, intended respectively to form a first electron reservoir, also called the source region, and a second electron reservoir, also called the drain region. The semiconductor regions 26, 27 are produced by epitaxial growth on remaining portions of the surface semiconductor layer 12 arranged on either side of the gate 22 and the spacers 24 ([Fig. 5F]).

[0084] In the embodiment described above, a quantum island is formed in a semiconductor structure comprising a doped semiconductor region 14a interposed between an undoped semiconductor region 12a on which a lower face of the doped semiconductor region 14a rests and another undoped semiconductor region 16a resting on a upper face of the semiconductor region A doped conductive region 14a is positioned opposite the upper face. Partial encapsulation of the doped semiconductor region 14a by a dielectric material is achieved. This doped region 14a, confined between two undoped regions 12a and 16a, is, in this example, covered with the dielectric material of the spacers 24 only at its lateral edges. Lateral diffusion of the dopants is prevented.

[0085] Another example of a process, in which a complete encapsulation of the doped semiconductor region 14a of the quantum island is implemented, will now be described in connection with Figures 6A-6G.

[0086] In this embodiment, a semiconductor-on-insulator substrate as described above can be used, and a layer 13 can be formed on the surface semiconductor layer 12, at least one region of which is intended to form a sacrificial zone. The layer 13 is based on a material suitable for selective etching with respect to that of the surface semiconductor layer 12, and which is preferably a semiconductor. The layer 13 can, for example, be made of silicon germanium, particularly when the surface semiconductor layer 12 is made of silicon. The layer 13 can be provided with a thickness e3, for example, between 3 nm and 100 nm, for example, on the order of 3 nm.

[0087] Then, the doped semiconductor layer 14 is formed by epitaxy on the layer 13, one area of ​​which is suitable for forming a sacrificial area ([Fig.6A]).

[0088] Nanowires 28 are then etched into the stack of layers 12, 13, 14 ([Fig.6B]).

[0089] A grid 22 is then produced which extends orthogonally to the direction in which the nanowires 28 extend. The grid 22 is typically partially encapsulating around the nanowires 28 and produced by etching, using a hard mask 21 as an etching mask ([Fig.6C]).

[0090] Then, portions of the stack of semiconductor layers 12, 13, 14 are removed which are not arranged opposite the hard mask 21 and are thus located on either side of the grid 22. The removal is carried out in such a way as to maintain a thickness e'i of the surface layer 12 ([Fig.6D]).

[0091] A selective removal of the sacrificial semiconductor layer 13 is then performed. When this sacrificial layer 13 is made of SiGe, the removal can be carried out, for example, using a wet etching method such as acetic acid etching. Removing the semiconductor layer 13 from beneath the doped semiconductor layer 14 creates an empty space 30. This empty space 30 exposes the lower face of the doped semiconductor region 14a ([Fig. 6E]).

[0092] This empty space 30 is then filled with a dielectric material 25, so as to form a zone of dielectric material against the lower face of the doped semiconductor region 14a. Advantageously, this step is carried out during the formation spacers 24 are placed on either side of the grid 22 ([Fig. 6F]). The dielectric material of the spacers 24 then covers the lateral sides of the grid, the lateral edges of the doped and undoped regions 14a and 12a, and fills the empty space 30 beneath the doped semiconductor region 14a. In this example, the doped semiconductor region 14a is thus completely encapsulated by a dielectric material. This prevents lateral and vertical diffusion of the dopants.

[0093] The semiconductor regions 26, 27 are then grown on the remaining portions of the surface semiconductor layer 12 ([Fig.6G]).

[0094] In the process examples just described, the grid electrode is made before the source and drain regions forming electron reservoirs.

[0095] An alternative embodiment is illustrated in figures 7A-7H.

[0096] In this embodiment, one can start from the same semiconductor-on-insulator substrate as described above and form distinct blocks 38 by etching the surface semiconductor layer 12 ([Fig. 7A]). Prior to defining the semiconductor blocks 38, the surface semiconductor layer 12 can be thinned to maintain a thickness, for example, on the order of 4-5 nm.

[0097] A sacrificial grid 122 is then made on the blocks 38 ([Fig.7B]).

[0098] The sacrificial grid 122 produced by etching a grid stack using a hard mask 121 as an etching mask. The grid stack is, for example, formed of a polysilicon layer on a silicon oxide layer.

[0099] Next, spacers 124 are formed on either side of the sacrificial grid and the hard mask 121 ([Fig.7C]).

[0100] Then, the source and drain semiconductor regions 26, 27 are grown by epitaxy on the portions of the surface semiconductor layer 12 that are not protected by the mask of 121 ([Fig.7D]).

[0101] A layer of dielectric material 128, for example a PMD (pre-metal dielectric) layer of SiO2, is then formed on the source and drain regions 26 and 27 and on the sacrificial grid. A CMP (Chemical Mechanical Planarization), also called planarization, is then performed to bring the top surface of the dielectric material layer 128 to the same level as the top of the hard mask 121. The dielectric material layer 128, together with the spacers 124, forms a protective mask. The hard mask 121 is then exposed and surrounded by this protective mask ([Fig. 7E]).

[0102] Next, the hard mask 121 and the sacrificial grid 122 between the insulating spacers 124 are removed. This step results in the formation of a cavity 135 between the spacers 124 ([Fig. 7F]). The removal of the sacrificial grid 122 can be carried out, for example, by selective etching using an NH40H technique in order to remove the polysilicon and HF are used to remove silicon dioxide. Alternatively, etching can be performed using TMAH.

[0103] Once the sacrificial grid 122 is removed, a region of the surface semiconductor layer 12 is exposed at the bottom of the cavity 135. In this cavity 135, a doped semiconductor region 214a is then formed by epitaxial growth with in situ doping on the exposed region of the surface semiconductor layer. In other words, the semiconductor region 215a is grown while being doped.

[0104] This growth can be preceded by epitaxial growth of an undoped semiconductor layer 212a in order to increase the thickness of undoped semiconductor material in an area located between the spacers 124 ([Fig.7G]).

[0105] Next, a gate dielectric layer 219 and a gate material layer 220 are formed on the doped semiconductor region 214a ([Fig. 7H]). For example, the dielectric layer 219 is made of SiO2 while the material 220 is made of polysilicon. According to another example, the dielectric layer 219 is made of HfO2 while the material 220 is made of W.

[0106] A partial removal of the grid material 220 can then be carried out in order to define a location. This location is then filled with a given material, which can be dielectric and for example based on silicon nitride in order to form a protective plug 225 ([Fig.7I]).

[0107] A selective removal of the dielectric material layer 128 is then carried out. For example, when the protective cap 225 and the spacers 124 are made of silicon nitride and the dielectric material layer 128 is made of silicon oxide, the selective removal is carried out by plasma etching.

[0108] The source and drain semiconductor regions 26, 27 are then revealed again ([Fig.7J]).

[0109] Regions 226, 227 of metal and semiconductor alloy can then be formed on the semiconductor regions 26, 27. In the case where the semiconductor regions 26, 27 are silicon this step is carried out by silicification by depositing a metallic layer, for example nickel, and then carrying out thermal annealing ([Fig.7K]).

[0110] Either of the examples of processes just described has the advantage of allowing co-integration of the quantum device with one or more transistors, the transistor(s) being able to have a planar channel structure or a channel structure formed of one or more nanowires. The process according to the invention is thus particularly well suited to CMOS technologies using a transistor fabrication method commonly referred to as "gate-first" or "gate-last".

[0111] It is therefore possible to carry out certain steps of the quantum device realization process at the same time as those of implementing transistors.

[0112] In particular, the transistor gate can be fabricated simultaneously with that of the quantum device. The transistor spacers can also be formed simultaneously with those of the quantum device. It is also possible to fabricate the transistor's source and drain regions simultaneously with the quantum device's source and drain regions. Similarly, if the transistor is designed with a channel structure in the form of one or more nanowires, this nanowire or these nanowires are fabricated simultaneously with the one or ones intended to form the quantum island structure.

[0113] The process according to the invention is also adapted to co-integration with transistors made on a thin semiconductor film, according to a technology for example of the FDSOI type.

Claims

Demands

1. A quantum-effect semiconductor device comprising: - at least one quantum island structure comprising a doped semiconductor region (14a), - an undoped semiconductor region (12a) opposite said doped semiconductor region (14a), - an electrostatic control grid (22, 22a, 22b) arranged opposite the undoped semiconductor region (12a) and the second doped semiconductor region (14a), - insulating spacers (24a) arranged on either side of the electrostatic control grid (22, 22a, 22b), the insulating spacers (24) extending against lateral edges of the doped semiconductor region (15a), - a first tunnel barrier under one insulating spacer and a second tunnel barrier under another insulating spacer, - a source semiconductor region (26) and a semiconducting drain region (27) on either side of the grid (22, 22a, 22b) and insulating spacers (24),wherein the doped semiconductor region (14a) is disposed on and in contact with the undoped semiconductor region (12a) or with a region (25) of dielectric material interposed between the doped semiconductor region (14a) and the undoped semiconductor region (12a).

2. Device according to claim 1, further comprising between the source semiconductor region and the drain semiconductor region: - another quantum island structure arranged in series with said quantum island and, - another electrostatic control grid (22b) of the other quantum island.

3. A quantum-effect semiconductor device according to claim 1 or 2, wherein the undoped semiconductor region (14a) belongs to a surface semiconductor layer (12) of a semiconductor-on-insulator substrate comprising an insulating layer (11) on and in contact with which the surface layer (12) is disposed and a semiconductor support layer on and in contact with which the insulating layer is arranged, the insulating layer being designed with a material and thickness so as to allow electrostatic coupling between the quantum island and the semiconductor support layer.

4. Device according to any one of claims 1 to 3, wherein the doped semiconductor region (14a) is disposed on and in contact with an undoped semiconductor region (12a) and wherein another undoped semiconductor region (16a) is disposed on and in contact with said doped semiconductor region (12a).

5. A method for making a quantum device according to any one of claims 1 to 3, wherein the doped semiconductor region (14a) is disposed on the undoped semiconductor region (12a), the doped semiconductor region and the doped semiconductor region being made by forming a stack comprising a first semiconductor layer (12) based on undoped semiconductor material on which at least a second doped semiconductor layer (14) is grown by epitaxy, the doping of the second semiconductor layer being carried out during the growth by epitaxy, the method further comprising the formation on said stack and opposite said undoped semiconductor region (12a) and doped semiconductor region: of at least one electrostatic control grid (22) of the quantum island.

6. A method according to claim 5, wherein the formation of said stack comprises the growth of a third semiconductor layer (16) based on undoped semiconductor material on the second semiconductor layer.

7. A method according to any one of claims 5 or 6, comprising after formation of the electrostatic control grid: - thinning portions of said stack located on either side of said doped (14a) and undoped (12a) semiconductor regions and of the grid (22), the thinning being carried out so as to expose lateral edges of said doped semiconductor region (14a), a thickness (e'i) of the first semiconductor layer (12) being retained, then - formation of insulating spacers (24) on either side of the grid (22), the insulating spacers covering the lateral edges of said doped semiconductor region (14a).

8. A method according to claim 7, wherein the stack formation comprises, prior to growth by epitaxy of the second semiconductor layer (14): a growth of another semiconductor layer (13) on the first semiconductor layer (12) based on undoped semiconductor material, a region (13a) of this other semiconductor layer being able to form a sacrificial zone, the process further comprising, after formation of the grid and prior to the formation of the insulating spacers, steps consisting of: - removing the sacrificial zone (13a), so as to form an empty space (30) between said first region (12a) and said second region (14a), then, - during the formation of the spacers (24): filling said empty space with a dielectric material.

9. A method according to any one of claims 7 or 8, comprising after formation of the spacers (24), growth of source and drain semiconductor regions (26, 27) on thinned areas of the stack.

10. Method according to any one of claims 5 to 9, after formation of the stack and prior to the formation of the electrostatic control grid (22): etching of the stack so as to form a semiconductor block (18, 28).

11. A method according to any one of claims 5 or 6, wherein prior to the formation of the stack, the method comprises the steps of: - forming on the first semiconductor layer (12) a sacrificial grid block (122), - forming a masking (124-128) around the sacrificial grid block (122), then - removing the sacrificial grid block (122) so as to form a cavity (135), the cavity revealing the first region (212a) of the first semiconductor layer (12), the growth of the second semiconductor layer (214a) by epitaxy being carried out in the cavity (135), the electrostatic control grid also being carried out in the cavity.

12. A method according to any one of claims 5 to 11, wherein the first semiconductor layer (12) is a surface layer of a semiconductor-on-insulator type substrate, the surface layer resting on an insulating layer (11) of the substrate.

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