Device for generating pilot ramps for emitting devices

Abstract

The invention relates to a scene display device comprising: - a plurality of pixels arranged in a matrix; - a ramp digital-to-analog converter; - a plurality of electronic blocks; the display device being characterized in that the ramp digital-to-analog converter is configured to generate a first voltage ramp and a second voltage ramp having opposite directions of variation and joining at a peak value (Vref2), the peak value (Vref2) being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks and through the plurality of pixels. Figure for the abstract: Fig. 7

Description

Title of the invention: Device for generating control ramps for emitting devices. Technical field

[0001] The invention relates to a device for displaying a scene, particularly in the infrared domain.

[0002] Infrared sensors and cameras are now widely used on a wide range of products for scene detection and analysis, for example for monitoring fire outbreaks.

[0003] For certain applications, it is difficult to work with a scene containing fire or other high-temperature materials. Therefore, it is preferable to use an infrared (IR) screen (display) to test infrared cameras, particularly in cases of fast-moving scene analysis, tracking, or with complex high-temperature scenarios.

[0004] Such an infrared display, illustrated in [Fig. 1], consists of a matrix 2 of pixels 1 which radiate in the infrared wavelength. To achieve this, each pixel has one or more membranes 20 (or emissive devices) and a substrate 21.

[0005] Figure 2 illustrates the structure of a pixel in more detail. The membrane is schematically represented by a resistor 4. The pixel is also equipped with a transistor 5 capable of controlling the membrane 4, which converts a setpoint electrical input voltage Vcons into a control current Imembrane of the resistor 4. The resistor consequently dissipates a corresponding amount of heat, or thermal energy, depending on the amplitude of this input voltage Vcons. This transistor 5 induces a difference between the setpoint electrical input voltage Vcons and the voltage Vmemb across the resistor 4. Advantageously, a control and feedback block 7 adjusts the control voltage Vcmde of the transistor 5 to maintain Vcons = Vmemb. This input voltage Vcons is commonly stored across a memory capacitor (not shown in this figure) located upstream of the control block 7.The descriptions in the remainder of this document are made with the presence of this block 7 which simplifies the explanations; the proposed invention also works without this block with some adaptations known to those skilled in the art.

[0006] Thus, by precisely adjusting the input voltage Vcons of each pixel, and therefore the Imembrane current which passes through the resistor 4, we control the infrared emission of the pixel, and thus define an infrared image with a plurality of pixels.

[0007] Fig. 2 illustrates the principle of voltage control from an NMOS transistor; a person skilled in the art could transpose this mode of operation into PMOS or CMOS technology.

[0008] During the digital / analog conversion phase, a 3-ramp digital / analog converter (or DAC for Digital Analog Converter) scans all the voltage values, and comparator and sampling logic distributes the target voltages at each pixel.

[0009] The ramp digital-to-analog converter generates an analog output by converting a digital input signal via a process that gradually increases or decreases the voltage.

[0010] Figure 3 describes the ramp generation principle. A reference clock (MCK) drives the sequencing of the digital-to-analog converter (DAC), which generates a ramp on its output voltage (Vdac). This ramp generator charges a capacitor (implemented and / or parasitic) to an initial analog value (potential difference) and increments or decrements this value in fixed (or variable, depending on the code: the concept of a range) steps at each MCK clock cycle. This creates a stepped ramp of the Vdac voltage. Simultaneously, a digital counter generates a sequence of binary numbers from a reference value, synchronized to the same reference clock (MCK). The digital value of the counter can be used to trigger the DAC's ramp voltage storage command.

[0011] Figure 4 illustrates an example of an ideal case of a ramp generated by the digital-to-analog converter. The ramp has as its initial value the voltage Vref, which may correspond to the off-bias voltage of the transistors in the display device.

[0012] A digital comparator compares at each step the output of the digital-to-analog converter counter to the desired digital encoding (for example in the form of a binary word) equivalent to the desired setpoint voltage Vcons for the processed pixel.

[0013] If the output of the counter associated with the digital-to-analog converter is lower than the digital setpoint (as in the case of an incremental counter), the voltage storage device Vcons follows the voltage of the Vdac ramp. When the setpoint corresponds to the output value of the DAC counter, the digital-to-analog converter output Vdac is stored (sampled in a capacitor, for example) and will be applied as the Vcons voltage to the addressed pixel.

[0014] Once the value of the digital setpoint is reached, the stored digital-to-analog converter output voltage Vcons remains stable and corresponds to the digital value of the setpoint.

[0015] Thus with the presence of the servo and control block 7 in the pixel, with reference to [Fig.4], when the setpoint voltage is equal to the reference voltage Vref, this is equivalent to a zero potential difference applied to the membrane which is therefore switched off.

[0016] Each digital-to-analog converter addresses all or part of matrix 2 of pixels 1 (directly or sequentially), such as an entire or partial row, or an entire or partial column, or a specific area of ​​matrix 2.

[0017] Figure 5 illustrates a schematic diagram of the routing of the output voltage Vdac from the digital-to-analog converter to the emitting devices of certain pixels of a matrix.

[0018] The output voltage (or current) Vdac of the digital-to-analog converter is routed / propagated to the pixels to be stored there (sampling of the representative voltage or current, more generally of the electrical output quantity of the converter). This is done directly in the pixels or via temporary sampling in sample-and-hold (SH) blocks which store the converter ramp voltage as a function of the digital setpoint.

[0019] In [Fig. 5], the matrix comprises L rows and N columns of pixels, represented by The emissive devices DE; j^. To address pixels of a matrix with precision and linearity, it is necessary to re-amplify the output signal of the converter at the row level, and / or at the column level, and / or at the pixel level. Each propagation chain (for each row and / or for each column) uses copy devices such as feedback amplifiers BL; (row buffers) and / or BQ (column buffers) and / or BPk (pixel buffers), which act as voltage buffers, current buffers, voltage amplifiers, current amplifiers, etc.

[0020] The voltage output from the converter must therefore pass through several electronic blocks 6 of the signal propagation chain, which will be more or less dispersed relative to each other, in addition to the dispersions occurring between the different converters. Furthermore, the emissive elements 20 of the pixels 1 are themselves dispersed, and their own dispersions are added to those of the aforementioned electronic blocks 6. These dispersions modify the voltage supplied to the addressed pixel (Vcons), which modifies the value displayed by the pixel as well as the value emitted by the membrane.

[0021] Thus, as illustrated in [Fig. 6], in a real-world case, and particularly in the presence of a pixel matrix and electronic blocks 6, the setpoint voltages Vcons arrive dispersed across the membranes relative to the converter output voltage Vdac, due to technological variations between the blocks electronics 6. In addition, some pixels undergo technological variations at the level of their emitting device and react differently to instructions.

[0022] Thus, positively dispersed membranes are never switched off, even when the code 0 was initially transmitted to the pixel. This scenario is critical because, to ensure zero current in the membrane in a black scene, the setpoint voltage must be equal to the reference voltage Vref. With positive dispersion, image quality may be inconsistent if a black scene is to be displayed, as some pixels will be at the reference voltage, while others will be at a voltage higher than the reference voltage.

[0023] In negative dispersion, several control codes transmit the same reference value Vref, so there is a loss of information.

[0024] The total dispersion can reach a few millivolts, or even a few tens of millivolts, which is equivalent to many steps of the desired resolution.

[0025] There is therefore a need to provide a scene display device that compensates for the technological dispersions of the propagation chains of the ramp generated by a digital / analog converter. Summary of the invention

[0026] An object of the invention is therefore a display device for a scene comprising a plurality of pixels arranged in a matrix; a ramp digital-to-analog converter configured to traverse a set of values ​​of an output voltage, and to distribute, at the level of each pixel of the matrix, a first reference voltage and an output voltage corresponding to one of the output voltage values, among said set of values; a plurality of electronic blocks configured to propagate the desired output voltage from the ramp digital-to-analog converter to the pixels of the matrix;the ramp digital-to-analog converter being configured to generate a first voltage ramp and a second voltage ramp having opposite directions of variation and joining at a peak value, the peak value being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks and through the plurality of pixels.

[0027] Advantageously, the first ramp is decreasing, and the second ramp is increasing.

[0028] Advantageously, the device includes a correction table configured to correct the voltage at each pixel, the correction being determined so as to obtain a uniform response over all pixels.

[0029] Advantageously, the ramp-type digital-to-analog converter includes at least one switched-capacitor circuit, the switched-capacitor circuit comprising a first input port configured to be connected to the positive terminal of the voltage source, an output port configured to provide a voltage ramp, a transimpedance operational amplifier whose positive input is connected to a reference potential, a second capacitor connected between the negative input of the transimpedance operational amplifier and the output port; at least one switched capacitor circuit, the switched capacitor circuit comprising a first capacitor connected between a first switch and a fourth switch, the first switch being connected to the input port, to a first terminal of the first capacitor and to a first terminal of a second switch, the second switch having a second terminal connected to the reference potential; a third switch connected to a second terminal of the first capacitor and to the reference potential;a fourth switch connected on one side to the negative input of the transimpedance operational amplifier and on the other side to a second terminal of the first capacitor and to the third switch; the first switch, the second switch, the third switch and the fourth switch being respectively controlled by a first control signal, by a second control signal, by a third control signal and by a fourth control signal, timed by the same clock signal, in which the ramp digital-to-analog converter is configured to apply a phase shift between two of the control signals so as to obtain the desired direction of variation of the first voltage ramp and the second voltage ramp.

[0030] Advantageously, the digital-to-analog ramp converter includes a switched-capacitor circuit, in which, to generate the first voltage ramp, the first control signal and the fourth control signal are in phase with each other, and in opposite phase with respect to the second and third control signals; in which, to generate the second voltage ramp, the first and third control signals are in phase with each other, and in opposite phase with respect to the second and fourth control signals.

[0031] Advantageously, the digital-to-analog ramp converter comprises a first switched-capacitor circuit and a second switched-capacitor circuit, the switched-capacitor circuits being sequentially driven by the control signals of the first switched-capacitor circuit and then by the control signals of the second switched-capacitor circuit so as to obtain a first and a second scale of the second voltage ramp.

[0032] Advantageously, the switched-capacitor circuits are further controlled in such a way as to obtain a third range by simultaneously activating the control signals of the first switched-capacitor circuit and the control signals of the second switched-capacitor circuit.

[0033] Advantageously, the device comprises at least one pair of switched-capacitor circuits, the pair of switched-capacitor circuits comprising a first switched-capacitor circuit and a second switched-capacitor circuit, the first input port being common to both switched-capacitor circuits, the control signals of the two switched-capacitor circuits being such that, during an activation period of a first range, when a charge packet is generated in the capacitor of the first switched-capacitor circuit at the same time as the amount of charge created during the previous period in the capacitor of the second switched-capacitor circuit is summed in the second capacitor and is visible at the output terminal, then, during an activation period of a second range, when a charge packet is generated in the capacitor of the second switched-capacitor circuit,At the same time, the amount of charge created during the previous period in the capacitor of the first switched-capacitor circuit is summed in the second capacitor.

[0034] Advantageously, the device comprises at least two pairs of switched-capacitor circuits, each pair of switched-capacitor circuits being configured to be connected on the one hand to its own voltage source, on the other hand to the same transimpedance operational amplifier, the pairs of switched-capacitor circuits being sequentially driven by the control signals of the first pair of switched-capacitor circuits and then by the control signals of the second pair of switched-capacitor circuits so as to obtain a first and a second range of the second voltage ramp; wherein, to generate the first voltage ramp, the first control signal and the fourth control signal are in phase with each other, and in opposite phase with respect to the second and third control signals;in which, to generate the second voltage ramp, the first control signal and the third control signal are in phase with each other, and in opposite phase with respect to the second control signal and the fourth control signal.

[0035] Advantageously, the device is configured to vary the amplitude and / or the sign of the voltage difference supplied by the voltage source, according to the direction of variation of the desired ramp and / or the magnitude of the ramp.

[0036] Advantageously, the ramp-type digital-to-analog converter comprises a first pulsed current source connected to a first switch and a second pulsed current source connected to a second switch, the first pulsed current source and the second pulsed current source being connected in parallel with each other and their terminals mounted in reverse, the digital converter analog ramp being configured to activate either of the current sources sequentially or simultaneously.

[0037] Advantageously, the ramp digital-to-analog converter further includes a third pulsed current source connected to a third switch, in parallel with the second pulsed current source connected to a second switch.

[0038] Advantageously, the pixels are configured to emit in the infrared range.

[0039] The invention also relates to a method of displaying a scene by a plurality of pixels arranged in a matrix, comprising steps consisting of: - traversing, by a ramp digital-to-analog converter, a set of values ​​of an output voltage, and distributing, at the level of each pixel of the matrix, a first reference voltage and an output voltage corresponding to one of the output voltage values, among said set of values; - propagate the desired output voltage through a plurality of electronic blocks, from the ramp digital-to-analog converter to the pixels of the matrix; - generate a first voltage ramp and a second voltage ramp having opposite directions of variation and joining at the level of a peak value, the peak value being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks and through the plurality of pixels. Description of the figures

[0040] Other features, details and advantages of the invention will become apparent from the description made with reference to the accompanying drawings given by way of example.

[0041] Fig. 1, already described, illustrates an example of an infrared display.

[0042] Fig. 2, already described, illustrates in more detail the structure of a pixel.

[0043] Fig. 3, already described, illustrates the principle of supplying a ramp.

[0044] Figure 4, already described, illustrates an example of an ideal case of ramp generated by the digital-to-analog converter.

[0045] Fig. 5, already described, illustrates a schematic diagram of the routing of the output voltage Vdac from the digital-to-analog converter to the emitting devices of certain pixels of a matrix.

[0046] Fig. 6, already described, illustrates a real-world example of a ramp generated by the digital-to-analog converter, propagated through several propagation chains to the different pixels.

[0047] Fig. 7 illustrates curves of the setpoint output voltage applied to the membrane of a pixel with respect to a peak value Vref2.

[0048] Figure 8 illustrates an example of the value displayed as a function of the code sent, in the absence of a correction table (LUT).

[0049] Fig. 9 illustrates an example of ramp correction using a correction table (LUT).

[0050] Fig. 10 illustrates an example of an implementation of the circuit capable of generating two ramps in opposite directions.

[0051] Fig. 11 illustrates timing diagrams of the control signals of the switches of Fig. 10, as well as the corresponding output voltage.

[0052] Fig. 12 illustrates, in detail, a circuit with switched capacitors to generate a two-gauge ramp.

[0053] Figure 13 illustrates a detailed diagram of a circuit capable of generating a first increasing ramp, with a "ping-pong" type input.

[0054] Figure 14 illustrates a detailed diagram of a circuit capable of generating a second decreasing ramp, with a "ping-pong" type input.

[0055] Figure 15 illustrates a block diagram of a circuit capable of generating a first increasing ramp, with a "ping-pong" type input.

[0056] Figure 16 illustrates a block diagram of a circuit capable of generating a first decreasing ramp, with a "ping-pong" type input.

[0057] Fig. 17 illustrates another example of multi-caliber architecture.

[0058] Fig. 18 illustrates timing diagrams of the switching control signals of the switches in Fig. 16.

[0059] Fig. 19 illustrates a synoptic diagram of a multi-caliber solution.

[0060] Figure [Fig. 20] illustrates a curve of the setpoint voltage applied to the membrane of a pixel relative to a second reference value, according to a multi-caliber embodiment.

[0061] Figure [Fig. 21] illustrates an architecture including current sources. Detailed description

[0062] The device according to the invention is described with reference to [Fig.7]. Within the framework of the present invention, the ramp digital-to-analog converter traverses a set of voltage values.

[0063] The idea behind the present invention is to generate a first voltage ramp RI and a second voltage ramp R2 having opposite directions of variation and joining at a peak value Vref2, the peak value Vref2 being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks 6 and the plurality of pixels 1 (in particular during propagation through the pixels).

[0064] The peak voltage Vref2 is determined so that it satisfies the following relationship:

[0065] Vref2 - Vref > VsetMax - Vdac

[0066] Vdac corresponds to the value supplied at the output of the converter, before propagation through the electronic blocks of the propagation chains.

[0067] Vref corresponds to a low supply line called the first reference voltage.

[0068] VconsigneMax corresponds to the largest measured deviation (in positive dispersion) from the ideal setpoint value from the converter. This deviation is determined by physical test / calibration procedures, which turn off all pixels in the matrix. The deviation VconsigneMax corresponds to the number of clock cycles Ncomp required to reach this value, and this number of clock cycles is stored in a register so that it can later be used to generate the negative ramp RL

[0069] For the pixels for which the dispersion is the greatest, at the end of the RI ramp (after Ncomp clock strokes), the voltage Vcons applied at their input corresponds well to the value Vref, which turns off the membrane.

[0070] As illustrated by [Fig.7], in the Ncomp code, the membrane with the greatest dispersion has a zero potential difference between the VconsigneMax voltage and the first reference voltage.

[0071] Thus, the display dynamics are optimized as closely as possible with respect to the dispersions measured in the propagation lines, which guarantees total extinction of all the matrix membranes.

[0072] Using a peak value Vref2 that does not depend on an external voltage source allows for a good correlation between the noise generated by the first reference voltage Vref and that generated by the peak value Vref2.

[0073] Indeed, the voltage precision required for the smallest words (i.e., words corresponding to small numerical values), on the order of a hundred microvolts, necessitates a very low-noise electronic architecture. However, the reference voltage Vref is one of the major noise contributors. Thus, in order to minimize the noise generated, it is advantageous to generate only a single reference voltage (both during ramp generation at the converter output and during the various samplings of the setpoint voltage in the propagation chain, or as a common reference potential for the membranes), with the peak value being generated from the first reference voltage. The noise of the two reference voltages is thus correlated with each other.

[0074] Fig. 7 illustrates a particularly advantageous embodiment, which makes it possible to obtain a peak value Vref2 (i.e. to initialize the ramp R2 to a peak value Vref2).

[0075] To this end, the set of values ​​of the setpoint voltage includes a first ramp RI (offset ramp) which corresponds to the first codes up to Nocmp to be converted by the digital analog ramp converter, and a second ramp R2 which corresponds to the following codes, the directions of variation of the first and second ramp being different.

[0076] According to an embodiment illustrated in [Fig. 7], the first ramp RI is decreasing, and the second ramp R2 is increasing, depending on the decimal value of the codes. The opposite configuration can be considered, namely the first ramp is increasing, and the second ramp is decreasing depending on the topology retained in the pixels.

[0077] Thus, the actual ramp, namely the one corresponding to the setpoint voltage supplied to the pixel, starts at a level lower than the reference voltage Vref. The descent phase thus serves to position the second ramp R2 at a level (peak value Vref2) that allows the setpoint voltage to be equal to the reference voltage Vref when the least significant word is to be transmitted to the pixel.

[0078] Thus the voltage VconsigneMax is at least equal to Vref for the first codes of the R2 ramp, thus ensuring a scene without heating or lighting.

[0079] The membrane receiving the VconsigneMin voltage (maximum negative dispersion) is off for all these first codes (codes over the range Dl, [Fig. 7]). [Fig. 8] illustrates the target value and the uncorrected response (i.e., without a correction table) as a function of the sent codes, in the absence of a display for the first codes. In this figure, codes 1 to 6 (Dl=6 in this example) are incorrect since the pixel remains off. This can be advantageously corrected by a correction table (or LUT for "Look-Up Table"), in order to ensure the code shift necessary to correct the dispersions of the propagation chains. The display corrected with a correction table is illustrated by [Fig. 9].

[0080] Thus, with the use of a correction table, all the dispersions produced and represented in [Fig. 6] are corrected, allowing a uniform response for all pixels close to that of [Fig. 4]. A correction table is generally implemented in display devices, particularly infrared displays. Integrated into a real-time processor external to the matrix, it allows, in any type of display device, the correction of the word to be converted by the converter, taking into account the pixel's transfer function. The correction table often consists of applying a gain correction and a correction offset to the word (i.e. to the numeric value to be converted) which are specific to each pixel.

[0081] The peak voltage Vref2 must be offset from the first reference voltage Vref by at least a value that corresponds to the maximum dispersion encountered on the matrix; however, it is preferable that the offset be exactly equal to a value that corresponds to the maximum dispersion encountered on the matrix, in order to limit the number of words to be corrected in the table.

[0082] Thus, within the scope of the present invention, it is advantageous to use a correction table to correct the codes. In this case, the correction table is configured to correct the voltage at each pixel, the correction being determined so as to obtain a uniform response across all pixels. Therefore, the displayed value for the first codes can be non-zero except for the first code. For subsequent codes, it corrects other variations, such as the gain, for example. Furthermore, even if some codes are "lost" by the correction table, the method according to the invention makes it possible to minimize their number.

[0083] Preferably, the correction table which corrects the value of the word taking into account the transfer function of each pixel can be used, so as not to add bulk to the display device, with an additional correction table.

[0084] Fig. 10 illustrates an embodiment of the switched-capacitor circuit 34 configured to generate the increasing and decreasing ramps.

[0085] It may be noted that, in the present application, the notions of "capacitor" and "capacitance" are considered equivalent, although, strictly speaking, a capacitor refers to a physical component used to store energy in the form of an electric field, and capacitance refers to the physical quantity that measures the ability of a capacitor to store electrical energy.

[0086] The switched-capacitor circuit comprises: - a first input port 23 configured to be connected to the positive terminal of the voltage source 27; - a second input port 24 configured to be connected to a reference potential Vref and to the negative pole of the voltage source 27; - a 25 output port configured to provide a Vdac output voltage; - a transimpedance operational amplifier 7 whose positive input 29 is connected to the reference potential Vref; - a first capacitor Cl connected on one side to a first switch 9, second switch 10, on the other side to a third switch 11 and to a fourth switch 28; - a second capacitor C2 connected between the negative input 30 of the transimpedance operational amplifier 7 and the output port 25; - a first switch 9 connected to the input port 23 and to the first terminal of the first capacitor Cl and to one terminal of the switch 10; - a second switch 10 connected to the first terminal of the first capacitor Cl and to the reference potential Vref; - a third switch 11 connected to the second terminal of the first capacitor Cl and to the reference potential Vref; - a fourth switch 28 connected on one side to the negative input of the transimpedance operational amplifier 7 and on the other side to the second terminal of the first capacitor Cl and to the third switch 11.

[0087] The first switch 9, the second switch 10, the third switch 11 and the fourth switch 28 are respectively controlled by a first control signal <1> A, by a second control signal <bB, par un troisième signal de commande <1> W and by a fourth control signal <1> R, timed by the same clock signal (MCK, [Fig. 11]).

[0088] To generate the first voltage ramp (see [Fig. 7]), the first control signal <bA et le quatrième signal de commande <bR sont en phase entre eux, et en opposition de phase par rapport au deuxième signal de commande <bB et au troisième signal de commande <FW.

[0089] This can be seen on [Fig.1 1], in the "Caliber 0" section of the chronograms.

[0090] To generate the second voltage ramp (see [Fig. 7]), the first signal of order <bA et le troisième signal de commande <FW sont en phase entre eux, et en opposition de phase par rapport au deuxième signal de commande <bB et au quatrième signal de commande <bR.

[0091] This can be seen on [Fig.1 1], in the "Caliber 1" section of the chronograms.

[0092] It may be advantageous to apply an input voltage AVin that is higher for the first ramp (range 0 Offset on [Fig. 1 1]) to that of the second ramp (Range 1), which allows the peak value Vref2 to be reached more quickly. For the second ramp, having a lower input voltage AVin allows for a finer resolution for the converter output.

[0093] In the case where the first control signal <bA et le troisième signal de commande <bw sont en phase, pendant chaque phase active du troisième signal de commande <bw, un paquet de charges Ql=Cl*AVin est constitué aux bornes du premier condensateur Cl. Pendant ces mêmes phases actives du troisième signal de commande <bw, on suppose la présence d’un potentiel mémorisé aux bornes du second capacitor C2 inducing on output port 25 a voltage equal to Vdac=Vref +AV0.

[0094] In the case where the first control signal <1> A and the third control signal <1> W are in phase, during each subsequent active phase of the fourth control signal <1> R, the charge packet Ql=Cl*AVin generated during the previous active phase of the third control signal <1> W is converted across the second capacitor C2 into a potential difference AVadd which sums to the previous value of Vdac, with AVadd=Ql / C2.

[0095] At the end of each active phase of the fourth control signal <1> R, the voltage on output port 25 increases by a potential difference AVadd.

[0096] The new voltage on output port 25 is equal to:

[0097] Vdac = Vref + AV0 + Cl*AVin / C2, in order to generate a growing ramp

[0098] Vdac = Vref + AV0 - Cl*AVin / C2 if the second control signal <e>B and the third control signal <1> W are in phase and opposite phase with the first control signal <1> A is the fourth control signal <1> R.

[0099] The sequence of active phases of the third control signal <1> W and the fourth control signal <1> R generates the summation of the AVadd voltage steps on output port 25 visible in [Fig. 10]. There is always, during the third control signal <bw, l’écriture (la création) d’un paquet de charge Q1 dans le premier condensateur Cl et la lecture (le transfert) de ce paquet de charge (ou la différence de charge créée entre <bw et <bR) dans le second condensateur C2 lors du quatrième signal de commande <bR. Ainsi un cycle de création d’une différence de potentiel AVadd en sortie du DAC nécessite toujours la succession d’une commande <bw suivie d’une commande <bR sur laquelle AVadd sera créée comme sur les figures 11 et 18.

[0100] For each diagram shown, a reset device (not shown in these figures) allows the second capacitor C2 to be discharged before the start of the ramp, setting the voltage on output port 25 to the first reference voltage, Vdac=Vref.

[0101] This reset device can be implemented using a switch placed in parallel with the second capacitor C2 and controlled by a specific signal <bRAZ actif seulement en début de rampe lors de cette réinitialisation.

[0102] Depending on the phases of the first control signal <bAet du deuxième signal de commande <bB utilisées et du signe du potentiel de la source de tension 27 il est possible de générer un échelon de tension AVadd positif ou négatif au niveau de la tension sur le port de sortie 25. Ainsi, selon un mode de réalisation avantageux, le dispositif selon l’invention peut faire varier l’amplitude et / ou le signe de la différence The AVin voltage supplied by the voltage source varies according to the desired ramp direction and / or ramp gauge. The amplitude and / or sign can be controlled by a control unit connected to and / or integrated into the converter.

[0103] For example, in [Fig. 11], the amplitude of the voltage difference AVin can be greater for gauge 2 than for gauge 1, which allows higher rank codes to be reached more quickly.

[0104] Another way to reverse the sign of the ramp would be to invert the input voltage signal of the converter, for a sufficient number of iterations to reach the peak value Vref2. This embodiment thus does not require a phase change between the different control signals.

[0105] It may be noted that the structure of the switched-capacitor circuit used to generate the first ramp can be identical to that used to generate the second ramp in the opposite direction. Only the switching phases of the first control signal <bAet du deuxième signal de commande <bB peuvent changer d’une rampe à l’autre.

[0106] The generation of a first increasing ramp and a second decreasing ramp can be deduced from the embodiment described above, which relates to the generation of a first decreasing ramp and a second increasing ramp.

[0107] Figure 12 illustrates an embodiment of generating a two-range ramp. The range corresponds to the "steepness" of the ramp. The device comprises two switched-capacitor circuits (32, 33) upstream of the transimpedance amplifier 7. Each circuit (32, 33) is driven by separate clock signals, enabling the activation of a first range via the control signals OA, α, β, and β. <bWi géré par le condensateur Cli et la source de tension AVinl, puis un second calibre via les signaux de commande <bA2, <bB2 d>R2 and <bw2 géré par le condensateur Cl2 et la source de tension AVin2 272.

[0108] Advantageously, switched-capacitor circuits can also be controlled to obtain a third range by simultaneously activating the control signals (<bAi, Om dv et C> wl) of the first switched-capacitor circuit and the control signals ( <bA2, <bB2 <bR2 et d>w2) of the second switched-capacitor circuit.

[0109] According to an advantageous embodiment, the device according to the invention may comprise two identical switched-capacitor circuits upstream of the transimpedance amplifier 7 in a "ping-pong" configuration, thus forming a pair of switched-capacitor circuits, the configuration being illustrated by the synoptic diagram [Fig. 15], by the detailed circuit diagram [Fig. 13]. The detailed example in [Fig. 13] is placed in the case of generating the second DAC ramp, the case where, with respect to the layout diagram in [Fig. 10]: - For the capacitor Cn of the switched-capacitor block 38, the first control signal <e>A and the third control signal <1> W are in sync with each other and become <e>Wi, and in opposite phase to the second control signal <e>B and the fourth control signal <1> R and become R <e>Laugh, - For capacitor Ci2 of the switched-capacitor block 37, the first control signal <bA et le troisième signal de commande <FW sont en phase entre eux et deviennent <bw2, et en opposition de phase par rapport au deuxième signal de commande <bB et au quatrième signal de commande <bR et deviennent <bR2,

[0110] Thus when a charge packet Q11 is generated in the capacitor Cn, at the same time the quantity of charge Q12 created during the previous period is summed over the voltage Vdac of the output terminal 25 according to the equations described previously, then inversely over the following period in Ci2 (Q12) and Cn.

[0111] Similarly, [Fig. 14] illustrates the detailed example of the generation of the first DAC ramp in relation to the synoptic diagram of [Fig. 16], which corresponds to a case where, with respect to the layout diagram of [Fig. 10]: - For the capacitor Cn of the switched capacitance block 38, the first control signal <bA et le quatrième signal de commande <bR sont en phase entre eux et deviennent <bRi, et en opposition de phase par rapport au deuxième signal de commande <bB et troisième signal de commande <FW et deviennent <bW|. - For capacitor Ci2 of switched capacitance block 37, the first control signal <bA et le quatrième signal de commande <bR sont en phase entre eux et deviennent <bR2, et en opposition de phase par rapport au deuxième signal de commande <bB et troisième signal de commande <FW et deviennent <bw2.

[0112] The advantage of the "ping-pong" architecture is that it leaves a full period for the transimpedance amplifier to manage the transfer of charges from alternately capacitor C11 and capacitor C12. This results in the main clock generating all the MCK driving phases of [Fig. 18] operating at a frequency divided by 2 compared to the MCK of the timing diagram of [Fig. 11].

[0113] For a multi-range architecture (example on two ranges in [Fig. 17]), it is possible to share the second capacitor C2 (as well as its reset device, not shown) and the transimpedance amplifier whose output voltage is 25 represents the summation of the voltage steps generated either by the "ping-pong" block associated with caliber 1 when the clocks <e>X i are active or associated with the "ping-pong" block of caliber 2 when the clocks <b x 2 actives en même temps), induisant des échelons de tension avadd liés aux deux blocs « ping-pong ».

[0114] le dispositif comprend ainsi paires (45, 46) circuits à capacités commutées, chaque paire commutées étant configurée pour être connectée d’une part une source (47, 48) qui lui est propre, d’autre au amplificateur opérationnel transimpédance 7.

[0115] chronogramme la [fig. 18] illustre l’exemple pilotage architecture génération rampe suivant calibres partir » représentée sur le synoptique 17].

[0116] dans [fig.18], les signaux d’horloges orm, ow2-i, ®r2 i, correspondent respectivement d’horloge commandent commutation l’ensemble commutateurs 9, 12, 15, 10, 13, 16, 17 et 14 du calibre 1.

[0117] les c>Wi_2, dLi 2, C>w2 2, ^^ correspond respectively to the clock signals which control the switching of all switches 9, 12, 15, 10, 13, 16, 17 and 14 of caliber 2.

[0118] In [Fig.18], the set of clock signals as represented allows to chain steps of amplitude specific to caliber 1 (adjusted via the values ​​Cil / C12 of the block of caliber 1 and AVhicali) then steps of amplitude specific to caliber 2 (adjusted via the values ​​Cl 1 / C12 of the block of caliber 2 and AVinCAL2) then again steps of caliber 1 before ending with steps of caliber 2.

[0119] To generate a voltage step at the output of the integrator, there must be a sequence of activation of a write control signal <bw suivi de l’activation d’un signal de commande de lecture <PR.

[0120] At the beginning and end of the caliber, the clocks <bW| et <PR2 sont légèrement différentes entre-elles, et les horloges <PW2 et <PRi sont identiques. Ceci s’explique car les échelons de tensions sont générés sur des horloges (à condition que la capacité d’entrée ait été pré-chargée pendant C> wi / C>w2).

[0121] The following numerical example illustrates the small impact of adding the first generation ramp of the second reference value (or offset) on the number of periods to be generated to obtain the same ramp dynamics.

[0122] The following table describes, for a multi-range display device according to the prior art, the total dynamic range of each range, the height of each step, the number of periods covered by each range (i.e. the number of words), the total capacity (taking into account the parallel connection of circuits with switched capacities), and the AVinDAC input voltage, for a display device that does not generate an offset ramp (multi-range display device according to the prior art) using a capacitor C2=150pF: Caliber 1 Caliber 2 Caliber 3 Dynamic (V) 0.5 1 2 Steps (pV) 200 400 1000 Nx: Number of periods 2500 2500 2000 Clx (fF) 75 75 150 AVinDAC (V) 0.4 0.8 1

[0123] For the three ranges, the addressed voltage dynamics with their increment steps are respectively 0.5 V / 200 pV, 1 V / 400 pV and 2 V / 1000 pV.

[0124] The three calibers require, due to their steps and dynamics, 7000 clock periods (2500 + 2500 + 2000) therefore addressable on 13 bits (8192 possible values).

[0125] The input stages of the switched-capacitor circuits are sized with capacitances Cl1 and C12 of 75 fF, with an input adjustment range of 1 V under 6 bits, which allows them to adjust their value to 15.6 mV. At the converter output, this results in adjustable steps with a step size of 7.8 pV with a C2 = 150 pF.

[0126] For setting “3”, it is possible to connect in parallel two switched capacitance circuits of 75 fF each, which is equivalent to an equivalent capacitance of 150 fF. This results in adjustable steps with a step size of 15.6 pV at the output of the converter.

[0127] Figures 19 and 20 illustrate the use of the display device according to the invention with three different gauges, in addition to the first offset ramp.

[0128] The following table, in conjunction with Figures 19 and 20, describes the total dynamic range of each scale, the height of each step, the number of periods covered by each scale, the total capacitance, and the input voltage AVinDAC. The matrix is ​​powered at a dynamic range of 3.58V with the following scales: Caliber 0 Offset Caliber 1 Caliber 2 Caliber 3 Dynamic (V) 0.08 0.58 1 2 Steps (pV) 1000 200 400 1000 Nx: Number of periods 80 2900 2500 2000 Clx (fF) 150 75 75 150 AVinDAC (V) 1 0.4 0.8 1

[0129] For the "O / offset" range, which generates the peak value Vref2, it is advantageous to use two switched-capacitor circuits in parallel, each with a capacitance Cioffset = 75 fF (whether with a "ping-pong" or "non-ping-pong" architecture), which is equivalent to a total capacitance of 150 fF. This allows the same converter to be reused as for the other ranges. For this "O / offset" range, this translates into adjustable 15.6 pV steps ready at the output of the ramp converter.

[0130] To compensate for the 80 mV of dispersions with steps of 1000 pV, only eighty clock periods are needed, which is about 1.1% more periods than the 7000 required to generate the ramp.

[0131] These 80 mV generated by the "0" setting must also be taken into account in the dynamics of the "1" setting which therefore goes from 500 mV to 580 mV and therefore requires 400 more periods.

[0132] Calibrates 1 and 2 (cf. [Fig. 17]) can be generated with a single capacitance Cl (= Ci-caii = Ci cai2 = 75 fF), the input voltage of the second caliber AVinDAc 2 being in this case greater than the input voltage of the first caliber AVinDAC i.

[0133] The 3rd gauge (cf. [Fig.20]) can be generated by connecting in parallel two switched capacitance circuits (with a "ping-pong" or "non-ping-pong" architecture) so as to double the capacitance Cl (Ci caB = 75 fF), and by providing an input voltage AVinl)ACÎ also greater than or equal to those of the first two gauges.

[0134] The display device according to the invention, with the numerical values ​​of this example, requires a total of 7480 periods, therefore 480 additional periods, which represents 6.4% more periods than without compensation.

[0135] Thus, the above-mentioned numerical example illustrates the fact that the generation of a second reference value Vref2 from the first reference value Vref has a very limited impact on the number of periods to be generated, while allowing the pixels to be completely turned off, despite the dispersions that may propagate in the pixel matrix.

[0136] Thus, if we consider that the first ramp corresponds to a set of the first N codes to be converted from among the total M codes to be converted, and the second ramp corresponds to the following codes, it may be advantageous to have an N / M ratio between 0.2 and 0.5%, preferably between 0.3 and 0.4%. This range of values ​​makes it possible to obtain pixels that are completely off across the entire matrix, with a reduced impact (6.4%) on the number of periods to be generated for the voltage ramps.

[0137] Fig. 21 illustrates an embodiment of implementing a converter capable of generating ramps with opposite growth directions, using a current source.

[0138] To this end, the ramp digital-to-analog converter 3 comprises a first pulsed current source 18 connected in series with a first switch 20 and a second pulsed current source 19 connected in series with a second switch 21. The first pulsed current source 18 and the second pulsed current source 19 are connected in parallel with each other and their terminals are reverse-connected. The positive terminal of the first pulsed current source 18 is connected to the bias voltage Vref and to the negative terminal of the second pulsed current source 19.

[0139] To obtain a multi-range ramp, as previously described for a voltage ramp with a switched-capacitor circuit, at least a third pulsed current source 26 is connected in parallel, with the same arrangement as for the second pulsed current source 19. Similarly, a fourth pulsed current source 28 is connected in parallel.

[0140] The negative terminal of the first pulsed current source 18 and the positive terminals of other pulsed current sources (19, 26, 40) are selectively directly connected to the positive terminal of the trans-impedance operational amplifier 7. The negative terminal of the trans-impedance operational amplifier 7 is connected to the output terminal 25 which provides the multi-range ramp.

[0141] The ramp 3 digital-to-analog converter is thus configured to sequentially activate one or the other of the current sources (18 then 19 / 26 / 40).

[0142] This solution also requires a master clock needed to "count" the time in order to drive the Vdac voltage samplers.

[0143] Initially, the ramp is initialized via switch 31 by activating the reset signal Oraz; the voltage across the integration capacitor Cint is zero.

[0144] Closing the first switch 20 by activating the signal causes the current 10 from the first pulsed current source 18 to integrate into the integration capacitor Cint with a voltage ramp slope dVout'DAC / dt = -I0 / Cint, which corresponds to the first RI ramp,

[0145] The closing of the second switch 21 then follows, activating the signal ^CalV cc'a induces that the current II from the second pulsed current source 19 integrates into the integration capacitor Cint with a slope of the voltage ramp dVout'DAc / dt = Il / Cint, which corresponds to the first scale of the second ramp R2.

[0146] The same applies successively to currents 12 and 13 via the control of switches 41 and 29 via the signals ct ^Ca / 3-

[0147] Two current sources (or more) can also be activated simultaneously such as current sources 12 and 13 via the simultaneous control of switches 41 and 29 via the signals ^cal'2 ct ^CaZ3' inducing a slope of the voltage ramp dVout'DAc / dt = (I2+I3) / Cint.

[0148] Assuming that the integration capacitance Cint is 100 pF and the durations of each step of the ramp are 100 ns, the gauges can be parameterized as follows: Caliber 0 Offset Caliber 1 Caliber 2 Caliber 3 Dynamic Range (V) 0.08 0.58 1 2 Number of periods 80 2900 2500 2000 Caliber duration (ps) 8 290 250 200 Caliber (pA) 1.00 0.20 0.40 1.00

[0149] The operation of the different validation clocks for the different current sources can be as follows:

[0150] The OcalO clock which validates the current source 18 with an intensity 10=1.0 pA is valid for 8 ps;

[0151] Then, the Ocall clock which validates the current source 19 with an intensity 11=0.2 pA is valid for 290 ps;

[0152] Then, the clock cal2 which validates the current source 26 with an intensity 12=0.4 pA is valid for 250 ps;

[0153] Then, the clock cal3 which validates the current source 28 with an intensity 13=1.0 pA is valid for 200ps.

[0154] It is also possible to activate several current sources in parallel, for example in the following manner, assuming:

[0155] The current source 18 with an intensity 10=1,OpA is activated from 0 to 8 ps.

[0156] Then the current source 19 with an intensity II = 0.2pA is activated from 8 ps to 748 ps. This generates caliber 1 of 0.2 pA via II from 8 to 298ps.

[0157] The current source 26 with an intensity 12 = 0.2pA is activated from 298 ps to 748 ps. This generates the 2-gauge current of 0.4 pA via the sources 19 and 26 from 298 to 548 ps.

[0158] The current source 40 with an intensity 13 = 0.6 pA is activated from 548 ps to 748 ps. This generates caliber 3 of 1.0 pA via sources 19, 26 and 40 from 548 to 748 ps. ​< / e> < / e> < / e> < / e> < / e> < / e>

Claims

Demands

1. A scene display device comprising: - a plurality of pixels (1) arranged in a matrix (2); - a ramp digital-to-analog converter (3) configured to traverse a set of output voltage values, and to distribute, at each pixel (1) of the matrix (2), a first reference voltage (Vref) and an output voltage (VoutDAC) corresponding to one of the output voltage values, from said set of values; - a plurality of electronic blocks (6) configured to propagate the desired output voltage from the ramp digital-to-analog converter (3) to the pixels (1) of the matrix (2);the display device being characterized in that the ramp digital-to-analog converter (3) is configured to generate a first voltage ramp and a second voltage ramp having opposite directions of variation and joining at the level of a peak value (Vref2), the peak value (Vref2) being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks (6) and through the plurality of pixels (1).

2. Device according to claim 1, wherein the first ramp is decreasing, and the second ramp is increasing.

3. 3. Device according to any one of the preceding claims, comprising a correction table (LUT) configured to correct the voltage at each pixel, the correction being determined so as to obtain a uniform response over all pixels.

4. 4. Device according to any one of the preceding claims, the ramp digital-to-analog converter (3) comprising at least one switched-capacitor circuit, the switched-capacitor circuit comprising: - a first input port (23, 232) configured to be connected to the positive terminal of the voltage source (27); - an output port (25) configured to provide a voltage ramp; - a transimpedance operational amplifier (7) having its positive input (29) connected to a reference potential; - a second capacitor (C2) connected between the negative input (30) of the transimpedance operational amplifier (7) and the output port (25); - at least one switched capacitance circuit (32, 33, 34, 37, 38), the switched capacitance circuit (32, 33, 34, 37, 38) comprising: — a first capacitor (Cl, Cli, Cl2) connected between a first switch (9, 92, 13) and a fourth switch (28, 282, 10, 14), the first switch (9, 92, 13) being connected to the input port (23, 232, 35), to a first terminal of the first capacitor (Cl, Ch, Cl2) and to a first terminal of a second switch (10, 102, 12, 16), the second switch (10, 102, 12, 16) having a second terminal connected to the reference potential (Vref); — a third switch (11, 112, 15, 17) connected to a second terminal of the first capacitor (Cl, Cl 1, Cl2) and to the reference potential (Vref);— a fourth switch (28, 282, 10, 14) connected on one side to the negative input (30) of the transimpedance operational amplifier (7) and on the other side to a second terminal of the first capacitor (Cl, Cl1, Cl2) and to the third switch (11, 112, 15, 17); the first switch (9), the second switch (10), the third switch (11) and the fourth switch (28) being respectively controlled by a first control signal (9>A), by a second control signal (9V), by a third control signal (9¼) and by a fourth control signal ( <bR), cadencés par un même signal d’horloge, dans lequel le convertisseur numérique analogique à rampe (3) est configuré pour appliquer un déphasage entre deux des signaux de commande de façon à obtenir le sens de variation souhaité de la première rampe de tension et de la deuxième rampe de tension.;

5. 5. Device according to the preceding claim, wherein the ramp-to-analog digital converter (3) comprises a switched-capacitor circuit (34), and wherein, to generate the first voltage ramp, the first control signal ( <PA) et le quatrième signal de commande (<PR) sont en phase entre eux, et en opposition de phase par rapport au deuxième signal de commande (<DB) et au troisième signal de commande (9> w); in which, to generate the second voltage ramp, the first control signal ( <1> A) and the third control signal (Ow) are in phase with each other, and in opposite phase with respect to the second control signal ( <hB) et au quatrième signal de commande (<hR).

6. 6. Device according to claim 4, wherein the ramp digital-to-analog converter (3) comprises a first switched-capacitor circuit (32) and a second switched-capacitor circuit (33), the switched-capacitor circuits being sequentially driven by the control signals ( <hAi, <hHi ^ri et 0>wl) of the first switched-capacitor circuit and then by the control signals (<hA2, d> B2 d>R2 and <hw2) du deuxième circuit à capacités commutées de façon à obtenir un premier calibre et un deuxième calibre de la deuxième rampe de tension.

7. Device according to claim 6, wherein the switched-capacitor circuits are further controlled to obtain a third range by simultaneously activating the control signals ( <bAi, d’si Ori et <bWi) du premier circuit à capacités commutées et les signaux de commande (<bA2, <bB2 <bR2 et <hw2) du deuxième circuit à capacités commutées.

8. 8. A device according to claim 4 comprising at least one pair of switched-capacitor circuits, the pair of switched-capacitor circuits comprising a first switched-capacitor circuit (37) and a second switched-capacitor circuit (38), the first input port (35) being common to both switched-capacitor circuits (37, 38), the control signals of the two switched-capacitor circuits (37, 38) being such that, during an activation period of a first range, when a charge packet (Q11) is generated in the capacitor (C1) of the first switched-capacitor circuit (37), at the same time the amount of charge (Q12) created during the previous period in the capacitor (C2) of the second switched-capacitor circuit (38) is summed in the second capacitor (C2) and is visible at the output terminal (25), then, during an activation period of a second range,when a charge packet (Q12) is generated in the capacitor (C12) of the second switched-capacitor circuit (38), at the same time the amount of charge (Q11) created during the period, previous in the capacitor (Cl 1) of the first switched capacitance circuit (37) is summed in the second capacitor (C2).

9. 9. Device according to claim 8, comprising at least two pairs (45, 46) of switched-capacitor circuits, each pair of switched-capacitor circuits being configured to be connected on the one hand to its own voltage source (47, 48), and on the other hand to the same transimpedance operational amplifier (7), the pairs of switched-capacitor circuits being sequentially driven by the control signals (0wm, ,3>r2-i) of the first pair of switched-capacitor circuits and then by the control signals ( <hwi_2, ^1-2,^2 2,^R2 2) de la deuxième paire de circuit à capacités commutées de façon à obtenir un premier calibre et un deuxième calibre de la deuxième rampe de tension dans lequel, pour générer la première rampe de tension, le premier signal de commande (OwH) et le quatrième signal de commande ( <1> R 2-i) are in phase with each other,and in opposite phase to the second control signal (Orm) and the third control signal ( <1> W 24); in which, to generate the second voltage ramp, the first control signal ( <1> wm) and the third control signal (¢^ 2) are in phase with each other, and in opposite phase with respect to the second control signal (, <bri-2) et au quatrième signal de commande (<hw2 2).

10. 10. Device according to any one of the preceding claims, configured to vary the amplitude and / or the sign of the voltage difference (AVin) supplied by the voltage source, according to the desired direction of variation of the ramp and / or the magnitude of the ramp.

11. 11. Device according to any one of claims 1 to 3, wherein the ramp digital-to-analog converter (3) comprises a first pulsed current source (18) connected to a first switch (20) and a second pulsed current source (19) connected to a second switch (21), the first pulsed current source (18) and the second pulsed current source (19) being connected in parallel with each other and their terminals mounted in reverse, the ramp digital-to-analog converter (3) being configured to activate either of the current sources (18, 19) sequentially or simultaneously.

12. 12. Device according to claim 11, wherein the ramp digital-to-analog converter (3) further comprises a third pulsed current source (26) connected to a third switch (41), in parallel with the second pulsed current source (19) connected to a second switch (21).

13. 13. Device according to any one of the preceding claims, wherein the pixels are configured to emit in the infrared range.

14. 14. Method of displaying a scene by a plurality of pixels (1) arranged in a matrix (2), comprising steps of: - traversing, by a ramp digital-to-analog converter (3), a set of values ​​of an output voltage, and distributing, at the level of each pixel (1) of the matrix (2), a first reference voltage (Vref) and an output voltage (VoutDAC) corresponding to one of the output voltage values, from said set of values; - propagating the desired output voltage by a plurality of electronic blocks (6), from the ramp digital-to-analog converter (3) to the pixels (1) of the matrix (2);- generate a first voltage ramp and a second voltage ramp having opposite directions of variation and joining at the level of a peak value (Vref2), the peak value (Vref2) being determined as a function of the maximum dispersion encountered on the matrix during the propagation of the output voltage through the plurality of electronic blocks (6) and through the plurality of pixels (1).;

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