Silicon brain

Abstract

The standard for calculating memory capacity in modern computing is the bit, and the number of transistors (elements) that make up a node, i.e., the number of bits, is also the unit of modern information communication volume. In contrast, the human brain is made up of neural circuits, and human memory capacity is not based on the number of neural circuits (number of nodes). nerves Circuit complexity far exceeds bit capacity, and modern AI that attempts to replicate the human brain through bit-based computing is inherently wasteful because it handles information in a fundamentally different way. Moreover, bit-based computing is always at the limit of integration. The present invention provides a bit-independent information storage system using a three-dimensional silicon circuit network. [Solution] By switching the electrical connections of non-volatile memory cells distributed in a three-dimensional array, Reproducing the information processing mechanism of the human brain.

Description

[Technical Field]

[0001] The present invention relates to a technique for implementing a 3D neural network on a silicon chip. [Background technology]

[0002] In conventional semiconductor-based computing methods, a storage device (memory) and an arithmetic processing unit (CPU, etc.) work together. A storage device (semiconductor memory) consists of a collection (array, cell array, memory cell array, or storage element array) of storage elements called memory cells (memory elements, bit cells, or simply cells). Each element consists of at least a source, a drain, and a gate (or control gate). The source and drain are respectively , source line, and, The gates can be connected to bit lines, and the gates can be connected to word lines. This connection is generally made through contacts (terminals), such as word line contacts (terminals) or bit line contacts (terminals). When a set of such elements is distributed on a two-dimensional plane, each memory element is accessed by word lines (WL) and bit lines (BL) arranged in the X and Y directions, which are perpendicular to each other on the two-dimensional plane. For example, the address of a memory element arranged at the intersection of the Ath word line and the Bth bit line is (A, B). This is called the address of the memory element. However, A is specifically called the address on the X axis (X address), and B is specifically called the address on the Y axis (Y address).

[0003] For a long time, the mainstream of semiconductor memory technology development was to integrate as many memory elements as possible on the surface of a silicon wafer using semiconductor manufacturing processes in accordance with Moore's Law (see Non-Patent Document 1). However, in recent years (since 2015), it has become difficult to increase the integration density of memory elements on a two-dimensional plane, and the method of placing memory elements in three-dimensional space has become mainstream, even at the mass-produced level. In this case, addresses can be represented as (A, B, C), where C is the address on the Z axis (Z address), which is perpendicular to the XY plane.

[0004] However, whether it is two-dimensional or three-dimensional, the current method of recording information in semiconductor memory devices is based on memory elements, and when each memory element (cell) has two values, 0 and 1, it is said that one cell has a memory capacity (amount of information that can be stored) of 1 bit. If there are two such memory elements, the memory capacity is said to be 2 bits. In this case, there are four possible combinations of 0 and 1: (00), (01), (10), and (11). In this case, the number can be calculated by raising to the power of 2. If a cell array is made up of N memory elements, the memory capacity of the cell array is N bits. In this case, the number can be calculated by raising to the power of 2N.

[0005] Therefore, the amount of information (number of bits) of a conventional semiconductor device is expressed as a logarithm with 2 as the low.

[0006] In contrast, the human brain is not made up of memory elements. If there were something that corresponds to a memory element, it would be the cell body that makes up part of the nerve cell, but this cell body does not store information such as 0 or 1.

[0007] As shown simply in Figure 1, a nerve cell (neuron) generally consists of three parts: a cell body, several (e.g., several tens) dendrites, and an axon. The cell body can receive external input from these several dendrites. The axon generally extends longer than the dendrites, and its tip further branches into several tens to several hundred branches. The tip of these branched axons is called the axon terminal (or axon termination).

[0008] As shown simply in Figure 2, the axon terminal approaches and forms a junction with one of the dendrites of another cell body, called a synapse.

[0009] There are now two cell bodies, cell A and cell B. Cell body A receives multiple external inputs x(n) through multiple dendrites (n), where n is an integer between 1 and N. Cell body A assigns a weight W(n) to each input x(n). The signal summed according to these weights is called SUM. SUM is transferred to one of the axon terminals via the axon. When SUM exceeds a certain threshold (threshold of exitation), the neuron generates an action potential, driving synapsis and transmitting neurotransmitters from cell body A to cell body B.

[0010] This threshold changes as signals are transmitted repeatedly. In other words, by repeatedly learning from experience, synaptic connections become stronger, break, or are replaced. The strengthening of synaptic connections can be explained by a lowering of the threshold. The breakage of synapses can be explained by an increase in the threshold. The replacement of synapses can be explained by a lowering of the threshold of other synapses.

[0011] This is modeled as shown in Figure 3. When neurotransmitters are transmitted, the output y is set to 1 (y=1), and when not, it is set to y=0. This model is called a perceptron, and is widely used in deep learning and machine learning.

[0012] There are two main ways to implement a perceptron on a computer.

[0013] In the traditional method, the input x(n), weight w(n), SUM, threshold, and output y are all represented as bits, i.e., a computer program.

[0014] The problem with this method is that it places a heavy load on computers. There is a greater need than ever before to improve calculation speeds and reduce power consumption. Deep learning and machine learning require the instantaneous processing of huge amounts of data, and if calculations that place a heavy load were to flood the world, the power consumption of data centers would increase explosively, making it difficult to operate them practically. Furthermore, there are growing concerns that this could accelerate global warming (see Non-Patent Document 2).

[0015] The main cause of the limit on computing speed is excessive data communication between the processor and main memory. Although processors can still be made faster, the communication speed of the data bus between the processor and main memory has reached a ceiling. This is called the von Neumann bottleneck (or memory bus problem).

[0016] The main reason for this increase in power consumption is that the main memory devices currently in use are volatile memory devices called dynamic random access memory (DRAM), which means that the power consumed by refreshing recorded data is becoming non-negligible.

[0017] A recent trend is to replicate the perceptron directly on a semiconductor chip in order to avoid the von Neumann bottleneck and simultaneously reduce power consumption. However, the neural networks of the human brain are generally designed to generate synapses between two unspecified pairs of neurons. While current semiconductor technology makes it possible to place perceptrons at precisely specified addresses on a two-dimensional plane or in three-dimensional space, it is not easy to replicate synapses between arbitrary pairs of neurons or to freely reassign them according to learning.

[0018] As mentioned above, information is recorded in bits in existing memory architectures, whereas in the human brain, information is stored in synapses, i.e., in the neural network. informationIn other words, reproducing deep learning or machine learning on a program written in bits means that a whole program has already been written to model one unit (perceptron) of a neural network. This results in a significant loss of information processing.

[0019] For example, suppose a perceptron program can be written in about 1,000 lines. If each line contains 80 bytes (1 byte is 8 bits), then 80 kilobytes of information is required to recreate a perceptron as a computer program. Even if the program could be compiled and compressed to one-tenth the size, it would still only be 8 kilobytes. If this could be recreated in 100 bits on a semiconductor chip, then the computer program would waste 640 times the amount of information per perceptron.

[0020] The number of neurons in the entire human brain (cerebrum and cerebellum) is said to be approximately 86 billion. If we assume that the number of neurons and the number of perceptrons are roughly the same, then in order to achieve artificial intelligence with human-level capabilities, the computer would need to process a huge amount of unnecessary information.

[0021] Deep learning and machine learning are not yet artificial intelligence that can compare to the human brain, and as artificial intelligence develops, the amount of information that computers are forced to process unnecessarily is expected to increase.

[0022] Next, we compare the amount of information in the network with the amount of information in bits.

[0023] The study of networks is called graph theory in mathematics. A network is generally a collection of points connected by lines. In contrast, bit-based information processing involves processing information only at points, without any lines.

[0024] The above points are called vertices or nodes, and the above lines are called edges or links. Nodes and links are terms preferred by physics, but they refer to the same things as vertices and edges, respectively.

[0025] To begin with, networks are complex, and in order to accurately estimate the amount of information in a network, significant limitations must be imposed. Figure 4 shows an example of this.

[0026] When connecting any two points (1 and 2), if the direction from 1 to 2 and the direction from 2 to 1 are considered to be different links, it is called a directed network. If not, it is called an undirected network. In a directed network, links are represented by arrows, as shown in Figure 4. The start and end points are represented by circles. See the case where r=2 in Figure 4. There are two possible combinations with two circles and one arrow. Here, r is the number of nodes to be linked.

[0027] When r = 3, two arrows are short-circuited, connecting the start point and the end point. The number of cases in this case is 6. When r = 4, three arrows are short-circuited, connecting the start point and the end point. The number of cases in this case is 8. If the total number of nodes is N, the number of cases where the number of linked nodes is r is expressed as the product of r and the permutation P(N,r) of N and r. Adding this product from 3 to N and then adding P(N,2) gives the number of cases for the network under this constraint. This is obviously greater than the factorial of N (N!).

[0028] Although this does not cover all network possibilities, it is possible to show that the information content of such constrained networks is greater than the information content of a bit.

[0029] Consider a case where N nodes are distributed across a memory cell array. The amount of information per bit is simply N bits. In contrast, the amount of information in the example network shown in Figure 4 is greater than log(2, N!), where log(2, x) is the base 2 logarithm of x.

[0030] Using Stirling's rule, when N is large enough (effectively at least greater than 20), log(2,N!) is (Nlog(e,N)-N) / log(e,2), where log(e,x) is the logarithm of x to the base e. Dividing this value by N gives (log(e,N)-1) / log(e,2), which is greater than 1 when N is large enough.

[0031] When converted to 128Gbit DRAM, the number of nodes (N) is roughly 10 to the 11th power. Since log(2, e) is approximately 1.9, looking at Figure 5, it is obvious that the amount of information in the network in Figure 4 will be much larger than the amount of information in bits.

[0032] Next, in a network, information can be recorded that has different paths even if the starting point and the end point are the same.

[0033] Figure 6 shows several examples of paths from a starting point (1) to an end point (2), including two, three, four, and five links from the left.

[0034] When there are two links, there is an intermediate node between the start point (1) and the end point (2). Depending on the address of this intermediate node, the signal flowing into the end point (2) may differ.

[0035] When there are three links, there are two intermediate nodes between the starting point (1) and the end point (2). Depending on the order of the addresses of these two intermediate nodes, the signal flowing into the end point (2) may be different.

[0036] When there are four links, there are three intermediate nodes between the starting point (1) and the end point (2). Depending on the order of the addresses of these three intermediate nodes, the signal flowing into the end point (2) may differ.

[0037] When there are five links, there are four intermediate nodes between the starting point (1) and the end point (2). Depending on the order of the addresses of these four intermediate nodes, the signal flowing into the end point (2) may differ.

[0038] Thus, it can be seen that the amount of information that a network can store is much greater than the amount of information stored by bits with the same number of nodes.

[0039] We compare the information content of two-dimensional networks and three-dimensional networks.

[0040] The extent of a two-dimensional network on the XY plane is determined by the number of elements at address X and the number of elements at address Y. For simplicity's sake, let's assume that both are L, and the number of nodes, N, is the square of L. Therefore, using Stirling's formula, the amount of information in a two-dimensional network is 2log(e,L)-1 multiplied by the square of L.

[0041] The extent of a three-dimensional network in XYZ space is determined by the number of elements at X address, Y address, and Z address. For simplicity, let's assume that all of these are L, and the number of nodes, N, is the cube of L. Therefore, using Stirling's formula, the amount of information in a three-dimensional network is 3log(e,L)-1 multiplied by the cube of L.

[0042] The ratio of the information content of the 3D network to that of the 2D network is plotted in Figure 7. As can be seen, as L increases, the information content of the 3D network overwhelms that of the 2D network.

[0043] As mentioned above, conventional memory systems can only store information at 2 to the power of N, or N bits, where N is the number of bit cells (nodes). This is inherently inferior when compared to the information capacity of a network with the same number of nodes. If the memory mechanism of the human brain is a three-dimensional network of neurons, then there will be an explosion in power consumption before artificial intelligence based on conventional computers can achieve the same capabilities as the human brain. In the first place, the von Neumann bottleneck will hinder the development of artificial intelligence.

[0044] Considerable knowledge of memory architecture technology Without innovation, it will be difficult for artificial intelligence to have the same capabilities as the human brain. DISCLOSURE OF THE INVENTION [Problem to be solved by the invention]

[0045] The present invention has been made in view of the above circumstances, and has as its object to provide a method for generating a three-dimensional network within a silicon chip and recording information therein. [Means for solving the problem]

[0046] In order to solve the above problems, the present invention employs the following means.

[0047] The solution proposed by the present invention is a first unit and a second unit connected in series in a first axial direction; second, third, fourth, and fifth word lines extending in a second axial direction; first and sixth word lines extending in a third axis direction; first and third bit lines extending in a second axial direction; a second bit line extending in a third axis direction; It is a module consisting of the second bit line is connected to both the first and second units; the first unit comprises first, second, and third elements; the first, second, and third elements are connected in series in the first axial direction; the first, second, and third elements each have a control gate; the first element has a source; the third element has a drain; a control gate of the first element connected to the first word line; a control gate of the second element connected to the second word line; a control gate of the third element connected to the third word line; a source of the first element connected to the first bit line; a drain of the third element connected to the second bit line; the second unit comprises a fourth, fifth, and sixth element; the fourth, fifth, and sixth elements are connected in series in the first axial direction; the fourth, fifth, and sixth elements each have a control gate; the fourth element has a source; the sixth element has a drain; a control gate of the fourth element connected to the fourth word line; a control gate of the fifth element connected to the fifth word line; a control gate of the sixth element connected to the sixth word line; the source of the fourth element is connected to the second bit line; a drain of the sixth element connected to the third bit line; It is characterized by the fact that

[0048] Furthermore, seventh, eighth, and ninth elements; The aforementioned seventh and eighth word lines extending in the second axial direction; The aforementioned a ninth word line extending in the third axial direction; The aforementioned a fourth bit line extending in a third axial direction; the seventh, eighth, and ninth elements are connected in series in the first axial direction; the seventh, eighth, and ninth elements each have a control gate; the seventh element has a source; the eighth element has a drain; a control gate of the seventh element connected to the seventh word line; a control gate of the eighth element connected to the eighth word line; a control gate of the ninth element connected to the ninth word line; the source of the seventh element is connected to the fourth bit line; a drain of the ninth element connected to the first bit line; It is characterized by the fact that

[0049] Furthermore, tenth, eleventh, and twelfth elements; The aforementioned eleventh and twelfth word lines extending in a second axial direction; The aforementioned a tenth word line extending in the third axial direction; The aforementioned a fifth bit line extending in the third axial direction; the tenth, eleventh, and twelfth elements are connected in series in the first axial direction; the tenth, eleventh, and twelfth elements each have a control gate; the tenth element has a source; the twelfth element has a drain; a control gate of the tenth device connected to the tenth word line; a control gate of the eleventh element connected to the eleventh word line; the control gate of the twelfth element is connected to the twelfth word line; the source of the tenth element is connected to the third bit line; the drain of the twelfth element is connected to the fifth bit line; It is characterized by:

[0050] The solution proposed by the present invention further has the following features. It has first and second wiring metal layers, the first bit line is connected to the first wiring metal layer; the second word line is connected to the second wiring metal layer; the third word line is connected to the first wiring metal layer; the fourth word line is connected to the second wiring metal layer; the fifth word line is connected to the first wiring metal layer; the third bit line is connected to the second wiring metal layer; Furthermore, the first and sixth word lines are connected to one of the first and second wiring metal layers; the second bit line is connected to the other of the first and second wiring metal layers; It is characterized by:

[0051] The solution proposed by the present invention further has the following features. applying a first voltage to the first, third, seventh, and ninth word lines; the first voltage is less than a threshold voltage; the threshold voltages are threshold voltages that are required to apply to the gates of the first, second, third, seventh, eighth, and ninth elements, respectively, to allow current to flow between the source and drain of the first, second, third, seventh, eighth, and ninth elements; changing the voltage of the first and ninth word lines from the first voltage to a transmission voltage; the transmission voltage is higher than the threshold voltage of any of the first, second, third, seventh, eighth, and ninth elements; applying a read voltage to the second and eighth word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; Furthermore, applying a first voltage to the first, third, fourth, and sixth word lines; the first voltage is less than a threshold voltage; the threshold voltages are threshold values of voltages to be applied to the gates of the first to sixth elements, respectively, that are required to allow current to flow between the sources and drains of the first to sixth elements; changing the voltage of the third and fourth word lines from the first voltage to a transmission voltage; the transmission voltage is higher than a threshold value of any of the first to sixth elements; applying a read voltage to the second and fifth word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; Furthermore, applying a first voltage to the first, third, and twenty-first word lines; the first voltage is less than a threshold voltage; the threshold voltage is a threshold voltage applied to the gates of the first, third, and twenty-first elements necessary to allow current to flow between the source and drain of the first, third, and twenty-first elements; changing a voltage applied to the first and twenty-first word lines from the first voltage to a transmission voltage; the transmission voltage is higher than the threshold voltage of any of the first, third, and twenty-first elements; applying a read voltage to the second word line; the read voltage is higher than the first voltage and lower than the transmission voltage; Furthermore, applying a first voltage to the first, third, and thirty-third word lines; the first voltage is less than a threshold voltage; the threshold voltage is a threshold voltage applied to the gates of the first, third, and thirty-third elements necessary to allow current to flow between the source and drain of the first, third, and thirty-third elements; changing the voltage applied to the third and 33rd word lines from the first voltage to a transmission voltage; the transmission voltage is higher than the threshold of any of the first, third, and thirty-third elements; applying a read voltage to the second and 32nd word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; It is characterized by: [Effects of the Invention]

[0052] According to the present invention, it is possible to reproduce the information processing method of the human brain within a silicon chip without converting it into bit data.

[0053] The best mode for carrying out the invention will now be described in detail. BEST MODE FOR CARRYING OUT THE INVENTION

[0054] As mentioned above, this invention proposes a method for reproducing the information processing method of the human brain on a semiconductor chip (silicon chip) without converting it into bit information (without relying on a computer program). This will be explained in detail below with reference to the drawings. (First embodiment)

[0055] Figure 8 shows coordinates for defining addresses in three-dimensional space. An address in the X-axis direction (X address) is represented by an integer i between 1 and Lx. An address in the Y-axis direction (Y address) is represented by an integer j between 1 and Ly. An address in the Z-axis direction (Z address) is represented by an integer k between 1 and Lz.

[0056] FIG. 9 is a circuit diagram showing a portion of an embodiment of the present application, extending in the Z-axis direction (Z direction). The XY address is (i, j). From above, cell gates CG(i, j, k+1), CG(i, j, k), and CG(i, j, k-1) are arranged. Each cell gate is connected in series between an upper select gate SGU and a lower select gate SGD. In other words, a one-cell, two-select gate (SG) structure forms one unit {SGU(i, j, k), CG(i, j, k), SGD(i, j, k)}.

[0057] In other words, three units are connected in series in the Z direction from above. This is considered one module and is represented as {SGU(i,j,k+1), CG(i,j,k+1), SGD(i,j,k+1) / SGU(i,j,k), CG(i,j,k), SGD(i,j,k) / SGU(i,j,k-1), CG(i,j,k-1), SGD(i,j,k-1)}. In this case, by changing k from 2 to L-1, the entire structure in the Z direction can be explained. However, if k+1 is changed to k-1 in the upper unit, it becomes the same as the lower unit. This means that there is a second-order periodicity with respect to the Z address (k). In other words, in this embodiment, there is a second-order periodicity in the Z direction based on two units.

[0058] In this embodiment, the word lines WCX(j, k+1), WCX(j, k), and WCX(j, k-1) of the cell gate CG all extend (are wired) in the X-axis direction (X direction).

[0059] The word lines of the upper select gate SGU include those that extend in the X direction and those that extend in the Y-axis direction (Y direction). For example, the word line WUX(j, k+1) of SGU(i, j, k+1) extends in the X direction. The word line WUY(i, k) of SGU(i, j, k) extends in the Y direction. The word line WUX(j, k-1) of SGU(i, j, k-1) extends in the X direction. In this way, in this embodiment, the word lines of the SGU alternate between the X direction and the Y direction (in the Z direction) for each layer.

[0060] The word lines of the lower select gate SGD are divided into those that extend in the X direction and those that extend in the Y direction. For example, the word line WDY(i,k+1) of SGD(i,j,k+1) extends in the Y direction. The word line WDX(j,k) of SGD(i,j,k) extends in the X direction. The word line WDY(i,k-1) of SGD(i,j,k-1) extends in the Y direction. In this way, in this embodiment, the word lines of the SGD alternate between the Y direction and the X direction (in the Z direction) for each layer. (This is the opposite of the word lines of the SGU.)

[0061] In other words, {WUX(j, k+1), WDY(i, k+1)}, {WUY(i, k), WDX(j, k)}, {WUX(j, k-1), WDY(i, k-1)} are repeated for each layer. In this embodiment, the word lines of the select gates (SG) alternate between the X and Y directions. This is symmetrical to the word lines of the cell gates, which extend only in the X direction.

[0062] Each word line has a word line select gate, which is controlled by a decoder. The decoder consists of an X decoder that controls the select gates of the word lines wired in the X direction, and a Y decoder that controls the select gates of the word lines wired in the Y direction.

[0063] For example, an X-direction word line select gate WSGUX(j,k+1) is provided in WUX(j,k+1). An X-direction word line select gate WSGCX(j,k+1) is provided in WCX(j,k). An X-direction word line select gate WSGCX(j,k) is provided in WCX(j,k). An X-direction word line select gate WSGDX(j,k) is provided in WDX(j,k). An X-direction word line select gate WSGUX(j,k-1) is provided in WUX(j,k-1). An X-direction word line select gate WSGCX(j,k-1) is provided in WCX(j,k-1).

[0064] For example, a Y-direction word line select gate WSGY(i,k+1) is installed in WDY(i,k+1), a Y-direction word line select gate WSGY(i,k) is installed in WUY(i,k), and a Y-direction word line select gate WSGY(i,k-1) is installed in WDY(i,k-1).

[0065] In this embodiment, the select gates of the word lines connected to the select gates are distributed alternately in the X and Y directions for each layer (every k layers), except that the select gates of the word lines connected to the cell gates are distributed in the X direction.

[0066] The word lines and bit lines extending in the X direction are controlled by an X decoder, and the word lines and bit lines extending in the Y direction are controlled by a Y decoder.

[0067] That is, in this embodiment, the gate electrodes connected to the upper and lower select gates Word lines are layer by layer (k by layer) This is done alternately with the X decoder and the Y decoder. However, the cell gate The word line connected to To be controlled.

[0068] In this embodiment, between each unit, there is a bit line BLX extending in the X direction or Y The bit lines BLY are wired in the direction.

[0069] Therefore, a bit line BLX(j,k) is wired in the X direction between SGD(i,j,k+1) and SGU(i,j,k). A bit line BLX(j,k-2) extends (is wired) in the X direction below SGD(i,j,k-1).

[0070] Similarly, a bit line BLY(i,k+1) is wired in the Y direction above SGU(i,j,k+1). A bit line BLY(i,k-1) is wired in the Y direction between SGD(i,j,k) and SGU(i,j,k-1).

[0071] In this manner, in this embodiment, the bit lines are wired (extend) alternately in the X direction and the Y direction for each layer (for each kth layer).

[0072] Each bit line has a bit line select gate, which is controlled by a decoder. The decoder consists of an X decoder that controls the select gates of the bit lines wired in the X direction, and a Y decoder that controls the select gates of the bit lines wired in the Y direction.

[0073] For example, a Y-direction bit line select gate BSGY(i,k+1) is installed in BLY(i,k+1). An X-direction bit line select gate BSGX(j,k) is installed in BLX(j,k). A Y-direction bit line select gate BSGY(i,k-1) is installed in BLY(i,k-1). An X-direction bit line select gate BSGX(j,k-2) is installed in BLX(j,k-2).

[0074] That is, in this embodiment, the control of the select gate of the bit line is alternately performed by the X decoder and the Y decoder for each layer (for each kth layer).

[0075] Figure 10 shows this circuit expanded in the X-axis direction. As an example, three of the above modules are connected in the X-axis direction.

[0076] That is, three modules: {SGU(i-1, j, k+1), CG(i-1, j, k+1), SGD(i-1, j, k+1) / SGU(i-1, j, k), CG(i-1, j, k), SGD(i-1, j, k) / SGU(i-1, j, k-1), CG(i-1, j, k-1), SGD(i-1, j, k-1)} and {SGU(i, j, k+1), CG(i, j, k+1), SGD(i, j, k+1) / SGU(i, j, k), CG(i, j, k), SGD(i, j, k) / SGU(i, j, k-1), CG(i, j, k-1), SGD(i, j, k-1)}, {SGU(i+1, j, k+1), CG(i+1, j, k+1), SGD(i+1, j, k+1) / SGU(i+1, j, k), CG(i+1, j, k), SGD(i+1, j, k) / SGU(i+1, j, k-1), CG(i+1, j, k-1), SGD(i+1, j, k-1)} and are arranged in the X direction.

[0077] Figure 11 shows this circuit diagram expanded in the Y-axis direction. Y There are three in a row.

[0078] That is, three modules: {SGU(i, j-1, k+1), CG(i, j-1, k+1), SGD(i, j-1, k+1) / SGU(i, j-1, k), CG(i, j-1, k), SGD(i, j-1, k) / SGU(i, j-1, k-1), CG(i, j-1, k-1), SGD(i, j-1, k-1)} and {SGU(i, j, k+1), CG(i, j, k+1), SGD(i, j, k+1) / SGU(i, j, k), CG(i, j, k), SGD(i, j, k) / SGU(i, j, k-1), CG(i, j, k-1), SGD(i, j, k-1)}, {SGU(i, j+1, k+1), CG(i, j+1, k+1), SGD(i, j+1, k+1) / SGU(i, j+1, k), CG(i, j+1, k), SGD(i, j+1, k) / SGU(i, j+1, k-1), CG(i, j+1, k-1), SGD(i, j+1, k-1)} and are arranged in the Y direction.

[0079] The select gate and cell gate are any three-terminal elements. A three-terminal element is an electronic device having three terminals, including at least a gate terminal. The gate terminal is connected to a word line, and a control voltage can be input from the word line. The two terminals other than the gate terminal can be connected to one of the bit lines, allowing an output current to flow to one of the bit lines. However, the select gate and cell gate may also include terminals other than these three terminals.

[0080] For example, the select gate and cell gate that can be used in the present application may be any one of a transistor, a non-volatile memory cell, a volatile memory cell, a phase change memory cell, a magnetoresistive memory cell, a resistance change memory cell, a ferroelectric memory cell, etc. In any case, it does not deviate from the concept and technical essence of the present application.

[0081] Alternatively, the select gate and cell gate that can be used in the present application may include at least one of a transistor, a nonvolatile memory cell, a volatile memory cell, a phase change memory cell, a magnetoresistive memory cell, a resistance change memory cell, a ferroelectric memory cell, etc. as a component, without departing from the concept and technical essence of the present application.

[0082] In the circuit diagrams of Figures 9-11, as an example, nonvolatile memory cells with charge storage regions are used for the select gates and cell gates (SGU, CG, SGD) that make up the units. Transistors are used for the word line and bit line select gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY) as an example. However, transistors can also be used for the select gates (SGU, SGD) that make up the units, just like the word line and bit line select gates.

[0083] There are two main types of charge storage regions on the market. One is a floating gate, which is widely used in NOR flash and 2D NAND flash. The other is a charge trapping layer, which is widely used in 3D NAND flash. Either type does not deviate from the concept and technical essence of the present application.

[0084] FIG. 12 shows an example of the concept of the transistor characteristics (electrical characteristics) of the cell gate (CG) according to the present invention.

[0085] The horizontal axis represents the control voltage applied from the word line terminal. The vertical axis represents the output current flowing between two terminals other than the word line terminal. The control voltage controls this output current depending on the state of the charge storage region. Generally, this output current can be passed to one of the bit lines. If a sense amplifier is connected to the bit line, it is possible to read the state of this charge storage region. Generally, such a sense amplifier is included in the decoder.

[0086] When the control voltage is sufficiently high, i.e., when a pass-through voltage (Vpass) is applied to the word line terminal, the cell gate (CG) outputs a constant output current regardless of the state of the charge storage region (layer). At this time, the cell gate transistor is said to be in a switched-on state. Note that the state of the charge storage region refers to the amount of charge stored in the charge storage region. "Regardless of the state of the charge storage region" means that the amount of charge stored in the charge storage region is independent of the amount of charge stored in the charge storage region as long as it is within a certain range. Furthermore, the amount of charge stored in the charge storage region can be intentionally changed by programming or erasing the element. The pass-through voltage should be higher than the threshold voltage of any element whose charge storage region is within a certain range.

[0087] When the control voltage is low enough, i.e., when a constant voltage (Voff) is applied to the word line terminal, the cell gate (CG) outputs almost no current, regardless of the state of the charge storage region. At this time, the cell gate transistor is said to be in the switched-off state. That is, Voff is a voltage lower than the threshold voltage (Vt). Applying a sufficiently high voltage to the gate of the cell gate transistor allows current to flow between the source and drain of the cell gate transistor. The threshold voltage of the cell gate transistor is the threshold voltage required to allow this current to flow.

[0088] In general, this threshold voltage does not correspond to the threshold of excitation of the synapse that drives synapsis and moves neurotransmitters from cell body A to cell body B.

[0089] In Figure 12, Other than Vpass Three dotted lines are drawn vertically. For example, Vread can be adjusted between the two dotted lines. Currents (1), (2), and (3) correspond to the output when Vread is located at the center dotted line, for example.

[0090] When the control voltage is the read voltage (Vread), the output current is variable depending on the state of the charge storage region, as shown in (1), (2), and (3) of Figure 12. This can be rephrased as a variable voltage (threshold voltage, Vt) at which the output current begins to flow. However, Vread is a voltage between Voff and Vpass, and Vread can also be adjusted as needed.

[0091] By injecting (writing) electrons into the charge storage region, it is possible to reduce the output current when Vrea is applied. An example of this is (3) in Figure 12. This corresponds to an increase in Vt and is called writing. Conversely, by extracting (erasing) electrons from the charge storage region (layer), it is possible to increase the output current when Vread is applied. An example of this is (1) in Figure 12. This corresponds to a decrease in Vt and is called erasing.

[0092] Since both writing and erasing are performed within a predetermined range, there are convenient upper and lower limits for Vt. That is, Vpass is a voltage higher than at least this convenient upper limit of Vt. Therefore, Vpass is higher than the read voltage (Vread). Voff is a voltage lower than this convenient lower limit of Vt.

[0093] When Vt is applied as the control voltage, the output current has just begun to flow, and as the control voltage is further increased from Vt, the output current increases. When the control voltage is further increased and becomes sufficiently high, the output current saturates. This current is called the saturation current. Vpass is a voltage high enough that the output current saturates even when Vt is written to its convenient upper limit. In other words, Vpass is high enough that the same amount of output current flows when Vt is written to its convenient upper limit as when it is written to its convenient lower limit.

[0094] The difference between Vpass and the expedient upper limit of Vt can be kept low as the S factor (the voltage required to increase the current by one digit near Vt) becomes smaller. As for the transistor characteristics in Figure 12, the lower the S factor, the better the transistor characteristics.

[0095] FIG. 13 shows an example of the concept of the transistor characteristics (electrical characteristics) of the word line and bit line select gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY) related to the present application. These word line and bit line select gates do not require charge storage regions, and therefore, unlike FIG. 12, the threshold voltage (Vt) is not necessarily variable.

[0096] In general, this threshold voltage does not correspond to the threshold of exitation of the SUM, which drives synapsis and moves neurotransmitters from cell body A to cell body B.

[0097] A control voltage is input to the word line and bit line select gates from a decoder. The horizontal axis of FIG. 13 represents the control voltage, and the vertical axis represents , which flows to the bit line according to the control voltage. This is the output current. If the control voltage is higher than Vt, for example, if a high voltage (Von) corresponding to the dotted line in the figure is applied as the control voltage, the output current flows and the transistor is switched on. In other words, Von is a voltage higher than Vt.

[0098] If the control voltage is lower than Vt, for example, if Voff is applied as the control voltage, almost no output current flows and the transistor is switched off. In other words, Voff is a voltage lower than Vt. If Vt in Figure 13 is higher than the convenient lower limit of Vt in Figure 12, Voff in Figure 13 and Voff in Figure 12 can usually be made the same.

[0099] The transistor characteristics (electrical characteristics) of the SGD and SGU may be either those shown in FIG. 12 or FIG. 13. That is, the SGD and SGU may or may not have a charge storage region. However, semiconductor manufacturing costs can be reduced if the SGD and SGU have the same element structure as the cell gate CG. Therefore, in this embodiment, as an example, the SGD and SGU are nonvolatile memory cells having charge storage regions. In this case, the element structure is the same as that of the cell gate CG, and they can be manufactured using the same manufacturing method as that for manufacturing the CG. Therefore, in this case, the transistor characteristics (electrical characteristics) of the SGD and SGU are also as shown in FIG. 12. However, it is not necessary to adjust the state of the charge storage region of the SGD and SGU in coordination with the cell gate CG in the same unit.

[0100] However, it would not go beyond the scope of the present application if SGD and SGU were transistors having the characteristics of Figure 13. Also, it would not go beyond the scope of the present application if any of the word line and bit line select gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY) were transistors having the characteristics of Figure 12. (Second embodiment)

[0101] To create a free three-dimensional network like the human brain within a semiconductor chip, at least a method is required to link any two cell gates CG arranged on a three-dimensional cell array.

[0102] An example of a link between two cells enclosed by dashed lines, CG(i, j, k+1) and CG(i, j, k), is shown in Figure 14. Figure 15 shows an example of a voltage set for connecting (linking) these two cells enclosed by dashed lines.

[0103] The bit line BLX(j,k) exists between two cells surrounded by dashed lines, CG(i,j,k+1) and CG(i,j,k). First, to isolate this from the other cells, apply Voff to BSGX(j,k), Voff to WDY(i',k+1), and Voff to WUY(i',k). Note that i' is an integer between 1 and Lx, and is different from i.

[0104] Furthermore, Voff is applied to WUX(j, k+1), Vread to WCX(j, k+1), Voff to WDY(i, k+1), Voff to WUY(i, k), Vread to WCX(j, k), and Voff to WDX(j, k). This puts BLX(j, k) into a floating state.

[0105] Apply Von to WSGUX(j,k+1), WSGCX(j,k+1), WSGDY(i,k+1), WSGUY(i,k), WSGCX(j,k), and WSGDX(j,k). Next, when the voltage of WDY(i,k+1) and WUY(i,k) is increased from Voff to Vpass, the two cells enclosed by the dashed line, CG(i,j,k+1) and CG(i,j,k), are connected (linked).

[0106] Furthermore, to link cell gate CG(i,j,k) to CG(i,j,k-1), the voltage at WDX(j,k) must be increased from Voff to Vpass. Furthermore, to link cell gate CG(i,j,k+1) to CG(i,j,k+2), the voltage at WUX(j,k+1) must be increased from Voff to Vpass.

[0107] Since there is second-order periodicity in the Z direction, CG(i, j, k) and CG(i, j, k-1) must be linked in a different way than in Figure 14. An example of this is explained in Figures 16 and 17. In Figure 16, CG(i, j, k) and CG(i, j, k-1) are surrounded by dashed lines.

[0108] The bit line BLY(i,k-1) exists between two cells, CG(i,j,k) and CG(i,j,k-1), enclosed by dashed lines. To separate this from cells other than CG(i,j,k) and CG(i,j,k-1), Voff is applied to BSGY(i,k-1), Voff is applied to WDX(j',k-1), and Voff is applied to WUX(j',k-1). Note that j' is an integer between 1 and Ly, and is different from j.

[0109] Furthermore, Voff is applied to WUY(i,k), Vread to WCX(j,k), Voff to WDX(j,k), Voff to WUX(j,k-1), Vread to WCX(j,k-1), and Voff to WDY(j,k-1). This puts BLY(i,k-1) into a floating state.

[0110] Von is applied to WSGUY(i, k), WSGCX(j, k), WSGDX(j, k), WSGUX(j, k-1), WSGCX(j, k-1), and WSGDY(i, k-1).

[0111] Next, when the voltages of WDX(j, k) and WUX(j, k-1) are increased from Voff to Vpass, the two cells surrounded by dashed lines, CG(i, j, k) and CG(i, j, k-1), are connected (linked).

[0112] Further connecting cell gate CG(i,j,k) to CG(i,j,k+1) requires increasing the voltage on WY(i,k) from Voff to Vpass. Further connecting cell gate CG(i,j,k-1) to CG(i,j,k-2) requires increasing the voltage on WDY(i,k-1) from Voff to Vpass.

[0113] Next, an example of a method for linking (connecting) in the X direction will be described with reference to FIGS.

[0114] In Figure 18, a link in the X direction is realized using bit line BLX(j, k). First, to make it independent from cells other than the two cells surrounded by dashed lines, CG(i, j, k) and CG(i+1, j, k), Voff is applied to BSGX(j, k), Voff is applied to WUY(i', k), and Voff is applied to WDY(*, k+1). However, i' is an integer between 1 and Lx that is different from i, and * is an arbitrary integer between 1 and Lx. Furthermore, by applying Voff to WUY(i, k) and WUY(i+1, k), BLX(j, k) can be put into a floating state. By applying Voff to WDX(j, k), it is disconnected from the bit line BLY(*, k-1) in the Y direction. However, * is an integer between 1 and Lx. When the voltage applied to WUY(i, k) and WUY(i+1, k) is increased from Voff to Vread, the two cells enclosed by the dashed lines , CG(i, j, k) and CG(i+1, j, k), can be linked (connected).

[0115] To connect the two cells enclosed by dashed lines, CG(i, j, k) and CG(i+1, j, k), to another cell in the Y direction, it is necessary to increase the voltage applied to WDX(j, k) from Voff to Vpass.

[0116] Next, using Figures 20 and 21, to An example of a linking (connection) method will now be described.

[0117] In Figure 20, a link in the Y direction is realized using the bit line BLY(i, k-1). First, to make it independent from cells other than the two cells surrounded by dashed lines, CG(i, j, k) and CG(i, j+1, k), Voff is applied to BSGY(i, k-1), Voff is applied to WDX(j', k), and Voff is applied to WUX(*, k-1). Here, j' is an integer between 1 and Ly that is different from j, and * is an arbitrary integer between 1 and Ly. Furthermore, by applying Voff to WDX(j, k) and WDX(j+1, k), BLY(i, k-1) can be put into a floating state. By applying Voff to WUY(i, k), it is disconnected from the bit line BLX(*, k) in the X direction. Here, * is an integer between 1 and Ly. Let any integer be used. When the voltage applied to WDX(j, k) and WDX(j+1, k) is increased from Voff to Vread, the two cells enclosed by the dashed lines , CG(i, j, k) and CG(i, j+1, k) can be linked (connected).

[0118] To connect the two cells enclosed by dashed lines, CG(i, j, k) and CG(i, j+1, k), to another cell in the X direction, it is necessary to increase the voltage applied to WUY(i, k) from Voff to Vpass. (Third embodiment)

[0119] In the second embodiment, a method for connecting any two cell gates distributed in a three-dimensional space has been described. In Fig. 22 to Fig. 28, which explain this embodiment, the two cell gates (or simply called cells, corresponding to memory cells) connected in the second embodiment are simplified and shown enclosed by solid lines.

[0120] However, to reproduce the perceptron in Figure 3, a mechanism for adding up multiple inputs is further required. Figure 22 explains how the output currents of cells CG(i, *, k) arranged in the Y direction are added up by bit line BLY(i, k-1). Here, * is an arbitrary integer between 1 and Ly. First, to make BLY(i, k-1) floating, Voff is applied to BSGY(i, k-1), Voff is applied to WDX(*, k), and WUX(* , k-1) and apply Voff.

[0121] Of course, it is not necessary to add up the outputs from all the cells arranged in the Y direction. to It is sufficient to have the function of adding together the outputs from the various selected cells. D Apply Vread to X(j1, k), where j1 is the Y address (first selected Y address) of the cell selected to sum the outputs in BLY(i, k-1). The number of first selected addresses (j1) can be multiple or single.

[0122] The cell allocated to the first selected Y address can output a current according to the state (Vt) of the charge storage region. As an example, Figure 12 illustrates three states (1), (2), and (3), but the number of states is not necessarily limited to three. The number of states can be two, four, or even more. That is, M states are possible, where M is generally an integer greater than one. This is called M Level Per Cell (MLC), and in the field of flash memory technology, MLC is conventionally considered to have four states. Eight states higher than this are called TLC, and 16 states are called QLC. Thus, it is known that the number of states per cell is already possible up to 16 at the product level (see Non-Patent Document 3). Technological innovations may lead to further increases, and it is not necessary to limit the number to multiples of two. Therefore, M (the number of states per cell) can be any integer greater than one.

[0123] To isolate BLY(i,k-1) from the layer below, Voff is applied to WUX(*,k-1), where * is an integer between 1 and Ly. The voltage applied to WDX(j1,k) of the first selected Y address (j1) is raised from Voff to Vpass. Alternatively, if Voff is applied to the unselected WCX (unselected j,k), Vpass can be applied to WDX(*,k) of all Y addresses (*). * is an integer between 1 and Ly. When the voltage applied to the Y-direction bit line select gate BSGY(i,k-1) is Voff, it is in standby mode. When this Voff is raised to Von, the output currents of the selected cells CG(j1,k) are summed by BLY(i,k-1) and sensed by the sense amplifier (S / A).

[0124] The sense amplifier is usually included in the decoder, but it can also be installed separately from the decoder. In either case, it is installed outside the cell array. The sense amplifier determines whether the current level added up by BLY(i, k-1) is higher or lower than a predetermined threshold, and after that determination, applies Voff again to BSGY(i, k-1). If the added current level is higher than the predetermined threshold, it is considered to be in a synapse activated state. If not, it is considered to be in a synapse inactivated state.

[0125] In the synapse activation state, as shown in Figure 23, the voltage applied to WUX(j2,k-1) is increased from Voff to Vpass, and the current added by BLY(i,k-1) is transferred as a new input to the second selected cell CG(j2,k-1). Here, j2 is the second selected Y address. Applying Von, Von, and Vpass to BSGX(j2,k-2), WSGDY(i,k-1), and WDY(i,k-1), respectively, enables the output from the second selected cell CG(j2,k-1) to be read by a sense amplifier. This sense amplifier may be the same as the sense amplifier in Figure 22 or may be a separately installed sense amplifier. In this case, the voltage applied to WCX(j,k-1) is either Vread or Vpass.

[0126] In this way, the cell body (A) in Figures 1 and 2 is simulated using BLY(i, k-1), BSGY(i, k-1), and a sense amplifier. Cells CG(i, j1, k) with the first selected Y address (j1) as an argument, either singular or plural, correspond to the dendrites of the cell body (A) in Figure 2. That is, the current input to CG(i, j1, k) corresponds to the signal input to the dendrites of the cell body (A) in Figure 2. This signal corresponds to x(j1) in Figure 3. The Vt of these cells is variable and is in a pre-programmed state. When Vread is applied to each word line, the output from the cell CG(i, j1, k) with j1 as an argument varies depending on the state of the programmed Vt. This corresponds to multiplying the input x(j1) by the weight W(j1) in the perceptron in Figure 3. Here, j1 is an integer between 1 and N in Figure 3. That is, the input to CG(i, j1, k) is x(j1) in Figure 3, and the output from CG(i, j1, k) is the product with the weight x(j1)W(j1). In BLY(i, k-1), this product x(j1)W(j1) is summed from 1 to N. Can be handled This is the SUM of the perceptron in Figure 3. In this case, BLY(i, k-1) can be considered as the body of the cell body (A) in Figure 2. The sense amplifier and select gate BSGY(i, k-1) are used to explain the function of the cell body (A).

[0127] The SUM is sensed by a sense amplifier and compared with a threshold of excitation. If the SUM is higher than the threshold, it is considered to be in a synaptic activation state, and Vpass is applied to WUX(j2, k-1) to activate the second selected Y address ( j2) is connected to CG(i, j2, k-1) which has it as an argument. This is how a synapse is formed. In other words, CG(i, j2, k-1) plays the role of the dendrite on the cell body (B) side, which forms the synapse between the cell body (B) and the cell body (A) in Figure 2. In this case, BLX(j2, k-2) is considered to be the body of the cell body (B) in Figure 2. The selector gate BSGX(j2, k-2) and the sense amplifier are used to explain the function of the cell body (B).

[0128] Figure 24 shows an example of how to add up the outputs from CG(*, j, k+1) using BLX(j, k). * is any integer between 1 and Lx. Vread is applied to the word line WCX(j, k+1) connected to each cell. Next, to make BLX(j, k) floating, Voff is applied to BSGX(j, k), and Voff is applied to WUY(*, k) and WDY(*, k+1). vinegar The voltage of WDY(i1, k+1) connected to the selected X address (first selected X address i1) is increased from Voff to Vpass. Here, the first selected address i1 can be single or multiple. Next, Vpass is applied to WUY(i2, k) connected to the selected X address (second selected X address i2), and the current added up by BLX(j, k) can be transferred to cell CG(i2, j, k).

[0129] In this way, the cell body (A) in Figures 1 and 2 is simulated using BLX(j, k), BSGX(j, k), and a sense amplifier. The cells CG(i1, j, k+1) with the first selected X address (i1) as an argument, either singular or plural, correspond to the dendrites of the cell body (A) in Figure 2. The current input to CG(i1, j, k+1) corresponds to the signal input to the dendrites of the cell body (A) in Figure 2. This input signal corresponds to x(i1) in Figure 3. The Vt of these cells is variable and each is in a pre-programmed state. When Vread is applied to each word line, the output from the cell CG(i1, j, k+1) with i1 as an argument varies depending on the state of the programmed Vt. This corresponds to multiplying the input x(i1) by the weight W(i1) in the perceptron in Figure 3. Here, i1 is an integer from 1 to N in FIG. 3. That is, the input to CG (i1, j, k) is x( i 1) and the output from CG (i1, j, k) is the product of the weight x(i1) W(i1). In BLX(j, k), this product x(i1) W(i1) is summed from 1 to N. can be obtained This is the SUM of the perceptron in Figure 3. In this case, BLX(j, k) can be considered to be the body of the cell body (A) in Figure 2. The sense amplifier and select gate BSGX(j, k) are used to explain the function of the cell body (A).

[0130] The SUM is sensed by a sense amplifier and compared with a threshold (threshold of excitation). If SUM is higher than the threshold, it is considered an activated synapse, and Vpass is applied to WUY(i2, k), connecting it to CG(i2, j, k) with the second selection X address (i2) as an argument. This creates a synapse. In other words, CG(i2, j, k) plays the role of the dendrite on the cell body (B) side, which constitutes the synapse between cell body (B) and cell body (A) in Figure 2. In this case, BLY(i2, k-1) is considered to be the main body of cell body (B) in Figure 2. The selection gate BSGY(i2, k-1) and the sense amplifier are used to explain the function of cell body (B).

[0131] In this way, in the present invention, the bit line plays the role of the cell body, and the cell (memory cell) plays the role of the dendrite. This is one of the greatest features of the present invention. (Fourth embodiment)

[0132] By repeating the method described in the second embodiment, it is possible to extend various connections in the X, Y, and Z directions. This means that it is possible to connect any two cells distributed in the cell array. Figure 25 shows an example. The starting cell is CG(i', j', k') and the ending cell is CG(i, j, k). For simplicity, the cells that pass through to transfer data from the starting point to the ending point are represented by hollow square symbols (□). For simplicity, the upper and lower select gates that form a unit with each cell (□) through which data passes are omitted, but Vpass is applied to the upper and lower select gates that form a unit with each passing cell (□). The number of passing cells (□) connecting the starting point and the ending point may be zero, one, or multiple. In the third embodiment, the number of passing cells (□) connecting the starting point and the ending point is shown as a square symbol (□). cell This corresponds to the case where the number of (□) is zero.

[0133] The transit cells (□) are used to reproduce the axons in Figures 1 and 2. The starting cell CG (i', j', k') and the ending cell CG (i, j, k) play the role of dendrites that make up the synapse between the cell body (A) and the cell body (B) in Figure 2. In this case, the starting cell CG (i', j', k') is the dendrite on the cell body (A) side. axon terminal corresponds to the dendrite on the cell body (B) side, and the terminal cell CG(i, j, k) corresponds to the dendrite on the cell body (B) side.

[0134] In the example of Figure 22, from the cell CG(i, j, k) that adds up the output signals in BLY(i, k-1), it is possible to repeat the connection in the X, Y, and Z directions as shown in Figure 25.

[0135] As an example, Figure 26 illustrates the case where inputs from three starting points, CG(ii1, jj1, kk1), CG(ii2, jj2, kk2), and CG(ii3, jj3, kk3), are weighted and then added together at BLY(i, k-1). Of course, the number of starting points is not limited to three. It can be one or two, or any larger integer. The upper limit of the number of starting points is the product of Lx, Ly, and Lz. These starting points each play the role of the dendrites in Figures 1 and 2.

[0136] In Figures 22 and 23, CG(i, j1, k), which takes the first selected Y address (j1) as an argument, is the last cell passed through in BLY(i, k-1). Here, j1 is an integer between 1 and N. N is the number of external inputs received by the perceptron in Figure 3. In this example, it can be considered the same as the number of starting points. That is, the input to the starting cell is the input x(j1) to the perceptron in Figure 3. Vread is applied to the word line of the starting cell. Here, when BLY(i, k-1) adds up the input currents, it is multiplied by a weight W(j1) according to the Vt state of each starting cell. The roles of BLY(i, k-1), BSGY(i, k-1), and the sense amplifier are the same as those described in Figures 22 and 23, so details are omitted.

[0137] Apply Vpass or Vread to the word line of each passing cell. The integer kk3 can be equal to, smaller than, or greater than k-1. The integer ii2 can be equal to, larger than, or smaller than i. The integer jj2 can be equal to, larger than, or smaller than j.

[0138] As an example, Figure 27 illustrates the case where inputs from three starting points, CG(ii1, jj1, kk1), CG(ii2, jj2, kk2), and CG(ii3, jj3, kk3), are weighted and then added together in BLX(j, k). Of course, the number of starting points is not limited to three. It can be one or two, or even a larger integer. The upper limit of the number of starting points is the product of Lx, Ly, and Lz. These starting points each play the role of the dendrites in Figures 1 and 2.

[0139] In Figure 24, CG(i1,j,k) with the first selected X address (i1) as an argument is the last cell passed through in BLX(j,k-1). Here, i1 is an integer between 1 and N. N is the number of external inputs received by the perceptron in Figure 3. In this example, it can be considered the same as the number of starting points. In other words, the input to the starting cell is the input x(i1) to the perceptron in Figure 3. Vread is applied to the word line of the starting cell. Here, when the inputs are added in BLX(j,k), they are multiplied by a weight W(i1) according to the Vt state of each starting cell. The functions of BLX(j,k), BSGX(j,k), and the sense amplifier are the same as those explained in Figure 24, so details are omitted.

[0140] Let's go back to Figure 25. Either Vpass or Vread needs to be applied to the word line of each passing cell between the starting point CG(i', j', k') and the ending point CG(i, j, k). When Vread is applied to the word lines of all passing cells, the input current flowing into the starting point and the current transferred to the ending point can be considered to be at roughly the same level, excluding the effects of wiring resistance, parasitic resistance, etc. In this case, it doesn't matter what path the current takes from the starting point to the ending point.

[0141] Conversely, when Vread is applied to one or more passing cells on a path from the starting point to the end point, the current transferred from the starting point to the end point may vary depending on the path. This is because the Vt of the cells passed along the way may be different. If the Vt is different, the output current from the passing cell will be different, as shown in Figure 12. In other words, as shown in Figure 28, even if the starting point CG(i', j', k') and the end point CG(i, j, k) are the same, the currents flowing into BLY(i, k+1) through two different paths (path-A and path-B) may be different from each other. Similarly, as shown in Figure 29, even if the starting point CG(i', j', k') and the end point CG(i, j, k) are the same, the currents flowing into BLY(i, k+1) through two different paths (path-A and path-B) may be different from each other. C and path- D ) flowing into BLX(j, k) may be different from each other.

[0142] In other words, when Vread is applied to the word line of the passing cell, it becomes possible to record information in a path (network) from the start point to the end point. In this way, one of the features of the present invention is that, even though it is a silicon chip, it is possible to record information in a path (network) similar to a neural network.

[0143] Let's return to Figure 12. In the Vread voltage region, the current varies depending on the pre-programmed Vt. In other words, a cell to which Vread is applied can be considered a variable resistor. In other words, when Vread is applied to each passing cell, changing the path from the start point to the end point is the same as changing the resistance of the path from the start point to the end point. In this way, it becomes possible to record information in a network, just like the neural circuits in the human brain. (Fifth embodiment)

[0144] FIG. 9 is an equivalent circuit diagram illustrating an example of the first embodiment, where the X address is i and the Y address is j. At the top is a Y-direction bit line BLY(i,k+1), and at the bottom is an X-direction bit line BLX(j,k-2). Cell gates CG(i,j,k+1), CG(i,j,k), and CG(i,j,k-1) are sandwiched between them. Between CG(i,j,k+1) and CG(i,j,k), the X-direction bit line BLX(j,k) is located. Between CG(i,j,k) and CG(i,j,k-1), the Y-direction bit line BLY(i,k-1) is located. This reflects the second-order periodicity characteristic of the present application. Each cell gate is sandwiched between an upper select gate SGU and a lower select gate SGD to form one unit. That is, FIG. 9 shows an equivalent circuit of one module including three units in the Z-axis direction.

[0145] Fig. 30 is a cross-sectional view on the ZY plane showing an example of a cell design that realizes the equivalent circuit of Fig. 9. Here, the X address is i and the Y address is j.

[0146] At the top end of one module in the Z-axis direction is a bit line BLY(i, k+1) extending in the Y-direction. At the bottom end of one module in the Z-axis direction is a bit line BLX(j, k-2) extending in the X-direction. Three units consisting of a cell gate CG, an upper select gate SGU, and a lower select gate SGD are lined up from the top along the Z-axis. From the top, they are Unit(k+1), Unit(k), and Unit(k-1). Between Unit(k+1) and Unit(k) is BLX(j, k) extending in the X-direction, and between Unit(k) and Unit(k-1) is BLY(i, k-1) extending in the Y-direction.

[0147] In this cross-sectional view, when z-address (k) is converted to k-2, Unit(k+1) is converted to Unit(k-1). These two units have exactly the same word line layout. Considering one module in the Z-axis direction in this way, it can be seen that this embodiment has second-order periodicity in the Z-axis direction. In other words, to explain the characteristics of the cross-sectional view of this embodiment, it is sufficient to explain one pair of Unit(k+1) and Unit(k). The same is true for Figure 9.

[0148] Unit(k+1) consists of a cell gate CG(i,j,k+1) and an upper select gate SGU(i,j,k+1) and a lower select gate SGD(i,j,k+1) sandwiching it from above and below. SGU(i,j,k+1) receives Vpass or Voff from a word line WUX(j,k+1) extending in the X direction. SGD(i,j,k+1) receives Vpass or Voff from a word line WDY(i,k+1) extending in the Y direction. CG(i,j,k+1) receives Vread, Vpass, or Voff from a word line WCX(j,k+1) extending in the X direction. In this way, it has the same features as the first embodiment.

[0149] Unit(k) consists of a cell gate CG(i,j,k) and an upper select gate SGU(i,j,k) and a lower select gate SGD(i,j,k) sandwiching it from above and below. SGU(i,j,k) receives Vpass or Voff from a word line WUY(i,k) extending in the Y direction. SGD(i,j,k) receives Vpass or Voff from a word line WDX(j,k) extending in the X direction. CG(i,j,k) receives Vread, Vpass, or Voff from a word line WCX(j,k) extending in the X direction. In this way, it has the same features as the first embodiment.

[0150] The Z-direction module in Figure 30, used as an example for explanation, is placed at XY address (i, j) on the XY plane. At this XY address (i, j), a hole is dug in the Z-axis direction and filled with a semiconductor material or the like to form a channel via. The semiconductor material can be polysilicon, amorphous silicon, epitaxial silicon, or other semiconductor materials.

[0151] Channel vias (CVs) are formed between each bit line BLY(i,k+1), BLX(j,k), BLY(i,k-1), and BLX(j,k-2). Because bit lines are typically made of thin metal films, a diffusion layer must be formed between the bit line and the junction (bit line contact, BL contact) to prevent Schottky junction defects. In Figure 30, a dense N-type diffusion layer (N+ layer) is formed. The technique for forming such junctions is common in semiconductor manufacturing. For example, holes are first drilled in an etched metal film. Semiconductor material is then filled into the hole, and a dopant is mixed into the chamber as the hole approaches the metal film layer. Annealing is then performed as needed. Therefore, the distance between the bit line and each unit must be sufficiently large.

[0152] FIG. 31 is a top view of bit lines BLY(i, k+1) and BLY(i, k-1) extending in the Y direction. That is, it is a view cut horizontally to the XY plane at the layers of BLY(i, k+1) and BLY(i, k-1). The bit line width is 1 / 2 sq. m, even when manufacturing variations are taken into consideration. Channel Section The bit line width must always be larger than the hole (CV) for making the bit line. Therefore, a sufficient margin is required for the difference in size between the bit line width and the CV. In FIG. 31, multiple bit line contacts (BL contacts) are lined up in the Y direction. In this embodiment, as an example, an N+ diffusion layer is formed in the CV.

[0153] Figure 32 shows a bit line extending in the X direction. BLX(j, k) and BLX(j, k-2)32 is a top view of the bit line contacts (BL contacts) shown in FIG. 32. That is, it is a view cut horizontally in the XY plane at the BLX(j, k+1) and BLX(j, k-1) layers. The bit line width must always be larger than the vertical via (CV) opened to create the channel region, even taking into account manufacturing variations. Therefore, a sufficient margin is required for the difference between the bit line width and the CV size. In FIG. 32, multiple bit line contacts (BL contacts) are lined up in the X direction. In this embodiment, as an example, an N+ diffusion layer is formed in the CV.

[0154] Figure 33 is a top view of the word line WCX(j,k+1) extending in the X direction and connected to the cell gate CG(i,j,k+1). In other words, it is a view cut horizontally to the XY plane at the layer of CG(i,j,k+1). Even taking into account manufacturing variations, the word line width must always be larger than the vertical hole (CV) opened to create the channel section. Therefore, there must be a sufficient margin between the word line width and the size of the CV.

[0155] The inside of the channel via (CV) is made up of the following layers from the center: core, tunnel oxide film (or simply tunnel oxide), charge storage layer, layer ), a block film, a control gate, etc. The core is the channel part through which current flows when the switch is turned on, and can be made of polysilicon, for example. The tunnel oxide film is a thin film through which electrons or holes can pass by quantum tunneling, and can be made of a thin insulating film such as silicon oxide, for example. However, quantum tunneling is quoted as a representative example of Fowler-Nordheim tunneling (FN tunneling) and direct tunneling, etc. The charge storage layer can store electrons and holes that have passed through the tunnel oxide film from the core, and can be made of a thin insulating film such as silicon nitride. Incidentally, storing electrons or holes from the core in the charge storage layer by quantum tunneling is called writing (programming). Conversely, storing electrons or holes by quantum tunneling is charge storage layerErasing refers to the process of extracting electrons or holes from the charge storage layer to the core. The block film is used to confine the electrons and holes stored in the charge storage layer so that they do not escape to the control gate, and can be made of a fairly thick insulating film such as a high-dielectric oxide film. A high dielectric constant is required to make the block film as thick as possible to increase the confinement effect. The control gate is connected to the word line and controls the electric field applied by the word line to the core, and can be made of a thin film of conductive material such as metal. As shown in the cross-sectional view of Figure 33, it is a cylindrical conductive thin film (cylindrical conductive film).

[0156] FIG. 34 is a top view of a word line WUX(j, k+1) extending in the X direction and connected to an upper select gate SGU(i, j, k+1). That is, it is a diagram cut horizontally to the XY plane at the layer of SGU(i, j, k+1). The word line width is approximately 1 / 2 sq. m, even when manufacturing variations are taken into consideration. Channel Section To make vertical It must always be larger than the hole (CV). Therefore, there must be a sufficient margin between the word line width and the size of the CV. The contents of the CV are the same as in Figure 33, so we will not explain them here. However, since it is used as a select gate even though the coaxial structure is the same, the write state to the charge storage layer only requires that Vt be adjusted so that a constant output current (saturation current) flows when Vpass is applied to the word line. As an example, it is desirable for Vt to always remain within the range of Vread in Figure 12.

[0157] Figure 35 shows a top view of the Y-direction word line WDY(i,k+1) connected to the lower select gate SGD(i,j,k+1). That is, it is a view cut horizontally in the XY plane at the SGD(i,j,k+1) layer. The word line width must always be larger than the hole (CV) for the word line, even taking into account manufacturing variations. Therefore, a sufficient margin is required for the difference between the word line width and the CV size. The contents of the CV are similar to those in Figure 33, so a detailed explanation is omitted. However, since it is used as a select gate despite the same coaxial structure, the write state of the charge storage layer only requires that Vt be adjusted so that a constant output current (saturation current) flows when Vpass is applied to the word line. As an example, it is desirable for Vt to always remain within the Vread range shown in Figure 12.

[0158] FIG. 36 is a top view of the word line WCX(j, k) extending in the X direction and connected to the cell gate CG(i, j, k). That is, it is a diagram cut horizontally in the XY plane at the layer of CG(i, j, k). The word line width is Channel Section To make vertical It must always be larger than the hole (CV). Therefore, there must be a sufficient margin between the word line width and the CV size. The contents of the CV are the same as those in Figure 33, so the explanation will be omitted.

[0159] Figure 37 shows a top view of a word line WUY(i,k) extending in the Y direction and connected to an upper select gate SGU(i,j,k). This is a view cut horizontally across the XY plane at the SGU(i,j,k) layer. The word line width must always be larger than the hole (CV) used to create the word line, even taking into account manufacturing variations. Therefore, a sufficient margin is required for the difference between the word line width and the CV size. The contents of the CV are similar to those in Figure 33, so a detailed explanation is omitted. However, because it is used as a select gate despite having the same coaxial structure, the write state of the charge storage layer can be achieved by adjusting Vt so that a constant output current (saturation current) flows when Vpass is applied to the word line. As an example, it is desirable for Vt to always remain within the Vread range shown in Figure 12. The explanation of FIG. 38 is omitted because it is almost the same as the explanation of FIG.

[0160] As described above, the cross-sectional view of one module in the Z-direction in the ZX plane can be explained. Figure 39 shows an example where three Z-direction modules are lined up in the X-direction. Figure 10 is a diagram showing an example of an equivalent circuit corresponding to Figure 39.

[0161] Figure 40 shows the module in the Z direction at address YZ (i,j) as seen from a cross section in the ZY plane. Figure 30 shows the same module as seen from a cross section in the ZX plane. The explanation is the same as for Figures 30 to 38, so it will be omitted here.

[0162] Fig. 41 shows three modules of Fig. 40 arranged in the Y-axis direction. Fig. 11 is a diagram showing an example of an equivalent circuit corresponding to Fig. 41.

[0163] Figure 42 shows an example of the internal structure of the core described in Figures 33 to 38. As described above, the core is surrounded by a tunnel oxide film, a charge storage layer, a block film, and a control gate. However, the tunnel oxide film can be replaced with another tunnel film.

[0164] As an example, the core can be further divided into a dielectric core and a channel silicon from the center. The dielectric core is made of a dielectric or insulating material, and the channel silicon is made of silicon, amorphous silicon, polysilicon, or other material, and serves as the channel portion of the device through which current flows when the device is switched on. When the channel silicon is polysilicon, this structure is used to reduce the average grain size of the channel silicon and suppress variations in the current flowing through the channel silicon. Furthermore, the core is shared by at least three devices connected in series in the Z-axis direction, and the channel silicon serves as a channel portion shared by the three devices connected in series in the Z-axis direction. Therefore, when current flows in the channel portion, it is when current flows across the three devices connected in series. (Sixth embodiment)

[0165] It is generally known that the channel vias of three-dimensional (3D) NAND flash can be manufactured by the gate-last method (see Non-Patent Document 4). However, the device structure of the present application has a two-order periodicity in the Z direction as described above. To manufacture the two-order periodicity in the Z direction characteristic of the present application, a manufacturing method different from the general gate-last method is required.

[0166] First, before explaining the features of the present invention, we will start by explaining the general gate-last method.

[0167] Figures 43 and 44 are diagrams for simply explaining the general gate-last method.

[0168] First, as shown in (a) in the figure, oxide and nitride films are stacked alternately in the Z-axis direction (vertical direction in the drawing). The horizontal axis in the drawing corresponds to the X-axis direction. Next, as shown in (b), vertical holes are drilled through the stacked oxide and nitride films (Etch hole), the side walls are covered with polysilicon (Poly on wall), and the oxide film is filled in (Fill oxide). Next, slits are dug in a location separate from the vertical holes (Etch slit). The slits extend in the Y-axis direction. The angle at which the X and Y axes intersect can be any angle other than 180 degrees (or zero degrees), but a 90-degree angle has the potential to maximize the density of vertical holes in the XY plane.

[0169] Next, a gas that strips the nitride film is injected through the slit, and after removing the nitride film, a tunnel oxide film is deposited. Next, a charge trapping layer is formed and a high-k dielectric film (High-K) is applied, resulting in the cross-sectional view shown in (e). However, to clarify the charge trapping layer, which is difficult to depict due to space limitations, (f) is an enlarged view of the dashed line area. In this way, a charge storage layer is formed sandwiched between the tunnel oxide film and the high-k dielectric film.

[0170] Next, as shown in (g), a metal gate is formed (metal gate fill). Then, as shown in (h), the metal gate and part of the high-k dielectric film are etched (Etch metal & high-K) and stripped away. In this way, as shown in (i), the low-k dielectric film is filled (fill low-K).

[0171] The gate-last method is commonly used in the fabrication of 3D NAND flash. In the cross-sectional view (i), the poly-on-wall extending vertically (in the Z-axis direction) is the channel, which serves as the charge path for 3D NAND flash. This channel resembles a cylindrical shell with the oxide film deposited in (b) as its core, surrounded by a tunnel oxide film, charge trap layer, high-k dielectric film, and metal gate. Therefore, the metal gate has a circular shell (doughnut shape), and each metal gate corresponds to one cell (or memory cell). In this cross-sectional view, four metal gates are integrated to share the vertically extending channel. In other words, multiple vertically integrated gates are connected in series, which is a characteristic of 3D NAND. In this application, three vertically connected cells are considered to form one unit. The top one is designated the upper select gate (SGU), the middle one the cell gate (CG), and the bottom one the lower select gate (SGD). A further feature of the present application is that the upper side of each unit is connected to one of BLX and BLY, and the lower side is connected to the other.

[0172] However, in the present invention, bit lines BLX extending in the X direction and bit lines BLY extending in the Y direction are alternately laid out as shown in Figure 9. This feature is not found in conventional 3D NAND flash.

[0173] For example, in Figure 9, six gates are connected in series between two BLXs (BLX(j,k-2) and BLX(j,k)). From the bottom up, the gates are SGD(i,j,k-1), CG(i,j,k-1), SGU(i,j,k-1), SGD(i,j,k), CG(i,j,k), and SGU(i,j,k). Between SGU(i,j,k-1) and SGD(i,j,k) is a connection to BLY(i,k-1).

[0174] The word line WDY(i,k-1) connected to the gate electrode (or metal gate) of SGD(i,j,k-1) extends in the Y-axis direction. The word line WCX(j,k-1) connected to the gate electrode (or metal gate) of CG(i,j,k-1) extends in the X-axis direction. The word line WUX(j,k-1) connected to the gate electrode (or metal gate) of SGU(i,j,k-1) extends in the X-axis direction.

[0175] The word line WDX(j,k) connected to the gate electrode (or metal gate) of SGD(i,j,k) extends in the X-axis direction. The word line WDX(j,k) connected to the gate electrode (or metal gate) of CG(i,j,k) extends in the X-axis direction. The word line WUY(i,k) connected to the gate electrode (or metal gate) of SGU(i,j,k) extends in the Y-axis direction.

[0176] In other words, in the present application, the word line directions are cyclically repeated as follows: one in the Y direction (WDY(i, k-1)), two in the X direction (WCX(j, k-1), WUX(j, k-1)), two in the X direction (WDX(j, k), WCX(j, k)) sandwiched between BLY(i, k-1), and one in the Y direction (WUY(j, k)).

[0177] In FIG. 43(c), the slits are cut only in the Y-axis direction, so with the conventional gate-last method, it is not possible to form word lines periodically in the X and Y directions as in the present invention.

[0178] The manufacturing method of the present invention will be described in detail below with reference to the drawings.

[0179] 45 shows how metal that will become bit lines is patterned on a substrate. The upper row is a cross-sectional view in the ZY plane, and the lower row is a cross-sectional view in the ZX plane.

[0180] First, a metal film (or simply metal) is deposited (depo metal), and then the metal film is patterned (patterning). In this figure, as an example, the patterning of the bit line BLX extending in the X direction is used. If the X and Y axes are swapped, the explanation becomes as to the patterning of the bit line BLY extending in the Y direction.

[0181] After patterning, an oxide film is deposited (depo oxide). (ay) is a cross section in the ZY plane, and (ax) is a cross section in the ZX plane. Patterning has already formed bit lines BLX extending in the X direction. Normally, this is followed by a chemical-physical process (CMP) to flatten the surface of the deposited oxide film. However, the deposited oxide film is also thinned by being scraped away. The thickness of the deposited oxide film must be controlled taking into account the reduction in film thickness due to CMP, etc. (by) is a cross section in the ZY plane, and (bx) is a cross section in the ZX plane.

[0182] Figure 46 is a view from above (in the XY plane). (a) shows the case where the bit lines are patterned to extend in the X direction, which corresponds to the case described in Figure 45. (b) shows the case where the bit lines are patterned to extend in the Y direction. Either patterning can be freely selected.

[0183] Figure 45 illustrates an example in which a substrate (Sub) such as a silicon substrate is patterned, but the substrate surface does not necessarily have to be flat. A metal film deposited on a suitably patterned substrate surface may be patterned as needed. Alternatively, a metal film deposited on suitably patterned polysilicon may be patterned. In either case, as explained in Figure 46, it is necessary to intentionally pattern the metal film in the X or Y direction. Furthermore, as explained in Figures 45(by) and (bx), it is desirable to deposit an oxide film after metal patterning and planarize it using CMP or similar methods. Considering compatibility with silicon or polysilicon, it is also desirable for the metal film to be a silicide.

[0184] 47 to 60 illustrate a manufacturing process for forming an example of the features of the present application on a metal film patterned to extend in the X direction.

[0185] Figure 47(a) shows a cross-sectional view of a metal layer (Metal) covered with a deposited oxide layer planarized by CMP or other methods, with a nitride layer, oxide layer, nitride layer, and oxide layer laminated in layers. The metal layer is patterned to extend in the X direction, forming the bit line BLX extending in the X direction. This corresponds to Figure 46(a). The metal layer can also be silicide. The nitride layer, which will later become the gate, is common to the gate-last method. In other words, in this example, two cells are connected in series along the Z axis (vertical direction). If only one nitride layer is used, only one cell is formed in the Z axis direction. If three nitride layers are used, three cells are connected in series along the Z axis. The number of cells connected in series along the Z axis can be determined by the number of nitride layers laminated. Here, two cells are connected in series along the Z axis as an example.

[0186] (b) Next, a vertical hole is opened (Etch hole), N+ type polysilicon (N+ poly) is deposited, and planarized by CMP or the like. (c) The N+ polysilicon is selectively etched, and then planarized by CMP or the like. The thin film of N+ polysilicon remaining at the bottom of the vertical hole becomes the contact to the BLX.

[0187] Figure 48(d) The sidewalls of the vertical hole are covered with polysilicon (poly on wall), and an oxide film is deposited to seal the vertical hole. (e) Slits are cut in the Y-axis direction (Y-etch slits), and (f) etching gas is injected through the slits to selectively strip off only the nitride film. Then a tunnel oxide film is deposited.

[0188] Figure 49(g) After forming a charge trap layer on the sidewall, it is covered with a high-dielectric film (High-K). (g1) is an enlarged view of the dotted line area. The charge trapping layer is sandwiched between the tunnel oxide film and the high-dielectric film.

[0189] Figure 50(h) The slit is covered with metal (metal gate fill) to become a metal gate later. (i) The metal and part of the high-k dielectric film are stripped off (Etch metal & high-K), and a low-k dielectric film is deposited in the slit (fill low-K), after which the surface is planarized using CMP or other methods.

[0190] In Figure 51, an oxide film, a nitride film, and an oxide film are laminated on top of that. Since the nitride film that will later become the gate is a single layer, here, as an example, one cell is added vertically. (kx) is a cross-sectional view of the ZX plane, and (ky) is a cross-sectional view of the Z- Y FIG.

[0191] Figure 52 begins at (ky) in Figure 51. In other words, we move from this drawing to a ZY cross section and continue the explanation. (l) Etch holes into the oxide film that was first applied in Figure 51. At this time, the position of the holes in the XY plane should be aligned as closely as possible with the position of the holes opened in Figure 47. Polysilicon is then deposited. Furthermore, it is desirable to flatten the surface using CMP or similar.

[0192] (m) The polysilicon is partially stripped away, leaving only the sidewalls (remove poly), and (n) an oxide film is deposited to fill the vertical hole. (o) Slits are then cut in the X-axis direction (X-etch slits). Cutting slits while alternating between the X-axis and Y-axis directions is one of the features of the manufacturing method of this application.

[0193] Figure 53(p) Gas is injected through the slit to selectively strip away the nitride film (remove nitride). Next, a tunnel oxide film is deposited, a charge trapping layer is formed, and then a high-k dielectric film is applied (high-K fill). (p1) Enlarging the dotted line area shows that the charge trapping layer is sandwiched between the tunnel oxide film and the high-k dielectric film.

[0194] Figure 54 starts with (p). (q) The slit is filled with metal (film) that will later become the metal gate (metal gate fill). (r) Some of the metal and high-k dielectric film inside the slit are stripped away, leaving only the area that will become the metal gate (etch metal & high-K). (sy) A low-k dielectric film is deposited in the slit, and the surface is planarized using CMP or similar.

[0195] In Figure 55, N+ polysilicon, which will later become the contact for the Y-direction bit line BLY, is patterned. Specifically, resist is patterned and N+ polysilicon is deposited to align with the vertical hole (align, resist patterning, N+poly depo). After planarizing the surface using CMP or similar, the resist is stripped off, an oxide film is deposited, the surface is planarized using CMP or similar, and a metal film that will later become BLY is deposited. It is desirable to further planarize the surface using CMP or similar. (tx) is a cross-sectional view in the ZX plane, and (ty) is a cross-sectional view in the ZY plane.

[0196] In Figure 56, resist is then patterned on the deposited metal film, and after etching the metal, a low-dielectric film is filled in the gaps (metal patterning or subtractive method), and then an oxide film is deposited and the surface is planarized by CMP or the like. (ux) is a cross-sectional view of the ZX plane, and (uy) is a cross-sectional view of the ZY plane. However, the metal patterning can also be replaced with a damascene process or the like.

[0197] In either case, this forms the Y-direction bit line BLY. In this example, three gates are connected in series from the bottom between BLX and BLY, forming one unit consisting of one cell sandwiched between two select gates. Both ends of the vertically extending channel are contacted with N+ polysilicon. BLX is located below the bottom N+ polysilicon, and BLY is located on top of the top N+ polysilicon. Each of the three layers of gate metal becomes a word line. The bottom two word lines extend in the Y direction, and the top word line extends in the X direction.

[0198] In Figure 57, a nitride film, an oxide film, a nitride film, and an oxide film are laminated on top of that. Here, since there are two nitride film layers, the number of cells that can be stacked on top of this is two. (vx) is a cross-sectional view of the ZX plane, and (vy) is a cross-sectional view of the ZY plane.

[0199] In Figure 58, a vertical hole is dug in the stacked oxide-nitride layers to align with the position of the underlying contact (N+ polysilicon) of the BLY. Next, N+ polysilicon is deposited (N+poly depo), and the surface is planarized by CMP or other methods. (wx) is a cross-sectional view in the ZX plane, and (wy) is a cross-sectional view in the ZY plane.

[0200] In Figure 59, the N+ polysilicon in the vertical hole is appropriately etched (etch N+poly), and the N+ polysilicon remaining at the bottom of the vertical hole is used as the upper contact to the BLY. The sidewalls are covered with polysilicon (poly on wall), the inside is filled with an oxide film (fill oxide), and the surface is then planarized by CMP or other methods. (w2x) is a cross-sectional view in the ZX plane, and (w2y) is a cross-sectional view in the ZY plane.

[0201] FIG. 60 is a cross-sectional view when (b) is selected in FIG. 46. Since the Y-direction bit line BLY is formed at the bottom, the upper bit line is BLX in the X direction. In other words, BLX and BLY are exchanged (replace BLX&BLY). The other manufacturing processes are exactly the same as those in FIG. 59. In other words, the direction in which the bit line is patterned is changed. 46 59. Therefore, detailed explanations will be omitted to avoid duplication. (zx) is a cross-sectional view in the ZX plane, and (zy) is a cross-sectional view in the ZY plane.

[0202] Figure 61 shows Figure 59 with X and Y swapped. Swapping the X and Y directions is a coordinate conversion between right-handed and left-handed systems, and there is no change in the fabricated device structure. (w3x) is a cross-sectional view in the ZX plane, and (w3y) is a cross-sectional view in the ZY plane. After this, slits are made in the X-axis direction, and the process of forming word lines in the X direction begins. The process from this point onwards is the same as Figure 48(e) onwards, so a description will be omitted. Rather, the purpose of Figure 61 is to clarify that the structure sandwiched between BLX and BLY corresponds to one unit in Figure 9.

[0203] Figure 62 compares (w3x) in Figure 61 with a portion (1 unit) of the module in Figure 9. It can be seen that BLX in Figure 61 corresponds exactly to BLX(j, k+1) in Figure 9, and BLY in Figure 61 corresponds to BLY(i, k) in Figure 9.

[0204] Figure 63 shows a device structure obtained by changing the combination of the number of nitride film layers in Figure 59. That is, the number of nitride film layers stacked in Figure 47 is changed from 2 to 1, and the number of nitride film layers stacked in Figure 51 is changed from 1 to 2, but otherwise it is a cross-sectional view of a device structure obtained by going through the same manufacturing processes as in Figures 47 to 59. (w4x) is a cross-sectional view in the ZX plane, and (w4y) is a cross-sectional view in the ZY plane.

[0205] In Figure 64, (w4x) in Figure 63 is compared with a part (1 unit) of the module in Figure 9. BLX(j, k-2) 9, and it can be seen that BLY in FIG. 64 corresponds to BLY(i, k) in FIG.

[0206] Thus, according to this embodiment, it is possible to manufacture a device structure having a two-fold periodicity in the Z-axis direction, which is characteristic of the present invention. Note that the two-fold periodicity means that the same structure can be obtained by shifting the value of the Z address (k) by 2 in both the cross-sectional view in the ZX plane and the cross-sectional view in the ZY plane. (Seventh embodiment)

[0207] In 3D integrated circuits, the number of word lines and bit lines generally tends to increase with the number of layers in the Z-axis (vertical) direction, and the number of contacts to peripheral circuits also tends to be larger than in 2D integrated circuits. Therefore, ingenuity in contact methods is required to save chip area. Naturally, the characteristics of the core device structure affect the contact method.

[0208] In this application, there is a feature of second-order periodicity of Z addresses (k). How this affects the method of contacting peripheral circuits will be explained in detail using drawings.

[0209] Figure 65 is a diagram for explaining how to make contacts between the word line group (WUX and WCX group) and the bit line group (BLX group) extending in the X-axis direction. Note that this figure illustrates a module located at the end of the X-axis direction (i=Lx) with Z addresses from k+1 to k-2.

[0210] Generally, the size of the contact parts (MC0 and MC1) is larger than the diameter of the metal via part dug in the Z-axis direction. Therefore, it is desirable that adjacent contact parts are divided into the wiring metal 0 layer (M0 layer) (or simply the metal 0 layer) and the wiring metal 1 layer (M1 layer) (or simply the metal 1 layer) and arranged alternately. However, the contact on the M0 layer is MC0, and the contact on the M1 layer is MC1.

[0211] However, in this application, due to the second-order periodicity of the Z addresses (k), not all word lines and bit lines extend in the X direction. In the example of FIG. WDY(Lx, k+1), WUY(Lx, k) and WDY(Lx, k-1) are , are word lines extending in the Y direction. BLY(Lx, k+1) and BLY(Lx, k-1) are bit lines extending in the Y direction.

[0212] In Figure 65, the contact of WUX(j, k+1) is MC0, the contact of WCX(j, k+1) is MC1, the contact of BLX(j, k) is MC0, the contact of WCX(j, k) is MC1, the contact of WDX(j, k) is MC0, the contact of WUX(j, k-1) is MC1, the contact of WCX(j, k-1) is MC0, and the contact of BLX(j, k-2) is MC1.

[0213] Figure 66 is a module that follows Figure 65, and the Z addresses are from k-1 to k-4. The contact of WUX(j, k-1) is MC1, the contact of WCX(j, k-1) is MC0, the contact of BLX(j, k-2) is MC1, the contact of WCX(j, k-2) is MC0, the contact of WDX(j, k-2) is MC1, the contact of WUX(j, k-3) is MC0, the contact of WCX(j, k-3) is MC1, and the contact of BLX(j, k-4) is MC0.

[0214] Figure 67 is a module that follows Figure 66, and the Z addresses are from k-3 to k-6. The contact of WUX(j, k-3) is MC0, the contact of WCX(j, k-3) is MC1, the contact of BLX(j, k-4) is MC0, the contact of WCX(j, k-4) is MC1, the contact of WDX(j, k-4) is MC0, the contact of WUX(j, k-5) is MC1, the contact of WCX(j, k-5) is MC0, and the contact of BLX(j, k-6) is MC1.

[0215] Figure 68 is a module that follows Figure 67, and the Z addresses are from k-5 to k-8. The contact of WUX(j, k-5) is MC1, the contact of WCX(j, k-5) is MC0, the contact of BLX(j, k-6) is MC1, the contact of WCX(j, k-6) is MC0, the contact of WDX(j, k-6) is MC1, the contact of WUX(j, k-7) is MC0, the contact of WCX(j, k-7) is MC1, and the contact of BLX(j, k-8) is MC0.

[0216] Figure 69 shows which word line or bit line each contact is connected to, divided into the M1 layer and the M0 layer.

[0217] According to Figure 69, in order to reduce the area occupied by contacts to the peripheral circuitry for Y address (j), a fourth-order periodicity (period of M1) appears in the Z-axis direction for the set of WUX(j,k+3), BLX(j,k+2), WDX(j,k+2), WCX(j,k+1), and WCX(j,k) arranged in the X-axis direction on the M1 layer. That is, the same pattern appears when Z address (k) is shifted by four. As is clear from Figures 65 to 68, as we move in the X-address direction, the word lines and bit lines to which the contacts connect also become deeper, and the number of Z addresses increases. In other words, this contact pattern in the X-axis direction is related to the structure in the Z-axis direction.

[0218] Similarly, on the M0 layer, aligned in the X-axis direction WUX (j, k+1), BLX (j, k), WDX (j, k), WCX (j, k-1), WCX (j, k-2) A fourth-order periodicity (period of M0) appears in the Z-axis direction in the set. In other words, the same pattern appears when the Z address (k) is shifted by 4. This contact pattern in the X-axis direction is related to the structure in the Z-axis direction. In particular, the fourth-order periodicity appears because the contacts are divided and laid out in the X-axis and Y-axis directions, as will be explained later.

[0219] Let's consider shifting the Y address from j to j+1 one by one. In this case, it is also necessary to alternately allocate the contacts adjacent in the Y-axis direction to the M0 layer and the M1 layer. Therefore, for the Y address (j+1), the contacts arranged in the X-axis direction on the M0 layer WUX(j+1, k+3), BLX (j+1, k+2), WDX (j+1, k+2), WCX (j+1, k+1), WCX (j+1, k) A fourth-order periodicity (period of M0) occurs in the Z-axis direction in the set of M0. Also, the M1 layer is aligned in the X-axis direction. WUX (j+1, k+1), BLX (j+1, k), WDX (j+1, k), WCX (j+1, k-1), WCX (j+1, k-2) A fourth-order periodicity (period of M1) appears in the set of

[0220] FIG. 70 is a diagram showing an example of a layout of MC0 and MC1 on the XY plane so as to satisfy the above-mentioned fourth-order periodicity in the Z-axis direction.

[0221] Figure 71 is a diagram for explaining how to make contacts between the word line group (WDY and WUY group) and the bit line group (BLY group) extending in the Y-axis direction. Note that this diagram illustrates a module located at the end of the Y-axis direction (i=Ly) with Z addresses from k+1 to k-2.

[0222] As mentioned above, although the Z addresses have a second-order periodicity in this application, not all word lines and bit lines extend in the Y direction. In the example of Figure 71, WUX(Ly,k+1), WCX(Ly,k+1), WCX(Ly,k), WDX(Ly,k), WUX(Ly,k-1), and WCX(Ly,k-1) are word lines extending in the X direction. BLX(Ly,k) and BLX(Ly,k-2) are bit lines extending in the X direction. However, this cell is located at the end (Ly) in the Y direction. WDY(i,k+1), WUY(i,k), and WDY(i,k-1) are word lines extending in the Y direction. BLY(i,k+1) and BLY(i,k-1) are bit lines extending in the Y direction.

[0223] In Figure 71, the contact of BLY(i, k+1) is MC0, the contact of WDY(i, k+1) is MC1, the contact of WUY(i, k) is MC0, the contact of BLY(i, k-1) is MC1, and the contact of WDY(i, k-1) is MC0.

[0224] Figure 72 is a module that follows Figure 71, and the Z addresses are k-1 to k-4. The contact of BLY(i, k-1) is MC1, the contact of WDY(i, k-1) is MC0, the contact of WUY(i, k-2) is MC1, the contact of BLY(i, k-3) is MC0, and the contact of WDY(i, k-3) is MC1.

[0225] Figure 73 is a module that follows Figure 72, and the Z addresses are k-3 to k-6. The contact of BLY(i, k-3) is MC0, the contact of WDY(i, k-3) is MC1, the contact of WUY(i, k-4) is MC0, the contact of BLY(i, k-5) is MC1, and the contact of WDY(i, k-5) is MC0.

[0226] Figure 74 is a module that follows Figure 73, and the Z addresses are k-5 to k-8. The contact of BLY(i, k-5) is MC1, the contact of WDY(i, k-5) is MC0, the contact of WUY(i, k-6) is MC1, the contact of BLY(i, k-6) is MC0, and the contact of WDY(i, k-7) is MC1.

[0227] FIG. 75 shows which word line or bit line each contact is connected to, divided into the M1 layer and the M0 layer.

[0228] According to FIG. 75, in order to reduce the area occupied by contacts to the peripheral circuit for the X address (i), BLY(i, k-1), WUY (i, k-2), WDY (i, k-3) In the Z-axis direction 3 A periodicity of M1 appears. That is, if Z address (k) is 3The same pattern appears when the contacts are shifted. As is clear from Figures 71 to 74, as we move in the Y address direction, the word lines and bit lines to which the contacts connect also become deeper, and the number of Z addresses increases. In other words, this contact pattern in the Y axis direction is related to the structure in the Z axis direction.

[0229] Similarly, on the M0 layer, aligned in the X-axis direction BLY (i, k+1), WUY (i, k), WDY (i, k-1) In the Z-axis direction 3 A periodicity of M0 appears. That is, if Z address (k) is 3 The same pattern appears when the contact is shifted. This contact pattern in the Y-axis direction is related to the structure in the Z-axis direction. In particular, 3 The reason why this appears as a step periodicity is that the contacts are laid out in a divided manner in the X-axis direction and the Y-axis direction, as will be explained later.

[0230] Let's consider shifting the X address from i to i+1 one by one. In this case, it is necessary to alternately allocate the contacts adjacent in the X-axis direction to the M0 layer and the M1 layer. Therefore, for the X address (i+1), the contacts arranged in the Y-axis direction on the M0 layer BLY(i+1, k-1), WUY (i+1, k-2), WDY (i+1, k-3) A fourth-order periodicity (period of M0) occurs in the Z-axis direction in the set of M0. Also, a fourth-order periodicity (period of M0) occurs in the set of M1 aligned in the Y-axis direction on the M1 layer. 3 A periodicity of M1 appears.

[0231] FIG. 76 shows the above 3 10 is a diagram showing an example of layout of MC0 and MC1 on the XY plane so as to satisfy the step periodicity.

[0232] 77 to 80 are diagrams showing an example of layout of bit lines, bit line contacts, word lines, and word line contacts on the XY plane.

[0233] As shown in Figures 65 and 71, BLX(*, k) is sandwiched between WDY(*, k+1) and WUY(*, k) on the top and bottom. Figure 77 is a diagram showing an example of layout of BLX(*, k), WDY(*, k+1), contact MC0, and contact MC1 on the XY plane. On the Z axis, WDY(*, k+1) is above BLX(*, k). Also, for example, the contact of BLX(j, k) is on the M0 layer, the contact of BLX(j+1, k) is on the M1 layer, the contact of WDY(i-1, k+1) is on the M0 layer, and the contact of WDY(i, k+1) is on the M1 layer.

[0234] Figure 78 is a diagram showing an example of layout of BLX(*,k), WUY(*,k), contact MC0, and contact MC1 on the XY plane. WUY(*,k) on the Z axis is below BLX(*,k). Also, for example, the contact of WUY(i-1,k) is on the M1 layer, and the contact of WUY(i,k) is on the M0 layer.

[0235] As shown in Figure 65 and Figure 71, BLY(*, k-1) is WDX(*, k) above and below. WUX(*, k-1) FIG. 79 is a diagram showing an example of layout of BLY(*, k-1), WDX(*, k), contact MC0, and contact MC1 on the XY plane. WDX(*, k) on the Z axis is above BLY(*, k-1). Also, for example, the contact of BLY(i, k-1) is on the M1 layer, the contact of BLY(i+1, k-1) is on the M0 layer, the contact of WDX(j, k) is on the M0 layer, and the contact of WDX(j+1, k) is on the M1 layer.

[0236] FIG. 80 is a diagram showing an example of layout of BLY(*, k-1), WUX(*, k-1), contact MC0, and contact MC1 on the XY plane. WUX(*, k-1) on the Z axis is below BLY(*, k-1). Also, for example, the contact of WUX(j, k-1) is on the M1 layer, and the contact of WUX(j+1, k-1) is on the M0 layer.

[0237] [Non-Patent Document 1] Goodon E. Moore, “Cramming more components onto integrated circuits”, Electronics, volume 38, Number 8, April 19, 1965. [Non-patent document 2] Masanet, E.; Shhehabi, A.; Lei, N.; Smith, S.; Koomey, J. Recalibrating global data center energy-use estimates. Science 2020, vol. 3667, 984―986. [Non-patent document 3] CC Lu et al., "Analysis and Realization of TLC or even QLC Operation with a High-Performance Multi-Times Verify Scheme in 3D NAND Flash memory," 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 2.2.1―2.2.4, doi: 10.1109 / IEDM.2018.8614548. [Non-patent document 4] J.-H. Jang et al., "Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High-Density NAND Flash Memory," the 2009 Symmposium on VLSI Technology Digest of Technical Papers, pp. 192-193, 2009. (Eighth Embodiment)

[0238] It is sometimes desirable for the width of the bit lines and word lines to be wide enough to include multiple channel vias. This is related to the reliability of the channel via manufacturing. The deeper (longer) the channel via is, the more likely it is that the channel via will collapse during manufacturing. To prevent this, a method of reinforcing it with bit lines or word lines is sometimes used. This will be explained in detail using Figures 81 to 96.

[0239] Figure 81 is a drawing corresponding to Figure 31 and shows an example of the width of the Y-direction bit line. The differences from Figure 31 are that two rows of channel vias are lined up within the width of the Y-direction bit line, and that the two channel vias are bundled together into one bit line contact. In contrast, in Figure 31, only one row of channel vias is lined up within the width of the Y-direction bit line. This prevents the channel vias from easily tilting in the X direction. Looking at the cross section taken along A-A' (right figure), it can be seen that the channel vias are resting on the left end of the Y-direction bit line.

[0240] Figure 82 is a diagram corresponding to Figure 31, and shows another example of the width of the Y-direction bit line. It is characterized in that three channel vias are bundled together into one bit line contact.

[0241] Figure 83 is a diagram corresponding to Figure 31, and shows another example of the width of the Y-direction bit line. It is characterized in that four channel vias are bundled together into one bit line contact.

[0242] 84 is a drawing corresponding to FIG. 31 and shows another example of the width of the Y-direction bit line. It is characterized in that three rows of channel vias are lined up within the width of the Y-direction bit line and five channel vias are bundled together into one bit line contact.

[0243] Figure 85 is a drawing corresponding to Figure 32 and shows an example of the width of the X-direction bit line. The difference from Figure 32 is that two rows of channel vias are arranged within the width of the X-direction bit line, and two channel vias are bundled together into one bit line contact. In contrast, in Figure 32, only one row of channel vias is arranged within the width of the X-direction bit line. This prevents the channel vias from easily tilting in the Y direction. Looking at the cross section taken along B-B' (right figure), it can be seen that the channel vias are aligned with the left end of the Y-direction bit line.

[0244] Figure 86 is a diagram corresponding to Figure 32, and shows another example of the width of the X-direction bit line. It is characterized in that three channel vias are bundled together into one bit line contact.

[0245] Figure 87 is a diagram corresponding to Figure 32, and shows another example of the width of the X-direction bit line. It is characterized in that four channel vias are bundled together into one bit line contact.

[0246] Figure 88 is a drawing corresponding to Figure 32, and shows another example of the width of the X-direction bit line. It is characterized by the fact that three rows of channel vias are lined up within the width of the X-direction bit line, and that five channel vias are bundled together into one bit line contact.

[0247] FIG. 89 is a drawing corresponding to FIGS. 33, 34, 36, and 38, and shows an example of the width of the X-direction word line. The differences from FIGS. 33, 34, 36, and 38 are that the channel vias are arranged in two rows within the width of the X-direction word line, and that two channel vias are bundled together into one cell gate or select gate (CG, SGU, SGD). In contrast to this, in FIGS. 33, 34, 36, and 38, Within the width of the X-direction word line There is only one row of channel vias, which prevents the channel vias from easily falling in the Y direction.

[0248] 90 is a drawing corresponding to FIGS. 33, 34, 36, and 38, and shows another example of the width of the X-direction word line. It is characterized in that two rows of channel vias are arranged within the width of the X-direction word line, and that three channel vias are bundled together into one cell gate or select gate (CG, SGU, SGD).

[0249] 91 is a drawing corresponding to FIGS. 33, 34, 36, and 38, and shows another example of the width of the X-direction word line. It is characterized in that the channel vias are arranged in two rows within the width of the X-direction word line, and that four channel vias are bundled together into one cell gate or select gate (CG, SGU, SGD).

[0250] 92 is a drawing corresponding to FIGS. 33, 34, 36, and 38, and shows another example of the width of the X-direction word line. It is characterized in that the channel vias are arranged in three rows within the width of the X-direction word line, and that five channel vias are bundled together into one cell gate or select gate (CG, SGU, SGD).

[0251] FIG. 93 is a drawing corresponding to FIGS. 35 and 37, and shows an example of the width of the Y-direction word line. The differences from FIGS. 35 and 37 are that two rows of channel vias are arranged within the width of the Y-direction word line, and that the two channel vias are bundled together into one select gate (SGD, SGU). In contrast, in FIGS. 35 and 37, only one row of channel vias is arranged within the width of the Y-direction bit line. This prevents the channel vias from easily tilting in the X direction.

[0252] 94 is a drawing corresponding to FIGS. 35 and 37, and shows another example of the width of the Y-direction word line. It is characterized in that three channel vias are bundled together into one select gate (SGD, SGU).

[0253] FIG. 95 is a drawing corresponding to FIGS. 35 and 37, and shows another example of the width of the Y-direction word line. 4 channel vias A distinctive feature is that these are bundled together into a single select gate (SGD, SGU).

[0254] 96 is a drawing corresponding to FIGS. 35 and 37, and shows another example of the width of the Y-direction word line. It is characterized in that three rows of channel vias are arranged within the width of the Y-direction word line, and five channel vias are bundled together into one select gate (SGD, SGU).

[0255] As described above, it is desirable to combine multiple channel vias into one bit line contact, cell gate, or select gate. In this case, the number of channel vias combined into one is not limited to 2-5. The arrangement of channel vias combined into one is not limited to those shown in Figures 81-96.

[0256] When the number of channel vias grouped together is two or more, the number of columns of channel vias aligned in the direction of the word line or bit line must be at least two. Therefore, it is desirable for the width of the word line or bit line to be at least twice the diameter of the channel via. The reason for this can be easily explained using Figure 97. The ends of the word line or bit line are represented by lines (0) and (1). In other words, the width of the word line or bit line is the distance between lines (0) and (1). It is considered that the most efficient way to save width in the direction of dashed lines (A)-(D) is when half of the two columns of channel vias (CV) overlap horizontally. In this case, the width in the direction of dashed lines (A)-(D) is about three times the radius of the channel via. If a margin about the radius of the channel via is left outside (A) and outside (B), the distance between lines (0) and (1) is about twice the diameter of the channel via.

[0257] The features of the present invention have been described above.

[0258] Finally, the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. [Industrial Applicability]

[0259] Silicon technology will make it possible to provide a method for realizing the information processing mechanisms of the human brain on semiconductor chips. [Brief explanation of the drawings]

[0260] [Figure 1] A diagram illustrating an example of a nerve cell. [Figure 2] 1 is a diagram illustrating an example of synapsis. [Figure 3] An example diagram illustrating the concept of a perceptron. [Figure 4] 10 is a diagram illustrating an example of a method for counting the number of links between two points. [Figure 5]A plot of the ratio of the network information volume to the bit information volume (number of bits) against the number of nodes (N). [Figure 6] A diagram showing that even if the start and end points are the same, the input to the end point may be different if the path (route) is different. [Figure 7] A diagram plotting the ratio of the information capacity of a 3D network to that of a 2D network against the size of one side of the cell array. [Figure 8] A drawing explaining the definitions of addresses X, Y, and Z. [Figure 9] 10 is a diagram illustrating an example of one module in the Z direction. [Figure 10] 10 is a diagram illustrating an example in which one module in the Z direction is expanded in the X direction. [Figure 11] 10 is a diagram illustrating an example of one module in the Z direction expanding in the Y direction. [Figure 12] 1 is a diagram for explaining the transistor characteristics (electrical characteristics) of a cell gate. [Figure 13] 1 is a diagram for schematically explaining the transistor characteristics (electrical characteristics) of the select gates of the word lines and bit lines; [Figure 14] 10 is a diagram illustrating an example of a method for linking two adjacent cell gates in the Z direction. [Figure 15] 10 is a diagram illustrating an example of how to apply a voltage to link two adjacent cell gates in the Z direction. [Figure 16] 10 is a diagram illustrating an example of a method for linking two adjacent cell gates in the Z direction. [Figure 17] 10 is a diagram illustrating an example of how to apply a voltage to link two adjacent cell gates in the Z direction. [Figure 18] 10 is a diagram illustrating an example of a method for linking two cell gates adjacent in the X direction. [Figure 19] 10 is a diagram illustrating an example of how to apply a voltage to link two cell gates adjacent in the X direction. [Figure 20] 10 is a diagram illustrating an example of a method for linking two adjacent cell gates in the Y direction. [Figure 21]10 is a diagram illustrating an example of how to apply a voltage to link two adjacent cell gates in the Y direction. [Figure 22] 10 is a diagram for explaining an example of an embodiment in which the Y-direction bit line BLY(i, k−1) serves as a cell body. [Figure 23] 10 is a diagram for explaining an example of an embodiment in which the Y-direction bit line BLY(i, k-1) serves as a cell body. [Figure 24] 10 is a diagram for explaining an example of an embodiment in which the X-direction bit line BLX(j, k) serves as a cell body. [Figure 25] 10A and 10B are diagrams illustrating an example of an embodiment for forming a link. [Figure 26] 10 is a diagram for explaining an example of an embodiment in which the Y-direction bit line BLY(i, k-1) serves as a cell body. [Figure 27] 10 is a diagram for explaining an example of an embodiment in which the X-direction bit line BLX(j, k) serves as a cell body. [Figure 28] 10A and 10B are diagrams illustrating an example of an embodiment in which information is recorded by a route. [Figure 29] 10A and 10B are diagrams illustrating an example of an embodiment in which information is recorded by a route. [Figure 30] A diagram explaining that one module in the Z direction is made up of three units. [Figure 31] FIG. 1 is a diagram illustrating an example of a view (XY plan view) of a cross section in a layer where BLY(i, k+1) or BLY(i, k−1) exists, viewed from above. [Figure 32] FIG. 1 is a diagram illustrating an example of a cross section (XY plan view) of a layer where BLX(j, k) or BLX(j, k-2) exists, viewed from above. [Figure 33] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k+1) exists. [Figure 34] FIG. 10 is a diagram illustrating an example of a view (XY plan view) of a cross section in a layer where SGU (i, j, k+1) exists, viewed from above. [Figure 35] A diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where SGD (i, j, k+1) exists. [Figure 36] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k) exists. [Figure 37] FIG. 10 is a diagram illustrating an example of a view (XY plan view) of a cross section in a layer where SGU (i, j, k) exists, viewed from above. [Figure 38] A diagram illustrating an example of a cross section of a layer where SGD (i, j, k) exists, viewed from above (XY plan view). [Figure 39] 1 is a diagram illustrating an example of a cross section of three modules arranged in the X direction. [Figure 40] 1 is a diagram illustrating an example of a cross section of one module expanded in the Y direction. [Figure 41] 1 is a diagram illustrating an example of a cross section of three modules arranged in the Y direction. [Figure 42] 1 is a diagram illustrating an example of the internal structure of a core. [Figure 43] A diagram illustrating the general gate-last method. [Figure 44] A diagram illustrating the general gate-last method. [Figure 45] 10 is a diagram illustrating an example of patterning of a metal that becomes a bit line. [Figure 46] A diagram showing the top view (XY plane) after patterning of the metal that will become the bit line. (a) shows the case where the bit line is patterned so that it extends in the X direction. (b) shows the case where the bit line is patterned so that it extends in the Y direction. [Figure 47] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 48] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 49] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 50]1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 51] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 52] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 53] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 54] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 55] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 56] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 57] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 58] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 59] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 60] 1A and 1B are diagrams illustrating an example of a manufacturing process for forming a unit having the features of the present application on a metal film patterned to extend in the X direction. [Figure 61]A diagram for explaining the case where X and Y in Figure 59 are interchanged. [Figure 62] A drawing for comparing (w3x) in Figure 61 with a portion (1 unit) of the module in Figure 9. [Figure 63] A diagram illustrating an example of a unit manufactured by changing the combination of the number of nitride film layers in Figure 59. [Figure 64] A drawing for comparing part of the module (1 unit) in Figure 63 (w4x) with that in Figure 9. [Figure 65] 10 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WUX and WCX) extending in the X-axis direction and a group of bit lines (a group of BLX). [Figure 66] 10 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WUX and WCX) extending in the X-axis direction and a group of bit lines (a group of BLX). [Figure 67] 10 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WUX and WCX) extending in the X-axis direction and a group of bit lines (a group of BLX). [Figure 68] 10 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WUX and WCX) extending in the X-axis direction and a group of bit lines (a group of BLX). [Figure 69] A diagram explaining which word line or bit line each contact is connected to, divided into the M1 and M0 layers. [Figure 70] 10 is a diagram for explaining an example of a method for laying out MC0 and MC1 on the XY plane so as to satisfy the periodicity in the Z-axis direction that is characteristic of the present application. [Figure 71] 1 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WDY and WUY) extending in the Y-axis direction and a group of bit lines (a group of BLY). [Figure 72] 1 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WDY and WUY) extending in the Y-axis direction and a group of bit lines (a group of BLY). [Figure 73] 1 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WDY and WUY) extending in the Y-axis direction and a group of bit lines (a group of BLY). [Figure 74] 1 is a diagram for explaining an example of how to make contact between a group of word lines (a group of WDY and WUY) extending in the Y-axis direction and a group of bit lines (a group of BLY). [Figure 75] A diagram explaining which word line or bit line each contact is connected to, divided into the M1 layer and the M0 layer. [Figure 76] 10 is a diagram for explaining an example of a method for laying out MC0 and MC1 on the XY plane so as to satisfy the periodicity in the Z-axis direction that is characteristic of the present application. [Figure 77] 1 is a diagram for explaining an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on an XY plane. [Figure 78] 1 is a diagram for explaining an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on an XY plane. [Figure 79] 1 is a diagram for explaining an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on an XY plane. [Figure 80] 1 is a diagram for explaining an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on an XY plane. [Figure 81] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where BLY(i, k±1) exists. [Figure 82] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where BLY(i, k±1) exists. [Figure 83] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where BLY(i, k±1) exists. [Figure 84] FIG. 1 is a diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where BLY(i, k±1) exists. [Figure 85] FIG. 1 is a diagram illustrating an example of a cross section (XY plan view) of a layer where BLX(j, k) or BLX(j, k-2) exists, viewed from above. [Figure 86]FIG. 1 is a diagram illustrating an example of a cross section (XY plan view) of a layer where BLX(j, k) or BLX(j, k-2) exists, viewed from above. [Figure 87] FIG. 1 is a diagram illustrating an example of a cross section (XY plan view) of a layer where BLX(j, k) or BLX(j, k-2) exists, viewed from above. [Figure 88] FIG. 1 is a diagram illustrating an example of a cross section (XY plan view) of a layer where BLX(j, k) or BLX(j, k-2) exists, viewed from above. [Figure 89] A diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k) exists. [Figure 90] A diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k) exists. [Figure 91] A diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k) exists. [Figure 92] A diagram illustrating an example of a top view (XY plan view) of a cross section in a layer where CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k) exists. [Figure 93] A diagram illustrating an example of a top view (XY plan view) of a cross section at a layer where SGD(i, j, k+1), SGU(i, j, k+1) or SGU(i, j, k) exists. [Figure 94] A diagram illustrating an example of a top view (XY plan view) of a cross section at a layer where SGD(i, j, k+1), SGU(i, j, k+1) or SGU(i, j, k) exists. [Figure 95] A diagram illustrating an example of a top view (XY plan view) of a cross section at a layer where SGD(i, j, k+1), SGU(i, j, k+1) or SGU(i, j, k) exists. [Figure 96] A diagram illustrating an example of a top view (XY plan view) of a cross section at a layer where SGD(i, j, k+1), SGU(i, j, k+1) or SGU(i, j, k) exists. [Figure 97] 10 is a diagram showing an example of the relationship between the diameter of a channel via and the width of a word line or a bit line. [Explanation of symbols]

[0261] BLX X-direction bit line BLY Y-direction bit line BSGX Bit line select gate for X direction bit lines BSGY Bit line select gate for Y direction bit lines SGU Upper Selector Gate CG Cell Gate SGD Lower Selector Gate WUX X-direction word line of upper select gate WCX X-direction word line of cell gate WDX X-direction word line of the lower select gate WUY Y-direction word line of upper select gate WCY Y-direction word line of cell gate WDY Y-direction word line of the lower select gate WSGUX X-direction word line of upper select gate WSGCX Cell gate X-direction word line WSGDX X-direction word line of the lower select gate WSGUY Y-direction word line of upper select gate WSGDY Y-direction word line of the bottom select gate BL bit line WL Word Line CV channel via or vertical hole drilled to create a channel section Core: Center of the channel via Tunnel oxide / tunnel oxide film Charge storage / charge storage layer Control gate Block film Dielectric core Channel silicon Sub / Circuit Board Polysilicon Metal Silicide Oxide Nitride / nitride film N+poly / N+ type polysilicon High-K / High dielectric constant Metal contacts on MC0 / M0 layers Metal contacts on MC1 / M1 layers

Claims

1. a first unit and a second unit connected in series in a first axial direction; second, third, fourth, and fifth word lines extending in a second axial direction; first and sixth word lines extending in a third axis direction; first and third bit lines extending in the second axial direction; a second bit line extending in a third axis direction; It is a module consisting of the second bit line is connected to both the first and second units; the first unit comprises a first, second, and third element; the first, second, and third elements are connected in series in the first axial direction; the first, second, and third elements each have a control gate; the first element has a source; the third element has a drain; a control gate of the first element connected to the first word line; a control gate of the second element connected to the second word line; a control gate of the third element connected to the third word line; a source of the first element connected to the first bit line; a drain of the third element connected to the second bit line; the second unit comprises a fourth, fifth, and sixth element; the fourth, fifth, and sixth elements are connected in series in the first axial direction; the fourth, fifth, and sixth elements each have a control gate; the fourth element has a source; the sixth element has a drain; a control gate of the fourth element connected to the fourth word line; a control gate of the fifth element connected to the fifth word line; a control gate of the sixth element connected to the sixth word line; the source of the fourth element is connected to the second bit line; a drain of the sixth element connected to the third bit line; A semiconductor device characterized by:

2. each of the first to sixth elements is a cylindrical channel via including a tunnel oxide film, a charge storage layer, a blocking film, and a conductive thin film; the first to third elements each have a first core; the fourth to sixth elements each have a second core; the first core is a cylindrical member extending in the first axial direction and constituting a channel portion for the first to third elements; the second core is a cylindrical member extending in the first axial direction and constituting a channel portion for the fourth to sixth elements; the tunnel oxide film surrounds the first core for each of the first to third elements, and surrounds the second core for each of the fourth to sixth elements, the charge storage layer surrounds the tunnel oxide film for each of the first to sixth elements; the blocking film covers the charge storage layer for each of the first to sixth elements, the conductive thin film covers the blocking film for each of the first to sixth elements, the control gates of the first to sixth elements are the conductive thin film; 2. The semiconductor device according to claim 1.

3. the width of the first to sixth word lines is greater than the diameter of the cylindrical channel via; the widths of the first to third bit lines are greater than the diameter of the cylindrical channel via; 2. The semiconductor device according to claim 1.

4. seventh, eighth, and ninth elements; and seventh and eighth word lines extending in the second axial direction; a ninth word line extending in the third axial direction; a fourth bit line extending in the third axis direction; the seventh, eighth, and ninth elements are connected in series in the first axial direction; the seventh, eighth, and ninth elements each have a control gate; the seventh element has a source; the eighth element has a drain; a control gate of the seventh element connected to the seventh word line; a control gate of the eighth element connected to the eighth word line; a control gate of the ninth device connected to the ninth word line; the source of the seventh element is connected to the fourth bit line; a drain of the ninth element connected to the first bit line; 2. The semiconductor device according to claim 1.

5. tenth, eleventh, and twelfth elements; eleventh and twelfth word lines extending in the second axial direction; a tenth word line extending in the third axis direction; a fifth bit line extending in the third axial direction; the tenth, eleventh, and twelfth elements are connected in series in the first axial direction; the tenth, eleventh, and twelfth elements each have a control gate; the tenth element has a source; the twelfth element has a drain; a control gate of the tenth device connected to the tenth word line; a control gate of the eleventh element connected to the eleventh word line; a control gate of the twelfth element connected to the twelfth word line; the source of the tenth element is connected to the third bit line; the drain of the twelfth element is connected to the fifth bit line; 2. The semiconductor device according to claim 1.

6. 21st, 22nd, and 23rd elements; and a 21st word line and a 22nd bit line extending in the third direction; the 21st, 22nd, and 23rd elements are connected in series in the first axial direction; the 21st, 22nd, and 23rd elements each have a control gate; the twenty-first element has a source; the 23rd element has a drain; a control gate of the 21st element is connected to the 21st word line; a control gate of the 22nd element connected to the second word line; a control gate of the 23rd device connected to the third word line; the source of the 21st element is connected to the first bit line; the drain of the 23rd element is connected to the 22nd bit line; 2. The semiconductor device according to claim 1.

7. 24th, 25th, and 26th elements; a 26th word line extending in the third direction; the 24th, 25th, and 26th elements are connected in series in the first axial direction; the 24th, 25th, and 26th elements each have a control gate; the 24th element has a source; the 26th element has a drain; a control gate of the 24th device connected to the fourth word line; a control gate of the 25th device connected to the 5th word line; the control gate of the 26th device is connected to the 26th word line; the source of the 24th element is connected to the 22nd bit line; 7. The semiconductor device according to claim 6.

8. a thirty-first element, a thirty-second element, and a thirty-third element; 32nd and 33rd word lines extending in the second direction, and 31st, the 31st, 32nd, and 33rd elements are connected in series in the first axial direction; the 31st, 32nd, and 33rd elements each have a control gate; the 31st element has a source; the 33rd element has a drain; a control gate of the 31st element is connected to the first word line; a control gate of the 32nd element is connected to the 32nd word line; a control gate of the 33rd element is connected to the 33rd word line; the source of the 31st element is connected to the 31st bit line; a drain of the 33rd element connected to the second bit line; 2. The semiconductor device according to claim 1.

9. 34th, 35th, and 36th elements; and 34th and 35th word lines and 36th bit lines extending in the second direction; the 34th, 35th, and 36th elements are connected in series in the first axial direction; the 34th, 35th, and 36th elements each have a control gate; the thirty-fourth element has a source; the 36th element has a drain; the control gate of the thirty-fourth device is connected to the thirty-fourth word line; the control gate of the thirty-fifth device is connected to the thirty-fifth word line; a control gate of the thirty-sixth device connected to the sixth word line; the source of the 34th element is connected to the second bit line; the drain of the 36th element is connected to the 36th bit line; 9. The semiconductor device according to claim 8.

10. applying a first voltage to the first, third, seventh, and ninth word lines; the first voltage is less than a threshold voltage; the threshold voltages are threshold voltages of voltages to be applied to the gates of the first, second, third, seventh, eighth, and ninth elements, respectively, that are necessary to allow current to flow between the sources and drains of the first, second, third, seventh, eighth, and ninth elements; changing the voltage of the first and ninth word lines from the first voltage to a transmission voltage; the transmission voltage is higher than the threshold of any of the first, second, third, seventh, eighth, and ninth elements; applying a read voltage to the second and eighth word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; 5. The method for operating a semiconductor device according to claim 4.

11. applying a first voltage to the first, third, fourth, and sixth word lines; the first voltage is less than a threshold voltage; the threshold voltages are threshold values ​​of voltages to be applied to the gates of the first to sixth elements, respectively, that are necessary to allow current to flow between the sources and drains of the first to sixth elements; changing the voltage of the third and fourth word lines from the first voltage to a transmission voltage; the transmission voltage is higher than a threshold value of any of the first to sixth elements; applying a read voltage to the second and fifth word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; 2. The method for operating a semiconductor device according to claim 1.

12. applying a first voltage to the first, third, and twenty-first word lines; the first voltage is less than a threshold voltage; the threshold voltage is a threshold voltage of a voltage to be applied to the gates of the first, third, and twenty-first elements, which is necessary to allow a current to flow between the source and drain of the first, third, and twenty-first elements; changing a voltage applied to the first and twenty-first word lines from the first voltage to a transmission voltage; the transmission voltage is higher than the threshold voltage of any of the first, third, and twenty-first elements; applying a read voltage to the second word line; the read voltage is higher than the first voltage and lower than the transmission voltage; 7. The method for operating a semiconductor device according to claim 6.

13. applying a first voltage to the first, third, and thirty-third word lines; the first voltage is less than a threshold voltage; the threshold voltage is a threshold voltage of a voltage to be applied to the gates of the first, third, and thirty-third elements that is necessary to allow a current to flow between the source and drain of the first, third, and thirty-third elements; changing the voltage applied to the third and thirty-third word lines from the first voltage to a transmission voltage; the transmission voltage is higher than a threshold value of any of the first, third, and thirty-third elements; applying a read voltage to the second and thirty-second word lines; the read voltage is higher than the first voltage and lower than the transmission voltage; 9. The method for operating a semiconductor device according to claim 8.

14. one of the second and third directions is designated as a first selection axis, and the other is designated as a second selection axis; on a first conductive layer patterned to extend along the first selected axis; The first to fifth films are stacked, the first, third, and fifth films are first-type insulating films; the second and fourth films are second-type insulating films, etching the first to fifth films along the second selected axis to provide a first slit; the first slit extends in the direction of the second selected axis; Peeling off the second and fourth films; After performing a predetermined treatment, a third type insulating film is filled in the first slit; After performing a predetermined treatment, sixth, seventh, and eighth films are laminated on the fifth film; the sixth and eighth films are the first type insulating films, the seventh film is the second type insulating film, etching the sixth to eighth films in the direction of the first selected axis to open a second slit; the second slit extends in the direction of the first selected axis; Peeling off the seventh film; After performing a predetermined treatment, the third type insulating film is filled in the second slit; the first conductive layer is a bit line extending in the first selection axis direction; 2. The method for manufacturing a semiconductor device according to claim 1.

15. After performing a predetermined treatment on the eighth film, patterning the second conductive layer to extend along the second selected axis; the second conductive layer is a bit line extending in the second selection axis direction, 9th to 13th films are stacked on the second conductive layer; the ninth, eleventh, and thirteenth films are the first type insulating films, the tenth and twelfth films are the second type insulating films, the second conductive layer is a bit line extending in the second selection axis direction, the first and second conductive layers intersect each other in a plane defined by the first and second selected axes; 15. The method for manufacturing a semiconductor device according to claim 14.

16. the first type insulating film is made of an oxide film, the second type insulating film is made of a nitride film, the third type insulating film is made of a low dielectric film, the first and second conductive layers are made of metal or silicide; 16. The method for manufacturing a semiconductor device according to claim 15.

17. one of the second and third directions is a 21st selection axis, and the other is a 22nd selection axis; on a twenty-first conductive layer patterned to extend along the twenty-first selected axis; 21st to 23rd films are stacked, the 21st and 23rd films are 21st type insulating films, the 22nd film is a 22nd type insulating film, etching the 21st to 23rd films along the 22nd selected axis to open a 21st slit; the 21st slit extends in the direction of the 22nd selection axis, Peeling off the 22nd film; After performing a predetermined treatment, a 23rd type insulating film is filled in the 21st slit; After a predetermined treatment is performed, the 24th to 28th films are laminated on the 23rd film, the 24th, 26th, and 28th films are the 21st type insulating films, the 25th and 27th films are the 22nd type insulating films, Etching the 24th to 28th films in the direction of the 21st selection axis to open a 22nd slit; the 22nd slit extends in the direction of the 21st selected axis, Peel off the 25th and 27th films, After performing a predetermined treatment, the 22nd slit is filled with the 23rd type insulating film; the 21st conductive layer is a bit line extending in the 21st selection axis direction; 2. The method for manufacturing a semiconductor device according to claim 1.

18. After performing a predetermined treatment on the 28th film, patterning a twenty-second conductive layer to extend along the twenty-second selected axis; the 22nd conductive layer is a bit line extending in the 22nd selection axis direction, on the 22nd conductive layer, Stacking the 29th to 31st films, the 29th and 31st films are 21st type insulating films, the 30th film is the 22nd type insulating film, the 22nd conductive layer is a bit line extending in the 22nd selection axis direction, the 21st and 22nd conductive layers intersect each other in a plane defined by the 21st selection axis and the 22nd selection axis; 18. The method for manufacturing a semiconductor device according to claim 17.

19. the 21st type insulating film is made of an oxide film, the 22nd type insulating film is made of a nitride film, the 23rd insulating film is made of a low dielectric film, the 21st and 22nd conductive layers are made of a metal or a silicide; 20. The method for manufacturing a semiconductor device according to claim 18.

20. It has first and second wiring metal layers, the first bit line is connected to the first wiring metal layer; the second word line is connected to the second wiring metal layer; the third word line is connected to the first wiring metal layer; the fourth word line is connected to the second wiring metal layer; the fifth word line is connected to the first wiring metal layer; the third bit line is connected to the second wiring metal layer; 2. The semiconductor device according to claim 1.

21. the first and sixth word lines are connected to one of the first and second wiring metal layers; the second bit line is connected to the other of the first and second wiring metal layers; 21. The semiconductor device according to claim 20.

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