Electro-optical device, and display

Abstract

To provide an electro-optical device that can prevent a trouble such as display unevenness.SOLUTION: A liquid crystal device 100 comprises: a substrate 10a; a pixel electrode 11; common wiring 18; a TFT 30 provided between the substrate 10a and the common wiring 18; a scan line 13 provided along a first direction between the substrate 10a and the TFT 30; a capacitive element 60 provided between the substrate 10a and the scan line 13, and overlapping the scan line 13 in plan view; and a second relay electrode 82 electrically connected with the common wiring 18, and overlapping the scan line 13 in plan view. The second relay electrode 82 and a first capacitive electrode 61 as one electrode of the capacitive element 60 are electrically connected with each other through a contact hole C4 overlapping the scan line 13 and the first capacitive electrode 61 in plan view. The scan line 13 has a notch part 13c provided between the second relay electrode 82 and the first capacitive electrode 61 and surrounding at least three directions around the contact hole C4.SELECTED DRAWING: Figure 5B

Description

Technical Field

[0001] The present invention relates to an electro-optical device and a display device including the electro-optical device.

Background Art

[0002] Conventionally, as shown in Patent Document 1, in an electro-optical device, a thin film transistor (hereinafter referred to as TFT) as a switching element of a pixel, a scanning line that is disposed between the TFT and a substrate and also serves as a light shielding film of the TFT, and a holding capacitor having a laminated structure that is disposed between the scanning line and the substrate are disclosed. In the holding capacitor of Patent Document 1, one capacitive electrode also serves as a common wiring. That is, the first conductive layer as one capacitive electrode has a portion arranged in a lattice pattern in the display region and a portion drawn out outside the display region, and a common potential is supplied to the portion drawn out outside the display region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the case of the one described in Patent Document 1, when the resistance value of the first conductive layer as one capacitive electrode becomes high due to the film thickness, wiring dimensions, film quality, etc. of the first conductive layer, the potential of one capacitive electrode is likely to fluctuate due to the influence from other signal lines, and problems such as display unevenness are likely to occur. Furthermore, when the film thickness is increased to reduce the resistance of the first conductive layer, the film thickness of the light transmission region also increases, which may cause a decrease in transmittance.

Means for Solving the Problems

[0005] An electro-optical apparatus according to one aspect of the present invention comprises a substrate, a pixel electrode, a capacitive wiring provided between the substrate and the pixel electrode, a transistor provided between the substrate and the capacitive wiring, a light-shielding member provided between the substrate and the transistor along a first direction, a capacitive element provided between the substrate and the light-shielding member and overlapping with the light-shielding member in a plan view, and a conductive member electrically connected to the capacitive wiring and overlapping with the light-shielding member in a plan view, wherein the light-shielding member has a notch provided between the conductive member and one electrode of the capacitive element, and the conductive member and the one electrode of the capacitive element are electrically connected via a contact hole provided inside the notch in a plan view, at least a portion of which is located inside.

[0006] A display device according to one aspect of the present application comprises the electro-optical device described above. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic plan view of the liquid crystal device according to Embodiment 1. [Figure 2] A schematic cross-sectional view along line AA in Figure 1. [Figure 3] An equivalent circuit diagram showing the electrical configuration of a liquid crystal display device. [Figure 4] A plan view of a pixel. [Figure 5A] Cross-sectional view along the YY line in Figure 4. [Figure 5B] Cross-sectional view along the line S1-S1 in Figure 4. [Figure 5C] Cross-sectional view along the line S2-S2 in Figure 4. [Figure 6] A flowchart illustrating the manufacturing process of the device substrate. [Figure 7] A plan view showing the pixel configuration during the trench formation process of the element substrate. [Figure 8A] Cross-sectional view along the YY line in Figure 7. [Figure 8B] Cross-sectional view along line XX in Figure 7. [Figure 9]Plan view showing the pixel pattern in one step of the element substrate. [Figure 10A] Cross-sectional view taken along the Y-Y line of FIG. 9. [Figure 10B] Cross-sectional view taken along the X-X line of FIG. 9. [Figure 11] Plan view showing the pixel pattern in one step of the element substrate. [Figure 12A] Cross-sectional view taken along the Y-Y line of FIG. 11. [Figure 12B] Cross-sectional view taken along the X-X line of FIG. 11. [Figure 12C] Cross-sectional view taken along the Z-Z line of FIG. 11. [Figure 13] Plan view showing the pixel pattern in one step of the element substrate. [Figure 14A] Cross-sectional view taken along the Y-Y line of FIG. 13. [Figure 14B] Cross-sectional view taken along the X-X line of FIG. 13. [Figure 14C] Cross-sectional view taken along the Z-Z line of FIG. 13. [Figure 15] Plan view showing the pixel pattern in one step of the element substrate. [Figure 16A] Cross-sectional view taken along the Y-Y line of FIG. 15. [Figure 16B] Cross-sectional view taken along the X-X line of FIG. 15. [Figure 17] Plan view showing the pixel pattern in one step of the element substrate. [Figure 18A] Cross-sectional view taken along the Y-Y line of FIG. 17. [Figure 18B] Cross-sectional view taken along the X-X line of FIG. 17. [Figure 18C] Cross-sectional view taken along the Z-Z line of FIG. 17. [Figure 19] Plan view showing the pixel pattern in one step of the element substrate. [Figure 20A] Cross-sectional view taken along the Y-Y line of FIG. 19. [Figure 20B] Cross-sectional view taken along the X-X line of FIG. 19. [Figure 20C] Cross-sectional view taken along the Z-Z line of FIG. 19. [Figure 21] Plan view showing the pixel pattern in one step of the element substrate. [Figure 22A] Cross-sectional view along the YY line in Figure 21. [Figure 22B] Cross-sectional view along line XX in Figure 21. [Figure 23] A plan view showing the pixel configuration in one manufacturing process of an element substrate. [Figure 24A] Cross-sectional view along the YY line in Figure 23. [Figure 24B] Cross-sectional view along line XX in Figure 23. [Figure 25] A plan view showing the pixel configuration in one manufacturing process of an element substrate. [Figure 26A] Cross-sectional view along the YY line in Figure 25. [Figure 26B] Cross-sectional view along line XX in Figure 25. [Figure 26C] Cross-sectional view along the ZZ line in Figure 25. [Figure 27] A plan view showing the pixel configuration in one manufacturing process of an element substrate. [Figure 28] A schematic diagram of the projection display device according to Embodiment 2. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. In the following diagrams, the scale of each component has been altered from its actual size in order to make each component recognizable. Furthermore, each figure shows three mutually orthogonal axes: the X-axis, Y-axis, and Z-axis, as needed. The direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, the direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. The direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction. The plane containing the X-axis and Y-axis is also called the "XY plane," and viewing the XY plane in the Z1 or Z2 direction is referred to as a "planar view" or "planar perspective," while viewing it from a direction perpendicular to the cross-section containing the Z-axis is referred to as a "cross-sectional view" or "cross-sectional perspective."

[0009] Furthermore, in the following explanation, for example, the phrase "on the substrate" in relation to a substrate means one of the following: when placed in contact with the substrate, when placed on the substrate via other structural elements, or when a part is placed in contact with the substrate and a part is placed via other elements. Furthermore, while the following explanation may include descriptions of the materials and film thicknesses of elements used in electro-optical devices, these are merely examples and do not limit the materials or film thicknesses unless otherwise specified.

[0010] 1. Embodiment 1 In this embodiment, an active-drive liquid crystal device equipped with a TFT for each pixel is described as an example of an electro-optical device. This liquid crystal device can be suitably used as an optical modulation device in a projection-type display device, which will be described later.

[0011] 1.1. Overview of the structure of a liquid crystal display device The structure of the liquid crystal device as an electro-optical device according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic plan view showing the configuration of a transmissive liquid crystal device as an electro-optical device according to Embodiment 1. Figure 2 is a schematic cross-sectional view showing the structure of the liquid crystal device along line AA in Figure 1.

[0012] As shown in Figures 1 and 2, the liquid crystal apparatus 100 of this embodiment includes an element substrate 10, a counter substrate 20 positioned opposite the element substrate 10, and a liquid crystal layer 5 as an electro-optical layer sandwiched between the element substrate 10 and the counter substrate 20.

[0013] For the substrate 10a of the element substrate 10, a substrate such as a glass substrate or a quartz substrate is used. For the substrate 20a of the opposing substrate 20, a transparent substrate such as a glass substrate or a quartz substrate is used.

[0014] The element substrate 10 has a larger shape than the opposing substrate 20 in a plan view. The element substrate 10 and the opposing substrate 20 are joined via a sealing material 6 arranged along the outer edge of the opposing substrate 20. A liquid crystal layer 5 is provided by sealing liquid crystal having positive or negative dielectric anisotropy in the gap between the element substrate 10 and the opposing substrate 20.

[0015] Inside the sealing material 6, a display area E is provided, which includes multiple pixels P arranged in a matrix. The area outside the display area E is the peripheral area F. In the peripheral area F, a trim portion 23 made of light-shielding material is provided between the sealing material 6 and the display area E, along the outer edge of the display area E. In addition, dummy pixels, which do not contribute to the display and are not shown, are provided at positions that overlap with the trim portion 23 in a plan view.

[0016] A terminal section with multiple external connection terminals 43 arranged in a plurality of positions is provided in the peripheral region F of the element substrate 10. In the peripheral region F, a data line drive circuit 47 is provided between the first side along the terminal section and the sealing material 6. Also in the peripheral region F, a test circuit 41 is provided between the sealing material 6 along the second side opposite the first side and the display area E.

[0017] In the peripheral region F, a scan line drive circuit 45 is provided between the sealing material 6 and the display region E, along the third and fourth sides which are perpendicular to the first side and face each other. In addition, multiple wires 49 connecting the two scan line drive circuits 45 are provided between the sealing material 6 on the second side and the inspection circuit 41.

[0018] The wiring 49 connected to the data line drive circuit 47 and the scan line drive circuit 45 is connected to a plurality of external connection terminals 43 arranged along the first side. However, the arrangement of the test circuit 41 is not limited to the above. Here, in this specification, the direction along the first edge of the substrate 10a, i.e., the X1 direction or X2 direction along the X axis, corresponds to the first direction, and the direction along the third or fourth edge of the substrate 10a, i.e., the Y1 direction or Y2 direction along the Y axis, corresponds to the second direction.

[0019] As shown in Figure 2, the surface of the substrate 10a on the liquid crystal layer 5 side is provided with light-transmitting pixel electrodes 11 and TFTs 30 as transistors, wiring 49, and an alignment film 12 covering them, each of which is provided for each pixel P. The TFTs 30 and pixel electrodes 11 are components of the pixel P. The element substrate 10 includes the substrate 10a, the pixel electrodes 11, TFTs 30, wiring 49, and alignment film 12 provided on the substrate 10a.

[0020] The surface of the substrate 20a on the liquid crystal layer 5 side is provided with a trim portion 23, an insulating layer 25 formed by covering the trim portion, a counter electrode 21 as a common electrode provided by covering the insulating layer 25, and an alignment film 22 covering the counter electrode 21. In this embodiment, the opposing substrate 20 includes at least the trim portion 23, the counter electrode 21, and the alignment film 22. In this embodiment, an example is shown in which the common electrode is provided as the counter electrode 21 on the opposing substrate 20 side, but the common electrode may be provided on the element substrate 10 side.

[0021] As shown in Figure 1, the scan line drive circuit 45 and the inspection circuit 41 overlap the trim section 23 in a plan view. The trim section 23 shields the peripheral circuits, such as the scan line drive circuit 45, from light L from a laser light source (not shown) that is incident from the opposing substrate 20 side, thereby preventing the peripheral circuits from malfunctioning.

[0022] The insulating layer 25 is made of an inorganic material such as light-transmitting silicon oxide (SiO2). The insulating layer 25 covers the trim portion 23 and is provided so that the surface on the liquid crystal layer 5 side is flat.

[0023] The counter electrode 21 covers the insulating layer 25 and is electrically connected to the upper and lower conductive portions 7 provided at the four corners of the counter substrate 20. The upper and lower conductive portions 7 are electrically connected to the common wiring 18, which will be described later as capacitive wiring, on the element substrate 10 side.

[0024] The pixel electrode 11 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment film 12 and the alignment film 22 are selected based on the optical design of the liquid crystal device 100. Examples of materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide and organic alignment films such as polyimide.

[0025] Such a liquid crystal display device 100 employs an optical design in which the light transmittance of pixel P when no voltage is applied is greater than the transmittance when voltage is applied, or in a normally black mode where the transmittance of pixel P when no voltage is applied is less than the transmittance when voltage is applied. In the liquid crystal display device 100, polarizing elements are arranged on the light incident side and the light exit side, respectively, according to the optical design.

[0026] In this embodiment, we will describe an example in which the inorganic alignment films described above are used as alignment films 12 and 22, and a liquid crystal having negative dielectric anisotropy is used as the liquid crystal layer 5, and an optical design in normally black mode is applied.

[0027] 1.2. Overview of the Electrical Configuration of Liquid Crystal Devices Next, the electrical configuration of the liquid crystal device 100 will be described with reference to Figure 3. Figure 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device.

[0028] As shown in Figure 3, the liquid crystal display device 100 has scan lines 13, data lines 16, and common wiring 18 as light-shielding members on the substrate 10a of the element substrate 10. The scan lines 13 extend in the X1 direction, which is the first direction. The data lines 16 and common wiring 18 extend in the Y1 direction. In Figure 3, the common wiring 18 is shown extending along the Y1 direction, but this is not the only way it can be shown.

[0029] The region demarcated by the scan line 13 and the data line 16 becomes a pixel P. The pixel P is provided with a pixel electrode 11, a TFT 30, and a capacitive element 60. The scan line 13 is electrically connected to the gate electrode of the TFT 30, and the data line 16 is electrically connected to the source of the TFT 30. The scan line 13 has the function of simultaneously controlling the on / off state of the TFTs 30 located in the same row. The pixel electrode 11 is electrically connected to the drain of the TFT 30.

[0030] The data line 16 is electrically connected to the data line drive circuit 47 and supplies image signals D1, D2, ..., Dn supplied from the data line drive circuit 47 to the pixels P. The scan line 13 is electrically connected to the scan line drive circuit 45 and supplies scan signals SC1, SC2, ..., SCm supplied from the scan line drive circuit 45 to each pixel P.

[0031] The image signals D1 to Dn supplied from the data line drive circuit 47 to the data line 16 may be supplied in this order in line sequence, or they may be supplied to multiple adjacent data lines 16 in groups. The scan line drive circuit 45 supplies the scan signals SC1 to SCm to the scan line 13 in line sequence at predetermined timings.

[0032] When a scanning signal SC1 is input to the TFT30, the TFT30 turns on for a certain period of time. As a result, the image signal D1 supplied from the data line 16 is written to the pixel electrode 11 at a predetermined timing. The image signal D1, which has been written to the liquid crystal layer 5 via the pixel electrode 11, is then held for a certain period of time between the pixel electrode 11 and the counter electrode 21 which is positioned opposite to it via the liquid crystal layer 5.

[0033] To prevent the retained image signal D1 from leaking, a capacitive element 60 is electrically connected to a liquid crystal capacitance provided between the pixel electrode 11 and the counter electrode 21. One electrode of the capacitive element 60 is electrically connected to a common wiring 18 to which a constant potential is applied, and the other electrode of the capacitive element 60 is electrically connected to the drain of the TFT 30 and the pixel electrode 11.

[0034] Although not shown in Figure 3, a test circuit 41 is connected to data line 16. Therefore, during the manufacturing process of the liquid crystal display 100, it is possible to detect image signals D1, D2, ..., Dn and check for malfunctions in the liquid crystal display 100.

[0035] 1.3. Overview of the Element Substrate Configuration Next, the planar and cross-sectional configurations of the pixel P on the element substrate 10 will be described with reference to Figures 4, 5A, 5B, and 5C. Figure 4 is a planar view of the pixel, showing a section E1, which is part of the display area E in Figure 1. Figure 5A is a cross-sectional view along the YY line in Figure 4, Figure 5B is a cross-sectional view along the S1-S1 line in Figure 4, and Figure 5C is a cross-sectional view along the S2-S2 line in Figure 4. Also, the alignment film 12 is not shown in Figures 5A, 5B, and 5C.

[0036] As shown in Figure 4, the light-shielding region SD, indicated by the dashed line, is arranged in a grid pattern surrounding the light-transmitting region of the pixel P. Of the light-shielding region SD, the portion extending along the X-axis is mainly shielded by the scan line 13, and the portion extending along the Y-axis is mainly shielded by the data line 16 and the common wiring 18. The light-shielding region SD overlaps with the pixel electrode 11 in a plan view. A TFT 30 (not shown) and a capacitive element 60 are arranged in the light-shielding region SD, and the pixel electrode 11 is electrically connected to the TFT 30 and the capacitive element 60 via a contact hole C20.

[0037] Contact hole C4, which functions as a contact hole, is positioned to overlap with contact hole C20 in a plan view. Specifically, contact hole C201 of pixel P1 overlaps with contact hole C42 of pixel P2, which is adjacent to pixel P1, in a plan view, and contact hole C202 of pixel P2 overlaps with contact hole C43 of pixel P3, which is adjacent to pixel P2, in a plan view.

[0038] Here, pixels P1, P2, and P3 have similar configurations in both planar and cross-sectional views. Therefore, they are described using a common reference numeral. However, when describing the configurations of pixels P1, P2, and P3 separately, different reference numerals are used. Specifically, the configuration of pixel P1 is indicated by adding a 1 to the end of the common code. Similarly, the configuration of pixel P2 is indicated by adding a 2 to the end of the common code, and the configuration of pixel P3 is indicated by adding a 3 to the end of the common code. For example, in the case of pixel electrode 11, pixel electrode 111 indicates that it is the configuration of pixel P1, pixel electrode 112 indicates that it is the configuration of pixel P2, and pixel electrode 113 indicates that it is the configuration of pixel P3. Similarly, in the case of contact hole C20, contact hole C201 indicates that it is the configuration of pixel P1, and contact hole C202 indicates that it is the configuration of pixel P2. The same applies to other configurations below.

[0039] As shown in Figures 5A, 5B, and 5C, the element substrate 10 has a configuration in which multiple functional layers are stacked on a base substrate 10a. More specifically, the following are stacked on the substrate 10a in this order: a first conductive layer including a second capacitance electrode 62 as the other electrode of the capacitance element 60; a second conductive layer including a first capacitance electrode 61 as one electrode of the capacitance element 60; a third conductive layer including a scanning line 13 as a light-shielding member; a semiconductor layer 31 of the TFT 30; a gate electrode 32 of the TFT 30; a fourth conductive layer including a second relay electrode 82 and a fifth relay electrode 85 as conductive members; a fifth conductive layer including a light-shielding film 50; a data line 16; a sixth conductive layer including a first relay electrode 81 and a fourth relay electrode 84; a seventh conductive layer including a common wiring 18 as a capacitance wiring and a third relay electrode 83; and a pixel electrode 11.

[0040] A dielectric film 63 is provided between the second capacitance electrode 62 of the first conductive layer and the first capacitance electrode 61 of the second conductive layer. A first interlayer insulating layer 71 is provided between the second conductive layer and the third conductive layer. A second interlayer insulating layer 72 is provided between the third conductive layer and the semiconductor layer 31. A gate insulating film 332 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer. A third interlayer insulating layer 73 is provided between the fourth conductive layer and the fifth conductive layer. A fourth interlayer insulating layer 74 is provided between the fifth conductive layer and the sixth conductive layer. A fifth interlayer insulating layer 75 is provided between the sixth conductive layer and the seventh conductive layer. A sixth interlayer insulating layer 76 is provided between the seventh conductive layer and the pixel electrode 11.

[0041] Figure 5A shows the configuration of pixel P2. The TFT 302 and capacitive element 602 of pixel P2 are located between pixel P1 and pixel P2 in Figure 4. The capacitive element 602 has a first capacitive electrode 612 located on the scan line 13 side and a second capacitive electrode 622 located on the substrate 10a side. The second capacitive electrode 622 is electrically connected to a fifth relay electrode 852 of the pixel P2, which is provided on the fourth conductive layer, via a contact hole C32 of the pixel P2 provided on the first interlayer insulating layer 71 and the second interlayer insulating layer 72. The fifth relay electrode 852 is electrically connected to the drain 31d2 of the TFT 302 and is also electrically connected to the light-shielding film 502 of the pixel P2, via a contact hole C52 of the pixel P2, which is provided on the third interlayer insulating layer 73.

[0042] A trench 10c2 is provided in the substrate 10a. A portion of the capacitive element 602 is located in the trench 10c2, thereby increasing the capacitance. Furthermore, the data line 16 is electrically connected to the source 31s2 of the TFT 302 via the contact holes C62 of the pixel P2 provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73.

[0043] Figure 5B shows a configuration in which the pixel electrode 111 and the capacitive element 601 are electrically connected in pixel P1. The pixel electrode 111 is electrically connected to the protruding portion 831a of the third relay electrode 831 of the pixel P1, which is provided on the seventh conductive layer, via the contact hole C201 of the pixel P1 provided on the sixth interlayer insulating layer 76. The third relay electrode 831 is electrically connected to the fourth relay electrode 841 of the pixel P1, which is provided in the sixth conductive layer, via the contact hole C101 of the pixel P1, which is provided in the fifth interlayer insulating layer 75.

[0044] The fourth relay electrode 841 is electrically connected to the light-shielding film 501 of the pixel P1, which is provided on the fifth conductive layer, via a contact hole C81 of the pixel P1 provided on the fourth interlayer insulating layer 74. The light-shielding film 501 is electrically connected to the fifth relay electrode 851 of the pixel P1, which is provided in the fourth conductive layer, via the contact hole C51 of the pixel P1, which is provided in the third interlayer insulating layer 73. The fifth relay electrode 851 is electrically connected to the drain 31d1 of the TFT 301 of the pixel P1, and is also electrically connected to the second capacitive electrode 621 via the contact hole C31 of the pixel P1 provided in the second interlayer insulating layer 72 and the first interlayer insulating layer 71. The gate electrode 321 of the TFT 301 is electrically connected to the scan line 13 via the contact hole C11 of the pixel P1 provided in the second interlayer insulating layer 72.

[0045] Furthermore, Figures 5B and 5C show a configuration in which the protruding portion 612a of the first capacitive electrode 612 of the pixel P2 and the protruding portion 822a of the second relay electrode 822 are positioned to overlap cross-sectionally in the Z1 direction, and a configuration in which the contact hole C42 provided between the protruding portion 612a and the protruding portion 822a is provided in a position that does not overlap with the scan line 13 in order to avoid the scan line 13.

[0046] The contact hole C42 penetrates the second interlayer insulating layer 72 and the first interlayer insulating layer 71, and is provided such that the protruding portion 612a of the first capacitive electrode 612 of the capacitive element 602 of the pixel P2 is exposed at the bottom of the contact hole C42. A second relay electrode 822 is deposited on the inside of the contact hole C42, and the second relay electrode 822 is electrically connected to the protruding portion 612a of the first capacitive electrode 612 at the bottom of the contact hole C42. In the second relay electrode 822, the film thickness of the portion deposited on the inner wall of the contact hole C42 is thinner than the film thickness of the portion deposited on the gate insulating film 33.

[0047] Figure 5B also shows a configuration in which the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are located in positions that overlap cross-sectionally in the Z1 direction, and a configuration in which the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are located in positions that overlap cross-sectionally in the Z1 direction. As shown in Figure 4, the contact hole C201 of pixel P1 and the contact hole C42 of pixel P2 are located in positions that overlap in a plan view. Therefore, the protruding portion 831a of pixel P1 and the protruding portions 822a and 612a of pixel P2 are located in positions that overlap in a plan view.

[0048] Figure 5C shows a configuration in which the common wiring 18 and the capacitive element 602 of pixel P2 are electrically connected. The common wiring 18 is electrically connected to the first relay electrode 812 of the pixel P2, which is provided on the sixth conductive layer, via a contact hole C92 of the pixel P2, which is provided on the fifth interlayer insulating layer 75. The first relay electrode 812 is electrically connected to the second relay electrode 822, which is provided on the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73, via a contact hole C72 of the pixel P2, which is provided on the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73. The second relay electrode 822 is electrically connected to the first capacitive electrode 612 of the capacitive element 602, via a contact hole C42 of the pixel P2, which is positioned between the protruding portion 822a of the second relay electrode 822 and the protruding portion 612a of the first capacitive electrode 612 of the capacitive element 602.

[0049] Furthermore, Figure 5C shows a cross-sectional view of a configuration in which the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3, as shown in Figure 4, are located in overlapping positions in a plan view. As shown in Figure 5C, the contact hole C202 of pixel P2 and the contact hole C43 of pixel P3 are located in overlapping positions in the Z1 direction in cross-section.

[0050] Similarly, the protruding portion 832a of pixel P2 and the protruding portions 823a and 613a of pixel P3 are located in positions that overlap in the Z1 direction. Therefore, the protruding portion 832a of pixel P2 and the protruding portions 823a and 613a of pixel P3 are located in positions that overlap in a plan view.

[0051] The contact hole C43 penetrates the second interlayer insulating layer 72 and the first interlayer insulating layer 71, and is provided such that the protruding portion 613a of the first capacitive electrode 613 of the pixel P3 is exposed at the bottom of the contact hole C43. The first capacitive electrode 613 is electrically connected to the second relay electrode 823 of the pixel P3, which is provided on the fourth conductive layer, via the contact hole C43.

[0052] As shown in Figure 5C, the gate electrode 322 of pixel P2 is electrically connected to the scan line 13 through contact holes C12 and C22 of pixel P2 provided in the second interlayer insulating layer 72.

[0053] 1.4. Overview of Liquid Crystal Device Manufacturing Method Next, the manufacturing method of the liquid crystal device 100 according to this embodiment will be described. In the following description, with reference to Figures 6 to 27, the manufacturing process of the element substrate 10, including the characteristic parts of this embodiment, will be explained.

[0054] Figure 6 is a flowchart of the manufacturing process for the element substrate. Figures 7 to 27 are plan views or cross-sectional views showing the pixel correspondence during the manufacturing process of the element substrate. In these drawings, each plan view is a diagram showing the plan view of Figure 4 for each manufacturing process. Also, in each cross-sectional view, the positions of the XX, YY, and ZZ lines are the same.

[0055] The element substrate 10 can be manufactured using methods commonly used in semiconductor processes, such as reduced-pressure CVD (Chemical Vapor Deposition), atmospheric pressure CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or by combining these methods. While preferred manufacturing methods will be described below, other manufacturing methods may be used as long as they can form an equivalent structure and satisfy the functional and characteristic requirements of the configuration.

[0056] In Figure 6, step S1 forms a trench 10c as a groove in the substrate 10a. Alternatively, the trench 10c may be formed by depositing an interlayer insulating layer on the substrate 10a and creating the trench 10c in the interlayer insulating layer or in the relationship between the interlayer insulating layer and the substrate 10a.

[0057] Figure 7 is a plan view showing the pixel configuration of the element substrate in step S1, Figure 8A is a cross-sectional view along the YY line in Figure 7, and Figure 8B is a cross-sectional view along the XX line in Figure 7. As shown in Figure 7, the trench 10c is formed in the light-shielding region SD in the shape of a rectangle that is elongated in the Y1 direction.

[0058] In Figure 6, in step S2, the second capacitive electrode 62 of the capacitive element 60 is formed in the trench 10c. Figure 9 is a plan view showing the pixel configuration of the element substrate in step S2, Figure 10A is a cross-sectional view along the YY line in Figure 9, and Figure 10B is a cross-sectional view along the XX line in Figure 9.

[0059] In step S2, a second capacitive electrode 62 made of a conductive polysilicon film is formed on the substrate 10a, including the inner wall of the trench 10c. A first conductive layer made of phosphorus-containing depopolysilicon is deposited on the substrate 10a to a thickness of 50 nm to 100 nm, and then the second capacitive electrode 62 is formed by dry etching to the shapes shown in Figures 9, 10A, and 10B.

[0060] After forming the second capacitive electrode 62, an oxide island 71a is formed to cover a portion of the second capacitive electrode 62. The oxide island 71a is formed by depositing a silicon oxide film, such as a TEOS (Tetraethyl Orthosilicate) film or an HTO (High Temperature Oxide) film, to a thickness of approximately 100 nm, and then patterning it. The oxide island 71a is positioned where the contact hole C3, described later, will be provided, and functions as an etching stopper film to protect the second capacitive electrode 62 when patterning the first capacitive electrode 61, described later.

[0061] In Figure 6, step S3 involves forming the first capacitive electrode 61 of the capacitive element 60. Figure 11 is a plan view showing the pixel configuration of the element substrate in step S3, Figure 12A is a cross-sectional view along the YY line in Figure 11, Figure 12B is a cross-sectional view along the XX line in Figure 11, and Figure 12C is a cross-sectional view along the ZZ line in Figure 11.

[0062] In step S3, first, a dielectric film 63 is formed on the second capacitance electrode 62, and then the first capacitance electrode 61 is formed. A dielectric film 63, such as a silicon oxide (SiO2) film, a silicon nitride (SiN) film, or a metal oxide film (HfO2, ZrO2), is deposited on the second capacitance electrode 62 to a thickness of 20 nm.

[0063] Subsequently, a first capacitive electrode 61 made of a conductive polysilicon film is formed on the dielectric film 63. A second conductive layer made of phosphorus-containing depopolysilicon is deposited on the dielectric film 63 to a thickness of 50 nm to 100 nm, and then the dielectric film 63 and the first capacitive electrode 61 are formed by patterning using dry etching.

[0064] As shown in Figure 11, the first capacitance electrode 61 is formed to have a larger area than the second capacitance electrode 62, except for the portion where the contact hole C3 for the fifth relay electrode 85, which will be described later, is provided. Also, as shown in Figures 12A, 12B, and 12C, the dielectric film 63 is formed in the same shape as the second capacitance electrode 62, and a portion of its outer edge covers the second capacitance electrode 62 and is in contact with the substrate 10a.

[0065] As shown in Figure 12A, in the first capacitance electrode 61, a portion of the part that overlaps with the oxide film island 71a is removed during patterning.

[0066] As shown in Figure 11, the first capacitive electrode 61 has a protruding portion 61a that extends along the Y-axis direction. A contact hole C4, shown in Figures 5B and 5C, is provided at the location of the protruding portion 61a, and the first capacitive electrode 61 and the second relay electrode 82 are electrically connected via the contact hole C4.

[0067] In Figure 6, step S4 forms the scan line 13. Figure 13 is a plan view showing the pixel configuration of the element substrate in step S4, Figure 14A is a cross-sectional view along the YY line in Figure 13, Figure 14B is a cross-sectional view along the XX line in Figure 13, and Figure 14C is a cross-sectional view along the ZZ line in Figure 13.

[0068] In step S4, first, a first interlayer insulating layer 71 is formed on the first capacitance electrode 61, and then a scanning line 13 is formed. The first interlayer insulating layer 71 is made of, for example, a silicon oxide film made from TEOS, and its thickness is 400 nm to 600 nm.

[0069] A third conductive layer made of tungsten silicide (WSi) film is deposited on the first interlayer insulating layer 71 to a thickness of 100 nm to 400 nm, and then, as shown in Figure 13, patterning is performed to form a scanning line 13. The scanning line 13 extends along the X axis and, in a plan view, overlaps with the trench 10c, and has an overhang portion 13a extending in the Y1 and Y2 directions, a wide portion 13b that is wider in the X1 and X2 directions, and a notched portion 13c where it overlaps with the overhang portion 61a of the first capacitance electrode 61, where it is cut out in the Y2 direction and the width of the scanning line 13 in the Y2 direction is narrowed. The width of the scanning line 13 in the Y2 direction as a light-shielding member is narrowest at the location where the notched portion 13c is provided. Contact holes C1 and C2, described later, are formed at the location of the wide portion 13b, and contact hole C4, described later, is formed at the location where the scan line 13 is cut out by the notch portion 13c. The scan line 13 is made of a light-shielding metallic material and functions as a light-shielding portion of the TFT 30.

[0070] As shown in Figure 13, the protruding portion 61a of the first capacitive electrode 61 of the capacitive element 60 protrudes in the Y1 direction from the notch 13c of the scan line 13. Furthermore, a part of the protruding portion 61a protrudes into the light-transmitting region of the pixel P in a plan view.

[0071] In Figure 6, step S5 involves forming the semiconductor layer 31 of the TFT 30. Figure 15 is a plan view showing the pixel configuration of the element substrate in step S5, Figure 16A is a cross-sectional view along the YY line in Figure 15, and Figure 16B is a cross-sectional view along the XX line in Figure 15.

[0072] In step S5, first, a second interlayer insulating layer 72 is formed on the scan line 13, and then a semiconductor layer 31 is formed. The second interlayer insulating layer 72 is made of, for example, a TEOS film, and its thickness is 200 nm to 600 nm. After depositing amorphous silicon on the second interlayer insulating layer 72, a semiconductor layer 31 made of polysilicon is formed by heat treatment. As shown in Figures 15, 16A, and 16B, the semiconductor layer 31 is provided such that its channels overlap with the trench 10c in a plan view.

[0073] In Figure 6, step S6 forms contact holes C1, C2, C3, and C4. Figure 17 is a plan view showing the pixel configuration of the element substrate in step S6, Figure 18A is a cross-sectional view along the YY line in Figure 17, Figure 18B is a cross-sectional view along the XX line in Figure 17, and Figure 18C is a cross-sectional view along the ZZ line in Figure 17.

[0074] In step S6, first, a gate insulating film 33 is formed on the semiconductor layer 31, then contact holes C1 and C2 are formed, and then contact holes C3 and C4 are formed. A gate insulating film 33 made of HTO film is deposited on the semiconductor layer 31 to a thickness of 30 nm to 100 nm. Subsequently, channel doping is selectively performed on the channels of the semiconductor layer 31.

[0075] As shown in Figures 17 and 18B, the contact holes C1 and C2 are positioned on either side of the channel of the semiconductor layer 31 in a plan view, overlapping with the wide portion 13b of the scan line 13, and penetrate the gate insulating film 33 and the second interlayer insulating layer 72, exposing the scan line 13 at the bottom of the contact holes C1 and C2.

[0076] As shown in Figures 17 and 18A, the contact hole C3 penetrates the gate insulating film 33, the second interlayer insulating layer 72, the first interlayer insulating layer 71, and the oxide film island 71a, exposing the second capacitance electrode 62 of the capacitance element 60 at the bottom of the contact hole C3. The drain 31d of the semiconductor layer 31 is exposed inside the contact hole C3. Furthermore, at the entrance of the contact hole C3, a portion of the gate insulating film 33 covering the drain 31d of the semiconductor layer 31 is peeled off, exposing the drain 31d of the semiconductor layer 31.

[0077] As shown in Figures 17 and 18C, the contact hole C4 penetrates the gate insulating film 33, the second interlayer insulating layer 72, and the first interlayer insulating layer 71, exposing the protruding portion 61a of the first capacitive electrode 61 of the capacitive element 60 at the bottom of the contact hole C4.

[0078] Furthermore, as shown in Figure 17, the contact hole C4 is surrounded by the notch 13c of the scan line 13 in three directions, namely the Y2 direction, the X1 direction, and the X2 direction. By providing the notch 13c in the scan line 13 and placing the contact hole C4 in the notch 13c of the scan line 13 in this way, it is possible to reduce the amount by which the contact hole C4 and a part of the protruding portion 61a of the first capacitive electrode 61 protrude into the light transmission region of the pixel P in a plan view, compared to when the contact hole C4 is not placed in the notch 13c.

[0079] The inner wall of contact hole C4 is inclined at an angle of approximately 84° with respect to the surface of substrate 10a. The inner wall of contact hole C4 can be inclined to a desired angle by adjusting the etching gas. Because the inner wall of contact hole C4 is inclined at approximately 84°, the size (area) of the hole on the entrance side of contact hole C4 is larger than the size (area) of the hole on the bottom side. Therefore, the shape of contact hole C4 is an inverted truncated square pyramidal

[0080] By making the shape of the contact hole C4 an inverted pyramidal pyramid or the like, if the size of the entrance side of the contact hole C4 is the same, the position of the contact hole C4 when viewed from above can be brought closer to the scan line 13 than if the shape of the contact hole C4 were a rectangular prism or cylinder.

[0081] In this embodiment, the inclination angle of the inner wall of the contact hole C4 is set to be more inclined than usual. In this embodiment, the inclination angle of the inner wall of the contact hole C4 is set to approximately 84°, which is more inclined than usual. This allows the position of the contact hole C4, when viewed from above, to be closer to the scan line 13 than usual, while still ensuring clearance between the contact hole C4 and the scan line 13. Furthermore, in this embodiment, the inclination angle of the inner wall of the contact hole C4 is steeper than usual, so that clearance between the contact hole C4 and the scan line 13 can be secured without relying on miniaturization in the photolithography process. Therefore, the position where the contact hole C4 is provided when viewed from above can be brought closer to the scan line 13 than in the usual case.

[0082] In Figure 6, step S7 involves forming the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85. Figure 19 is a plan view showing the pixel configuration of the element substrate in step S7, Figure 20A is a cross-sectional view along the YY line in Figure 19, Figure 20B is a cross-sectional view along the XX line in Figure 19, and Figure 20C is a cross-sectional view along the ZZ line in Figure 19.

[0083] In step S7, a fourth conductive layer is formed on the gate insulating film 33 and inside the contact holes C1, C2, C3, and C4, consisting of a conductive polysilicon film and a light-shielding conductive tungsten silicide film. Since contact holes C3 and C4 are small in diameter and deep, so-called high aspect ratio contact holes, to ensure proper coverage inside contact holes C3 and C4, a phosphorus-containing depopolysilicon film is first deposited, followed by the lamination of a light-shielding conductive film, tungsten silicide. This allows the interior of contact holes C3 and C4 to be covered well by the fourth conductive layer.

[0084] After forming the fourth conductive layer, the fourth conductive layer is patterned as shown in Figure 19 to form the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85. As a result, the gate electrode 32 is electrically connected to the scan line 13 via contact holes C1 and C2.

[0085] The second relay electrode 82 has a protruding portion 82a that extends in the Y1 direction from the notch 13c of the scan line 13 in a plan view. This protruding portion 82a and the protruding portion 61a protrude from the scan line 13 and overlap in a plan view. The second relay electrode 82 and the first capacitive electrode 61 of the capacitive element 60 are electrically connected via a contact hole C4.

[0086] Furthermore, as shown in Figure 19, the protruding portion 82a of the second relay electrode 82 overlaps with the protruding portion 61a of the first capacitive electrode 61 in a plan view. Also, similar to the protruding portion 61a, the protruding portion 82a protrudes from the notch portion 13c of the scan line 13 along the Y1 direction, and a part of the protruding portion 82a protrudes into the light-transmitting region of the pixel P in a plan view.

[0087] The fifth relay electrode 85 is electrically connected to the second capacitive electrode 62 of the capacitive element 60 via the contact hole C3. As described above, the gate electrode 32 is formed on the semiconductor layer 31 and within the contact holes C1 and C2, and is provided so as to surround the semiconductor layer 31 in the Z1, X1, and X2 directions, thereby functioning as a light-shielding portion of the semiconductor layer 31.

[0088] In Figure 6, step S8 involves forming a light-shielding film 50. Figure 21 is a plan view showing the pixel configuration of the element substrate in step S8, Figure 22A is a cross-sectional view along the YY line in Figure 21, and Figure 22B is a cross-sectional view along the XX line in Figure 21.

[0089] In step S8, first, a third interlayer insulating layer 73 made of TEOS film is formed on the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 to a thickness of 200 nm to 400 nm. Then, a contact hole C5 is formed in the third interlayer insulating layer 73 to expose the fifth relay electrode 85.

[0090] Next, a light-shielding film 50 is formed. A fifth conductive layer, made of a metal film such as a tungsten silicide film, which is a light-shielding conductive film, is deposited on the third interlayer insulating layer 73 and inside the contact hole C5 to a thickness of 100 nm to 400 nm. Then, the fifth conductive layer is patterned as shown in Figures 21, 22A, and 22B to form a light-shielding film 50. The light-shielding film 50 is electrically connected to the fifth relay electrode 85 via the contact hole C5. As a result, the light-shielding film 50 is electrically connected to the second capacitance electrode 62 of the capacitance element 60 via the fifth relay electrode 85. The thickness of the light-shielding film 50 is approximately 100 nm. In a plan view, the light-shielding film 50 is positioned to overlap with the capacitance element 60.

[0091] In Figure 6, step S9 forms the data line 16. Figure 23 is a plan view showing the pixel configuration of the element substrate in step S9, Figure 24A is a cross-sectional view along the YY line in Figure 23, and Figure 24B is a cross-sectional view along the XX line in Figure 23.

[0092] In step S9, first, a fourth interlayer insulating layer 74 made of TEOS film is formed on the light-shielding film 50 to a thickness of 500 nm to 1000 nm, and then contact holes C6, C7, and C8 are formed.

[0093] As shown in Figure 24A, the contact hole C6 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73, exposing the source 31s of the TFT 30 at the bottom of the contact hole C6. As shown in Figure 24B, the contact hole C7 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73, exposing the second relay electrode 82 at the bottom of the contact hole C7. As shown in Figure 24B, the contact hole C8 penetrates the fourth interlayer insulating layer 74, exposing the light-shielding film 50 at the bottom of the contact hole C8.

[0094] Next, a sixth conductive layer is formed on the fourth interlayer insulating layer 74 and inside the contact holes C6, C7, and C8, consisting of a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers.

[0095] After forming the sixth conductive layer, the data line 16, the first relay electrode 81, and the fourth relay electrode 84 are formed by patterning the sixth conductive layer as shown in Figure 23. As shown in Figure 24A, the data line 16 is deposited inside the contact hole C6 and electrically connected to the source 31s of the semiconductor layer 31 exposed at the bottom of the contact hole C6.

[0096] As shown in Figure 24B, the first relay electrode 81 is formed inside the contact hole C7 and is electrically connected to the second relay electrode 82 which is exposed at the bottom of the contact hole C7. The fourth relay electrode 84 is formed inside the contact hole C8 and electrically connected to the light-shielding film 50 exposed at the bottom of the contact hole C8.

[0097] In Figure 6, in step S10, a common wiring 18 is formed. Figure 25 is a plan view showing the pixel configuration of the element substrate in step S10, Figure 26A is a cross-sectional view along the YY line in Figure 25, Figure 26B is a cross-sectional view along the XX line in Figure 25, and Figure 26C is a cross-sectional view along the ZZ line in Figure 25.

[0098] In step S10, first, a fifth interlayer insulating layer 75 made of TEOS film is formed on the data line 16, the first relay electrode 81, and the fourth relay electrode 84 to a thickness of 500 nm to 1000 nm.

[0099] Next, contact holes C9 and C10 are formed. As shown in Figure 25, the contact hole C9 is formed in a position that overlaps with the protruding portion 18a extending in the X2 direction from the common wiring 18 in a plan view. Also, as shown in Figure 26B, the contact hole C9 penetrates the fifth interlayer insulating layer 75, exposing the first relay electrode 81 at the bottom of the contact hole C9.

[0100] As shown in Figure 25, the contact hole C10 is formed in the X1 direction of the common wiring 18. Also, as shown in Figure 26B, the contact hole C10 penetrates the fifth interlayer insulating layer 75, exposing the fourth relay electrode 84 at the bottom of the contact hole C10.

[0101] Next, a seventh conductive layer is formed on the fifth interlayer insulating layer 75 and inside the contact holes C9 and C10, consisting of a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers.

[0102] After forming the seventh conductive layer, the common wiring 18 and the third relay electrode 83 are formed by patterning the seventh conductive layer as shown in Figure 25.

[0103] As shown in Figures 25, 26A, and 4, the common wiring 18 is formed in a position that overlaps with the data line 16 both planarly and cross-sectionally. Furthermore, as shown in Figure 26B, it is deposited inside the contact hole C9 and electrically connected to the first relay electrode 81 exposed at the bottom of the contact hole C9.

[0104] The third relay electrode 83 is positioned between the two common wirings 18, as shown in Figure 25. Furthermore, the third relay electrode 83 has a protruding portion 83a that extends in the Y1 direction from the scan line 13 in a plan view. The size of the protruding portion 83a is larger than the protruding portion 82a of the second relay electrode 82. As described above, the protruding portion 831a of the third relay electrode 831 of pixel P1 overlaps with the protruding portion 822a of the second relay electrode 822 of pixel P2 in a plan view. Also, the protruding portion 832a of the third relay electrode 832 of pixel P2 overlaps with the protruding portion 823a of the second relay electrode 823 of pixel P3 in a plan view. As shown in Figure 26B, the third relay electrode 83 is formed inside the contact hole C10 and electrically connected to the fourth relay electrode 84 exposed at the bottom of the contact hole C10.

[0105] In Figure 6, step S11 involves forming the pixel electrode 11. Figure 27 is a plan view showing the pixel configuration of the element substrate in step S11. In step S11, as shown in Figures 5A, 5B, and 5C, first, a sixth interlayer insulating layer 76 made of TEOS film is formed on the common wiring 18 and the third relay electrode 83 to a thickness of 500 nm to 1000 nm.

[0106] Next, a contact hole C20 is formed. As shown in Figures 27 and 5C, the contact hole C20 is formed in a position that overlaps with the protruding portion 83a of the third relay electrode 83 in a plan view. The contact hole C20 also penetrates the sixth interlayer insulating layer 76, exposing the third relay electrode 83 at the bottom of the contact hole C20. The contact hole C20 is provided in the shape of an inverted pyramidal prism or an inverted rounded pyramidal prism. The dimensions of the contact hole C20 are as follows: the longer side of the entrance portion of the hole, i.e., the side on which the pixel electrode 11 is provided, is 1.2 μm, and the shorter side is 0.5 μm. The dimensions of the bottom portion of the hole are 0.4 μm on both the longer and shorter sides. Next, ITO is deposited on the sixth interlayer insulating layer 76 and inside the contact holes C20, and then patterned to form a pixel electrode 11 for each pixel P.

[0107] As described above, the liquid crystal device 100 as an electro-optical device of this embodiment provides the following advantages. The liquid crystal apparatus 100 of this embodiment comprises a substrate 10a, a pixel electrode 11, a common wiring 18 as a capacitive wiring provided between the substrate 10a and the pixel electrode 11, a TFT 30 as a transistor provided between the substrate 10a and the common wiring 18, a scanning line 13 as a light-shielding member provided between the substrate 10a and the TFT 30 along a first direction, and a capacitive element 60 provided between the substrate 10a and the scanning line 13, which overlaps with the scanning line 13 in a plan view, and common The device comprises a second relay electrode 82 as a conductive member electrically connected to the wiring 18 and overlapping with the scan line 13 in a plan view, the scan line 13 having a notch 13c provided between the second relay electrode 82 and the first capacitive electrode 61 as one electrode of the capacitive element 60, and the second relay electrode 82 and the first capacitive electrode 61 of the capacitive element 60 are electrically connected via a contact hole C4 as a contact hole, at least a portion of which is provided inside the notch 13c in a plan view.

[0108] In this embodiment, the liquid crystal device 100 has a second relay electrode 82 and a first capacitive electrode 61 of a capacitive element 60 that are electrically connected via a contact hole C4 that overlaps the scan line 13 and the first capacitive electrode 61 in a plan view. Therefore, since each capacitive element 60 is connected to a common wiring 18 for each pixel P, the potential of the first capacitive electrode 61 connected to the common wiring 18 is stable, and problems such as display unevenness can be suppressed.

[0109] Furthermore, the scanning line 13 is provided between the second relay electrode 82 and the first capacitive electrode 61 and has a notch 13c that surrounds the contact hole C4 in at least three directions. Therefore, the amount by which the contact hole C4, the first capacitive electrode 61, and a part of the second relay electrode 82 protrude into the light-transmitting region of the pixel P in a plan view can be reduced. Note that the light-shielding member is not limited to the scan lines 13. For example, the light-shielding member may be other signal lines besides the scan lines 13, or a light-shielding film provided in the form of wiring or islands.

[0110] In this embodiment, the liquid crystal display device 100 further has the narrowest width in the second direction intersecting the first direction of the scan lines 13, which act as a light-shielding member, at the location where the notch 13c is provided. Therefore, the amount by which the contact hole C4, the first capacitive electrode 61, and the second relay electrode 82 protrude into the light-transmitting region of the pixel P in a plan view can be reduced.

[0111] In this embodiment, the liquid crystal apparatus 100 further includes a first capacitive electrode 61 as one of the electrodes, which contains polysilicon, and a second relay electrode 82 as a conductive member, which contains polysilicon. Thus, in the liquid crystal device 100 of this embodiment, since the first capacitive electrode 61 and the second relay electrode 82 each contain polysilicon, the protruding portions 61a and 82a are light-transmitting. Therefore, even if the protruding portions 61a and 82a protrude from the scan line 13 and are positioned in the light-transmitting region of the pixel P, the effect on transmittance is small, so electrical conductivity can be established between the second relay electrode 82 and the first capacitive electrode 61 while suppressing the dimming of the display.

[0112] In this embodiment, the liquid crystal apparatus 100 further comprises a second relay electrode 82 as a conductive member, which includes a layer containing polysilicon and a layer containing tungsten silicide.

[0113] In this embodiment, the liquid crystal display device 100 further has the scanning lines 13, which are conductive members, provided in the same layer as the gate electrode 32 of the TFT 30, which is a transistor. Thus, in the liquid crystal apparatus 100 of this embodiment, the second relay electrode 82 and the gate electrode 32 are provided on the same fourth conductive layer, the scan line 13 is provided on the third conductive layer, and the first capacitive electrode 61 is provided on the second conductive layer. Therefore, it is possible to prevent the distance between the second relay electrode 82 and the first capacitive electrode 61 from becoming too large, and thus it is possible to prevent the aspect ratio of the contact hole C4 provided between the protruding portion 82a and the protruding portion 61a from becoming too large, thereby ensuring good electrical connection between the second relay electrode 82 and the first capacitive electrode 61.

[0114] In this embodiment, the liquid crystal device 100 further has a portion of the scan line 13 that is located inside the contact hole C4, and the thickness of the portion located inside the contact hole C4 is thinner than the thickness of the gate electrode 32.

[0115] In this embodiment, the liquid crystal apparatus 100 further provides the contact hole C4 in the first interlayer insulating layer 71 and the second interlayer insulating layer 72, which serve as interlayer insulating layers between the scan line 13 and the first capacitive electrode 61, and the inner area of ​​the contact hole C4 on the scan line 13 side is larger than the inner area of ​​the contact hole C4 on the first capacitive electrode 61 side.

[0116] In other words, in this embodiment, the shape of the contact hole C4 is an inverted truncated cone or the like. Therefore, if the size (area) of the entrance side and the bottom side of the contact hole C4 are the same, that is, if the shape of the contact hole C4 is a rectangular prism or cylinder, the position of the contact hole C4 when viewed from above can be brought closer to the scan line 13. Furthermore, if the shape of the contact hole C4 is a rectangular prism or cylinder, in order to bring the contact hole C4 closer to the scan line 13 while ensuring clearance between the contact hole C4 and the scan line 13, it is necessary to further miniaturize the contact hole C4. However, in this embodiment, the position of the contact hole C4 when viewed from above can be brought closer to the scan line 13 without relying on miniaturization in the photolithography process. Therefore, the position of the contact hole C4 can be brought closer to the light-shielding region SD, the portion protruding into the light-shielding region can be reduced, and the decrease in transmittance can be further suppressed.

[0117] In this embodiment, the liquid crystal apparatus 100 further has a second capacitive electrode 62, which serves as the other electrode of the capacitive element 60, provided between the substrate 10a and the first capacitive electrode 61, and is electrically connected to the pixel electrode 11.

[0118] As described above, in the liquid crystal device 100 of this embodiment, the first capacitive electrode 61 of the capacitive element 60 is laminated on the second capacitive electrode 62, or in other words, it is formed on the second capacitive electrode 62. Therefore, the first capacitive electrode 61 is prone to unevenness and inconsistencies in its thickness. When unevenness or inconsistencies in thickness occur on the first capacitive electrode 61, the first capacitive electrode 61 becomes highly resistant, which can easily lead to problems such as display inconsistencies. However, in this embodiment, since the first capacitive electrode 61 is electrically connected to the common wiring 18, the occurrence of problems such as display inconsistencies can be suppressed. Furthermore, since the first capacitive electrode 61 is positioned between the second capacitive electrode 62, which is electrically connected to the pixel electrode 11, and the scan line 13, the second capacitive electrode 62 can be shielded from the scan line 13, thereby suppressing the impact on the display.

[0119] In this embodiment, the liquid crystal device 100 further has a portion of the first capacitive electrode 61 and the second capacitive electrode 62 of the capacitive element 60 located inside a trench 10c which serves as a groove. As described above, the liquid crystal device 100 of this embodiment has a portion in which the first capacitive electrode 61 and the second capacitive electrode 62 of the capacitive element 60 are provided inside the trench 10c, which makes the first capacitive electrode 61 prone to uneven film thickness and cracking. However, even if the first capacitive electrode 61 becomes highly resistive due to uneven thickness or cracking, the first capacitive electrode 61 is electrically connected to the common wiring 18, so problems such as display unevenness can be suppressed.

[0120] 2. Embodiment 2 2.1. Overview of Display Devices Figure 28 is a schematic diagram showing the configuration of a projection-type display device as a display device according to this embodiment. In this embodiment, a display device equipped with the liquid crystal device 100 as an electro-optical device described above will be explained using the projection-type display device 1000 as an example.

[0121] As shown in Figure 28, the projection-type display device 1000 of this embodiment includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, a liquid crystal device 100B for blue light, a liquid crystal device 100G for green light, a liquid crystal device 100R for red light, three reflective mirrors 1111, 1112, and 1113, three relay lenses 1121, 1122, and 1123, a dichroic prism 1130 as a color synthesis optical system, and a projection lens 1140 as a projection optical system.

[0122] The lamp unit 1001 employs, for example, a discharge-type light source. The type of light source is not limited to this, and solid-state light sources such as light-emitting diodes and lasers may also be used.

[0123] Light emitted from the lamp unit 1001 is separated into three colors of light in different wavelength ranges by two dichroic mirrors 1011 and 1012. These three colors of light are roughly red light, roughly green light, and roughly blue light. In the following explanation, the roughly red light will also be referred to as red light R, the roughly green light as green light G, and the roughly blue light as blue light B.

[0124] The dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. The red light R that has passed through the dichroic mirror 1011 is reflected by the reflective mirror 1111 and incident on the liquid crystal device 100R. The green light G reflected by the dichroic mirror 1011 is reflected by the dichroic mirror 1012 and then incident on the liquid crystal device 100G. The blue light B reflected by the dichroic mirror 1011 passes through the dichroic mirror 1012 and is emitted to the relay lens system 1120.

[0125] The relay lens system 1120 includes relay lenses 1121, 1122, and 1123, and reflective mirrors 1112 and 1113. Blue light B has a longer optical path compared to green light G and red light R, so its luminous flux tends to be larger. Therefore, relay lens 1122 is used to suppress the expansion of the luminous flux. Blue light B incident on the relay lens system 1120 is reflected by reflective mirror 1112 and focused near relay lens 1122 by relay lens 1121. Then, the blue light B passes through reflective mirror 1113 and relay lens 1123 before being incident on the liquid crystal device 100B.

[0126] In the projection-type display device 1000, the liquid crystal devices 100R, 100G, and 100B, which are optical modulation devices, are the liquid crystal device 100 as an electro-optical device according to Embodiment 1.

[0127] Each of the liquid crystal units 100R, 100G, and 100B is electrically connected to the higher-level circuit of the projection display device 1000. This allows image signals Dx, which specify the gradation levels of red light R, green light G, and blue light B, to be supplied from external circuits and processed by the higher-level circuit. This drives the liquid crystal units 100R, 100G, and 100B, modulating their respective color lights.

[0128] Red light R, green light G, and blue light B, modulated by the liquid crystal devices 100R, 100G, and 100B, are incident on the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. In the dichroic prism 1130, the red light R and blue light B are reflected at a 90-degree angle, while the green light G is transmitted. Therefore, the red light R, green light G, and blue light B are combined as display light to display a color image and emitted toward the projection lens 1140.

[0129] The projection lens 1140 is positioned facing outwards from the projection display device 1000. The display light is amplified and emitted through the projection lens 1140 and projected onto the screen 1200, which is the projection target.

[0130] In this embodiment, a projection-type display device 1000 is exemplified as the display device, but the display device to which the liquid crystal device 100 is applied is not limited to this. For example, it may be applied to display devices such as projection-type HUDs (Head-Up Displays), HMDs (Head-Mounted Displays), personal computers, digital cameras, and liquid crystal televisions. As described above, the projection display device 1000 of this embodiment provides the following effects in addition to the effects of each of the embodiments described above. The projection-type display device 1000, as a display device, preferably comprises a liquid crystal device 100 as an electro-optical device according to each of the above embodiments.

[0131] This configuration enables miniaturization or increased resolution of the liquid crystal display 100 mounted on the projection display device 1000. As a result, the projection display device 1000 equipped with the liquid crystal display 100 can be miniaturized, and high-resolution display can be achieved without increasing the size of the projection display device 1000, thus providing an excellent display device.

[0132] Furthermore, in the above embodiment, a transmissive liquid crystal device was exemplified as the liquid crystal device 100 as an electro-optical device, but the liquid crystal device 100 may also be a reflective liquid crystal device or an LCOS (Liquid crystal on silicon) type liquid crystal device. [Explanation of symbols]

[0133] 5…Liquid crystal layer, 6…Sealing material, 7…Upper and lower conductive section, 10…Element substrate, 10a…Substrate, 10c…Trench, 11,111,112,113…Pixel electrode, 12…Alignment film, 13…Scanning line, 13a…Protruding section, 13b…Wide section, 13c…Notch section, 16…Data line, 18…Common wiring, 18a…Protruding section, 20…Opposite substrate, 20a…Substrate, 21…Opposite electrode, 30,301,302…TFT, 31…Semiconductor layer, 31d…Drain 31s...Source, 32,321,322...Gate electrode, 33,332...Gate insulating film, 43...External connection terminal, 45...Scan line drive circuit, 47...Data line drive circuit, 49...Wiring, 50,501,502...Light-shielding film, 60,601,602...Capacitor element, 61,612,613...First capacitive electrode, 61a,612a,613a...Protruding portion, 62,621,622...Second capacitive electrode, 63...Dielectric film, 71...First interlayer insulating layer, 71a …Oxide film island, 72…Second interlayer insulating layer, 73…Third interlayer insulating layer, 74…Fourth interlayer insulating layer, 75…Fifth interlayer insulating layer, 76…Sixth interlayer insulating layer, 81,812…First relay electrode, 82,822,823…Second relay electrode, 82a,822a,823a…Protruding portion, 83,831,832…Third relay electrode, 83a,831a,832a…Protruding portion, 84,841…Fourth relay electrode, 85,851,852…Fifth relay electrode, 100 ,100B,100G,100R...Liquid crystal display unit, 1000...Projection type display device, 1001...Lamp unit, 1011,1012...Dichroic mirror, 1111,1112,1113...Reflective mirror, 1120...Relay lens system, 1130...Dichroic prism, 1140...Projection lens, 1200...Screen, C4,C42,C43...Contact hole, E...Display area, F...Peripheral area, P...Pixel, SD...Shading area.

Claims

1. A substrate; A pixel electrode; a capacitance wiring provided between the substrate and the pixel electrode; a transistor provided between the substrate and the capacitance wiring; a light blocking member provided along a first direction between the substrate and the transistor and having a notch; a capacitance element provided between the substrate and the light shielding member and overlapping the light shielding member in a plan view; a conductive member electrically connected to the capacitance wiring and overlapping the light blocking member in a plan view; the conductive member and one electrode of the capacitance element are electrically connected to each other through a contact hole, at least a portion of which is provided inside the cutout portion of the light blocking member in a plan view; Electro-optical device.

2. A width of the light blocking member in a second direction intersecting with the first direction is narrowest at a portion where the cutout portion is provided.

2. The electro-optical device according to claim 1.

3. the one electrode includes polysilicon, and the conductive member includes polysilicon; 2. The electro-optical device according to claim 1.

4. the conductive member has a layer containing polysilicon and a layer containing tungsten silicide; 2. The electro-optical device according to claim 1.

5. The conductive member is provided in the same layer as the gate electrode of the transistor.

2. The electro-optical device according to claim 1.

6. the conductive member has a portion provided inside the contact hole, and the thickness of the portion provided inside the contact hole is thinner than the thickness of the gate electrode; 6. The electro-optical device according to claim 5.

7. the contact hole is provided in an interlayer insulating layer between the conductive member and the one electrode, and an inner area of ​​the contact hole on the conductive member side is larger than an inner area of ​​the contact hole on the one electrode side; 2. The electro-optical device according to claim 1.

8. the other electrode of the capacitive element is provided between the substrate and the one electrode, and is electrically connected to the pixel electrode; 2. The electro-optical device according to claim 1.

9. a portion of the one electrode and the other electrode of the capacitance element is provided inside a groove provided in the substrate; 9. The electro-optical device according to claim 8.

10. A display device comprising the electro-optical device according to claim 1 .

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