Game machine

Abstract

To provide a game machine that allows a game to be played appropriately.SOLUTION: A game machine includes first control means for controlling the progress of a game, a first display unit corresponding to the first control means, second control means capable of communicating with the first control means, and a second display unit corresponding to the second control means. When one or both of a first event and a second event occur, the progress of a game is restricted. When the first event occurs, the first control means displays on the first display unit that the first event has occurred but the second control means does not display on the second display unit that the first event has occurred. When the second event occurs, the first control means displays on the first display unit that the second event has occurred and the second control means displays on the second display unit that the second event has occurred. When the second event occurs overlapping with the first event after the first event occurs, the first control means displays on the first display unit that the first event has occurred, and the second control means displays on the second display unit that the second event has occurred.SELECTED DRAWING: Figure 68

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Smart pachislot machines are being considered that can play without the use of actual medals while maintaining the playability of slot machines (for example, Patent Document 1).Smart pachinko machines are also being considered that use a sealed circulation system to allow players to play without touching the game balls (for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-134014 [Patent Document 2] Japanese Patent Publication No. 2020-156551 Summary of the Invention [Problem to be solved by the invention]

[0004] In such smart pachislots and smart pachinko machines, there is no need to provide a path for distributing gaming media such as gaming balls and medals outside the gaming machine, and physical gaming media themselves are unnecessary in smart pachislots. In this way, no gaming media is used in smart pachislots, and by using non-magnetic gaming balls in smart pachinko machines, it is possible to prevent cheating that requires the use of metallic gaming media. Furthermore, since there is no need to provide a mechanism for inserting and dispensing gaming media within the gaming machine, design and manufacturing costs can be reduced. Furthermore, by centrally managing the lending of gaming media to players and the counting of acquired gaming media, it is possible to prevent cheating and curb gambling.

[0005] On the other hand, for configurations that use electronic gaming media (gaming value) or non-magnetic gaming media instead of physical gaming media, a new mechanism is needed that manages the electronic gaming media while allowing the game to proceed appropriately.

[0006] In view of the above problems, the present invention aims to provide a gaming machine that allows the game to proceed appropriately. [Means for solving the problem]

[0007] In order to solve the above problem, the gaming machine of the present invention comprises a first control means for controlling the progress of the game, a first display unit corresponding to the first control means, a second control means capable of communicating with the first control means, and a second display unit corresponding to the second control means, wherein the progress of the game is restricted when either or both of a first event and a second event different from the first event occur, wherein when the first event occurs, the first control means displays on the first display unit that the first event has occurred, and the second control means does not display on the second display unit that the first event has occurred, wherein when the second event occurs, the first control means displays on the first display unit that the second event has occurred, and the second control means displays on the second display unit that the second event has occurred, wherein when the second event occurs after the first event has occurred and overlaps with the first event, the first control means displays on the first display unit that the first event has occurred, and the second control means displays on the second display unit that the second event has occurred. [Effects of the Invention]

[0008] According to the present invention, it is possible to progress the game appropriately. [Brief explanation of the drawings]

[0009] [Figure 1] This is an external view for explaining the general mechanical configuration of the smart pachislot. [Figure 2] A block diagram showing the general electrical configuration of the smart pachislot and the dedicated unit. [Figure 3] This is an external view for explaining the general mechanical configuration of the smart pachislot and dedicated unit. [Figure 4] 10 is a flowchart showing main processing of the main control board. [Figure 5] FIG. 10 is an explanatory diagram for explaining another substrate configuration. [Figure 6] FIG. 10 is an explanatory diagram for explaining the enclosure state of the case. [Figure 7] This is an explanatory diagram to explain the CPU and areas that execute each function of the smart pachislot. [Figure 8] FIG. 10 is an explanatory diagram for explaining the format of a gaming machine information notification. [Figure 9] FIG. 10 is an explanatory diagram for explaining the format of a gaming machine information notification. [Figure 10] FIG. 10 is an explanatory diagram for explaining the format of a gaming machine information notification. [Figure 11] FIG. 10 is an explanatory diagram for explaining the format of a gaming machine information notification. [Figure 12] FIG. 10 is an explanatory diagram illustrating the format of a counting notification. [Figure 13] FIG. 10 is an explanatory diagram illustrating the format of a loan acceptance result response. [Figure 14] FIG. 10 is an explanatory diagram illustrating the format of a lending notification. [Figure 15] 10 is a timing chart showing the timing of notification of gaming machine information, counting notification, loan notification, and loan receipt result response. [Figure 16] FIG. 10 is an explanatory diagram for explaining the timing of transmitting a gaming machine information notification. [Figure 17] 10 is a flowchart showing the flow of the counting switch monitoring process in the medal CPU. [Figure 18] 10 is a flowchart showing the flow of counting processing in the medal CPU. [Figure 19] 10 is a timing chart for explaining a counting process. [Figure 20]10 is a timing chart for explaining the display mode of the number of game medals. [Figure 21] 10 is a flowchart showing the flow of counting switch processing in the medal CPU. [Figure 22] 10 is a time chart illustrating the setting of the number of counted medals. [Figure 23] 10 is a flowchart showing the flow of count switch processing according to a modified example in which all signals received multiple times are effectively processed. [Figure 24] 10 is a time chart illustrating the setting of the number of counted medals according to a modified example in which all multiple signals are effectively processed. [Figure 25] 10A and 10B are diagrams illustrating the operation when the game sound and the counting sound overlap. [Figure 26] 10 is a flowchart illustrating a counting sound process executed by a performance control means. [Figure 27] FIG. 10 is an explanatory diagram for explaining errors managed by the main control board. [Figure 28] An explanatory diagram for explaining errors managed by the medal count control board. [Figure 29] 10 is a flowchart illustrating the flow of a volume control process executed by a performance control means. [Figure 30] 10 is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 31] 10 is a flowchart showing the flow of manufacturer code confirmation processing in the medal CPU. [Figure 32] 10 is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 33] 10 is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 34] 10 is a flowchart showing the flow of a process for outputting an anti-tamper signal. [Figure 35] 10 is a flowchart showing the flow of a process for outputting an anti-tamper signal. [Figure 36] 10 is a flowchart showing the flow of a command monitoring process. [Figure 37] 10 is a flowchart showing the flow of a command monitoring process. [Figure 38] 10 is a flowchart showing the flow of a command monitoring process. [Figure 39] 10 is a flowchart showing communication specifications when power is turned on. [Figure 40] 10 is a flowchart showing communication specifications during operation. [Figure 41] 10 is a flowchart showing communication specifications at the end of a game. [Figure 42] 10 is a flowchart showing the flow of bet processing in the medal CPU. [Figure 43] FIG. 10 is an explanatory diagram showing an example of actual calculation in the betting process. [Figure 44] 10 is a timing chart illustrating the communication mode between the main CPU and the medal CPU. [Figure 45] 10 is a timing chart illustrating the communication mode between the main CPU and the medal CPU. [Figure 46] 10 is a flowchart showing a process of updating a setting change signal. [Figure 47] 10 is a flowchart showing an update process of a setting confirmation signal. [Figure 48] FIG. 10 is an explanatory diagram showing a comparative example of communication processing between a main CPU and a medal CPU. [Figure 49] FIG. 10 is a flowchart illustrating the concept of transmitting one byte of a command, and a diagram illustrating the command. [Figure 50] FIG. 10 is an explanatory diagram showing communication processing between the main CPU and the medal CPU. [Figure 51] FIG. 2 is an explanatory diagram for explaining communication processing between a main CPU and a sub-CPU. [Figure 52] FIG. 10 is an explanatory diagram for explaining another communication process between the main CPU and the sub-CPU. [Figure 53] 10 is a flowchart illustrating a communication process. [Figure 54] FIG. 10 is an explanatory diagram for explaining the display mode of an electronic medal. [Figure 55] FIG. 10 is an explanatory diagram for explaining the display mode of an electronic medal. [Figure 56] FIG. 10 is an explanatory diagram for explaining a gaming machine information display. [Figure 57] 10 is an explanatory diagram for explaining a gaming machine information display and an addiction prevention display. FIG. [Figure 58] 10 is an explanatory diagram for explaining the gaming machine information display, the addiction prevention display, and the suggestion display. FIG. [Figure 59] FIG. 10 is an explanatory diagram for explaining a suggestion display. [Figure 60] 10A and 10B are explanatory diagrams showing display modes of possession count warning notification and error notification. [Figure 61] 10 is a timing chart showing changes in display modes due to notifications. [Figure 62] 5 is a flowchart showing the flow of the payout process in FIG. 4. [Figure 63] 10 is a flowchart showing the flow of an error monitoring process which is part of a timer interrupt process in the main control board. [Figure 64] 10 is a timing chart showing changes in display modes due to notifications. [Figure 65] 10 is a timing chart showing changes in display modes due to notifications. [Figure 66] 10 is a timing chart showing changes in display modes due to notifications. [Figure 67] 10 is a timing chart showing changes in display modes due to notifications. [Figure 68] 10 is a timing chart showing changes in display modes due to notifications. [Figure 69] This is an explanatory diagram for explaining the test firing test of smart pachislot. [Figure 70] FIG. 10 is an explanatory diagram for explaining the operation of the slot machine. [Figure 71] FIG. 10 is an explanatory diagram for explaining the operation of the smart pachislot. [Figure 72] FIG. 2 is a rear view of the gaming machine according to the embodiment. [Figure 73] FIG. 2 is a rear view of the gaming machine according to the embodiment with the cover member removed. [Figure 74] 1 is a plan view showing a board case for a sub-control board of an amusement machine according to an embodiment of the present invention. [Figure 75] FIG. 2 is a plan view showing a cover member of the gaming machine according to the embodiment. [Figure 76] 1 is a perspective view showing a board case for a frame control board of an amusement machine according to an embodiment of the present invention; [Figure 77] 10 is an oblique view showing a state in which the top surface side member of the board case for the frame control board of the gaming machine according to the embodiment has been removed. FIG. [Figure 78] FIG. 78 is a cross-sectional view showing the XX section of FIG. 77. [Figure 79] FIG. 2 is a perspective view showing a top surface of the electrolytic capacitor. [Figure 80] A cross-sectional view showing the configuration of a board case for a frame control board of a gaming machine according to a modified example. [Figure 81] FIG. 2 is a partially enlarged view showing the ball return prevention mechanism in the first state. [Figure 82] FIG. 4 is a partially enlarged view showing the ball return prevention mechanism in the second state. [Figure 83] A partially enlarged view showing the ball return prevention mechanism in a third state. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Dimensions, materials, and other specific values ​​shown in these embodiments are merely examples for facilitating understanding of the invention and, unless otherwise specified, do not limit the present invention. In this specification and drawings, elements having substantially the same functions and configurations are designated by the same reference numerals to avoid redundant explanation, and elements not directly related to the present invention are not shown.

[0011] (First embodiment: smart pachislot 100) The Smart Pachislot 100 maintains the gameplay of a slot machine while allowing the game to proceed without the use of actual medals. Slot machines are conventional gaming machines that have existed for a long time, and differ from the Smart Pachislot 100 in that the game proceeds with the use of actual medals. The Smart Pachislot 100 uses electronic medals as electronic game value for the game, instead of actual medals.

[0012] (Smart Pachislot 100 mechanical configuration) As shown in the external view of FIG. 1, a smart pachislot 100 gaming machine includes a cabinet 102 and an upper front door 104 and a lower front door 106 that are rotatably arranged vertically at one end of the front of the cabinet 102. A colorless and transparent symbol display window 108 made of a glass plate, a transparent resin plate, or the like is provided in the approximate center of the lower part of the upper front door 104. Three reels 110 (left reel 110a, center reel 110b, and right reel 110c) are provided in positions corresponding to the symbol display window 108 in the cabinet 102 so that they can rotate independently. A plurality of types of symbols are arranged on the outer peripheries of the left reel 110a, center reel 110b, and right reel 110c, each divided into, for example, 20 equal areas. Through the symbol display window 108, the player can see a total of nine consecutive symbols, three of which are located on the top, middle and bottom rows of the left reel 110a, the center reel 110b and the right reel 110c.

[0013] An operation unit installation stand 111 is formed on the top of the front lower door 106, and the operation unit installation stand 111 is provided with a counting switch 112, a game medal number display device 114, a bet switch 116, a start switch 118, a stop switch 120, a settlement switch 121, a performance switch 122, a main segment display unit 130, etc.

[0014] The counting switch 112 is a push switch that detects an operation to transfer some or all of the digitized medals that are electronically held in the smart pachislot 100 and available for use in games to the dedicated unit 350 (described later). The counting switch 112 can be operated in two ways: a short press of less than 500 msec and a long press of 500 msec or more. A short press of the counting switch 112 counts one digitized medal per operation, while a long press counts 50 digitized medals at a time when a count notification is issued every 300 msec. The total number of digitized medals that are electronically held in the smart pachislot 100 and available for use in games is referred to as the "game medal count," and the memory unit that holds the digitized medals is sometimes referred to as the "medal holding unit."

[0015] The medal count display 114 displays the total number of digitized medals held in the medal holding section, i.e., the number of medals held. However, this does not include the digitized medals bet. Therefore, the medal count display 114 displays the number of digitized medals acquired by the player minus the number of digitized medals bet. The medal count is displayed on a 5- or 6-digit 7-segment display or similar device located in a position visible to the player. The numerical range is expressed as follows: 0 to 16,368, taking into account the maximum difference in number of medals per business day. If the most significant digit is 0, that number is left blank (unlit). If the numerical value exceeds a predetermined warning value, e.g., 15,000, a number warning is issued to prompt the player to count the number of medals held, the lending of digitized medals is restricted, and a test count signal is output for approximately 3,500 msec. The warning value is not limited to 15,000; various values ​​can be set. However, even if a medal count warning is issued, the player can continue playing. Therefore, the number of medals may increase. If the number exceeds a predetermined upper limit, for example, 16,369, an error notification (medal over error notification) is issued, restricting the progress of the game. Specifically, the bet switch 116, start switch 118, and settlement switch 121 are prohibited from being operated. Instead of when the number exceeds 16,369, if the number is likely to exceed 16,369, payout of electronic medals may be prohibited until the player counts them. For example, if the number exceeds 16,357, which is calculated by subtracting 12 medals (the maximum number of medals that can be paid out in one game, e.g., 15 medals) minus a specified number (e.g., 3 medals)) from 16,369, the game may be stopped. Furthermore, the game medal count display device 114 reflects and displays the updated game medal count within approximately 300 msec after the number of game medals held in the smart pachislot 100 is updated. Note that the upper limit value to be held is not limited to 16369, and various values ​​can be set.

[0016] The bet switch 116 inserts (bet) a predetermined number of electronic medals from those held in the medal holding section. The bet switch 116 includes a max bet switch that inserts (bet) a specified number of electronic medals required for one game, and a 1 bet switch that inserts one additional electronic medal within the specified number.

[0017] The start switch 118 is composed of, for example, a lever that can detect tilting operations, and detects the player's operation to start a game. The stop switches 120 (stop switch 120a, stop switch 120b, stop switch 120c) are provided corresponding to the left reel 110a, center reel 110b, and right reel 110c, respectively, and detect the player's stop operation. The settlement switch 121 detects the operation of returning all electronic medals bet by a single operation of the bet switch 116 to the medal holding unit. The effect switch 122 is composed of, for example, a push switch and cross switches arranged up, down, left, and right, and detects the player's push operations and rotation operations. The main segment display unit 130 is composed of two 7-segment displays arranged side by side, and displays, for example, an error code indicating the type of error.

[0018] A liquid crystal display unit 124 that displays various images associated with the performance is provided approximately in the center of the top of the upper front door 104. Performance lamps 126, for example, composed of high-brightness light-emitting diodes (LEDs), are provided on the top and left and right sides of the upper front door 104. Speakers 128 that perform auditory performances using sound effects, musical tones, etc. are provided on the left and right sides of the lower front door 106.

[0019] In the smart pachislot 100, once a game can be started and a specified number of electronic medals have been bet, the active line is activated and operation of the start switch 118 is validated. Here, a bet includes both a case where an electronic medal held in the medal holding unit is inserted through operation of the bet switch 116, and a case where an electronic medal is automatically inserted based on the display of a replay combination on the active line. The active line is a line used to determine whether a winning combination has been achieved.

[0020] When the start switch 118 is operated by the player, the game begins, various processes such as a prize type lottery are executed, and the left reel 110a, center reel 110b, and right reel 110c are controlled to rotate. Thereafter, the left reel 110a, center reel 110b, and right reel 110c are stopped in response to the operation of the stop switches 120a, 120b, and 120c. If a winning combination that is eligible for the payout of electronic medals is achieved based on the results of the prize type lottery and the combination of symbols displayed on the active line, the number of electronic medals corresponding to the winning combination is paid out (stored) in the medal holding section, and the game ends. If the player does not win a prize type that is eligible for the payout of electronic medals, or if the player wins but does not win, the game ends when the left reel 110a, center reel 110b, and right reel 110c all stop.

[0021] In this embodiment, the above-mentioned one game refers to the game from when an electronic medal held in the medal holding section is inserted through the operation of the bet switch 116, or when an electronic medal is automatically inserted based on the display of a replay role on an active line, until the left reel 110a, center reel 110b, and right reel 110c are controlled to rotate and a winning type lottery is executed in response to the player's operation of the start switch 118, and depending on the result of the winning type lottery and the player's operation of the multiple stop switches 120a, 120b, and 120c, the left reel 110a, center reel 110b, and right reel 110c corresponding to the operated stop switch 120a, 120b, and 120c are controlled to stop, and if a winning role that can be awarded with an electronic medal is won, the electronic medal is paid out. Furthermore, if a player does not win a prize type that can receive a payout of electronic medals, or if a player wins but does not win a prize, one game ends when the left reel 110a, center reel 110b, and right reel 110c all come to a stop. However, the start of one game may be interpreted as the player operating the start switch 118 instead of the insertion of an electronic medal or winning a replay role. The number of times one game is repeated is defined as the number of games.

[0022] (Smart Pachislot 100 electrical configuration) FIG. 2 is a block diagram showing the schematic electrical configuration of the smart pachislot 100 and the dedicated unit 350. As shown in FIG. 2, the smart pachislot 100 and the dedicated unit 350 are electrically connected via a gaming ball dispenser connection terminal board 206. The smart pachislot 100 is equipped with control boards including a main control board 200 (main control unit) that controls the progress of the game, a sub-control board 202 (sub-control unit) that controls the presentation according to the progress of the game, and a medal count control board 204 that controls the number of electronic medals (number of gaming medals) held in the medal holding unit. Note that transmission of electrical signals between the main control board 200 and the sub-control board 202 is limited to one direction only, from the main control board 200 to the sub-control board 202, to prevent fraud, etc. The dedicated unit 350 is also equipped with a dedicated unit control board 360 that sends and receives electronic medals to and from the smart pachislot 100.

[0023] (Main control board 200) The main control board 200 has semiconductor integrated circuits including a main CPU 200a, which is a central processing unit, a main ROM 200b in which programs and the like are stored, and a main RAM 200c which functions as a work area, and controls the entire smart pachislot 100. Even if the power is turned off, the main RAM 200c retains data without erasing it unless a setting change is made and the RAM is cleared.

[0024] The main control board 200 also has functional units such as an initialization means 300, a betting means 302, a winning type lottery means 304, a reel control means 306, a determination means 308, a payout control means 310, a game status control means 312, a presentation status control means 314, and a command sending means 316, which function when the main CPU 200a cooperates with the main RAM 200c based on a program stored in the main ROM 200b.

[0025] The main control board 200 receives various detection signals from the bet switch 116, start switch 118, stop switches 120a, 120b, 120c, and settlement switch 121, and the main CPU 200a executes various processes based on the received detection signals.

[0026] The initialization means 300 executes initialization processing on the main control board 200. The betting means 302 bets electronic medals to be used in games. The win type lottery means 304, based on the operation of the start switch 118, performs a win type lottery to determine whether a winning combination has been achieved, more specifically, whether a winning type including the winning combination has been achieved, as will be described in detail later.

[0027] The reel control means 306 controls the rotation of the left reel 110a, center reel 110b, and right reel 110c in response to operation of the start switch 118, and controls the stopping of the corresponding left reel 110a, center reel 110b, and right reel 110c in response to operation of the stop switches 120a, 120b, and 120c corresponding to the rotating left reel 110a, center reel 110b, and right reel 110c, respectively.

[0028] A reel drive control unit 150 is also connected to the main control board 200. This reel drive control unit 150 drives a stepping motor 152 based on rotation start signals for the left reel 110a, center reel 110b, and right reel 110c sent from the reel control means 306 in response to an operation signal from the start switch 118. The reel drive control unit 150 also stops driving the stepping motor 152 based on stop signals for the left reel 110a, center reel 110b, and right reel 110c sent from the reel control means 306 in response to an operation signal from the stop switch 120 and a detection signal from the rotation position detection circuit 154.

[0029] The determination means 308 determines whether or not a symbol combination corresponding to a winning combination has been displayed on an active line. Here, the display of a symbol combination corresponding to a winning combination on an active line may simply be referred to as winning. The payout control means 310 pays out electronic medals to the medal holding section in the number (value amount) corresponding to the winning combination, based on the display of a symbol combination corresponding to a winning combination on an active line (winning).

[0030] The gaming state control means 312 transitions the gaming state to one of a plurality of gaming states by referring to the result of the winning type lottery and the determination result of the determination means 308. Furthermore, the presentation state control means 314 transitions the presentation state to one of a plurality of presentation states by referring to the result of the winning type lottery, the determination result of the determination means 308, and the transition information of the gaming state. The gaming states include a non-internal gaming state, an internal gaming state transitioned to by winning a bonus role in a non-internal gaming state, and a bonus gaming state transitioned to by a symbol combination corresponding to a bonus role being displayed on an active line in the internal gaming state. Furthermore, the presentation states include a non-AT (assist time) presentation state in which an assist presentation to assist the winning of a specific role is not executed when a specific role (correct role) and another winning role (incorrect role) overlap and an AT presentation state in which an assist presentation is executed. The specific winning combination is a winning combination that is more advantageous than other winning combinations in terms of not only the payout of electronic medals due to the winning combination but also all game profits that can be obtained by the winning combination.

[0031] The command sending means 316 sequentially determines game-related commands in accordance with the operation of the betting means 302, the winning type lottery means 304, the reel control means 306, the judgment means 308, the payout control means 310, the game status control means 312, the presentation status control means 314, etc., and sequentially sends the determined commands to the sub-control board 202.

[0032] The main control board 200 is also provided with a random number generator (random number generating means) 200d. The random number generator 200d sequentially increments a count value and resets it after counting a predetermined number of times (changing the number sequence to determine an initial value), thereby looping the count value within a predetermined numerical range. The main control board 200 obtains a random number value by extracting a count value from the random number generator 200d at a predetermined time point. The random number value generated by the random number generator 200d of the main control board 200 (hereinafter referred to as a win type lottery random number) is used to determine the gaming benefit to be awarded to the player, for example, the win type determined by the win type lottery means 304.

[0033] (Sub-control board 202) Similarly to the main control board 200, the sub-control board 202 has various semiconductor integrated circuits including a sub-CPU 202a which is a central processing unit, a sub-ROM 202b which stores programs and the like, and a sub-RAM 202c which functions as a work area, and controls, in particular, performances based on commands from the main control board 200. Similarly to the main RAM 200c, the sub-RAM 202c is also connected to a backup power supply (not shown), so that data is not erased and is retained even if the power is cut off. Similarly to the main control board 200, the sub-control board 202 is also provided with a random number generator (random number generating means) 202d, and the random number values ​​generated by the random number generator 202d (hereinafter referred to as performance lottery random numbers) are mainly used to determine the mode of performance.

[0034] In addition, the sub-control board 202 has functional units such as an initialization determination means 330, a command receiving means 332, and a performance control means 334, which function in cooperation with the sub-RAM 202c based on the program stored in the sub-ROM 202b.

[0035] The initialization decision means 330 executes initialization processing on the sub-control board 202. The command receiving means 332 receives commands from other control boards such as the main control board 200, and performs processing in response to the commands.

[0036] The effect control means 334 receives a detection signal from the effect switch 122 and determines the effect of the game to be performed by each device of the liquid crystal display unit 124, the speaker 128, and the effect lamp 126 based on the received command. Specifically, the effect control means 334 determines image data to be displayed on the liquid crystal display unit 124 and illumination data for effects using illumination devices such as the effect lamp 126, and also determines audio data constituting the sound to be output from the speaker 128. The effect control means 334 then executes the determined effect of the game. Note that the effects also include auxiliary effects.

[0037] (Medal count control board 204) The medal count control board 204 is connected to the main control board 200 and has various semiconductor integrated circuits including a medal CPU 204a which is a central processing unit, a medal ROM 204b which stores programs etc., a medal RAM 204c which functions as a work area etc., and manages the electronic medals used in games. The medal count control board 204 is also connected to the dedicated unit 350 via a game ball etc. lending device connection terminal board 206.

[0038] Here, the game ball etc. lending device connection terminal board 206 is a connection terminal board for connecting the smart pachislot 100 and the dedicated unit 350, and receives signals related to the lending of electronic medals, transmits the results of the lending of electronic medals, transmits signals related to the counting of electronic medals, and transmits various information about the smart pachislot 100.

[0039] (Dedicated unit 350) The dedicated unit 350 is installed near the smart pachislot 100 and can lend electronic medals to players and count the electronic medals that players have won. The dedicated unit 350 is provided with a dedicated unit control board 360. The dedicated unit control board 360 is connected to a cash insertion unit 362, a card insertion unit 364, a lending switch 366, a return switch 368, a game switch 370, a point display unit 372, and an acquired medal count display unit 374.

[0040] The cash insertion unit 362 functions as an insertion slot for inserting cash. The card insertion unit 364 allows the insertion and withdrawal of card media capable of storing electronic medals. The loan switch 366 is a push switch that detects the operation of transferring electronic medals corresponding to the number of points of cash held in the dedicated unit 350 to the smart pachislot 100. The return switch 368 is a push switch that detects the operation of transferring electronic medals held in the dedicated unit 350 to card media and withdrawing the card media from the dedicated unit 350 through the card insertion unit 364. The game switch 370 is a push switch that detects the operation of transferring electronic medals held in the dedicated unit 350 to the smart pachislot 100. The point display unit 372 displays the number of points held in the dedicated unit 350, i.e., the number of points equivalent to the cash inserted through the cash insertion unit. The acquired medal count display unit 374 displays the number of acquired medals, which is the total number of electronic medals held in the dedicated unit 350.

[0041] 3 is an external view for explaining the general mechanical configuration of the smart pachislot 100 and the dedicated unit 350. Here, the flow of starting a game on the smart pachislot 100 and the flow of ending a game will be explained with reference to FIG.

[0042] When a player attempts to play on the smart pachislot 100, he or she first inserts cash into the cash insertion section 362 of the dedicated unit 350 shown in FIG. 3. The dedicated unit 350 then displays the number of points corresponding to the inserted cash (e.g., "10" for an insertion of 1,000 yen) on its point display device 372. When the player operates the loan switch 366, electronic medals corresponding to the number of points held in the dedicated unit 350 (e.g., "50") are transferred to the smart pachislot 100 all at once. The smart pachislot 100 then displays the number of transferred electronic medals (e.g., "50") on its game medal count display device 114. Specifically, when the smart pachislot 100 receives a loan notification (described later) from the dedicated unit 350, if the loan notification is normal, it receives the transfer of the electronic medals and notifies "normal" in the loan receipt result response. On the other hand, if the message length and command values ​​in the loan notification are normal but other information is abnormal, the smart pachislot 100 will notify "abnormal" in the loan receipt result response described below. Also, if the loan notification is not received normally or the message length and command values ​​of the loan notification are abnormal, the smart pachislot 100 will discard the received message without displaying an error and will wait until it can receive a loan notification with at least a normal message length and command. In addition, if the loan process cannot be performed, that is, if the gaming machine information notification described later is abnormal, the counted medal count (the number of electronic medals transferred to the dedicated unit 350 at one time) in the counting notification described later is "1" or more, the number of gaming medals displayed on the gaming medal count display device 114 is 15,000 or more, the checksum of the received loan notification is abnormal, the loan serial numbers in the received loan notification are not consecutive, the number of loaned medals in the received loan notification is "51" or more, or the gaming machine information notification sent from the medal CPU 204a described later to the dedicated unit 350 notifies other than hall control / fraud monitoring information, the smart pachislot 100 will notify "abnormality" in the loan receipt result response.

[0043] Next, when the player operates the bet switch 116, electronic medals are bet. At this time, the game medal number display device 114 displays a value (e.g., "47") obtained by subtracting the number of electronic medals bet (e.g., "3") from the value. The player is then able to start playing. If, as a result of playing, a small combination resulting in a payout of 11 medals is won, the number of electronic medals paid out (e.g., "11") is displayed as a payout display in a portion of the liquid crystal display unit 124, and the game medal number display device 114 displays a value (e.g., "58") obtained by adding the number of electronic medals paid out.

[0044] Furthermore, if the settlement switch 121 is operated after the player operates the bet switch 116 to bet electronic medals and before the start switch 118 is operated (start of play), the number of electronic medals bet (for example, "3") is added to the game medal number display device 114 (for example, "50"), and the bet state is canceled.

[0045] When the player finishes playing, he operates the counting switch 112 to transfer the electronic medals held in the medal holding section to the dedicated unit 350. When this is done, the number of game medals held in the medal holding section is displayed on the acquired medal count display device 374 of the dedicated unit 350, and "0" is displayed on the game medal count display device 114. When the player operates the return switch 368, the electronic medals held in the dedicated unit 350 are transferred to a card, and the card is removed from the dedicated unit 350 through the card insertion section 364. In this way, the player can accumulate the electronic medals he has won on the card medium.

[0046] If the player wishes to play again, he or she can insert the card medium on which the digitized medals have been accumulated into the card insertion section 364 instead of cash, and play using the digitized medals accumulated on the card medium. When this is done, the digitized medals accumulated on the card medium are transferred to the dedicated unit 350, and the total number of digitized medals accumulated on the card medium is displayed on the acquired medal count display device 374. By operating the game switch 370 instead of the lending switch 366, the player can transfer the digitized medals held in the dedicated unit 350 to the smart pachislot 100.

[0047] When the lending switch 366 or the counting switch 112 is operated, the medal CPU 204a executes the lending process or counting process for the electronic medals and transmits a command to that effect to the main CPU 200a. The main CPU 200a, upon receiving the command, transmits a command to the sub-CPU 202a. The sub-CPU 202a then outputs a predetermined sound representing the movement of the electronic medals from the speaker 128 as the electronic medals are actually loaned or counted in the lending process or counting process. In the counting process, the sub-CPU 202a may output the predetermined sound from the speaker 128 in response to both a short press and a long press of the counting switch 112, or may output the predetermined sound from the speaker 128 in response to only either a short press or a long press of the counting switch 112. Furthermore, when the operation of the counting switch 112 in the counting process is completed (e.g., pressed and released), the sub-CPU 202a may output a predetermined sound indicating that the counting has been completed, or may output a predetermined sound to prevent the player from forgetting to remove the card from the card insertion portion 364 after the counting process is completed. In this way, the player can auditorily confirm that the lending process or the counting process is being performed properly. Furthermore, the sub-CPU 202a may notify the player that the lending process or the counting process is being performed not only through the speaker 128 but also through various devices such as the LCD display unit 124 and the performance lamp 126. Note that, although a CPU (Central Processing Unit) is used as an example of the controlling entity in the description here, various computing elements capable of performing computations, such as an MPU (Micro Processor Unit), a DSP (Digital Signal Processor), and an FPGA (Field Programmable Gate Array), may also be used.

[0048] Such a smart pachislot 100 eliminates the need for actual medals, making it possible to prevent cheating by inserting fake medals or using illegally brought medals. Furthermore, since there is no need to install a mechanism for inserting and dispensing gaming media within the gaming machine, design and manufacturing costs can be reduced. Furthermore, by centrally managing the lending of gaming media to players and the counting of acquired gaming media, it becomes possible to prevent fraud. Furthermore, centralized data management can curb gambling and ultimately strengthen measures against addiction.

[0049] Specific processing in the main control board 200 will be described below with reference to a flowchart.

[0050] (Main processing of the main control board 200) FIG. 4 is a flowchart showing the main processing of the main control board 200. First, an outline of one game after initialization will be described in accordance with the main processing of the main control board 200, and then each process will be described in detail. Also, here, processes related to the features of this embodiment will be described in detail, and explanations of configurations unrelated to the features of this embodiment will be omitted. Also, although detailed explanations will be omitted, when each process is performed, the switches used in each process (bet switch 116, start switch 118, stop switches 120a, 120b, 120c) are enabled at the start of the process and disabled at the end of the process.

[0051] (Step S100) When the smart pachislot 100 is powered on via the power switch and enters a powered state, the initialization means 300 executes initialization processing in preparation for the start of play. The initialization means 300 can also change settings. Setting changes involve changing the setting values, which indicate the degree of advantage in stages (e.g., six stages). Setting changes also include replaying to the same setting values ​​(changing (overwriting or maintaining) the current setting values ​​to the same setting values). The initialization means 300 generates backup data as needed while the power is on and stores the backup data in the main RAM 200c. Therefore, even if an unexpected power interruption occurs, the initialization processing can restore the state before the power interruption using the stored backup data. For example, even if an unexpected power interruption occurs while the reels 110 are spinning, the game will start again with each reel 110 spinning after the recovery operation. Therefore, the initialization processing does not generally initialize the main RAM 200c (RAM clearing).

[0052] (Step S200) Next, the betting means 302 bets electronic medals through the player's operation of the bet switch 116. The command transmitting means 316 generates an insertion command indicating that the operation has been performed, and transmits the generated insertion command to the sub-control board 202. The command transmitting means 316 also transmits a game medal insertion command including transmission information indicating the requested number of medals to be inserted to the medal count control board 204.

[0053] (Step S300) Next, the win type lottery means 304 validates a game start operation on the start switch 118 and transitions to a state waiting for operation of the start switch 118. Here, in response to operation of the start switch 118 by the player, the win type lottery means 304 obtains one win type lottery random number at the time the start switch 118 was operated from the win type lottery random numbers updated by the random number generator 200d of the main control board 200. Then, the win type lottery means 304 determines one win type lottery table corresponding to the currently set game state from the win type lottery table, determines which winning area in the determined win type lottery table the obtained win type lottery random number corresponds to, and determines the win type or no win for the determined winning area as the lottery result. In addition, when a winning combination "RBB" is determined in the win type lottery, the game state control means 312 transitions the game state from the non-internal game state to the RBB internal game state. In addition, after the lottery result is determined in response to the operation of the start switch 118, the command sending means 316 generates a winning type command including the lottery result of the winning type lottery (winning type or no winning) and information about the game status, and sends the generated winning type command to the sub-control board 202.

[0054] (Step S400) When the start switch 118 is operated, the reel control means 306 drives the stepping motor 152 to rotate the left reel 110a, center reel 110b, and right reel 110c. In this reel rotation process, when a predetermined time (e.g., 4.1 seconds) has elapsed (wait) from the start of rotation of the left reel 110a, center reel 110b, and right reel 110c in the previous game, the left reel 110a, center reel 110b, and right reel 110c in that game begin to rotate, and when all of the left reel 110a, center reel 110b, and right reel 110c have reached a steady rotation, the process proceeds to step S500.

[0055] (Step S500) Next, the reel control means 306 activates the stop switches 120a, 120b, and 120c, and when it receives an operation of the stop switches 120a, 120b, or 120c by the player, it controls to stop one of the left reel 110a, center reel 110b, or right reel 110c corresponding to that operation. Furthermore, when any of the stop switches 120a, 120b, or 120c is operated, the command sending means 316 generates a stop command (first stop command, second stop command, or third stop command) indicating information about the operated stop switch 120a, 120b, or 120c each time the switch is operated, and sends the generated stop commands to the sub-control board 202 in sequence.

[0056] (Step S600) Next, the determination means 308 determines which of the predetermined combinations (winning combination) the symbol combination displayed on the active line A, which is the line for determining whether a winning combination has been achieved, corresponds to. If the symbol combination is within the advantageous zone and a minor combination has been achieved, the determination means 308 updates the net increase number counter. Here, the advantageous zone is a game zone that is advantageous to the player, including a game zone that has the capability related to the instruction function, i.e., a game zone that executes an auxiliary effect (instruction function). Unlike the advantageous zone, a game zone that does not execute an auxiliary effect is called a non-advantageous zone. The advantageous zone is a game zone in which, when an auxiliary effect is activated as a result of a lottery or the like related to the activation of the auxiliary effect on the main control board 200, information indicating the content of the instruction may be transmitted to a peripheral board such as the sub-control board 202 only when the main control board 200 displays the content of the instruction on the notification means so that it can be identified. Furthermore, the gaming state control means 312 transitions the gaming state from the RBB internal gaming state to the RBB operating gaming state if the symbol combination displayed on the active line A in the RBB internal gaming state is a symbol combination corresponding to the winning combination "RBB." Furthermore, the command sending means 316 generates a winning command including the number of electronic medals to be paid out when the symbol combination displayed on the active line A or the symbol combination corresponding to the minor winning combination is displayed on the active line A, and sends the generated winning command to the sub-control board 202.

[0057] (Step S700) Furthermore, the payout control means 310 executes a payout process for electronic medals corresponding to a minor winning combination based on the symbol combination displayed on the active line A (the stopping state of the reels 110), for example, when a symbol combination corresponding to a minor winning combination is displayed on the active line A, and automatically executes a process for placing a bet for the next game when a symbol combination corresponding to a replay winning combination is displayed on the active line A. Furthermore, when a payout process for electronic medals is performed, the command sending means 316 generates a payout command indicating that the payout process has been performed, and sends the generated payout command to the sub-control board 202. Furthermore, the command sending means 316 sends a payout end command including communication information indicating the number of medals to be paid out to the medal count control board 204.

[0058] (Step S800) When a predetermined number of electronic medals are paid out in the RBB-operated gaming state, the gaming state control means 312 transitions the gaming state from the RBB-operated gaming state to a non-internal gaming state. The presentation state control means 314 also changes the presentation state and changes between advantageous and non-advantageous zones. When the gaming state or presentation state is changed, the command sending means 316 generates a gaming transition command including the changed gaming state or presentation state, and sends the generated gaming transition command to the sub-control board 202. In this way, the completion of the gaming transition process S800 ends the current game.

[0059] One game is executed through a series of processes from step S200 to step S800. Thereafter, steps S200 to S800 are repeated.

[0060] (Relationship between boards) Also, here, as shown in Figure 2, an example has been given in which a medal count control board 204 is provided separately from the main control board 200 in the smart pachislot 100, and the medal count control board 204 operates independently, but this is not the only case, and the configuration of the board and CPU can be made different.

[0061] 5 is an explanatory diagram for explaining another board configuration. In the embodiment described above, as shown in FIG. 5(a), a main CPU 200a (first control unit) that controls the progress of the game is arranged on the main control board 200, a medal CPU 204a (second control unit) that manages the electronic medals used in the game is arranged on the medal count control board 204, the main control board 200 and the medal count control board 204 are connected via a harness, and the medal count control board 204 and the game ball etc. lending device connection terminal board 206 are connected via a harness. The game ball etc. lending device connection terminal board 206 receives a supply of power (VL) from the dedicated unit 350, uses the power as input to an insulating element such as a photocoupler, generates a VL connection signal that indicates the connection status with the dedicated unit 350, and outputs it to the medal number control board 204. The medal count control board 204 can determine, by the ON / OFF of the VL connection signal, that power is being supplied from the dedicated unit 350, in other words, that the dedicated unit 350 is powered on and properly connected to the dedicated unit 350. With this board configuration, modifications to the configuration of the existing main control board 200 and increases in the occupied area can be kept to a minimum, thereby reducing design costs.

[0062] The medal count control board 204 does not necessarily have to be separate from the main control board 200, and may be formed integrally with the main control board 200 as long as it fulfills its function. Specifically, as shown in FIG. 5(b), the main control board 200 may be provided with both a main CPU 200a that controls the progress of the game and a medal CPU 204a that manages the electronic medals used in the game, and the main control board 200 and the game ball etc. lending device connection terminal board 206 may be connected via a harness. Here, by providing both the main CPU 200a and the medal CPU 204a on a single main control board 200, the connectors and harnesses used for information exchange between them can be eliminated, the occupied area can be reduced, and the reliability of information transmission can be improved.

[0063] 5(c), the main CPU 200a arranged on the main control board 200 manages the digitized medals used in the game in place of the medal CPU 204a, and the main control board 200 is connected via a harness to the game ball etc. lending device connection terminal board 206. Here, on the main control board 200, the main CPU 200a controls the progress of the game and manages the digitized medals, so there is no need for a connection line for exchanging information between the main CPU 200a and the medal CPU 204a, which further reduces the occupied area and improves the reliability of information transmission.

[0064] Here, at least the main control board 200 must be enclosed in a main board case to prevent fraud. In addition, if the medal count control board 204, which has the function of managing the electronic medals used in games, is a separate body, it must be enclosed in the main board case together with the main control board 200.

[0065] FIG. 6 is an explanatory diagram illustrating the enclosure of the case. For example, as shown in FIG. 5(a), if the main control board 200, the medal count control board 204, and the gaming ball etc. dispensing device connection terminal board 206 are each formed separately, and the main control board 200 and the medal count control board 204 are connected, and the medal count control board 204 and the gaming ball etc. dispensing device connection terminal board 206 are connected, it is possible to enclose the main control board 200, the medal count control board 204, and the gaming ball etc. dispensing device connection terminal board 206 all in a single main board case 200e, as shown in FIG. 6(a). Here, as shown in FIG. 6(a), an example is given in which the main control board 200 and the medal count control board 204 are integrally formed by directly and fixedly connecting their connectors without using a harness, but they may also be connected via a harness.

[0066] Furthermore, as shown in Figures 5(b) and 5(c), when a main CPU 200a and a medal CPU 204a are arranged on the main control board 200, or when the main CPU 200a is arranged alone and the main control board 200 and the gaming ball etc. lending device connection terminal board 206 are connected via a harness, the main control board 200 and the gaming ball etc. lending device connection terminal board 206 may be individually enclosed in the main board case 200e and the gaming ball etc. lending device connection terminal board 206 in the connection terminal board case 206e when they are connected, as shown in Figure 6(b), or it is possible to enclose the main control board 200 and the gaming ball etc. lending device connection terminal board 206 all in a single main board case 200e as shown in Figure 6(c).

[0067] In any case, the main control board 200, the medal count control board 204, and the game ball etc. dispensing device connection terminal board 206 are all enclosed in a case. In this case, the structure must be such that it is easy to check not only the front surface of the board but also the back surface of the board.

[0068] In the example shown in Figures 5(a) and 5(b), in the smart pachislot 100, the main CPU 200a and the medal CPU 204a operate independently, with the main CPU 200a controlling the progress of the game and the medal CPU 204a managing the electronic medals used in the game.

[0069] FIG. 7 is an explanatory diagram illustrating the CPUs and areas (used area or unused area) that execute each function of the smart pachislot 100. In FIG. 7, "◎" indicates a typical execution unit when functions are shared between two CPUs, the main CPU 200a and the medal CPU 204a, as in FIGS. 5(a) and 5(b), "◯" indicates an executable execution unit, and "×" indicates an inexecutable execution unit. Here, the used area is an area that stores instruction codes and program data of a program that executes some or all of the processing for controlling the progress of a game, as shown in FIG. 4. The unused area is an area that stores instruction codes and program data of a program that executes some or all of the processing of gaming machine test processing and security-related processing that is not specified to be stored in the used area and does not affect the progress of a game. For example, when functions are shared between two CPUs, as shown in No. 12 in Figure 7, the function of controlling the game medal count display device 114 and the function of controlling communication with the dedicated unit 350 are generally carried out in the usage area of ​​the medal CPU 204a (indicated by "◎" in Figure 7), but it is also possible for some or all of these functions to be carried out in the usage area of ​​the main CPU 200a (indicated by "○" in Figure 7).

[0070] (Communication between smart pachislot and dedicated unit) The above-described functional units allow the smart slot machine 100 and the dedicated unit 350 to exchange various information (messages) via serial communication to ensure their proper operation. The serial communication is asynchronous and full-duplex, with a communication speed of, for example, 62,500 bps, and each byte of data consisting of a 1-bit start bit, 8 data bits, and 1-bit stop bit. The character transmission time is 0.16 msec to 3.9 msec, and if the next start bit is not received within 3.9 msec, that character is considered to be one message. For example, the smart slot machine 100 (e.g., the medal CPU 204a of the medal count control board 204) transmits the following gaming machine information notification, count notification, and loan receipt result response to the dedicated unit 350 via this serial communication.

[0071] 8 to 11 are explanatory diagrams illustrating the format of a gaming machine information notification. As shown in FIG. 8, a gaming machine information notification transmits one of three types of gaming machine information, namely, gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information, to the dedicated unit 350, and the message length is variable, ranging from 18 to 57 bytes. Specifically, the first byte of the gaming machine information notification message indicates the message length (12h to 39h), and the second byte indicates "01h," indicating the type of command (here, gaming machine information notification). The third byte indicates a sequence number ranging from 00h to FFh. This sequence number is notified as 00h when the power is turned on, and is incremented by one with each notification. However, the notification following FFh is set to 01h, not 00h.

[0072] The fourth byte indicates the type of gaming machine. Bit 7 of the gaming machine type indicates the management medium, with gaming balls represented as "0" and medals represented as "1." Bits 6-4 indicate the organization classification, with Nikkoso represented as "0" and Nikdenkyo represented as "1." Bits 3-0 indicate the gaming machine type, with pachinko machines represented as "1," slot machines represented as "2," arrange ball machines represented as "3," and jankyu machines represented as "4." The fifth byte indicates the type of gaming machine information. For example, if the gaming machine information is gaming machine performance information, it is "00h." If the gaming machine information is gaming machine installation information, it is "01h." If the gaming machine information is hall control / fraud monitoring information, it is "02h." From the sixth byte onward, gaming machine information (either gaming machine performance information, gaming machine installation information, or hall control / fraud monitoring information) is indicated in variable length.

[0073] For example, if the gaming machine information type is "00h," the gaming machine performance information is represented by 51 bytes, and as shown in FIG. 9, includes the total number of inserted coins, the total number of paid-out coins, MY (maximum difference in number of coins), the total number of payout coins for special features, the total number of payout coins for consecutive features, the ratio of special features, the ratio of consecutive features, the ratio of advantageous zones, the ratio of special features with instructions, the ratio of special features and other statuses, the number of games played, the reserve, reservation 1, and reservation 2. The gaming machine performance information is transferred to the dedicated unit 350 and then further transmitted to the gaming machine information center (not shown). Here, MY indicates the difference between the number of electronic medals inserted (number of inserted medals) and the number of paid-out medals (number of paid-out medals) since the power was reset. Instead of or in addition to the difference in number of coins since the power was reset, MY can also be the difference in number of coins when the lowest difference in number is set to 0. Of this information, the byte order of the total number of coins inserted, total number of coins paid out, MY, total number of coins paid out from special devices, total number of coins paid out from consecutive special devices, and number of games played is little endian.

[0074] Furthermore, if the gaming machine information type is "01h," the gaming machine installation information is represented by 40 bytes, and as shown in FIG. 10, includes the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code. Here, the main control chip ID number (9 bytes) and medal count control chip ID number (9 bytes) are represented by 0 in the most significant 4 bytes, the following 4 bytes are represented by a chip individual number or chip code, and the least significant byte is represented by an identification code (LEM50A="21h," LES50A="22h," LEM7OA="23h," IDNAC8701="41h," IDNAC8702="42h," IDNAC8703="43h"). However, if the medal CPU 204a is not installed, all 9 bytes are represented by 0. The byte order of the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code is big endian.

[0075] Furthermore, if the gaming machine information type is "02h", the hall control / fraud monitoring information is represented as gaming machine information in 12 to 16 bytes, and as shown in Figure 11, it includes the number of gaming medals, the number of inserted medals, the number of paid out medals, main control status 1, main control status 2, gaming machine error status, gaming machine fraud 1, gaming machine fraud 2, gaming machine fraud 3, gaming information number, type information 1, count information 1, type information 2, and count information 2. Here, the relationship between the number of gaming medals, the number of inserted medals, and the number of paid out medals is "number of gaming medals" = "number of gaming medals" sent previously - "number of inserted medals" + "number of paid out medals" + "number of loaned medals" received after the number of gaming medals sent previously - "number of counted medals" sent after the number of gaming medals sent previously; therefore, if this relationship is not satisfied, it can be determined that the hall control / fraud monitoring information is abnormal. Furthermore, the setting change signal in bit 0 of gaming machine fraud 1 indicates that a setting change process is being performed (the power was turned on with the setting key turned on), the setting confirmation signal in bit 1 of gaming machine fraud 1 indicates that a setting value confirmation process is being performed, the fraud detection signal 1 in bit 2 of gaming machine fraud 1 indicates that a communication error has occurred in the main CPU 200a, and the fraud detection signals 2 and 3 in bits 3 and 4 of gaming machine fraud 1 indicate that an arbitrarily determined fraud has been detected. Furthermore, the setting door open signal in bit 0 of gaming machine fraud 2 indicates that, if a door is provided in a setting change device that accepts setting change operations by an administrator during setting change processing, the door provided in the setting change device is open, and the door open signal in bit 1 of gaming machine fraud 2 indicates that the front lower door 106 is open. Note that if a door is not provided in the setting change device, the setting door open signal is not used, and the bit position of the setting door open signal is set to a fixed value "0" as a reserved signal. Furthermore, if the cheating detection signal 2 or 3 is not used, a fixed value "0" is set in the corresponding bit position as a reserved signal. The other signals, gaming machine cheating 1, gaming machine cheating 2, and gaming machine cheating 3, may also be set to a fixed value "0" as a reserved signal. These signals must be output continuously for a predetermined time period equal to or longer than a lower limit time (for example, 3 seconds) to prevent cheating.Furthermore, if an event occurs during the output of these signals that interrupts the signal output, such as a power outage (power cut), the signal timing timer that was timing the predetermined time may be reset and the setting confirmation signal may be output again for the predetermined time. Alternatively, the value of the signal timing timer at the time of the power outage may be saved, and when power is turned on (when power is restored), timing may be resumed from the saved value of the signal timing timer and the setting confirmation signal may be output. In this case, the total time during which the setting confirmation signal is output before and after the power outage is restored becomes the predetermined time. Game information consisting of a combination of type information 1 and count information 1, or a combination of type information 2 and count information 2, indicates whether the specified number (when the start switch 118 is operated) or the number of coins to be paid out (at the end of the game) is determined by type information 1 and 2, and the number of coins is determined by count information 1 and 2. During replay, the specified number at the time of replay activation is notified. The number of pieces of game information indicates the number of pieces of game information, and if the number of pieces of game information is 0, the four items of type information 1, count information 1, type information 2, and count information 2 are not transmitted.

[0076] FIG. 12 is an explanatory diagram illustrating the format of the counting notification. The counting notification transmits the cumulative counted medal count, which will be described later, to the dedicated unit 350, and the message length is a fixed 7 bytes. Specifically, the first byte of the message indicates the message length (07h), and the second byte indicates "02h", which indicates the type of command (counting notification in this case). The third byte indicates a sequence number between 00h and FFh as the counting serial number. This counting serial number is notified as 00h when the power is turned on, and is incremented by 1 with each notification. However, the notification following FFh is set to 01h, not 00h. The fourth byte indicates the counted medal count. The counted medal count is the number of electronic medals counted at the time of the counting notification. The fifth byte indicates the cumulative counted medal count. The cumulative medal count is the value accumulated since it was cleared to 0000h when the Smart Pachislot 100 was turned on, and the value after FFFFh is 0000h. The 7th byte indicates the checksum.

[0077] FIG. 13 is an explanatory diagram illustrating the format of the loan receipt result response. The loan receipt result response is a response that reports the receipt result when a loan notification is received from the dedicated unit 350, and the message length is a fixed 5-byte length. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates "03h," which indicates the command type (here, loan receipt result response). The third byte indicates a sequence number between 00h and FFh as the loan serial number. This loan serial number is notified as 00h when the power is turned on. If the loan medal count receipt result (described later) is normal, it reflects the loan serial number received from the dedicated unit 350 as is. If the loan medal count receipt result is abnormal, it reflects the loan serial number that was used when the loan medal count receipt result was normally received from the dedicated unit 350. The fourth byte indicates the loan medal count receipt result (normal = 00h, abnormal = 01h). The fifth byte indicates a checksum.

[0078] In addition, the dedicated unit 350 sends the following lending notification to the smart pachislot 100 (here, for example, the medal CPU 204a).

[0079] FIG. 14 is an explanatory diagram illustrating the format of the loan notification. The loan notification is sent when the dedicated unit 350 receives a count notification from the smart pachislot 100, and transmits the number of loaned medals to the smart pachislot 100. The message length is a fixed 5-byte message. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates "13h," which indicates the type of command (here, loan notification). The third byte indicates a sequence number between 00h and FFh as the loan serial number. This loan serial number is notified as 00h when the power is turned on, and is incremented by 1 with each notification. However, the notification following FFh is set to 01h, not 00h. The fourth byte indicates the number of loaned medals. The number of loaned medals indicates the number of electronic medals loaned. If a gaming machine information notification has not been received, if a gaming machine information type other than "02h: Hall control / fraud monitoring information" is notified, or if the number of counted medals in the count notification is notified as "1" or more, the number of lent medals will be notified as "0". The fifth byte indicates the checksum.

[0080] If a specific abnormality occurs inside the smart pachislot 100, the smart pachislot 100 can prevent communication with the dedicated unit 350. For example, if a specific abnormality such as a backup abnormality, a RAM (RWM) abnormality, or a mismatch in manufacturer code occurs, the medal CPU 204a of the smart pachislot 100 issues a manufacturer code mismatch error (operation stop error) without completing the startup process, and restricts the start of communication with the dedicated unit 350.

[0081] 15 is a timing chart showing the timing of notifications of gaming machine information notification, counting notification, loan notification, and loan receipt result response. As shown in FIG. 15, the smart pachislot 100 (here, for example, the medal CPU 204a) transmits a gaming machine information notification to the dedicated unit 350 at intervals of 300 msec (not less than 300 msec and not more than 310 msec) from the completion of startup of the smart pachislot 100. The smart pachislot 100 also transmits a counting notification to the dedicated unit 350 100 msec (not less than 90 msec and not more than 100 msec) from the start of the gaming machine information notification. The dedicated unit 350 transmits a loan notification to the smart pachislot 100 within 170 msec from the start of reception of the counting notification. After completing reception of the loan notification, the smart pachislot 100 notifies the dedicated unit 350 of a loan receipt result response within 10 msec. In this way, a time of 20 msec or more can be secured between the time when the smart pachislot 100 notifies the loan acceptance result response and the time when the next gaming machine information notification is made.

[0082] FIG. 16 is an explanatory diagram illustrating the transmission timing of gaming machine information notifications. As described above, gaming machine information notifications are sent to the dedicated unit 350 every 300 msec. There are three types of gaming machine information in gaming machine information notifications: gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information. As shown in FIG. 16, each type of information has a different notification timing and priority. For example, gaming machine installation information is sent 60 seconds after the smart pachislot 100 has finished booting up, and is then sent every 60 seconds. Furthermore, gaming machine performance information is sent 180 seconds after the smart pachislot 100 has finished booting up, and is then sent every 180 seconds. Hall control / fraud monitoring information is sent every 300 msec after the smart pachislot 100 has finished booting up. However, the transmission timing of these three notifications may overlap. If the transmission timing overlaps, the gaming machine information notifications are sent sequentially according to priority. For example, if gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information overlap at 180 seconds, and there is no update to the main control status in the hall control / fraud monitoring information and there is no game information, the gaming machine installation information with the higher priority will be notified first, followed by the gaming machine performance information 300 msec later, and the hall control / fraud monitoring information 300 msec later. Also, if gaming machine installation information and hall control / fraud monitoring information overlap at 60 seconds, and there is no update to the main control status in the hall control / fraud monitoring information and there is no game information, the gaming machine installation information with the higher priority will be notified first, followed by the hall control / fraud monitoring information 300 msec later. However, if there is an update to the main control status or game information in the hall control / fraud monitoring information, the hall control / fraud monitoring information with the higher priority will be notified first, followed by the gaming machine installation information and gaming machine performance information. With this configuration, the smart pachislot 100 and the dedicated unit 350 can confirm gaming machine information notifications (gaming machine performance information, gaming machine installation information, hall control and fraud monitoring information), counting notifications, loan notifications, and loan receipt result responses with appropriate timing and appropriate priority.

[0083] (VL connection signal) As explained using FIG. 5, the game ball etc. dispensing device connection terminal board 206 receives power from the dedicated unit 350, uses this power as input to an insulating element such as a photocoupler, generates a VL connection signal indicating the connection status with the dedicated unit 350, and outputs this to the medal CPU 204a of the medal count control board 204. The medal CPU 204a may or may not send a command to the main CPU 200a indicating that it has received the VL connection signal. When the medal CPU 204a sends a command to the main CPU 200a indicating that it has received the VL connection signal, the main CPU 200a can restrict (prohibit) the activation of only the main control board 200, only the medal count control board 204, or both the main control board 200 and the medal count control board 204, or can stop the progress of the game, depending on whether the command indicates the reception of a VL connection signal. Furthermore, if the medal CPU 204a does not send a command to the main CPU 200a indicating that it has received the VL connection signal, the medal CPU 204a can individually restrict (prohibit) the activation of the medal count control board 204 or stop the progress of the game.

[0084] If the VL connection signal is ON, the smart pachislot 100 determines that it is properly connected to the dedicated unit 350 and that the dedicated unit 350 is powered on, allowing it to execute various processes targeting the main CPU 200a and the dedicated unit 350. On the other hand, if the VL connection signal is OFF, the smart pachislot 100 determines that it is not properly connected to (not connected to) the dedicated unit 350 or that the dedicated unit 350 is powered off, and restricts game progress. Specifically, if the VL connection signal is OFF, the smart pachislot 100 executes game stop processing. This game stop processing restricts game play by determining that the main control board 200 is in an error state (restricting (prohibiting) all electronic medal betting, operation of the settlement switch 121, processing for game progress based on operation of the start switch 118, and counting processing). If the VL connection signal is OFF, the main CPU 200a and the medal CPU 204a may not be started.

[0085] Here, the counting process refers to the process of transferring some or all of the digitized medals held in the medal holding section to the dedicated unit 350 in response to the player's operation of the counting switch 112. Specifically, if the counting switch 112 is not being accepted, if the number of game medals in the medal holding section is 0, if the VL connection signal is OFF, or if counting is disabled, the counted medal number (counting value number) is set to "0," and if a short press of the counting switch 112 is accepted, the counted medal number is set to "1." If a long press of the counting switch 112 is accepted, and if the number of game medals in the medal holding section is less than 50, all of the digitized medals (number of game medals) are set as the counted medal number, and if the number is 50 or more, the counted medal number is set to "50." Then, the counted medal number is added to the cumulative counted medal number, and the counting serial number is updated. The smart pachislot 100 performs a checksum to find the sum of the data string of the count notification message, regarding it as a string of integer values, and notifies the dedicated unit 350 of the count. In parallel with this, the number of counted medals is subtracted from the number of game medals held in the medal holding unit.

[0086] Here, if the counting switch 112 is operated while play is possible, the counting process is always executed. "While play is possible" refers to a state in which the smart pachislot 100 and the dedicated unit 350 are connected and both are powered on (a state in which a player can borrow electronic medals, play on the smart pachislot 100, and perform a series of operations to count the results of said play). Note that if the smart pachislot 100 is powered on but the dedicated unit 350 is not, or if the smart pachislot 100 and the dedicated unit 350 are not connected, even if the smart pachislot 100 accepts operation of the counting switch 112, there is a risk that the counted medal number will be lost. Therefore, operation of the counting switch 112 is invalid, and that period is not included in "while play is possible." Additionally, the "period during which play is possible" does not include the periods during which the smart pachislot 100 does not (cannot) proceed with play as a standalone unit, such as during initialization processing after power-on, during setting changes and setting confirmation, and during an error state that requires recovery processing by resetting, etc. During such periods during initialization processing after power-on, during setting changes and setting confirmation, and during an error state that requires recovery processing by resetting, etc., the counting process may or may not be executed.

[0087] Thus, when the VL connection signal is ON, the smart pachislot 100 continues playing the game and accepts counting processing while play is possible. On the other hand, when the VL connection signal is OFF, the smart pachislot 100 executes game stop processing and restricts (prohibits) all of the following: betting electronic medals, operation of the settlement switch 121, processing for game progress based on operation of the start switch 118, and the counting processing described above. This is because, as described above, when the VL connection signal is OFF, it can be determined that the smart pachislot 100 is not properly connected to the dedicated unit 350, or that the power to the dedicated unit 350 is OFF.

[0088] As explained using FIG. 15, the smart pachislot 100 (e.g., the medal CPU 204a) transmits a counting notification including information on the number of counted medals to the dedicated unit 350. Here, if the dedicated unit 350 is not properly prepared to receive the counting notification, for example, if the smart pachislot 100 and the dedicated unit 350 are not properly connected (e.g., not connected) or the dedicated unit 350 is powered off, when the smart pachislot 100 receives an input operation (e.g., a pressing operation) of the counting switch 112 and transmits the counting notification to the dedicated unit 350, there is a risk that the counted medal number based on the input operation will be lost. If the counted medal number is lost, the total number of digitized medals will decrease, causing an inconsistency in the digitized medals. In this embodiment, inconsistency refers to a situation in which, due to the unintended loss or increase of digitized medals, the total number of digitized medals, which is the sum of the number of game medals played and the number of acquired medals, which is the total number of digitized medals held in the dedicated unit 350, differs before and after the input operation of the counting switch 112. For example, when the total number of game medals is counted using the counting switch 112, an inconsistency has occurred if the number of game medals held in the smart pachislot 100 before the counting differs from the number of acquired medals transferred to the dedicated unit 350 by the counting.

[0089] Therefore, before sending a counting notification to the dedicated unit 350, the smart pachislot 100 (for example, the medal CPU 204a) determines whether the dedicated unit 350 is connected by checking the ON / OFF state of a VL connection signal indicating the connection status with the dedicated unit 350. If the VL connection signal is OFF, indicating that the dedicated unit 350 is not connected, the smart pachislot 100 sets the number of counted medals to "0" to limit the counting process itself.

[0090] When the counted medal count is set to "0", the smart pachislot 100 updates the number of game medals by subtracting the counted medal count "0" from the number of game medals. In other words, the updated number of game medals remains substantially unchanged from before the update. The smart pachislot 100 displays the updated number of game medals on the game medal count display device 114. Since the number of game medals remains substantially unchanged, the display on the game medal count display device 114 also remains unchanged.

[0091] Furthermore, the smart pachislot 100 transmits a counting notification including information on the counted medal count, which is set to "0," to the dedicated unit 350. If the dedicated unit 350 is not connected, the dedicated unit 350 cannot properly receive the counting notification, and therefore the number of earned medals does not change. Since the number of earned medals does not change, the display on the earned medal count display device 374 does not change either.

[0092] In this way, by setting the number of counted medals to "0," the number of game medals in the smart pachislot 100 and the number of medals acquired by the dedicated unit 350 do not change, and the total number of digitized medals also does not change. As a result, the smart pachislot 100 does not execute a counting process, and it is possible to prevent digitized medals from being lost in response to an input operation of the counting switch 112. In other words, it is possible to prevent inconsistencies in the digitized medals in the smart pachislot 100.

[0093] 17 is a flowchart showing the flow of the counting switch monitoring process in the medal CPU 204a. The counting switch monitoring process is executed when the counting switch 112 is pressed. Here, the process related to this embodiment will be explained, and processes unrelated to this embodiment will be omitted. The numerical values ​​of step S in this figure will be used only in the explanation of this figure.

[0094] As shown in FIG. 17, when the medal CPU 204a detects the pressing of the counting switch 112, specifically, when it detects the ON edge of the counting switch 112 (YES in S1), it acquires a VL connection signal and determines whether or not the VL connection signal is ON (S2). If the VL connection signal is ON (YES in S2), the medal CPU 204a starts timing of a timing counter provided in the smart pachislot 100 (S3). The timing counter starts timing in response to the detection of the ON edge of the counting switch 112, and measures the time from the ON edge to the OFF edge. Next, the medal CPU 204a determines whether or not it has detected an OFF edge of the counting switch 112 (S4). If the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether or not a predetermined time (e.g., 500 msec) has elapsed since the start of timing of the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the processing of step S4. If the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long press flag to ON (S6) and returns to the processing of step S4. The long press flag is a flag for identifying a long press, and if ON, indicates a long press, and if OFF, indicates that it is not a long press (i.e., a short press).

[0095] If the OFF edge of the counting switch is detected (YES in S4), the medal CPU 204a determines whether the long press flag is OFF or not (S7). If the long press flag is OFF (YES in S7), the medal CPU 204a sets the counted medal number to "1" and proceeds to the processing of step S9. The set counted medal number is stored in a predetermined register or RAM. If the long press flag is ON (NO in S7), the medal CPU 204a proceeds to the processing of step S9. In step S9, the medal CPU 204a clears (turns OFF) the long press flag. The medal CPU 204a clears the timing counter and ends the counting switch monitoring processing.

[0096] If the ON edge of the counting switch 112 is not detected (NO in S1), the counting switch monitoring process ends without performing any processing. If the VL connection signal is OFF (NO in S2), the medal CPU 204a sets the counted medal number to "0" (S11) and ends the counting switch monitoring process. The counted medal number "0" is stored in a specified register or RAM. In other words, even if the counting switch 112 is pressed, if the VL connection signal is OFF, the counted medal number is set to "0", and the player's operation to count the electronic medals is not accepted, or even if accepted, it is invalidated.

[0097] 18 is a flowchart showing the flow of the counting process in the medal CPU 204a. The counting process is a process related to updating the count of the number of game medals, and is executed at interrupt timings that are repeated at a predetermined cycle (e.g., 300 ms) regardless of whether the counting switch 112 is pressed. Here, the process related to this embodiment will be explained, and processes that are not related to this embodiment will be omitted. The numerical values ​​of step S in this figure will be used only in the explanation of this figure.

[0098] As shown in FIG. 18, when an interrupt timing occurs, which is repeated at a predetermined cycle, the medal CPU 204a acquires a VL connection signal and determines whether the VL connection signal is ON or not (S21). If the VL connection signal is ON (YES in S21), the medal CPU 204a proceeds to the processing of step S23. If the VL connection signal is OFF (NO in S21), the medal CPU 204a sets the counted medal number to "0" (S22), and proceeds to the processing of step S23. The counted medal number "0" is stored in a predetermined register or RAM. In step S23, the medal CPU 204a acquires the current number of game medals from the medal holding unit (S23).

[0099] Next, the medal CPU 204a determines whether or not the long press flag is ON (S24). If the long press flag is ON (YES in S24), the medal CPU 204a determines whether or not the number of game medals acquired in step S23 is "50" or more (S25). If the number of game medals is "50" or more (YES in S25), the medal CPU 204a sets the counted medal number to "50" (S26) and proceeds to the processing of step S28. If the number of game medals is less than "50" (NO in S25), the medal CPU 204a sets the game medal number to the counted medal number (S27) and proceeds to the processing of step S28. The counted medal number set in step S26 or step S27 is stored in a predetermined register or RAM. Furthermore, if the long press flag is OFF (NO in S24), the processing proceeds to the processing of step S28.

[0100] In step S28, the medal CPU 204a acquires the most recent stored counted medal count from the register or RAM in which the counted medal count is stored (S28). For example, assume that immediately before the current counting process, the counting switch monitoring process (see FIG. 17) is performed and the counted medal count is set to "1." In this case, in step S28 of the counting process (see FIG. 18), the medal CPU 204a acquires the counted medal count "1" stored in a predetermined register or RAM. Furthermore, if the counted medal count is set to "50" in step S26 of the current counting process, the medal CPU 204a acquires the counted medal count "50" stored in a predetermined register or RAM. Furthermore, if a number of game medals less than "50" is set as the counted medal count in step S27 of the current counting process, the medal CPU 204a acquires the number of game medals less than "50" stored in the predetermined register or RAM as the counted medal count. In addition, if the counted medal number is set to "0" in step S11 of the counting switch monitoring process (see Figure 17) or in step S22 of the counting process (see Figure 18), the medal CPU 204a obtains the counted medal number "0" stored in a specified register or RAM.

[0101] Next, the medal CPU 204a updates the number of game medals by subtracting the acquired counted number of game medals from the acquired number of game medals (S29). For example, if the acquired counted number of medals is "1," the number of medals obtained by subtracting "1" from the current number of game medals acquired becomes the updated (subtracted) number of game medals. Also, if the acquired counted number of medals is "50," the number of medals obtained by subtracting "50" from the current number of game medals acquired becomes the updated number of game medals. Also, if a number of game medals less than "50" is acquired as the counted number of game medals, all counted medals less than "50" are subtracted from the current number of game medals acquired, and the updated number of game medals becomes "0." Also, if the acquired counted number of medals is "0," the number of medals obtained by subtracting "0" from the current number of game medals acquired becomes the updated number of game medals. In other words, if the counted number of medals is "0," the number of game medals does not substantially change.

[0102] Next, the medal CPU 204a updates the display of the number of game medals on the game medal count display device 114 to the number of game medals derived in step S29 (S30). Next, the medal CPU 204a generates a counting notice including information on the acquired counted number of medals and transmits it to the dedicated unit 350 (S31). Next, the medal CPU 204a clears the counted number of medals upon completion of the counting notice (S32), and ends the counting process.

[0103] In this way, the medal CPU 204a checks whether the VL connection signal is ON / OFF, and if the VL connection signal is OFF, it sets the counted medal count to "0." Therefore, if the VL connection signal is OFF, even if the counting switch 112 is pressed, the updated number of game medals will not change substantially from the pre-update number of game medals. Furthermore, if the VL connection signal is OFF, the dedicated unit 350 cannot properly receive the counting notification, and therefore the number of acquired medals will not change. Therefore, even if a counting notification is sent even though the dedicated unit 350 is not properly prepared to receive the counting notification, the smart pachislot 100 will not lose or increase the number of electronic medals, and it is possible to avoid inconsistencies in the electronic medals.

[0104] 17, the medal CPU 204a sets the counted medal count to "0" immediately before updating the game medal count, in other words, immediately before sending the count notification. Therefore, in the smart pachislot 100, the counted medal count can be set to "0" more reliably, and inconsistencies in the electronic medals can be more reliably prevented.

[0105] Furthermore, the smart pachislot 100 determines whether the VL connection signal is ON / OFF in both the counting switch monitoring process and the counting process, and if the VL connection signal is OFF, sets the counted medal count to "0." As a result, for example, the counted medal count is set to "0" at the timing of the VL connection signal determination process executed first after the VL connection signal turns OFF, out of the VL connection signal determination process in the counting switch monitoring process and the VL connection signal determination process in the counting process, so the counted medal count can be set to "0" early. Furthermore, because the smart pachislot 100 determines whether the VL connection signal is ON / OFF in both the counting switch monitoring process and the counting process, there are two opportunities to determine whether the VL connection signal is ON / OFF, and the counted medal count can be set to "0" more reliably than in a mode where there is only one opportunity to determine whether the VL connection signal is ON / OFF.

[0106] Furthermore, in the smart pachislot 100, the medal CPU 204a performs count switch monitoring processing and counting processing. The storage capacity of the ROM or RAM (storage unit) in the medal count control board 204 is smaller than that of the main ROM 200b or main RAM 200c (storage unit), but because the processing load is low, the available space is large as a result. For this reason, even if a program performs the process of determining whether the VL connection signal is ON / OFF and setting the counted medal number to "0" when the VL connection signal is OFF in both the count switch monitoring processing and the counting processing, it does not put a strain on the storage capacity of the medal count control board 204.

[0107] The smart pachislot 100 may determine whether the VL connection signal is ON / OFF in either the counting switch monitoring process or the counting process, and omit the ON / OFF determination of the VL connection signal in the other. In this case, it is more preferable to omit the ON / OFF determination of the VL connection signal in the counting switch monitoring process and perform the ON / OFF determination of the VL connection signal in the counting process. Also, the smart pachislot 100 may determine whether the VL connection signal is ON / OFF before updating the number of game medals or notifying the count, and if the VL connection signal is OFF, the number of counted medals is set to "0." This is not limited to the form in which the ON / OFF determination of the VL connection signal is performed in the counting switch monitoring process or the counting process.

[0108] Furthermore, when the power of the smart pachislot 100 is turned on, if the dedicated unit 350 starts up later than the smart pachislot 100, the VL connection signal may not turn ON quickly enough, resulting in an error. In this case, the effect of an unintended error notification can be reduced by temporarily lowering the output of the error notification, particularly the speaker 128.

[0109] Furthermore, when the smart pachislot 100 is powered on, the main CPU 200a may wait for a predetermined waiting time (for example, 10 seconds) to start up the sub-CPU 202a and the medal count control board 204. This waiting time may be the CPU start-up time (for example, 0 to 100 msec) plus a time period with a certainty (for example, 5 seconds).

[0110] (Counting processing) As described above, the medal CPU 204a of the smart pachislot 100 performs a counting process to transfer at least a portion of the electronic medals held in the medal holding section to the dedicated unit 350 in response to the player's operation of the counting switch 112.

[0111] FIG. 19 is a timing chart for explaining the counting process. The medal CPU 204a measures the time during which the counting switch 112 is continuously operated to determine the player's desired counting mode (short press or long press). For example, as shown in FIG. 19(a), when a short press of the counting switch 112, i.e., an operation lasting less than 500 msec, is received (time point a), the counted medal count is set to "1." When the 300 msec cycle (predetermined transmission cycle) due to the timer interrupt shown in FIG. 15 arrives (time point b), "1" is subtracted from the game medal count. Here, it is assumed that the game medal count is "29" after "1" is subtracted from "30." The counted medal count and the game medal count are variables stored in RAM by the medal CPU 204a. The smart pachislot 100 then transmits a counting notification to the dedicated unit 350. When the dedicated unit 350 receives the counting notification, it adds the number of counted medals indicated in the counting notification (here, "1") to the number of medals earned (e.g., "0") and displays the result of the addition (e.g., "1") on the earned medal number display device 374.

[0112] Furthermore, for example, as shown in FIG. 19(b), if the player continues to operate the counting switch 112 and a 300 msec cycle arrives (time point c), and the counting switch 112 is pressed and held, i.e., the operation is continued for 500 msec or more, if the number of game medals in the medal holding section is 50 or more, the counted number of medals is set to "50." If the number of game medals is less than 50, the total number of counted medals is set to "30." Here, let's assume that the number of game medals is "30," and the total number of "30" is set as the counted number of medals by pressing and holding the switch. Accordingly, the total number of game medals, "30," is subtracted, and the total number of game medals becomes "0." The smart pachislot 100 then transmits a counting notification to the dedicated unit 350 and clears the counted number of medals (sets it to "0"). When the dedicated unit 350 receives the counting notification, it adds the number of counted medals indicated in the counting notification (here, "30") to the number of medals earned (e.g., "0") and displays the result of the addition (e.g., "30") on the earned medal number display device 374.

[0113] As described above, if the counting switch 112 is operated while a game is available, the counting process is always executed. Therefore, if a player operates the counting switch 112 while a game is in progress, the payout of electronic medals in the progress of the game and the counting process may be executed consecutively in a short period of time. For example, as shown in FIG. 19(c), when the number of game medals is "30," a small winning combination is won as the game progresses, and 15 electronic medals are paid out (time point d). The medal CPU 204a receives a payout end command including the number of payout medals, and adds the number of payout medals "15" to the number of game medals "30," thereby updating the number of game medals to "45" all at once. At the same time, if the player continues to operate the counting switch 112, and when a 300 msec cycle arrives (time point e), the medal CPU 204a accepts a long press of the counting switch 112, i.e., an operation that continues for 500 msec or more, and sets all electronic medals (here, "45") as the number of counted medals. Accordingly, the number of game medals "45" is all subtracted, and the number of game medals becomes "0." The smart pachislot 100 then transmits a counting notification to the dedicated unit 350 and clears the counted medal count. Upon receiving the counting notification, the dedicated unit 350 adds the counted medal number (here, "45") indicated in the counting notification to the number of acquired medals (e.g., "0"), and displays the result of the addition (e.g., "45") on the acquired medal number display device 374.

[0114] Here, the counting process is executed immediately after the electronic medals are paid out, depending on the timing of the winning of a small winning combination and the operation of the counting switch 112. Therefore, the number of gaming medals changes each time from "30" to "45" to "0." However, if the electronic medal payout process and counting process are executed consecutively within the 300 msec cycle in which the counting notification is sent, only the result will be notified in the counting notification. Therefore, regardless of the change in the number of gaming medals from "30" to "45" to "0," the dedicated unit 350 will only display the change in the number of earned medals from "0" to "45" on the earned medal count display device 374.

[0115] As shown in Figure 19, when the cycle for sending a counting notification arrives, regardless of the timing when the number of game medals changes, i.e., the timing when the electronic medal payout process or counting process is executed, and without waiting for the change in the number of game medals due to the electronic medal payout process to be displayed on the game medal number display device 114, if the counting switch 112 is operated continuously for a predetermined time (e.g., 500 msec) or more, the medal CPU 204a transmits some or all of the number of game medals (here, the whole, "45") to the dedicated unit 350 as the counted medal number. Therefore, even when the payout process and counting process of the electronic medals overlap, depending on the timing, the cycle for transmitting a counting notice may arrive, and as a result of the long press, the number of game medals may change from "30" to "0," and "30" may be transmitted to the dedicated unit 350 as the counted medal count. After that, the payout process of the electronic medals may change the number of game medals from "0" to "15," and again, the cycle for transmitting a counting notice may arrive, and as a result of the long press, the number of game medals may change from "15" to "0," and "15" may be transmitted to the dedicated unit 350 as the counted medal count. In this case, the display content of the acquired medal count display device 374 may change from "0" to "30" to "45," and as shown in FIG. 19(c), the display content of the acquired medal count display device 374 may also change from "0" to "45." However, since the player has already started counting the number of game medals by pressing and holding the count switch 112, it is sufficient for the player to confirm that the display content of the acquired medal number display device 374, which was "0," has finally become "45" when the number of game medals and the paid-out electronic medals are combined. Therefore, differences in the manner in which the number of game medals displayed on the acquired medal number display device 374 changes do not affect the progress of the game.

[0116] Here, regardless of the timing of the change in the number of game medals, if the counting switch 112 has been operated continuously for a predetermined time (e.g., 500 msec) or more when the cycle for sending a counting notification arrives, the medal CPU 204a transmits some or all of the number of game medals (here, "45") to the dedicated unit 350. This allows the player to quickly grasp the final number of medals won without unnecessarily waiting for the display update of the number of medals won display device 374, and to quickly start the next operation, thereby improving the operability of the smart pachislot 100.

[0117] Also, here, the medal CPU 204a always accepts operation of the counting switch 112 regardless of the number of game medals (even if the number of game medals is "0"), and measures the time during which the counting switch 112 is continuously operated.

[0118] For example, if the number of game medals is "0," the count notification will show the number of counted medals as "0" regardless of whether the counting process has been performed. Therefore, if the number of game medals is "0," it is conceivable that the counting process will not be performed, or that the time during which the counting switch 112 is continuously operated will not be measured. However, as shown in FIG. 19(c), if the payout process for electronic medals occurs, even if the number of game medals before the payout process was "0," the counting process can be performed for the paid-out electronic medals (number of game medals). In this case, if the time during which the counting switch 112 is continuously operated is measured only after the number of game medals becomes a number other than "0" (after the payout process is completed), the counting process will be delayed accordingly, resulting in poor operability.

[0119] Here, the medal CPU 204a is configured to measure the time that the counting switch 112 is continuously operated regardless of the number of game medals, so that it can reliably determine whether the counting switch 112 has been pressed and held when the cycle for sending the counting notification arrives, allowing the player to quickly grasp the final number of medals acquired and begin the next operation promptly, thereby improving the operability of the smart pachislot 100. Furthermore, the program executed by the medal CPU 204a does not require a determination (branch) as to whether the number of game medals is "0," thereby reducing the processing load and enabling a reduction in memory capacity.

[0120] The cycle (e.g., 300 msec) at which the medal CPU 204a sends count notifications and the cycle (predetermined display cycle by timer interrupt: e.g., 1 msec) at which the display of the game medal count display device 114 is updated are managed independently. Therefore, depending on the time relationship between the timing of the payout process and counting process of the electronic medals described above and the display update timing of the game medal count display device 114, the display mode of the game medal count on the game medal count display device 114 will differ.

[0121] FIG. 20 is a timing chart for explaining the display mode of the number of game medals. Here, as shown in FIG. 19(c), let's assume that a small win occurs as the game progresses, and 15 electronic medals are paid out. Concurrently, the player continues to operate the counting switch 112, and when a 300-msec cycle arrives, the medal CPU 204a accepts a long press of the counting switch 112, i.e., an operation that continues for 500 msec or more, and sets all electronic medals (here, "45") as the number of counted medals. Here, the number of game medals changes from "30" to "45" due to the electronic medal payout process, and from "45" to "0" due to the counting process. Furthermore, in the dedicated unit 350, the number of acquired medals changes from "0" to "45" due to the counting process.

[0122] 20(a), for example, suppose that the display content of the game medal number display device 114 is updated (changed) between the payout process and the counting process of the electronic medals. In this case, the medal CPU 204a changes the number of game medals displayed on the game medal number display device 114 from "30" to "45" when the cycle for updating the display of the game medal number display device 114 arrives (time point f) in response to the number of game medals changing from "30" to "45" due to the payout process of the electronic medals. Similarly, the medal CPU 204a changes the number of game medals displayed on the game medal number display device 114 from "45" to "0" when the cycle for updating the display of the game medal number display device 114 arrives (time point g) in response to the number of game medals changing from "45" to "0" due to the counting process.

[0123] Here, the display contents of the game medal count display device 114 are updated after the payout process for the electronic medals is executed and after the counting process is executed. Therefore, as the number of game medals changes from "30" to "45" to "0", the display on the game medal count display device 114 also changes from "30" to "45" to "0". In this case, the player can understand through the game medal count display device 114 that the number of game medals has changed from "30" to "45" to "0".

[0124] 20(b), assume that both the payout process and the counting process of electronic medals are executed during the period in which the display of the game medal count display device 114 is updated. In this case, the medal CPU 204a changes the number of game medals from "30" to "45" through the payout process of electronic medals, and from "45" to "0" through the counting process. However, when the period in which the display of the game medal count display device 114 is updated arrives (time point h), the number of game medals has already become "0," so the medal CPU 204a directly changes the display of the number of game medals on the game medal count display device 114 from "30" to "0."

[0125] Here, the display content of the game medal count display device 114 is updated after both the payout process and the counting process of the electronic medals are executed. Therefore, the number of game medals increases from "30" to "45" at one time, and then decreases to "0", while the display of the game medal count display device 114 immediately decreases from "30" to "0". In this case, the player understands through the game medal count display device 114 that the number of game medals has changed from "30" to "0".

[0126] Here, if we try to make the player understand through the game medal count display device 114 that the number of game medals has changed stepwise, such as from "30" to "45" to "0," the medal CPU 204a must wait for the display content of the game medal count display device 114 to be updated before performing the counting process, which delays the counting process accordingly. Note that in order to make the player aware of the update of the display on the game medal count display device 114, it becomes necessary to lengthen the display time long enough to make it recognizable, which delays the counting process accordingly and worsens operability.

[0127] Here, as shown in FIG. 20 , when the cycle for transmitting a counting notification arrives, the medal CPU 204a transmits part or all of the number of game medals (here, the whole number, “45”) to the dedicated unit 350 as the counted medal count, regardless of whether the display content of the game medal count display device 114 has been updated in response to a change in the number of game medals. Therefore, when the number of game medals changes from “30” to “45” to “0,” as shown in FIG. 20( a), the number of game medals displayed on the game medal count display device 114 may change from “30” to “45” to “0,” or as shown in FIG. 20( b), the number of game medals displayed on the game medal count display device 114 may change from “30” to “0.” However, since the player has already started counting the number of game medals by pressing and holding the counting switch 112, it is sufficient for the player to confirm that the display content of the game medal count display device 114, which was “30,” has finally changed to “0.” Furthermore, the player only needs to be able to confirm that the display content of the acquired medal count display device 374, which was "0," has finally become "45" when the number of game medals and the number of paid-out electronic medals are combined. Therefore, differences in the manner in which the number of game medals displayed on the game medal count display device 114 changes do not affect the progress of the game.

[0128] Here, regardless of the timing of the change in the number of game medals, if the counting switch 112 has been operated continuously for a predetermined time (for example, 500 msec) or more when the cycle for sending a counting notification arrives, the medal CPU 204a will transmit at least a portion of the game medal number (here, "45") to the dedicated unit 350.This configuration allows the player to quickly grasp the final game medal number and quickly start the next operation without unnecessarily waiting for the display update of the game medal number display device 114, thereby improving the operability of the smart pachislot 100.

[0129] Note that, here, in Figures 19 and 20, we have given an example in which the payout process and counting process of electronic medals are executed continuously, but the change in the number of game medals is not limited to such processes, and can be the subject of various processes, such as the insertion process of electronic medals.

[0130] As explained with reference to FIG. 15, the smart pachislot 100 (for example, the medal CPU 204a) transmits a gaming machine information notification to the dedicated unit 350 at a predetermined cycle (for example, every 300 msec). The smart pachislot 100 also transmits a counting notification to the dedicated unit 350 100 msec after transmitting the gaming machine information notification to the dedicated unit 350. In other words, the smart pachislot 100 transmits a counting notification including information on the number of counted medals to the dedicated unit 350 at a predetermined cycle (for example, every 300 msec), similar to the gaming machine information notification.

[0131] The counting switch 112 is an input operation unit that accepts a predetermined input operation (for example, a pressing operation) by the player. The smart pachislot 100 (for example, the medal CPU 204a) is capable of receiving a signal indicating the input operation from the counting switch 112 (input operation unit). Based on the signal received from the counting switch 112, the smart pachislot 100 sets the number of counted medals as described below. At the above-mentioned predetermined cycle (for example, 300 msec), the smart pachislot 100 updates the number of game medals by subtracting the set number of counted medals from the current number of game medals, and updates the display of the game medal number display device 114 to the updated number of game medals at a cycle different from the predetermined cycle (for example, 1 msec) as needed.

[0132] Once the update of the number of game medals is completed, the display content of the game medal number display device 114 is updated immediately, for example, in 1 msec, so that the display content is updated approximately at a predetermined cycle (for example, 300 msec). As a result, the smart pachislot 100 changes the display content of the game medal number display device 114 (i.e., the number of game medals displayed by the game medal number display device 114) based on the signal received from the counting switch 112, substantially at a predetermined cycle (for example, 300 msec).

[0133] The smart pachislot 100 also transmits a counting notification including information on the set number of counted medals to the dedicated unit 350 at the above-mentioned predetermined cycle (for example, 300 msec). In other words, the smart pachislot 100 outputs a counting notification to the outside based on the signal received from the counting switch 112 at a predetermined cycle.

[0134] Furthermore, the dedicated unit 350 updates the number of earned medals based on the received counting notification, and updates the display of the earned medal count display device 374 to the updated number of earned medals at a cycle (e.g., 1 msec) different from the predetermined cycle. When the dedicated unit 350 completes updating the number of earned medals based on the counting notification, the display content of the earned medal count display device 374 is updated immediately, for example, in 1 msec, so that the display content is updated approximately at a predetermined cycle (e.g., 300 msec). Therefore, the dedicated unit 350 updates the display of the earned medal count display device 374 substantially at a predetermined cycle (300 msec) based on the counting notification received from the smart pachislot 100.

[0135] Here, it is possible that a player may press the counting switch 112 multiple times in rapid succession. In such a case, the smart pachislot 100 may receive (be inputted with) a signal indicating a pressing operation multiple times within one cycle (e.g., within 300 msec) of a predetermined cycle (e.g., 300 msec cycle). The smart pachislot 100 is designed to display the dedicated unit 350 appropriately even if such multiple pressing operations are performed within one cycle.

[0136] Specifically, when the smart pachislot 100 (for example, the medal CPU 204a) receives signals from the counting switch 112 multiple times during one cycle, it validates only one of the multiple signals. More specifically, even if the smart pachislot 100 receives signals from the counting switch 112 multiple times during one cycle, it sets the counted medal number corresponding to the pressing operation of the counting switch 112 to a fixed value of "1." Then, based on the validated signal for one time (more specifically, based on the counted medal number of "1"), the smart pachislot 100 updates the display on the game medal number display device 114 and outputs a signal (for example, a counting notification) to the outside.

[0137] FIG. 21 is a flowchart showing the flow of counting switch processing in the medal CPU 204a. The counting switch processing is executed when the counting switch 112 is pressed. The counting switch processing corresponds to the processing of steps S3 to S10 that are performed when step S1 in FIG. 17 is YES. Here, processing related to this embodiment will be explained, and processing unrelated to this embodiment will be omitted. The numerical values ​​of step S in this figure will be used only in the explanation of this figure.

[0138] As shown in FIG. 21, when the medal CPU 204a detects a press of the counting switch 112 (specifically, when it detects an ON edge of the counting switch 112), it starts timing of the time counter of the smart pachislot 100 (S3). The medal CPU 204a determines whether or not it has detected an OFF edge of the counting switch 112 (S4). If the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether or not a predetermined time (e.g., 500 msec) has elapsed since the start of timing of the time counter (S5). If the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the processing of step S4. If the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long press flag to ON (S6) and returns to the processing of step S4.

[0139] If the OFF edge of the counting switch is detected (YES in S4), the medal CPU 204a determines whether or not the long press flag is OFF (S7). If the long press flag is OFF (YES in S7), the medal CPU 204a sets the counted medal number to "1" and proceeds to processing in step S9. The set counted medal number is stored in a predetermined register or RAM. If the long press flag is ON (NO in S7), the medal CPU 204a proceeds to processing in step S9. In step S9, the medal CPU 204a clears (turns OFF) the long press flag. The medal CPU 204a clears the time counter and ends the counting switch processing. Here, in step S8, the counted medal number is not incremented by "+1", but is set to "1".

[0140] Fig. 22 is a time chart for explaining how to set the number of counted medals. As shown in Fig. 22, for example, at time point a, the number of game medals is "50," a counting notification including information that the number of counted medals is "0" is sent from the smart pachislot 100 to the dedicated unit 350, and the number of acquired medals is "50." Then, suppose that the counting switch 112 is pressed three times from time point a until one cycle of 300 msec has elapsed.

[0141] The above-mentioned counting switch processing is started at the ON edge of the pressing operation of the counting switch 112, and at the OFF edge of the pressing operation, if the pressing is a short press, the counted medal number "1" is set. Since the counted medal number "1" is repeatedly set each time the counting switch 112 is short pressed, for example, even if it is the third short press in one cycle, the counted medal number is set to "1" rather than "3".

[0142] At time point b, when 300 msec, which is one cycle's worth of time, has elapsed from time point a, as described above with reference to FIG. 18, the smart pachislot 100 subtracts the set count medal number of "1" from the current number of game medals "50" to derive the number of game medals "49." The smart pachislot 100 updates the display of the number of game medals on the game medal number display device 114 from "50" to "49." In this way, even if three pressing operations are performed during one cycle, if the number immediately before the display update on the game medal number display device 114 is, for example, "50," the display is updated to "49" rather than "47."

[0143] Furthermore, at time point b, the smart pachislot 100 transmits a counting notification including information indicating the counted medal count of "1" to the dedicated unit 350. Upon receiving the counting notification, the dedicated unit 350 adds the received counted medal count of "1" to the number of earned medals of "50" to derive the number of earned medals of "51." The dedicated unit 350 updates the display of the number of earned medals on the earned medal count display device 374 from "50" to "51." In this way, even if three pressing operations are performed during one cycle, if the number immediately prior to the display update of the earned medal count display device 374 is, for example, "50," the display is updated to "51" rather than "53."

[0144] That is, even if multiple pressing operations are performed during one cycle, the medal CPU 204a can update the display of the earned medal count display device 374 of the dedicated unit 350 so that the counted medal number is increased by 1 every predetermined cycle (e.g., 300 msec) by setting the counted medal number to "1." For example, the display content of the earned medal count display device 374 does not jump from "50" to "53," but changes continuously by 1, such as from "50" to "51." Therefore, in the smart pachislot 100, the earned medal number can be appropriately displayed on the earned medal count display device 374 of the dedicated unit 350, and distrust among players can be prevented.

[0145] In the above-mentioned smart pachislot 100, when a signal (for example, an ON edge) of the counting switch 112 is received (input) multiple times during one cycle, only one of the multiple signals is considered valid. However, when the smart pachislot 100 receives a signal (for example, an ON edge) of the counting switch 112 multiple times during one cycle, it may process all of the multiple received signals as valid.

[0146] Fig. 23 is a flowchart showing the flow of counting switch processing according to a modified example in which all multiple signals are processed effectively. The flowchart in Fig. 23 differs from the flowchart in Fig. 21 in that step S8 in the flowchart in Fig. 21 is changed to step S18, but the other steps are the same as the flowchart in Fig. 21.

[0147] As shown in FIG. 23, when the long press flag is OFF (YES in S7), the smart pachislot 100 increments the counted medal number by "+1" (increment by 1).

[0148] Fig. 24 is a time chart for explaining the setting of the number of counted medals according to a modified example in which all multiple signals are effectively processed. As shown in Fig. 24, it is assumed that the counting switch 112 is pressed three times from time c until 300 msec, which is one cycle, has elapsed.

[0149] The counting switch processing in this modified example starts at the ON edge of the pressing operation of the counting switch 112, and at the OFF edge of the pressing operation, if the pressing is a short press, the number of counted medals is incremented by "1". Therefore, each time the counting switch 112 is short pressed during one cycle, the number of counted medals increases by "1". For example, at the second OFF edge during one cycle, the number of counted medals is set to "2", and at the third OFF edge during one cycle, the number of counted medals is set to "3".

[0150] At time point d, when one cycle of 300 msec has elapsed since time point c, as explained using Figure 18, the smart pachislot 100 subtracts the set count medal number of "3" from the current number of game medals "50" to derive the number of game medals "47." The smart pachislot 100 updates the display of the number of game medals on the game medal number display device 114 so that it decreases by "1" in succession, such as "50" → "49" → "48" → "47."

[0151] Furthermore, at time point d, the smart pachislot 100 transmits a counting notification including information on the counted medal number "3" to the dedicated unit 350 due to three pressing operations during one cycle. Upon receiving the counting notification, the dedicated unit 350 adds the received counted medal number "3" to the number of earned medals "50" to derive the number of earned medals "53." The dedicated unit 350 updates the display of the number of earned medals on the earned medal number display device 374 so that it increases by "1" in succession, such as "50" → "51" → "52" → "53."

[0152] In this way, even in the modified example in which all of the multiple signals are effectively processed, the number of acquired medals can be appropriately displayed on the acquired medal number display device 374 of the dedicated unit 350.

[0153] (Counting sound) As described above, in the smart pachislot 100, when the counting switch 112 is operated and the counting process is executed, a counting sound is output from the speaker 128 to notify the player that the counting switch 112 has been operated (to notify the player of the movement of the electronic medals). Similarly, in the smart pachislot 100, when the lending switch 366 is operated and the lending process is executed, a lending sound is output from the speaker 128 to notify the player that the lending switch 366 has been operated (to notify the player of the movement of the electronic medals). The lending process refers to the process of lending electronic medals by transmitting information for lending some or all of the electronic medals from the dedicated unit 350 to the smart pachislot 100 in response to the player's operation of the lending switch 366. The output of the counting sound and the lending sound will be explained below using the counting sound as an example.

[0154] 19 and the like, the medal CPU 204a sets the counted medal number to "0" when the counting switch 112 is not operated, sets the counted medal number to "1" when the counting switch 112 is pressed briefly, and sets the counted medal number to "50" (or the entire number if the number of game medals is 50 or less) when the counting switch 112 is pressed and held. Then, when the timing for sending a counting notification arrives, which occurs every 300 msec, the medal CPU 204a sends a counting notification including information about the set counted medal number to the dedicated unit 350.

[0155] When the medal CPU 204a transmits a counting notification including information on the counted medal number ("1," "50," or any number between "1" and "50") indicating that the counting switch 112 has been operated to the dedicated unit 350, the medal CPU 204a also transmits a signal indicating that the counting process has been performed (counting notification trigger signal) to the main control board 200 along with the transmission of the counting notification. When the main CPU 200a of the main control board 200 receives the counting notification trigger signal from the medal count control board 204, it transmits a counting sound notification to the sub-control board 202 instructing the output of a counting sound. When the sub-CPU 202a of the sub-control board 202 receives the counting sound notification through the main control board 200, it outputs the counting sound through the speaker 128. As a result, the counting sound is continuously output while the counting process is being executed in accordance with the operation of the counting switch 112.

[0156] In addition, the medal CPU 204a is not limited to transmitting the count notification trigger signal at the timing of transmitting the count notification containing information on the number of counted medals indicating that the count switch 112 has been operated. For example, the medal CPU 204a may transmit the count notification trigger signal at the timing when the number of counted medals indicating that the count switch 112 has been operated is set and then the number of game medals reflecting the set number of counted medals is displayed on the game medal number display device 114.

[0157] The smart pachislot 100 may be provided with a total of seven speakers 128, including two upper speakers, two lower speakers, two tweeters, and one bass speaker. The upper speakers are provided, for example, on the left and right sides of the symbol display window 108 on the upper front door 104. The upper speakers are installed on the back of the upper front door 104, and openings are provided in front of the upper speakers on the upper front door 104. The lower speakers are provided, for example, on the left and right sides of the lower front door 106. The lower speakers are installed on the back of the lower front door 106, and openings are provided in front of the lower speakers on the lower front door 106. For example, one tweeter is provided near the left upper speaker and one tweeter is provided near the right upper speaker. The tweeter is installed on the back of the upper front door 104, and an opening is provided in the upper front door 104 in front of the tweeter. The bass speaker is provided, for example, near the reel 110 inside the housing 102. No opening is provided in the housing 102 in front of the bass speaker. The upper and lower speakers output, for example, mid-range sounds. The tweeter outputs, for example, high-range sounds. The bass speaker is, for example, a woofer, and outputs low-range or deep-bass sounds. The counting sound can be output from any of the upper speaker, lower speaker, tweeter, and bass speaker.

[0158] Here, during a game, various sounds are output to effectively liven up the game, such as sound effects (e.g., background music), lines of characters used in the game (e.g., "Bonus confirmed"), and sound effects (SE). Hereinafter, these various sounds related to the game will be collectively referred to as game sounds. When the counting switch 112 is operated during a game, a counting sound may be output in addition to (overlap with) the above game sounds in response to the operation of the counting switch 112.

[0159] FIG. 25 illustrates the operation when the game sound and the counting sound overlap. FIG. 25(a) shows an example of the volume when the game sound and the counting sound do not overlap and only the game sound is output. As shown in FIG. 25(a), the game sound can be output from each speaker at the maximum volume (100%) that can be set for that speaker. Here, the higher the speaker volume, the greater the current flowing through the speaker's voice coil, and the greater the current flowing through the speaker's voice coil, the higher the speaker temperature. When the game sound and the counting sound do not overlap, as shown in FIG. 25(b), even if the game sound is output, the temperature of each speaker does not exceed the upper limit of the allowable temperature for that speaker (hereinafter referred to as the upper limit of the allowable temperature). Note that FIG. 25(b) illustrates the temperature of an arbitrary one of the speakers.

[0160] FIG. 25(c) shows an example of the volume when the game sound and the counting sound overlap. FIG. 25(c) shows a case where the game sound is output at the maximum volume (100%) that can be set for each speaker, and the counting sound is output at the maximum volume (100%) that can be set for each speaker. If the game sound and the counting sound overlap and both are output at maximum volume (maximum volume that can be set), as shown in FIG. 25(d), the temperature of each speaker may exceed the allowable upper temperature limit for each speaker. In this case, the speaker whose temperature exceeds the allowable upper temperature limit may be damaged. Note that FIG. 25(d) illustrates the temperature of an arbitrary one of the speakers.

[0161] Therefore, as shown in Figure 25(e), when the game sound and the counting sound overlap, the volume of the game sound is reduced from the maximum volume, and the volume of the counting sound is output at the maximum volume (the maximum volume that can be set (100%)). For example, in the upper speaker, the volume of the game sound is reduced by 10% from the maximum volume, and the game sound is output at 90% volume. In the lower speaker, tweeter, and bass speaker, the volume of the game sound is reduced by 50% from the maximum volume, and the game sound is output at 50% volume.

[0162] 25(f), even if the game sound and the counting sound are output at the same time, the temperature of each speaker can be prevented from exceeding the upper limit of the allowable temperature of each speaker. As a result, damage to the speakers can be prevented. Furthermore, although the volume of the game sound is reduced from the maximum volume, the game sound is still output, so that the player is prevented from feeling uncomfortable about the progress of the game, and the game can be progressed appropriately.

[0163] 25(e), the reduction in the volume of the game sounds output from the lower speaker, tweeter, and bass speaker is greater than the reduction in the volume of the game sounds output from the upper speaker. Because the upper speaker outputs mid-range sounds close to the player's ears, players are sensitive to the sounds from the upper speaker. If the reduction in the volume of the game sounds output from the upper speaker is large, the player will be more likely to notice the reduction in volume, which may reduce the effectiveness of the game sounds. On the other hand, because the lower speaker, tweeter, and bass speaker are relatively far from the player's ears, even if the reduction in the volume of the lower speaker, tweeter, and bass speaker is greater than that of the upper speaker, the player will be less likely to notice the reduction in volume, and the reduction in the effectiveness of the game sounds will be suppressed. As a result, by making the reduction in the volume of the game sounds output from the lower speaker, tweeter, and bass speaker greater than the reduction in the volume of the game sounds output from the upper speaker, it is possible to prevent damage to the speakers while suppressing a reduction in the effectiveness of the game sounds.

[0164] In addition, the amount of reduction in the volume of the game sounds output from the upper speaker, lower speaker, tweeter, and bass speaker other than the upper speaker is not limited to being greater than the amount of reduction in the volume of the game sounds output from the upper speaker, but for example, the amount of reduction in the volume of the game sounds output from speakers other than a specific speaker among the multiple speakers arranged in multiple positions in the smart pachislot 100 may be greater than the amount of reduction in the volume of the game sounds output from the specific speaker. This embodiment also makes it possible to prevent damage to the speakers and ensure proper gameplay.

[0165] In addition, the volume of the game sounds may be reduced by the same amount for all speakers, including the upper speaker, lower speaker, tweeter, and bass speaker. This also prevents damage to the speakers and allows the game to proceed properly.

[0166] Furthermore, in the smart pachislot 100, it is necessary to ensure that the total current value (hereinafter referred to as the total current value of the cabinet 102) obtained by combining the currents flowing through each part of the smart pachislot 100 does not exceed the upper limit of the current allowed for the cabinet 102 (hereinafter referred to as the allowable current upper limit). When the game sound and the counting sound are output at the same time, the current for outputting the counting sound flows in addition to the current for outputting the game sound. For this reason, when the game sound and the counting sound overlap, the temperature of each speaker rises and the total current value of the cabinet 102 may exceed the allowable current upper limit.

[0167] As described above, when the game sound and the counting sound overlap, the volume of the game sound is reduced from the maximum volume, and the volume of the counting sound is output at the maximum volume, thereby preventing the total current value of the cabinet 102 from exceeding the allowable current upper limit. As a result, damage to each part of the cabinet 102 can be prevented. Furthermore, by reducing the volume of the game sound, the total current value of the cabinet 102 can be reduced, which also makes it possible to miniaturize the power supply.

[0168] 25(e), the volume of the upper speaker is set to 90%, and the volume of the lower speaker, tweeter, and bass speaker is set to 50%. However, the values ​​of the volume of the game sounds are just an example, and the volume of the game sounds may be set to any value taking into consideration the temperature of each speaker and the total current value of the cabinet 102.

[0169] 26 is a flowchart illustrating the counting sound processing executed by the performance control means 334. The numerical values ​​of step S in this figure are used only in the explanation of this figure. The counting sound processing is a process of outputting a counting sound from each speaker based on the reception of a counting sound notification.

[0170] The performance control means 334 determines, for example, at a predetermined interval, whether a counting sound notification has been received (S1). If a counting sound notification has been received (YES in S1), the performance control means 334 sets the volume of the game sounds to be reduced (S2). For example, the performance control means 334 sets the volume setting values ​​of game sound tracks, such as the performance sound track, dialogue track, and sound effect track, to a predetermined volume value that is lower than the volume setting value immediately before (normally during) receiving the counting sound notification. This reduces the volume of the game sounds output from each speaker.

[0171] After the setting to reduce the volume of the game sounds is completed, the presentation control means 334 outputs a sound signal indicating a counting sound to each speaker (S3). As a result, the counting sound is output from each speaker. The presentation control means 334 outputs the counting sound each time it receives a counting sound notification. For example, if the counting switch 112 is pressed and held, the counting sound is output while the counting switch 112 is pressed and held.

[0172] Furthermore, if the counting sound notification has not been received as a result of determining at a predetermined period whether it has been received (NO in S1), the performance control means 334 determines whether the counting sound is being output (S4). If it determines that the counting sound is being output (YES in S4), the performance control means 334 stops outputting sound signals indicating the counting sound to each speaker (S5). This stops the output of the counting sound that has been output from each speaker. For example, if the long press of the counting switch 112 is released, the output of the counting sound is stopped in response to the release of the long press.

[0173] After the counting sound stops, the performance control means 334 sets the volume of the game sound to return to the volume immediately before receiving the counting sound notification (normal volume) (S4), and ends the counting sound process. As a result, the volume of the game sound output from each speaker returns to the normal volume.

[0174] As described above, the smart pachislot 100, an example of a gaming machine connectable to a specific unit (e.g., the dedicated unit 350) that lends gaming value, includes gaming value control means (e.g., the medal count control board 204) that manages gaming value (e.g., electronic medals) and presentation control means 334 that controls presentations. The presentation control means 334 outputs game sounds corresponding to the progress of a game through an audio output unit (e.g., each speaker). The gaming value control means (e.g., the medal count control board 204) may perform a counting process to transfer the gaming value to the specific unit. In the smart pachislot 100, an example of a gaming machine, a counting sound is output to notify the user that the counting process is being performed, and the volume of the game sounds is reduced during the counting process. This allows the game to proceed appropriately and prevents damage to the speaker due to the speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0175] In addition, when the game sounds and the lending sounds overlap, the volume of the game sounds may be reduced and output from each speaker, and the lending sounds may be output from each speaker, as in the case when the game sounds and the counting sounds overlap. In this case, too, the volume of the game sounds output from speakers other than a specific speaker among the multiple speakers arranged in multiple positions on the smart pachislot 100 may be reduced by more than the volume of the game sounds output from a specific speaker, or the volume of the game sounds may be reduced by the same amount for all speakers, including the upper speaker, lower speaker, tweeter, and bass speaker. These modes also allow the game to proceed appropriately and prevent damage to the speakers due to the speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0176] In addition, the amount of reduction in the volume of the game sounds when the game sounds and counting sounds overlap may be the same as the amount of reduction in the volume of the game sounds when the game sounds and lending sounds overlap (the reduction amounts may not be different), or may be different.

[0177] For example, the amount of reduction in the volume of the game sounds when the game sounds and the lending sounds overlap (e.g., a reduction of 25%) may be less than the amount of reduction in the volume of the game sounds when the game sounds and the counting sounds overlap (e.g., a reduction of 50%). Generally, it is assumed that the lending switch 366 is operated more frequently than the counting switch 112. Therefore, by reducing the amount of reduction in the volume of the game sounds when they overlap with the lending sounds compared to the amount of reduction in the volume of the game sounds when they overlap with the counting sounds, it is possible to prevent the player from feeling uncomfortable about the progress of the game.

[0178] Also, for example, the amount of reduction in the volume of the game sounds when the game sounds and the counting sound overlap (e.g., a reduction of 25%) may be less than the amount of reduction in the volume of the game sounds when the game sounds and the lending sound overlap (e.g., a reduction of 50%). When the counting switch 112 is operated when the number of game medals is relatively high, it is expected that the counting switch 112 will be operated more frequently or for a longer period of time, which will momentarily increase the frequency of operation of the counting switch 112. For this reason, by reducing the amount of reduction in the volume of the game sounds when the counting sound overlaps with the volume of the game sounds compared to the amount of reduction in the volume of the game sounds when the lending sound overlaps with the volume of the game sounds, it is possible to prevent the player from feeling uncomfortable about the progress of the game.

[0179] Furthermore, the counting sounds and the rental sounds may be the same sounds or different sounds. Different sounds may mean, for example, different types of sounds (the sounds themselves), different pitches (intervals), different lengths, different rhythms, or different phrases. When the counting sounds and the rental sounds are different sounds, for example, the counting sounds may be an ascending phrase (ascending phrase) and the rental sounds may be a descending phrase (ascending phrase), or the counting sounds may be a descending phrase (ascending phrase) and the rental sounds may be an ascending phrase (ascending phrase). An ascending phrase (ascending phrase) is a group of sounds that is composed of multiple sounds and whose pitch increases as they are produced. A descending phrase (ascending phrase) is a group of sounds that is composed of multiple sounds and whose pitch decreases as they are produced.

[0180] When the lending switch 366 is operated, basically, electronic medals are moved in units of 50 from the dedicated unit 350 to the smart pachislot 100. However, when the lending switch 366 is operated, all of the electronic medals held in the dedicated unit 350 may be moved from the dedicated unit 350 to the smart pachislot 100.

[0181] Furthermore, when the game sound and the lending sound overlap, or even if the lending switch 366 is operated regardless of whether or not there is overlap with the game sound, the lending sound may not be output from each speaker. Because the lending notification transmitted from the dedicated unit 350 to the smart pachislot 100 is transmitted every 300 msec, there may be a time lag between the operation of the lending switch 366 and the reception of the lending notification by the smart pachislot 100. A relatively long time lag may cause the player to feel uneasy about the lending. By not outputting the lending sound, it is possible to avoid causing the player to feel uneasy about the lending. Similarly, when the game sound and the counting sound overlap, or even if the counting switch 112 is operated regardless of whether or not there is overlap with the game sound, the counting sound may not be output from each speaker. By not outputting the counting sound, it is possible to avoid causing the player to feel uneasy about the counting.

[0182] Furthermore, in the smart pachislot 100, if any of various errors, such as a door open error, occurs during the game, error information is displayed on the liquid crystal display unit 124 and the main segment display unit 130, and an error sound is output from the speaker 128. There are cases where the error sound and the counting sound overlap. Here, we will first explain the types of errors that will output an error sound.

[0183] (Error type) FIG. 27 is an explanatory diagram for explaining errors managed by the main control board 200. As shown in FIG. 27, a "backup error" represented by error code "E7" occurs when backup of the main RAM (RWM) 200c of the main control board 200 fails, and can be recovered by executing a setting change. A "door open error" represented by error code "E8" occurs when at least one of the front upper door 104 or the front lower door 106 is detected to be open, and is automatically recovered by closing both the front upper door 104 and the front lower door 106. A "RWM error" represented by error code "EA" occurs when reading and writing to the main RAM (RWM) 200c of the main control board 200 cannot be performed normally, and can be recovered by executing a setting change. A "setting value error" represented by error code "EC" occurs when an abnormal setting value is displayed, and can be recovered by executing a setting change. The "medal over error," represented by the error code "EH," occurs when the number of game medals exceeds, for example, 16,369. It automatically recovers when the counting process reduces the number of game medals to less than 16,369. The "dispensing device connection error," represented by the error code "EL," occurs when the dedicated unit 350 jig is not connected. It automatically recovers when the jig is connected. The "medal count control error," represented by the error code "EP," occurs when an abnormality occurs in communication with the medal count control board 204. It can be recovered by turning the power back on. The "play limit error," represented by the error code "Ey," occurs when the difference number counter exceeds a specified difference number, for example, 19,000, and can be recovered by changing the settings. Note that the specified difference number is not limited to 19,000 and can be set to various values. Such error codes are displayed on the main segment display unit 130. The main segment display unit 130 normally displays nothing (the segment LEDs are off). Only when an error such as the one described above occurs, does the error code continue to be displayed until the error is resolved.

[0184] When an error such as the one described above occurs, the performance control means 334 can display error information such as "Please call an attendant" on the liquid crystal display unit 124, or can output a warning sound and a voice such as "Please call an attendant" from the speaker 128. For example, in the case of a "stop error" represented by the error code "Ey," it is possible to display a message such as "Complete function in operation" on the liquid crystal display unit 124, but not output an error sound.

[0185] Figure 28 is an explanatory diagram for explaining errors managed by the medal count control board 204. The error code of such an error is displayed on the medal segment display unit 204d arranged on the medal count control board 204. The medal segment display unit 204d is composed of one seven-segment display unit.

[0186] As shown in FIG. 28, a "backup error 2" represented by error code "7" occurs when the backup of the medal RAM (RWM) 204c of the medal count control board 204 fails. This error can be resolved by turning the power back on while pressing an error release switch (not shown) on the medal count control board 204. An "RWM error 2" represented by error code "A" occurs when the medal RAM (RWM) 204c of the medal count control board 204 cannot be read or written normally. This error can be resolved by changing the settings. An "lending device connection error 2" represented by error code "L" occurs when the dedicated unit 350 jig is not connected. This error is automatically resolved by connecting the jig. A "main control communication error" represented by error code "P" occurs when an abnormality occurs in communication with the main control board 200. This error can be resolved by turning the power back on. An "manufacturer code error" represented by error code "U" occurs when the manufacturer codes of the medal count control board 204 and the main control board 200 do not match. This error can be resolved by replacing either board to match the manufacturer codes. The error code ".", i.e., the "medal count clear notification" represented by the seven-segment dot, occurs when the power is turned on while pressing the medal count clear button (not shown) and the medal count is cleared, and automatically returns to normal five seconds after transitioning to a medal insertion ready state. Note that the "medal count clear notification" occurs even if this process is performed when the medal count is 0. The error code "all flashing," i.e., "preparing to start" where all seven-segment LEDs are flashing, occurs while waiting for communication with the main control board 200 to begin, and automatically returns to normal when a startup command is received from the main control board 200. Note that if the "preparing to start" state continues, it can be determined that some kind of error has occurred in the main control board 200.

[0187] Here, the main CPU 200a monitors errors in the medal count control board 204 in addition to errors in the main control board 200. On the other hand, the medal CPU 204a monitors errors in the medal count control board 204, but does not monitor errors in the main control board 200.

[0188] Furthermore, the errors managed by the main control board 200 shown in FIG. 27 and the errors managed by the medal count control board 204 shown in FIG. 28 have the following relationship. For example, when a "lending device connection error 2" represented by error code "L" occurs on the medal count control board 204, the main CPU 200a of the main control board 200 also issues a "lending device connection error" represented by error code "EL" on the main control board 200 in response to the "lending device connection error 2." Therefore, the "lending device connection error 2" and the "lending device connection error" can be considered to be the same error. Furthermore, when communication cannot be established between the main CPU 200a and the medal CPU 204a, or when established communication is disconnected, the main CPU 200a issues a "medal count control error" represented by error code "EP" on the main control board 200, and the medal CPU 204a issues a "main control communication error" represented by error code "P" on the medal count control board 204. Therefore, the "lending device connection error" and "medal count control error" of the main control board 200 occur at the same time as the "lending device connection error 2" and "main control communication error" of the medal count control board 204, respectively.

[0189] While the above-mentioned error occurs, the progress of the game is restricted. For example, while a door open error occurs, the player cannot continue the game. However, even when an error occurs, the above-mentioned lending process and counting process may be executed.

[0190] For example, if an error such as "Backup Error 2" (a game value control event) represented by error code "7", "RWM Error 2" (a game value control event) represented by error code "A", "Lending Device Connection Error 2" (a game value control event) represented by error code "L", "Manufacturer Code Error" (a game value control event) represented by error code "U", or "Preparing to Start" (a game value control event) represented by error code "All Flashing" occurs, both the lending process and the counting process are restricted, as shown in Figure 28. However, the "Game Medal Count Clear Notification" represented by error code "." is not related to the lending process or the counting process, so the lending process and the counting process are possible. Furthermore, a "main control communication error" represented by error code "P" restricts both lending and counting processes only while a "lending device connection error 2" represented by error code "L" is occurring, and lending and counting processes are possible unless a "lending device connection error 2" represented by error code "L" is occurring. Note that while errors managed by the medal count control board 204 have been mainly cited and explained as events of game value control here, this is not limited to such cases and any error indicating that it has become difficult to move electronic medals (lending and counting processes) between the medal count control board 204 and the dedicated unit 350 may occur.

[0191] Furthermore, if an error (main control event) managed by the main control board 200 occurs solely in the main control board 200 without any errors occurring in the medal count control board 204, the lending process and counting process are possible. Therefore, even if a "door open error" represented by error code "E8" occurs, the medal count control board 204 is not affected, and therefore the lending process and counting process are possible. Furthermore, even if a "playing limit error" represented by error code "Ey" occurs, the lending process and counting process are possible. Therefore, the player can perform the counting process to reduce the number of game medals to less than 16,369, and voluntarily cancel the "playing limit error." While errors managed by the main control board 200 have been described as main control events here, this is not limited to such cases; other errors that occur when the movement of electronic medals (loaning process, counting process) between the medal count control board 204 and the dedicated unit 350 is possible may also occur.

[0192] In this way, the smart pachislot 100 connectable to a specific unit (e.g., the dedicated unit 350) that lends out game value includes a game value number holding unit that holds the number of game values ​​(e.g., the number of game medals), which is the total number of game values ​​(e.g., electronic medals) that can be used for games, and a control unit (e.g., the medal CPU 204a, the main CPU 200a) that manages the game value. The control unit may execute a lending process that transfers game value from the specific unit to the smart pachislot 100, and may transfer game value from the smart pachislot 100 to the dedicated unit 350. A counting process may be performed to transfer game value to a specific unit, and if a main control event (e.g., "door open error," "play stop error") or a game value control event different from a main control event (e.g., "backup error 2," "rental device connection error 2") occurs, the progress of the game is restricted (e.g., the progress of the game is stopped), and if a main control event occurs, at least one of the lending process and the counting process can be performed, and if a game value control event occurs, both the lending process and the counting process are restricted. This makes it possible to appropriately control the lending process and the counting process even if an error occurs.

[0193] Here, when an error sound is output in response to the occurrence of an error such as the above, the error sound and the counting sound may overlap. When the error sound and the counting sound overlap, both the error sound and the counting sound may be output from each speaker without lowering the volume of the error sound. Similarly, when the error sound and the lending sound overlap, both the error sound and the counting sound may be output from each speaker without lowering the volume of the error sound. Because the error sound has a higher priority than the game sound, outputting the error sound without lowering the volume of the error sound makes it easier for hall staff and others to recognize that an error has occurred.

[0194] Furthermore, when the error sound and the counting sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the counting sound may be output from each speaker by reducing the volume of the counting sound, or the counting sound may not be output from each speaker. Similarly, when the error sound and the rental sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the rental sound may be output from each speaker by reducing the volume of the rental sound, or the rental sound may not be output from each speaker. According to this embodiment, it is possible to easily make the hall staff or the like aware that an error has occurred while preventing the temperature of each speaker or the total current value of the housing 102 from exceeding the upper limit value.

[0195] Here, the main CPU 200a may monitor whether the difference between the number of electronic medals inserted (the number of medals bet) and the number of medals paid out since the power was reset has reached a first specified difference (specified value), and may activate a so-called complete function that limits the progress of the game when the first specified difference has been reached. When such a complete function has been activated, the presentation control means 334 displays complete activation information on the LCD display unit 124 to notify that the complete function is activated, and may output a complete activation sound from each speaker to notify that the complete function is activated. The main CPU 200a may also monitor whether the difference has reached a second specified difference, which is a predetermined difference less than the first specified difference at which the complete function is activated, and may indicate, when the second specified difference has been reached, that activation of the complete function is imminent (there is a possibility that the first specified difference will be reached). The performance control means 334 may output a complete operation indication sound from each speaker, which indicates that the complete function is about to be activated. Hereinafter, the complete operation sound and the complete operation indication sound will be collectively referred to as the complete function sound.

[0196] When the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the counting sound may also be output from each speaker. Similarly, when the complete function sound and the lending sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the lending sound may also be output from each speaker. Because the complete function sound has a higher priority than the game sounds, outputting the complete function sound without reducing the volume of the complete function sound makes it easier for players to recognize that the complete function is approaching activation or that the complete function has been activated.

[0197] Furthermore, when the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the counting sound may be output from each speaker by reducing the volume of the counting sound, or the counting sound may not be output from each speaker. Similarly, when the complete function sound and the lending sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the lending sound may be output from each speaker by reducing the volume of the lending sound, or the lending sound may not be output from each speaker. This embodiment makes it possible to easily notify a player that the complete function is approaching activation or that the complete function has been activated, while preventing the temperature of each speaker or the total current value of the cabinet 102 from exceeding an upper limit.

[0198] Furthermore, when the completion function sound and the counting sound overlap, the volume of the completion function sound may be lowered and the completion function sound may be output from each speaker, or the completion function sound may not be output from each speaker and the counting sound may be output from each speaker. Similarly, when the completion function sound and the lending sound overlap, the volume of the completion function sound may be lowered and the completion function sound may be output from each speaker, or the completion function sound may not be output from each speaker and the lending sound may be output from each speaker. This embodiment makes it possible to make the counting sound or the lending sound more easily noticeable to players and the like while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limits.

[0199] Furthermore, when the game sounds and the complete function sound overlap, the volume of the game sounds may be lowered and output from each speaker, and the complete function sound may be output from each speaker. This embodiment makes it possible to appropriately progress or limit the game, and also prevents damage to the speakers due to their temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0200] In addition, when the game sounds and the complete function sound overlap, the game sounds may be output from each speaker without reducing the volume of the game sounds, and the complete function sound may be output from each speaker. According to this embodiment, it is possible to appropriately progress or restrict the game.

[0201] Furthermore, when the game sounds and the complete function sound overlap, the game sounds may be output from each speaker without reducing the volume of the game sounds, and the complete function sound may be output from each speaker by reducing the volume of the complete function sound, or the complete function sound may not be output from each speaker. This embodiment makes it possible to appropriately progress or limit the game, and also to prevent damage to the speakers due to the speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0202] The medal CPU 204a may manage whether the number of game medals (possessed number of game values) has fallen below a predetermined number, and when the number of game medals falls below the predetermined number, may notify the player that the number of game medals has decreased. In this case, the presentation control means 334 issues a possession number warning to notify the player that the number of game medals has decreased. Specifically, the presentation control means 334 displays possession number warning information on the liquid crystal display unit 124 and outputs a possession number warning sound from each speaker.

[0203] When the counting sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker without lowering the volume of the possession number warning sound, and the counting sound may be output from each speaker. Similarly, when the lending sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker without lowering the volume of the possession number warning sound, and the lending sound may be output from each speaker. According to this aspect, it is possible to make the possession number warning sound and the counting sound, or the possession number warning sound and the lending sound, easier for the player to recognize.

[0204] When the counting sound and the possession number warning sound overlap, the volume of the possession number warning sound may be lowered and the possession number warning sound may be output from each speaker, or the possession number warning sound may not be output from each speaker and the counting sound may be output from each speaker. Similarly, when the lending sound and the possession number warning sound overlap, the volume of the possession number warning sound may be lowered and the possession number warning sound may be output from each speaker, or the possession number warning sound may not be output from each speaker and the lending sound may be output from each speaker. According to this embodiment, it is possible to make the counting sound or the lending sound more easily noticeable to the player while preventing the temperature of each speaker or the total current value of the cabinet 102 from exceeding an upper limit value.

[0205] When the counting sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker, the volume of the counting sound may be lowered and the counting sound may be output from each speaker, or the counting sound may not be output from each speaker. Similarly, when the lending sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker, the volume of the lending sound may be lowered and the lending sound may be output from each speaker, or the lending sound may not be output from each speaker. According to this embodiment, the possession number warning sound can be made more easily noticeable to the player while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limits.

[0206] When the error sound and the possession number warning sound overlap, the error sound may be output from each speaker without lowering the volume of the error sound, and the possession number warning sound may be output from each speaker without lowering the volume of the possession number warning sound. According to this embodiment, it is possible to make both the error sound and the possession number warning sound easily recognizable to the player, etc.

[0207] When the error sound and the possession number warning sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the possession number warning sound may be output from each speaker by reducing the volume of the possession number warning sound, or the possession number warning sound may not be output from each speaker. Depending on the content of the error, the error sound may have a higher priority than the possession number warning sound, and in such a case, it is possible to make the high-priority error sound more easily recognizable to the player, etc., while preventing the temperature of each speaker or the total current value of the cabinet 102 from exceeding the upper limit value.

[0208] When the error sound and the possession number warning sound overlap, the possession number warning sound may be output to each speaker without lowering the volume of the possession number warning sound, and the error sound may be output from each speaker by lowering the volume of the error sound, or the error sound may not be output from each speaker. Depending on the type of error, the possession number warning sound may have a higher priority than the error sound, so in such a case, it is possible to make the possession number warning sound, which has a higher priority, more easily recognizable to the player, while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limit values.

[0209] When the complete function sound and the possession count warning sound overlap, the complete function sound may be output from each speaker without lowering the volume of the complete function sound, and the possession count warning sound may be output from each speaker without lowering the volume of the possession count warning sound. This makes it easier for players to recognize both the complete function sound and the possession count warning sound.

[0210] When the complete function sound and the possession number warning sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the possession number warning sound may be output from each speaker by reducing the volume of the possession number warning sound, or the possession number warning sound may not be output from each speaker. According to this embodiment, it is possible to make the complete function sound more easily recognizable to players and the like while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limits.

[0211] When the complete function sound and the possession number warning sound overlap, the volume of the complete function sound may be lowered and output from each speaker, or the complete function sound may not be output from each speaker and the possession number warning sound may be output from each speaker without lowering the volume of the possession number warning sound. According to this embodiment, it is possible to make the possession number warning sound more easily noticeable to players and the like while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limits.

[0212] (Counting sound volume) As described above, the gaming state includes a bonus gaming state. The bonus gaming state is a state that is more advantageous to the player than other gaming states. The presentation state also includes an AT presentation state. The AT presentation state is a state that is more advantageous to the player than other presentation states. Note that the advantageous state is not limited to the bonus gaming state and the AT presentation state, but may be any state that is advantageous to the player, such as an RT gaming state in which the probability of winning a replay role is set high, an ART gaming state in which the AT presentation state and the RT gaming state proceed simultaneously, a chance zone (CZ), or the like.

[0213] The effect control means 334 outputs various sounds such as game sounds according to the progress of the game. In this way, the effect control means 334 also functions as a sound control means that controls the output of sounds according to the progress of the game.

[0214] When the player is in an advantageous state, the performance control means 334 (sound control means) outputs predetermined sounds, such as background music and character voices, at a first volume through an audio output unit such as a speaker. Here, the predetermined sounds include system sounds that correspond to the operation of the bet switch 116, start switch 118, stop switch 120, etc. The first volume indicates a normal volume with no restrictions. The first volume can also be adjusted through the menu screen of the smart pachislot 100.

[0215] Here, when in an advantageous state, if no operation for game progress is performed for a predetermined time (if the time during which no operation for game progress is performed continues for more than a predetermined time), the smart pachislot 100 as a gaming machine may enter a volume adjustment state. The volume adjustment state indicates a state in which the volume of the predetermined sound is limited to a second volume that is lower than the first volume. The second volume may include zero volume, i.e., muting. In the case of muting, the predetermined sound is not output from the audio output unit.

[0216] As described above, the medal count control board 204 is a gaming value control means that manages gaming values ​​(e.g., electronic medals). The medal count control board 204 may perform a counting process to transfer gaming values ​​to a specific unit (e.g., the dedicated unit 350). The medal count control board 204 may also perform a lending process to transfer gaming values ​​from a specific unit (e.g., the dedicated unit 350). As described above, the counting process and lending process can be performed at any timing, and therefore may be performed, for example, during an advantageous state, and may also be performed during the volume adjustment state described above during an advantageous state.

[0217] When the player is in an advantageous state, the presentation control means 334 outputs, via the audio output unit, a counting sound at a third volume in response to the execution of the counting process, which notifies the player that the counting process is being performed. The third volume is unrelated to the first and second volumes of the predetermined sound. However, the third volume may be louder than the first volume, the same as the first volume, or lower than the first volume but higher than the second volume. The counting sound, dispensing sound, and settlement sound are included in the transfer sound for transferring electronic medals and are distinguished from game sounds.

[0218] As described above, when the state transitions to the volume adjustment state while in an advantageous state, the performance control means 334 limits the volume of the predetermined sound from the first volume to the second volume. However, even when the state transitions to the volume adjustment state while in an advantageous state, the performance control means 334 outputs the counting sound at the third volume. In other words, the volume of the counting sound is not limited.

[0219] The medal CPU 204a transmits a counting notification in accordance with the player's operation of the counting switch 112, and transmits a signal indicating that the counting process has been performed (counting notification trigger signal) to the main control board 200. Upon receiving the counting notification trigger signal, the main CPU 200a transmits a counting sound notification instructing the output of a counting sound to the sub-control board 202. The sub-CPU 202a can receive the counting sound notification through the main control board 200. Upon receiving the counting sound notification, the performance control means 334 outputs the counting sound at a third volume through the audio output unit.

[0220] As described above, different tracks are assigned to different types of game sounds, such as tracks for performance sounds, character voices, and sound effects (SE). Furthermore, counting sounds and lending sounds are assigned transfer sound tracks separate from the game sound tracks. The counting sounds and lending sounds may be assigned the same track or different tracks. The settlement sound that notifies the user that a settlement process is being performed in response to the operation of the settlement switch 121 may also be assigned a track different from the game sounds.

[0221] When the performance control means 334 transitions to the volume adjustment state, it limits the volume of the predetermined sound track (tracks other than the counting sound track) from the first volume to the second volume. At this time, the volume of the counting sound track is maintained at the third volume. Because the volume of the counting sound track is maintained at the third volume, the performance control means 334 can output the counting sound at the third volume even if a counting process is performed in the volume adjustment state.

[0222] This makes it easier for players and parlor staff to recognize that counting processing is taking place in the smart pachislot 100, which is an example of a gaming machine, and allows the game to proceed appropriately.

[0223] Furthermore, when in the advantageous state, the performance control means 334 outputs, through the audio output unit, a rental sound at a third volume in response to the execution of the rental process, which notifies the user that the rental process is being performed. Even if the performance control means 334 transitions to a volume adjustment state when in the advantageous state, it outputs the rental sound at the third volume. In other words, the volume of the rental sound is not limited.

[0224] In response to receiving the loan notification transmitted from the dedicated unit 350, the medal CPU 204a transmits a signal (loan notification trigger signal) indicating that the loan process has been completed to the main control board 200. When the main CPU 200a receives the loan notification trigger signal from the medal count control board 204, it transmits a loan sound notification to the sub-control board 202, instructing the output of a loan sound. The sub-CPU 202a can receive the loan sound notification through the main control board 200. When the performance control means 334 receives the loan sound notification, it outputs the loan sound at a third volume through the audio output unit.

[0225] When the performance control means 334 transitions to the volume adjustment state, it limits the volume of the predetermined sound track (tracks other than the counting sound track) from the first volume to the second volume. At this time, the volume of the rental sound track is maintained at the third volume. Because the volume of the rental sound track is maintained at the third volume, the performance control means 334 can output the rental sound at the third volume even if a rental process is performed in the volume adjustment state.

[0226] This makes it easier for players and hall staff to recognize that the lending process is being carried out in the smart pachislot 100, which is an example of a gaming machine, and allows the game to proceed appropriately.

[0227] Figure 29 is a flowchart illustrating the flow of the volume control process executed by the performance control means 334. The numerical values ​​of step S in this figure will be used only in the explanation of this figure. The volume control process is a process for controlling the volume of the sound output from the audio output unit. For the sake of convenience, Figure 29 explains the counting sound, and the explanation of the lending sound is omitted as it is the same as the explanation of the counting sound.

[0228] The performance control means 334 determines at a predetermined interval whether or not the game is in an advantageous state (S1). If the game is not in an advantageous state (NO in S1), the performance control means 334 ends the volume control process.

[0229] If the player is in an advantageous state (YES in S1), the presentation control means 334 determines whether a predetermined time has elapsed during which no operation has been performed in the game progression (S2). If the predetermined time has not elapsed (NO in S2), the presentation control means 334 sets the volume of the predetermined sound to a first volume (S3). Then, the presentation control means 334 outputs a sound signal indicating the predetermined sound to the audio output unit (S4). As a result, the predetermined sound is output from the audio output unit at the first volume.

[0230] If the predetermined time has elapsed (YES in S2), the performance control means 334 limits the volume of the predetermined sound to the second volume (S5) and enters a volume adjustment state. Then, the performance control means 334 outputs a sound signal representing the predetermined sound to the audio output unit (S4). As a result, the predetermined sound is output from the audio output unit at the second volume.

[0231] After outputting the sound signal of the predetermined sound, the performance control means 334 determines whether or not a counting sound notification has been received (S10). If a counting sound notification has been received (YES in S10), the performance control means 334 outputs the sound signal of the counting sound to the audio output unit for a predetermined period of time (S11), and ends the volume control process. As a result, the counting sound is output from the audio output unit at the third volume, regardless of whether or not the volume is adjusted.

[0232] If the counting sound notification has not been received (NO in S10), the performance control means 334 determines whether the counting sound is being output (S13). If it is determined that the counting sound is not being output (NO in S12), the performance control means 334 ends the volume control process.

[0233] If it is determined that the counting sound is being output (YES in S12), the performance control means 334 stops outputting the sound signal indicating the counting sound from the audio output unit (S13) and ends the volume control process. This stops the output of the counting sound that has been output from the audio output unit. For example, if the long press of the counting switch 112 is released, the output of the counting sound is stopped in response to the release of the long press.

[0234] In this way, by maintaining the third volume without restricting the volume for counting and lending processes, it becomes easier for players and hall staff to recognize that counting and lending processes are being performed, allowing the game to proceed appropriately.

[0235] (Communication between the main CPU and medal CPU) The above describes the communication between the smart pachislot 100 and the dedicated unit 350. However, specifically, in parallel with the serial communication between the token CPU 204a and the dedicated unit 350, the main CPU 200a and the token CPU 204a also communicate serially within the smart pachislot 100. The token CPU 204a acquires information by sending and receiving commands to the main CPU 200a, and notifies the dedicated unit 350 of the information based on that information. The serial communication has a communication speed of, for example, 125,000 bps, and each byte of data is represented by one start bit, eight data bits, and one stop bit. Here, we explain the relationship between the main CPU 200a and the token CPU 204a, which is the precursor to notification between the token CPU 204a and the dedicated unit 350, and then detail the communication between them.

[0236] (Contents stored in RAM) Here, using Figures 5(a) and 5(b), we have explained an example in which the main CPU 200a and the medal CPU 204a are provided separately, each with its own independent ROM and RAM, and each performing processing based on an independent program. However, information such as the total number of inserted coins, the total number of paid-out coins, MY (maximum MY), the total number of payout coins for special features, the total number of payout coins for consecutive special features, and the number of games are all information that begins accumulating when the power is turned on and continues to accumulate until reset when power is restored after a power outage. If the main CPU 200a manages some of the information and the medal CPU 204a manages other information independently, the following problem may arise. That is, if the power of either the main CPU 200a or the medal CPU 204a is turned off while the power of the other remains on, for example, the total number of inserted coins and the total number of paid-out coins may be counted from a reset state, but the total number of payout coins for special features and the total number of payout coins for consecutive special features may continue to be counted in an accumulated state without being reset. Therefore, information related to accumulation such as the total number of inserted coins, the total number of paid-out coins, MY (maximum MY), the total number of paid-out coins from special devices, the total number of paid-out coins from consecutive special devices, and the number of games played is managed by one CPU. For example, in this case, the main CPU 200a manages all of this information. This configuration makes it possible to avoid inconsistencies in information and ensure that games proceed appropriately.

[0237] (Error priority) When betting electronic medals, the main CPU 200a refers to the number of electronic medals inserted, the number of medals paid out, the total number of medals inserted, the total number of medals paid out, etc. in the payout process, settlement process, and counting process to confirm that there are no inconsistencies in the relationships, and may notify an error if there are any inconsistencies. Furthermore, the main CPU 200a may also confirm that the number of medals inserted is between 1 and 3, and that the number of medals paid out is between 0 and 15, in the payout process of electronic medals, and notify an error if they are not within these ranges. Such processing may be performed in a use area or a non-use area. In addition to the above, the main CPU 200a may also check a specified number corresponding to the game status.

[0238] Here, it is assumed that the medal CPU 204a is configured to perform its own error determination process in addition to errors in the main CPU 200a. In such a configuration, if errors occur simultaneously in the main CPU 200a and the medal CPU 204a, the error occurring in the main CPU 200a may be given priority and reported via a device such as the speaker 128. It is also possible to set specific errors that may occur simultaneously in the main CPU 200a and the medal CPU 204a (for example, errors determined to be serious problems, such as backup errors or errors indicating abnormal RAM read / write operations), and to report the specific errors via a device if errors occur simultaneously in the main CPU 200a and the medal CPU 204a. Furthermore, if multiple errors occur simultaneously in the medal CPU 204a, the most recently occurring error may be given priority and reported via a device such as the game medal count display device 114. Furthermore, it is also possible to set priorities for multiple errors in advance, and if multiple errors occur simultaneously in the medal CPU 204a, to report the errors based on the set priorities. By predetermining the priority of error notification in this way, it becomes possible to respond quickly and effectively according to the urgency and priority of the error. For example, if multiple errors occur, the error with the highest priority, error 1, is notified. Here, when the cause of the error is removed and an error release operation is performed, error notification 1 at that time is erased, and the error with the next highest priority is sequentially notified. In other words, error notification 1 is erased in response to the release operation of error 1. Furthermore, in addition to the case where error notification 1 is erased in response to the release operation of error 1, it is also possible to control multiple error notifications whose causes have been removed to be erased simultaneously in response to the release operation of error 1. In this case, when an error release operation is performed, multiple error notifications whose causes have been removed are erased, and the error with the highest priority among the errors whose causes have not been removed is notified.In addition, an individual device such as a 7-segment device may be installed separately on the medal count control board 204, and if an error occurs in the medal CPU 204a, the individual device may be used to notify the error instead of or in addition to the game medal count display device 114.

[0239] (RAM abnormality) Furthermore, among errors, RAM abnormalities are processed in the non-used area of ​​the main CPU 200a, and in the used area of ​​the medal CPU 204a. This is because the main CPU 200a does not have a sufficient capacity for the used area, while the medal CPU 204a has a sufficient capacity for the used area. This configuration makes it possible to appropriately progress the game while suppressing an increase in memory capacity in the main ROM 200b.

[0240] (command sending and receiving) The main CPU 200a transmits a predetermined command to the medal CPU 204a. For example, the main CPU 200a may transmit a game medal insertion command consisting of identification information, transmission information indicating the requested number of medals to be inserted, and a checksum to the medal CPU 204a when the bet switch 116 is operated. Furthermore, the main CPU 200a may transmit a start lever press command consisting of identification information, transmission information indicating the requested number of medals to be inserted, and a checksum to the medal CPU 204a when the start switch is operated. Furthermore, the main CPU 200a may transmit a payout end command consisting of identification information, transmission information indicating the number of medals to be paid out, and a checksum to the medal CPU 204a when payout is completed. Furthermore, the main CPU 200a may transmit a game end command consisting of identification information, transmission information related to the winning combination, and a checksum to the medal CPU 204a when one game is completed. Furthermore, the main CPU 200a may transmit a startup command to the medal CPU 204a at startup, the startup command consisting of identification information, communication information required at startup, communication information related to the role ratio, and a checksum. The main CPU 200a may transmit a state transition command consisting of identification information and a checksum to the medal CPU 204a when the internal state changes, an error occurs, or an error is resolved. The length of the above-mentioned command can be set arbitrarily. The main CPU 200a calculates the role ratio-related communication information (information related to the use of electronic medals (game value) and information related to the acquisition of electronic medals (game value)), i.e., the total number of inserted medals, the total number of paid-out medals, MY (maximum difference in number of medals), the total number of payout medals for bonuses, the total number of payout medals for consecutive bonuses, the bonus ratio, the consecutive bonus ratio, the advantageous zone ratio, the bonus ratio with instructions, the bonus etc. state ratio, and the number of plays, and transmits the information to the medal CPU 204a. The medal CPU 204a extracts a portion of the role ratio-related transmission information from the command received from the main CPU 200a and stores it in the RAM of the medal count control board 204. The main CPU 200a may calculate the role ratio-related transmission information in a use area or in a non-use area. Furthermore, the medal CPU 204a may store the role ratio-related transmission information in a use area or in a non-use area of ​​the RAM.Furthermore, the medal CPU 204a may transfer the transfer information relating to the role ratio to the RAM in the use area or in the non-use area.

[0241] Of the above-mentioned game medal insertion command, start lever press command, payout end command, one game end command, startup command, and state transition command, the main CPU 200a sends the game medal insertion command, start lever press command, payout end command, one game end command, and startup command to the medal CPU 204a within the main loop, and the main CPU 200a sends the state transition command to the medal CPU 204a within a timer interrupt (for example, at a 1.49 msec cycle).

[0242] The medal CPU 204a can also determine errors based on commands received from the main CPU 200a. For example, the medal CPU 204a extracts the number of inserted and paid-out digitized medals from the medal insertion command, payout end command, and one-game end command, and confirms that there is no inconsistency between the total number of inserted and paid-out digitized medals. The medal CPU 204a also confirms that the number of inserted digitized medals is not 0 when a start lever press command is received. The medal CPU 204a may also confirm that there is no inconsistency between the specified number of digitized medals corresponding to the game status in the medal insertion command. The main CPU 200a may also control a one-bit confirmation signal indicating the transmission of a payout end command via an I / O other than serial communication. If the confirmation signal does not indicate the transmission of a payout end command, the medal CPU 204a may discard the received command regardless of whether it is a payout end command.

[0243] Here, let's assume that the command sent from the main CPU 200a to the medal CPU 204a is variable length. In this case, when the medal CPU 204a starts receiving the command, the length of the command is unknown, so it is unclear how long the command reception state should be maintained or at what timing the medal CPU 204a should begin analyzing the command. When the command is variable length in this way, the identification information can indicate what kind of command it is and how many bytes long it is, making it possible for the medal CPU 204a to easily understand the command.

[0244] Also, for example, if there is a bit in the identification information to which no information is assigned, that bit can be assigned to the "replay status" which is information required by the medal CPU 204a. In this way, the free space in the transmission data can be effectively utilized, and it is not necessary to generate a separate program to generate and transmit a one-byte command for the replay status.

[0245] The medal CPU 204a also transmits a predetermined command to the main CPU 200a. For example, when the medal CPU 204a receives the above commands (game medal insertion command, start lever press command, payout end command, startup command) from the main CPU 200a, it may transmit a reply command to the main CPU 200a that includes identification information, transmission information indicating the number of medals that can be inserted and the number of game medals, and a checksum. The main CPU 200a can determine an error by checking the checksum of the reply command received from the medal CPU 204a. Note that the medal CPU 204a does not transmit a reply command in response to a game end command or a state transition command.

[0246] Here, let us suppose that a predetermined bit of the identification information of the reply command is associated with an "ACK" indicating that the medal CPU 204a has successfully received the command sent from the main CPU 200a. This "ACK" is processed independently of other bits. For example, if the predetermined bit of the identification information is 1, the main CPU 200a can proceed to the next game process regardless of the contents of the other bits. Furthermore, if a bit other than the predetermined bit is set, the main CPU 200a performs processing corresponding to the set bit while continuing the game. This configuration makes it possible to effectively utilize the area of ​​the identification information and increase the efficiency of information transfer.

[0247] Furthermore, such communication between the main CPU 200a and the medal CPU 204a may be continuously performed or may be subject to a predetermined restriction. For example, bidirectional communication between the main CPU 200a and the medal CPU 204a may be initiated upon completion of a win type lottery or an AT lottery by operation of the start switch 118, and may be restricted upon completion of one game. In this embodiment, when the start switch 118 is operated, a random number is acquired (latched) from the random number generator 200d and used as a win type lottery random number for the win type lottery or for the AT lottery. Here, communication between the main CPU 200a and the medal CPU 204a is not performed until completion of a win type lottery or an AT lottery by operation of the start switch 118, and communication is initiated upon completion of the win type lottery or an AT lottery by operation of the start switch 118. This eliminates the risk that communication between the main CPU 200a and the medal CPU 204a will affect the latch timing of the random number, making it possible to appropriately acquire random numbers.

[0248] When the main CPU 200a and the medal CPU 204a are provided separately as in Figures 5(a) and 5(b), they transmit information using commands via the serial communication described above. On the other hand, when the main CPU 200a manages the electronic medals used in games instead of the medal CPU 204a as in Figure 5(c), the information is held as a common internal variable in the main RAM 200c.

[0249] (Command Management) As described above, the main CPU 200a transmits a number of types of commands (a game medal insertion command, a start lever press command, a payout end command, a game end command, a startup command, and a state transition command) as information to the medal CPU 204a. In addition, the medal CPU 204a transmits a reply command to the main CPU 200a. If the main CPU 200a receives the reply command normally and the contents of the reply command indicate "ACK," the main CPU 200a can proceed to the next process, assuming that communication between the main CPU 200a and the medal CPU 204a has been completed normally.

[0250] However, communication between the main CPU 200a and the medal CPU 204a does not always complete normally. For example, even if the main CPU 200a successfully transmits a command, the medal CPU 204a may not be able to receive the command correctly for some reason. Furthermore, even if the medal CPU 204a successfully receives a command from the main CPU 200a and successfully transmits a reply command in response to that command, the main CPU 200a may not be able to receive the reply command correctly for some reason. In either case, however, the main CPU 200a cannot determine whether the medal CPU 204a successfully received the command. Therefore, in order to proceed with the processing, the main CPU 200a resends the command it most recently transmitted to the medal CPU 204a.

[0251] Here, we will explain the case where the transmission of the payout end command is not completed normally. In the former case, that is, when the main CPU 200a transmits the command normally but the medal CPU 204a cannot receive the command normally, the medal CPU 204a does not process the payout end command itself effectively, so even if the main CPU 200a resends the payout end command, no problem will occur as long as the medal CPU 204a can receive the resent payout end command normally.

[0252] However, in the latter case, i.e., when the medal CPU 204a successfully receives a command from the main CPU 200a and successfully transmits a reply command in response to that command, but the main CPU 200a fails to successfully receive the reply command, it is highly likely that the medal CPU 204a has validly processed the payout end command. For example, suppose the medal CPU 204a successfully receives the payout end command and adds the number of payout medals included in the payout end command to the number of game medals. The medal CPU 204a successfully transmits the reply command, but is unable to determine whether the main CPU 200a successfully received the reply command. If the main CPU 200a fails to successfully receive the reply command and resends the payout end command, and the medal CPU 204a successfully receives the payout end command, there is a risk that the number of payout medals included in the payout end command will be further added to the number of game medals. In this case, the number of electronic medals paid out will be repeatedly added to the number of game medals for each payout trigger, and the player will gain unfair gaming profits. Also, if the harness between the main control board 200 and the medal count control board 204 is manipulated and a payout end command is sent fraudulently multiple times, the same situation as above may occur in which the number of payout medals is repeatedly added to the number of game medals.

[0253] Therefore, in this embodiment, a command transmitted from the main CPU 200a to the medal CPU 204a is appropriately validated only once. Specifically, when the medal CPU 204a receives the same type of command consecutively from the main CPU 200a (externally), it invalidates the second and subsequent received commands of the same type and does not process them. Here, the commands refer to the aforementioned medal insertion command, start lever press command, payout end command, one-game end command, startup command, and state transition command. For example, if a payout end command is received without receiving any other commands after a payout end command, this constitutes consecutive reception of the same type of command. Note that, when the same type of command is received two or more times consecutively from the main CPU 200a, the second and subsequent commands of the same type are not necessarily invalidated. For example, when a specific command of the same type is received two or more times consecutively under a specific condition that allows consecutive command reception, such as when a 1-bet switch is operated two or more times consecutively, the medal CPU 204a may also process the second and subsequent commands of the same type as valid.

[0254] Furthermore, when the medal CPU 204a receives a predetermined command from the main CPU 200a, it may invalidate any subsequent predetermined commands received until it receives a specific command different from the first predetermined command. For example, once the medal CPU 204a receives a payout end command from the main CPU 200a, it invalidates any subsequent payout end commands received until it receives a specific command, such as a start lever press command. In this case, the specific command received after the first predetermined command is only valid if it receives a specific command. Even if commands or information other than the specific command are received between the first and second predetermined commands, the subsequently received payout end commands are invalidated. For example, once the medal CPU 204a receives a payout end command as a predetermined command from the main CPU 200a, it invalidates any subsequent payout end commands received until it receives a start lever press command as a specific command, even if it receives other game medal insertion commands, one game end commands, startup commands, or state transition commands.

[0255] Here, we will explain an example in which, when the medal CPU 204a receives a specified command from the main CPU 200a, it effectively processes the specified command received after the first specified command received, provided that a specific command is received.However, the medal CPU 204a may effectively process the specified command received after the first specified command received, provided that it receives some command other than the specified command or any information, not limited to a specific command.

[0256] Figures 30 to 33 are flowcharts showing the flow of command reception processing in the medal CPU 204a. Here, processing related to this embodiment is described, and unrelated processing, such as specific command generation processing, is omitted. The numerical values ​​in step S in these figures are used only in the description of these figures. Also, here, 1-byte buffers (insertion request buffer, IN signal confirmation buffer, payout confirmation buffer, and main received command error buffer) are used as flags, switching between two values: "0h" and "FFh." Here, byte values ​​rather than bit values ​​are used as flags because, with bit values, after reading the byte value, further processing must be performed to determine the bit itself, which actually lengthens the total command size required for determination. Note that each of the above buffers used as flags is backed up and is not initialized even when the power is turned off.

[0257] As shown in FIG. 30, when the medal CPU 204a normally receives a command from the main CPU 200a, it determines whether the received command (received command) is a startup command (S1). If the received command is a startup command (YES in S1), the medal CPU 204a performs gaming machine installation information reception processing to receive gaming machine installation information (S2), performs manufacturer code confirmation processing to confirm the main control chip manufacturer code (S3), and terminates the command reception processing. This manufacturer code confirmation processing will be described in detail later. If the received command is not a startup command (NO in S1), the medal CPU 204a determines whether the received command is a payout end command (S4). If the received command is a payout end command (YES in S4), the medal CPU 204a executes payout number setting processing (S5) and terminates the command reception processing. This payout number setting processing will be described in detail later.

[0258] Furthermore, if the received command is not a payout end command (NO in S4), the medal CPU 204a determines whether or not the received command is a one-game end command (S6). As a result, if the received command is a one-game end command (YES in S6), the medal CPU 204a performs a gaming machine performance information setting process to set gaming machine performance information (S7), and ends the command reception process. Also, if the received command is not a one-game end command (NO in S6), the medal CPU 204a determines whether or not the received command is a state transition command (S8). As a result, if the received command is a state transition command (YES in S8), the medal CPU 204a executes a main control status reception process (S9) to receive the main control status, and ends the command reception process.

[0259] Furthermore, if the received command is not a state transition command (NO in S8), the medal CPU 204a executes a requested insertion number update process (S10) that updates the requested number of electronic medals to be inserted, and determines whether the received command is a start lever press command (S11). As a result, if the received command is a start lever press command (YES in S11), the medal CPU 204a executes a game start process (S12) and ends the command reception process. This game start process will be described in detail later. Furthermore, if the received command is not a start lever press command (NO in S11), the medal CPU 204a ends the command reception process.

[0260] In the flowchart of Fig. 30, processes are executed exclusively and independently depending on which of the multiple types of commands is received. For example, if the received command is a payout end command, the payout number setting process (S5) is executed, but the game start process (S12) is not executed. If the received command is a start lever press command, the game start process (S12) is executed, but the payout number setting process (S5) is not executed. In this embodiment, the payout number setting process (S5) executed in response to the reception of a payout end command and the game start process (S12) executed in response to the reception of a start lever press command are managed independently, and the payout confirmation buffer and the IN signal confirmation buffer are switched to appropriately manage the received commands by the medal CPU 204a.

[0261] (Manufacturer code confirmation process) The medal CPU 204a resets (OFF) the communication permission flag when the power is turned on. Here, the communication permission flag is a flag for controlling whether or not communication is possible between the medal CPU 204a and the dedicated unit 350. When the communication permission flag is ON (valid), the medal CPU 204a is able to communicate with the dedicated unit 350, and when the communication permission flag is OFF (invalid), the medal CPU 204a does not execute (start) communication with the dedicated unit 350.

[0262] In the manufacturer code confirmation process (S3) shown in Fig. 31, the medal CPU 204a extracts (acquires) a manufacturer code (identifier) ​​from the startup command (information) received from the main CPU 200a (S3-1), compares it with the manufacturer code (specific identifier) ​​of the medal count control board 204 that is pre-stored in the medal ROM 204b of the medal count control board 204, and determines whether or not they match (S3-2). Here, the manufacturer code is an identifier that can uniquely identify the manufacturer that produced the smart pachislot 100. Therefore, if the main control board 200 and the medal count control board 204 are boards from the same manufacturer, the manufacturer codes will match, and if the main control board 200 and the medal count control board 204 are boards from different manufacturers, the manufacturer codes will be different.

[0263] If the manufacturer codes are compared and the two match (YES in S3-2), the medal CPU 204a turns on the communication permission flag (S3-3) and ends the manufacturer code confirmation process. On the other hand, if the two do not match (NO in S3-2), the medal CPU 204a turns off the communication permission flag (or keeps it off if it is already off) (S3-4), sets a manufacturer code mismatch error managed by the medal CPU 204a (S3-5), and ends the manufacturer code confirmation process. In this case, since the communication permission flag is turned off, the medal CPU 204a cannot communicate with the dedicated unit 350, and as a result, the progress of the game is restricted. The error counter will be described in detail later.

[0264] Then, the medal CPU 204a checks the communication permission flag every time it sends a notification (gaming machine information notification, counting notification, loan receipt result response) to the dedicated unit 350 as shown in Figure 15, and if the communication permission flag is ON, it can send the notification.

[0265] Furthermore, when the medal CPU 204a receives a loan notification from the dedicated unit 350, if the timing is appropriate and the communication permission flag is ON, it executes processing for the loan notification. If the timing is inappropriate or the communication permission flag is OFF, the medal CPU 204a receives the loan notification but ignores (discards) the loan notification and does not execute processing for the loan notification. Here, the appropriate timing is approximately 170 msec after the medal CPU 204a sends the counting notification or approximately 270 msec after the medal CPU 204a sends the gaming machine information notification, as shown in FIG. 15.

[0266] In this way, after establishing communication with the main CPU 200a (first control unit), the medal CPU 204a (second control unit) receives a startup command (information) from the main CPU 200a and acquires a manufacturer code (identifier) ​​from the startup command. Then, if the medal CPU 204a determines that the manufacturer code is equal to a predetermined manufacturer code (specific identifier), it enables communication with the dedicated unit 350. With this configuration, the medal CPU 204a can communicate with the dedicated unit 350 when the connection between the medal CPU 204a and the main CPU 200a is correct and communication is being performed appropriately. Therefore, communication between the medal CPU 204a and the dedicated unit 350 will not be initiated if communication between the medal CPU 204a and the main CPU 200a is not being performed appropriately, and therefore, processing between the medal CPU 204a, the main CPU 200a, and the dedicated unit 350 can be performed appropriately.

[0267] Here, whether communication between the medal CPU 204a and the main CPU 200a is being performed properly is confirmed by a startup command when the smart pachislot 100 is powered on. The startup command is sent earliest among the commands (startup command, game medal insertion command, start lever press command, payout end command, one game end command, and state transition command) that the main CPU 200a sends to the medal CPU 204a. Therefore, communication between the medal CPU 204a and the main CPU 200a can be confirmed early before other commands (game medal insertion command, start lever press command, payout end command, one game end command, and state transition command), and communication between the medal CPU 204a and the dedicated unit 350 can be started early.

[0268] The information for confirming that communication between the medal CPU 204a and the main CPU 200a is being performed properly is not limited to the startup command, but may be other commands (a game medal insertion command, a start lever depression command, a payout end command, a one game end command, a state transition command). In this way, it is possible to confirm that communication between the medal CPU 204a and the main CPU 200a is being performed properly by using any of the commands.

[0269] Also, here, whether communication between the medal CPU 204a and the main CPU 200a is being performed appropriately is confirmed by the manufacturer code included in the startup command. However, this is not limited to this case, and any identifier that can identify the connection relationship between the main CPU 200a and the medal CPU 204a (the connection relationship between the main control board 200 and the medal count control board 204) will suffice, and for example, gaming machine information or chip ID, which is transmission information required at startup and included in the startup command, or any identifier included in other commands (game medal insertion command, start lever press command, payout end command, one game end command, state transition command) can also be used.

[0270] Also, here we have given an example of sending a command from the main CPU 200a (first control unit) to the medal CPU 204a (second control unit) in the smart pachislot 100, but this is not limited to this case and can be applied to serial communication between various independent CPUs, such as the first control unit and the second control unit, between other boards within the smart pachislot 100, for example.

[0271] In the payout number setting process (S5) shown in FIG. 32, the medal CPU 204a sets the input request buffer to 0h (S5-1) and the IN signal confirmation buffer to 0h (S5-2). By setting the IN signal confirmation buffer to 0h, the invalidation of the start lever press command received in the game start process (S12) described later is canceled. Next, the medal CPU 204a determines whether the payout confirmation buffer is 0h (S5-3). If the payout confirmation buffer is not 0h (NO in S5-3), this indicates that the payout end command has not been received for the first time, and the medal CPU 204a terminates the payout number setting process. On the other hand, if the payout confirmation buffer is 0h (YES in S5-3), this indicates that the payout end command has been received for the first time, and the medal CPU 204a sets FFh to the payout confirmation buffer (S5-4) to invalidate subsequent payout end commands. Next, the medal CPU 204a determines whether the number of medals to be paid out is 16 or more (S5-5). As a result, if the number of medals to be paid out is 16 or more (YES in S5-5), FFh is set in the main received command error buffer (S5-6), and the payout number setting process is terminated.

[0272] On the other hand, if the number of payout medals is 15 or less (NO in S5-5), the medal CPU 204a determines whether or not replay is activated (S5-7). As a result, if replay is not activated (NO in S5-7), the medal CPU 204a determines whether or not the number of payout medals is 0 (S5-8). As a result, if the number of payout medals is 0 (YES in S5-8), the medal CPU 204a ends the payout number setting process. On the other hand, if the number of payout medals is not 0 (NO in S5-8), the medal CPU 204a adds the number of payout medals to the number of game medals to update the number of game medals (S5-9), and sets the number of payout medals to the number of payout medals (S5-10). In this way, the number of game medals is appropriately updated. When the payout number is set to the payout medal number (S5-10), or if replay is activated (YES in S5-7), the medal CPU 204a performs a game information setting process to set game information (S5-11), and then terminates the payout number setting process.

[0273] In the game start process (S12) shown in FIG. 33, the medal CPU 204a determines whether the IN signal confirmation buffer is 0h (S12-1). As a result, if the IN signal confirmation buffer is not 0h (NO in S12-1), this means that the start lever press command has not been received for the first time, and the medal CPU 204a terminates the game start process. On the other hand, if the IN signal confirmation buffer is 0h (YES in S12-1), this means that the start lever press command has been received for the first time, and the medal CPU 204a sets FFh to the IN signal confirmation buffer (S12-2), invalidates the second and subsequent start lever press commands, performs game information setting process to set game information (S12-3), sets the payout confirmation buffer to 0h (S12-4), and terminates the game start process. Here, by setting the payout confirmation buffer to 0h, the invalidation of the payout end command received in the payout number setting process (S5) is canceled. In the above, step S12-4 is executed when the determination in step S12-1 is YES, but it may be executed before step S12-1.

[0274] Here, when the medal CPU 204a receives the same type of payout end command consecutively from the main CPU 200a, it invalidates the payout end command received the second time and thereafter. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 32, the medal CPU 204a determines that the payout end command has been received for the first time, switches the payout confirmation buffer to FFh, and normally executes the processing from step S5-6 onwards for the payout number. After that, even if the medal CPU 204a receives the next payout end command, it determines in step S5-3 that the payout confirmation buffer is not 0h (it is FFh), so the processing from step S5-6 onwards for the payout number is not executed (the payout end command is invalidated).

[0275] Furthermore, when the medal CPU 204a receives a start lever press command from the main CPU 200a under the condition that the received payout end command is invalidated, the medal CPU 204a cancels the invalidation of the payout end command. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 32, the medal CPU 204a switches the payout confirmation buffer to FFh, invalidating any payout end commands received thereafter. However, if a start lever press command is subsequently received, the payout confirmation buffer is reset to 0h in step S12-4 of FIG. 33. Therefore, when the next payout end command is received, the payout confirmation buffer is determined to be 0h in step S5-3 of FIG. 32, i.e., the payout end command is determined to be received for the first time, and the processing from step S5-4 onwards for the number of payout coins is normally executed.

[0276] Furthermore, when the medal CPU 204a receives the same type of start lever press command consecutively from the main CPU 200a, it invalidates the second and subsequent received start lever press commands. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 33, the medal CPU 204a determines that the start lever press command has been received for the first time, switches the IN signal confirmation buffer to FFh, and normally executes the game information setting process of step S12-3. Thereafter, even if the medal CPU 204a receives the next start lever press command, it determines in step S12-1 that the IN signal confirmation buffer is not 0h (is FFh), so the game information setting process of step S12-3 is not executed (the start lever press command is invalidated).

[0277] Furthermore, under the circumstances where the medal CPU 204a invalidates the received start lever press command, if the medal CPU 204a subsequently receives a payout end command from the main CPU 200a, it cancels the invalidation of the start lever press command. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 33, the medal CPU 204a switches the IN signal confirmation buffer to FFh, invalidating any start lever press commands received thereafter. However, upon receiving a payout end command, the IN signal confirmation buffer is reset to 0h in step S5-2 of FIG. 32. Therefore, when the next start lever press command is received, the IN signal confirmation buffer is determined to be 0h in step S12-1 of FIG. 33, i.e., the start lever press command is determined to be received for the first time, and the game information setting process in step S12-3 is executed normally.

[0278] In this way, when a command is received multiple times in succession, the same type of command received from the second time onwards is invalidated, so that a process that should only be executed once in response to the command is not executed multiple times, and the game proceeds appropriately. Also, even if an illegal board is attached between the main control board 200 and the medal count control board 204 and a command is illegally sent multiple times by this illegal board, the command is invalidated, so game profits will not be obtained unfairly.

[0279] In this example, if a payout end command is received multiple times in succession, the payout confirmation buffer is switched to invalidate subsequent receptions. Similarly, if a start lever press command is received multiple times in succession, the IN signal confirmation buffer is switched to invalidate subsequent receptions. Because the payout end command and the start lever press command are processed exclusively, one buffer is sufficient. However, if two values ​​in one buffer are assigned to allow the payout end command and the start lever press command, respectively, and one buffer is in a state where it allows either the payout end command or the start lever press command but not the other, if a backup abnormality occurs in the medal CPU 204a or a setting change occurs in the main control board 200, the other command that should be allowed will not be allowed, and game play may not proceed. Therefore, here, buffers (payout confirmation buffer, IN signal confirmation buffer) are provided for the payout end command and the start lever press command, and when predetermined initialization conditions such as a backup abnormality or setting change are met, both buffers are set to 0h, thereby transitioning to a state in which both commands are permitted. With this configuration, even if a backup abnormality occurs in the medal CPU 204a or a setting change occurs in the main control board 200, it is possible to properly proceed with the game.

[0280] This embodiment can also be implemented with a single buffer, for example, a command confirmation buffer, by separately providing a state that allows both the payout end command and the start lever press command. For example, a state that allows both the payout end command and the start lever press command is set to 0h, a state that allows only the payout end command but not the start lever press command is set to 1h, and a state that allows only the start lever press command but not the payout end command is set to 2h. When the medal CPU 204a receives a payout end command, it switches the command confirmation buffer to 2h to invalidate subsequent receptions of the payout end command if multiple consecutive payout end commands are received. When the medal CPU 204a receives a start lever press command, it switches the command confirmation buffer to 1h to invalidate subsequent receptions of the start lever press command if multiple consecutive start lever press commands are received. When a predetermined initialization condition, such as a backup abnormality or a setting change, is met, the command confirmation buffer is set to 0h, thereby transitioning to a state that allows both commands.

[0281] Here, commands have been described as an example of information sent and received between the main CPU 200a and the token CPU 204a, but the information is not limited to this and can include various contents such as data and signals.

[0282] (Anti-fraud signal) As described with reference to FIG. 31, when the communication permission flag is turned ON in the medal count control board 204, the medal CPU 204a establishes communication with the dedicated unit 350 and is able to send notifications (gaming machine information notification, counting notification, loan receipt result response). Then, if an abnormality is detected during game play, the medal CPU 204a transmits a predetermined signal or a specific signal to the dedicated unit 350. Here, a common signal for preventing fraud (fraud prevention signal) is used as the predetermined signal and specific signal transmitted to the dedicated unit 350. Specifically, the medal CPU 204a transmits the fraud prevention signal to the dedicated unit 350 via "Gaming Machine Fraud 1," "Gaming Machine Fraud 2," and "Gaming Machine Fraud 3" in the hall control / fraud monitoring information of the gaming machine information notification shown in FIG. 11. However, the predetermined signal and the specific signal do not necessarily have to be the same signal. Furthermore, various signals transmitted from the medal CPU 204a to the dedicated unit 350 can be used, not limited to fraud prevention signals. When the dedicated unit 350 receives such an anti-tamper signal, it transmits it to the hall computer.

[0283] For example, when a setting value confirmation process is performed, a setting confirmation signal is output as a fraud prevention signal in bit 1 of gaming machine fraud 1. Furthermore, when an abnormality is detected in the smart pachislot 100, a fraud detection signal 1, a fraud detection signal 2, and a fraud detection signal 3 are output as fraud prevention signals in bits 2 to 4 of gaming machine fraud 1. Furthermore, when the front lower door 106 is opened, a door open signal is output as a fraud prevention signal in bit 1 of gaming machine fraud 2. Such fraud prevention signals must be output continuously for at least three seconds. Here, an example will be described in which the medal CPU 204a outputs a fraud prevention signal to the dedicated unit 350 continuously for five seconds.

[0284] If an event occurs that interrupts the output of the anti-tamper signal, such as a power outage (power cut), while the anti-tamper signal is being output, the signal timing timer that has been timing five seconds can be reset, and the anti-tamper signal can be output again for five seconds after the interruption is resolved, such as after the power is restored. In this case, the total time that the anti-tamper signal is output will be more than five seconds, and the dedicated unit 350 will be able to reliably recognize the anti-tamper signal. Here, the signal timing timer is composed of a down counter and is used to count the predetermined time (here, five seconds) required to maintain the output of the anti-tamper signal.

[0285] However, depending on the timing of an abnormality in the smart pachislot 100, there may be insufficient time to output the fraud prevention signal. For example, suppose the power is turned on with the front lower door 106 open. In this case, the token CPU 204a attempts to continuously output a door open signal as a fraud prevention signal for bit 1 of gaming machine fraud 2 for five seconds immediately after power-on. However, as described above, after establishing communication with the main CPU 200a, the token CPU 204a receives a startup command from the main CPU 200a and confirms that the manufacturer code in the startup command is correct before transmitting a gaming machine information notification to the dedicated unit 350. In other words, even if the five-second timer starts immediately after power-on with the front lower door 106 open, the fraud prevention signal is not output to the dedicated unit 350 until the manufacturer code in the startup command is confirmed to be correct. This delays the start of the fraud prevention signal output, and insufficient time is secured for the fraud prevention signal output, making it difficult for the dedicated unit 350 to reliably recognize the fraud prevention signal.

[0286] Furthermore, although the medal count control board 204 can begin operating normally within, for example, one second after power is applied, the main control board 200 transmits information necessary for its own initialization process and the initialization process of the sub-control board 202, and so it takes time for the main control board 200 itself to begin functioning normally. Then, after the main CPU 200a begins functioning normally, it transmits a startup command to the medal CPU 204a. This could result in the medal CPU 204a taking five seconds or more (e.g., ten seconds) to confirm that the manufacturer code in the startup command is correct. In this case, with the front lower door 106 open, the medal CPU 204a will not be able to output a tamper-proof signal during the five seconds the signal timer is timing immediately after power is applied, and the dedicated unit 350 will not be able to recognize the tamper-proof signal.

[0287] Therefore, in this embodiment, transmission of the fraud prevention signal is started on the condition that the communication permission flag is ON.

[0288] Figure 34 is a flowchart showing the flow of the anti-tamper signal output process. The numerical values ​​of step S in this figure will be used only in the explanation of this figure. Here, it is assumed that the power is turned on with the front lower door 106 open.

[0289] After power-on, when it is recognized through the door switch (a switch that detects the opening of the lower front door 106) that the lower front door 106 is open, the medal CPU 204a sets a door open signal in bit 1 of gaming machine fraud 2 as an anti-fraud signal (S1). However, at this stage, the communication permission flag is OFF, so the anti-fraud signal is not output to the dedicated unit 350. In addition, the medal CPU 204a sets a count value corresponding to 5 seconds in the signal clock timer (S2). However, at this stage, the progress (counting) of the signal clock timer is limited (countdown is not performed). Note that when the door switch detects the opening of the lower front door 106, a signal to that effect may be acquired by both the main CPU 200a and the medal CPU 204a, or by either one of them. Therefore, the medal CPU 204a may indirectly recognize that the front lower door 106 is open through the main CPU 200a, or may directly recognize that the front lower door 106 is open through a signal from the door switch.

[0290] Then, the medal CPU 204a determines whether the communication permission flag is ON, i.e., after establishing communication with the main CPU 200a, receives a startup command from the main CPU 200a and determines whether the manufacturer code in the startup command is correct (S3). As a result, while the communication permission flag is OFF (NO in S3), the medal CPU 204a repeats the processing of step S3. For example, when the power is turned on, the main control board 200 transmits information necessary for initialization processing of the main control board 200 itself and initialization processing of the sub-control board 202, and then transmits the startup command (manufacturer code) to the medal CPU 204a. Therefore, during this time, the communication permission flag remains OFF, and no fraud prevention signal is output.

[0291] On the other hand, when the communication permission flag is turned ON (YES in S3), the medal CPU 204a establishes communication with the dedicated unit 350 and starts outputting an anti-fraud signal (door open signal) by transmitting a gaming machine information notification (S4). Furthermore, the medal CPU 204a starts the signal clock timer in response to the output of the anti-fraud signal (S5). Thus, while the signal clock timer is timing, the setting of the anti-fraud signal is maintained, and the output of the anti-fraud signal continues. Here, an example has been described in which the medal CPU 204a sets the door open signal in bit 1 of gaming machine fraud 2 as the anti-fraud signal and sets a count value in the signal clock timer. When the setting communication permission flag is turned ON, i.e., when the condition for starting the signal clock timer is satisfied, the signal clock timer starts counting and the anti-fraud signal is output. However, this is not limited to such a case. When the medal CPU 204a recognizes that the front lower door 106 is open, it sets a door open flag indicating that the door is open, and when the condition for starting the signal timing timer is met, at that timing, provided that the door open flag is set, it sets a door open signal in bit 1 of gaming machine fraud 2 as an anti-fraud signal, sets a count value in the signal timing timer, starts the signal timing timer, and outputs the anti-fraud signal.

[0292] Next, the medal CPU 204a determines whether the signal timing timer has timed out 5 seconds (S6). As a result, if 5 seconds have not been reached (NO in S6), the medal CPU 204a repeats the process of step S6. On the other hand, if 5 seconds have been timed out (YES in S6), the medal CPU 204a resets the fraud prevention signal, for example, the door open signal in bit 1 of gaming machine fraud 2 (S7). This ends the output of the fraud prevention signal. This fraud prevention signal output process may be performed within the use area of ​​the medal count control board 204, or, since this process is security-related, it may be performed in the non-use area. By performing the fraud prevention signal output process in the non-use area in this way, it is possible to make effective use of the use area.

[0293] In this way, the fraud prevention signal is generated, the medal CPU 204a starts communication with the main CPU 200a, the signal timer counts a predetermined time from the start of communication with the main CPU 200a (from the time the communication permission flag is turned ON), and while the predetermined time is counting, the fraud prevention signal is sent to the dedicated unit 350. As long as the dedicated unit 350 has already started up, the dedicated unit 350 can reliably receive the fraud prevention signal for the duration of the output. In this way, fraud in the smart pachislot 100 can be reliably prevented.

[0294] If a power outage occurs while the fraud prevention signal is being output, the medal CPU 204a may reset the signal timing timer that has been timing a predetermined time (for example, 5 seconds), and after confirming that the communication permission flag has been turned ON again, output the fraud prevention signal to the dedicated unit 350 for a predetermined time. Also, if it is possible to save the count value of the signal timing timer when a power outage occurs, the medal CPU 204a may save the count value of the signal timing timer at the time of the power outage, and after confirming that the communication permission flag has been turned ON when the power is turned on (when the power is restored after the power outage), restart timing from the saved count value of the signal timing timer and output the fraud prevention signal to the dedicated unit 350.

[0295] Also, here, an example has been described in which the medal CPU 204a sets a door open signal as an anti-fraud signal in bit 1 of gaming machine fraud 2 when it recognizes that the lower front door 106 is open, but this is not the only case. For example, in the setting change process, if a door is provided in a setting change device that accepts setting change operations by an administrator, the medal CPU 204a may recognize that the door provided in the setting change device is open and output a setting door open signal as an anti-fraud signal in bit 0 of gaming machine fraud 2. In that case, as described above, the medal CPU 204a may cause the signal timing timer to proceed after the communication permission flag is turned ON and communication between the medal CPU 204a and the dedicated unit 350 is established. Also, here, an example has been described in which a door switch is provided on the lower front door 106 and the medal CPU 204a recognizes through the door switch that the lower front door 106 is open, but this is not limiting; a door switch may be provided on the upper front door 104 and the medal CPU 204a may recognize through the door switch that the upper front door 104 is open, or door switches may be provided on both the upper front door 104 and the lower front door 106 and the medal CPU 204a may recognize through the door switch that both the upper front door 104 and the lower front door 106 are open. In this case, similar to the lower front door 106 described above, when the door switch detects that the upper front door 104 is open, a signal to that effect may be acquired by both the main CPU 200a and the medal CPU 204a, or by either one of them. Therefore, like the lower front door 106, the medal CPU 204a may recognize that the upper front door 104 is in an open state indirectly through the main CPU 200a, or may recognize that the upper front door 104 is in an open state directly through a signal from a door switch. Also, if the housing 102 is provided with a door other than the upper front door 104 or the lower front door 106, for example, a door with a projector, a door switch may be provided on such a door, and the medal CPU 204a may recognize that the door is in an open state through the door switch.

[0296] In addition, the example described here is one in which the medal CPU 204a ensures the duration of the anti-fraud signal output by running a signal timer after the communication permission flag is turned ON. However, this is not limited to this example. Alternatively, a signal timer may be provided in the main CPU 200a instead of the medal CPU 204a, and the main CPU 200a may ensure the duration of the anti-fraud signal output by running the signal timer after it becomes possible to send a startup command. Specifically, when it becomes possible to send a startup command or when it sends a startup command to the medal CPU 204a, the main CPU 200a starts outputting an anti-fraud signal (door open signal) and starts running the signal timer. Furthermore, the main CPU 200a ends output of the anti-fraud signal when the signal timer has timed out 5 seconds. At this time, the anti-fraud signal output process shown in FIG. 34 may be performed within the use area of ​​the main control board 200, or, since this process is security-related, may be performed in the non-use area. By performing the output process of the anti-tamper signal in the unused area in this way, it is possible to make effective use of the used area.

[0297] Also, while the medal CPU 204a has been described here as an example in which the signal timing timer advances after the communication permission flag is turned ON, this is not limiting. The signal timing timer may also advance after confirming that a medal can be inserted, as described below, or after confirming that the VL connection signal is ON, in addition to turning ON the communication permission flag. With this configuration, the medal CPU 204a can reliably ensure the duration of the anti-fraud signal output after successfully establishing communication with the main CPU 200a and the dedicated unit 350. In this way, the administrator can reliably prevent fraud.

[0298] In addition, in the above description, an example has been given in which the medal CPU 204a in the smart pachinko slot machine 100 generates an anti-fraud signal in response to detection of an abnormality, counts a predetermined time after starting communication with the main CPU 200a, and continuously transmits the anti-fraud signal to the dedicated unit 350 while the predetermined time is being counted. However, this is not limited to such a case. Alternatively, the frame CPU in the smart pachinko slot machine may generate an anti-fraud signal in response to detection of an abnormality, counts a predetermined time after starting communication with the main CPU, and continuously transmits the anti-fraud signal to the dedicated unit while the predetermined time is being counted. In addition, in the above description, an example has been given in which the main CPU 200a, instead of the medal CPU 204a, advances a signal timing timer after it becomes capable of transmitting a startup command, thereby ensuring the output duration of the anti-fraud signal. However, in the smart pachinko slot machine, the main CPU, instead of the frame CPU, advances a signal timing timer after it becomes capable of transmitting a startup command, thereby ensuring the output duration of the anti-fraud signal. The output processing of such anti-tampering signals may be performed within the use area of ​​the main control board of the smart pachinko machine, or may be performed in a non-use area.

[0299] In the above, an example has been described in which fraud prevention signals such as a setting confirmation signal, a fraud detection signal 1, a fraud detection signal 2, a fraud detection signal 3, and a door open signal are output to the dedicated unit 350 through "gaming machine fraud 1," "gaming machine fraud 2," and "gaming machine fraud 3" in the hall control fraud monitoring information of the gaming machine information notification shown in Fig. 11. However, the fraud prevention signals are not limited to such cases, and include, for example, a setting change signal and a gaming medal count clear detection, as shown in Fig. 11.

[0300] The setting change signal is assigned to bit 0 of "gaming machine fraud 1" in the hall control / fraud monitoring information of the gaming machine information notification, and is a signal output while the setting change process (under predetermined conditions) is being executed. When such a setting change signal is output to the dedicated unit 350, a security signal is also output to the dedicated unit 350.

[0301] The medal count clear detection is assigned to bit 3 of "Gaming Machine Fraud 2" in the hall computer fraud monitoring information of the gaming machine information notification. It is a signal output when the medal count held by the Smart Pachislot 100 is cleared to zero (under specified conditions). For example, if there are electronic medals remaining in the Smart Pachislot 100 as the medal count at the end of the hall's business hours or the beginning of the next day (including cases where the player left them unintentionally or intentionally), the hall staff will clear the medal count so that it becomes zero at the beginning of business hours. The occurrence of this medal count clear detection is stored in the hall computer, allowing the administrator to confirm whether or not the medal count was cleared and the time of clearing. Furthermore, the medal count clear detection output history can be used to prove whether or not the medal count was cleared.

[0302] When the dedicated unit 350 receives a setting change signal or a medal count clear detection, it transmits the signal to the hall computer. The hall computer receives the setting change signal or medal count clear detection, and while the signal continues to be output, it notifies the user that the setting change signal or medal count clear detection has been received, for example, by lighting the data lamp. To ensure the data lamp stays lit, the setting change signal continues to be output after the smart pachislot 100 is powered on until one regular game is completed, even if the setting change has already been completed. During this time, the data lamp remains lit. Furthermore, if the medal count clear detection is also configured to light the data lamp, the signal continues to be output until one regular game is completed on the smart pachislot 100, to ensure the data lamp stays lit. During this time, the data lamp remains lit. However, in this case, in order to stop the output of the setting change signal or the detection of the number of game medals cleared, the hall staff must play one game of the smart pachislot 100, which places a heavy workload on the staff to make a large number of smart pachislots 100 playable in a short period of time.

[0303] Therefore, here, the duration of the output of the setting change signal and the game medal count clear detection is not limited to the end of one game, but is limited to a predetermined time, just like the setting confirmation signal, fraud detection signal 1, fraud detection signal 2, fraud detection signal 3, door open signal, etc.

[0304] However, for fraud prevention signals such as the setting confirmation signal, fraud detection signal 1, fraud detection signal 2, fraud detection signal 3, and door open signal, the medal CPU 204a starts a five-second timer after the communication permission flag is turned ON. However, for the setting change signal and game medal count clear detection, the five-second timer starts when the communication permission flag is turned ON and game play is enabled, i.e., when the medal insertion state is enabled. The medal insertion state indicates a state in which electronic medals can be bet, and is entered when the VL connection signal indicating the connection state with the dedicated unit 350 is ON and there are no other errors. Therefore, the medal CPU 204a can indirectly determine that the VL connection signal is ON through the medal insertion state (playable state). The medal insertion state is managed by the main CPU 200a, and the medal CPU 204a can refer to the medal insertion state through commands transmitted from the main CPU 200a. The medal insertion state may also be managed by the medal CPU 204a. Here, by the medal CPU 204a understanding that the communication permission flag is ON and that medals can be inserted, it is possible to confirm not only that communication between the main CPU 200a and the medal CPU 204a has been established normally, but also that communication between the medal CPU 204a and the dedicated unit 350 has been established normally.

[0305] Figure 35 is a flowchart showing the process of outputting the fraud prevention signal. The numerical values ​​of step S in this figure are used only in the explanation of this figure. Here, it is assumed that the power is turned on with the number of game medals cleared.

[0306] After powering on, when the medal CPU 204a recognizes that a predetermined condition exists, i.e., that the number of game medals has been cleared, it sets the game medal count clear detection in bit 3 of gaming machine fraud 2 as an anti-fraud signal (S1). However, at this stage, the communication permission flag is OFF, so the anti-fraud signal is not output to the dedicated unit 350. In addition, the medal CPU 204a sets a count value corresponding to 5 seconds in the signal clock timer (S2). However, at this stage, the progress (time count) of the signal clock timer is limited (countdown is not performed).

[0307] The medal CPU 204a then determines whether the communication permission flag is ON and whether the medal insertion state is set (S3). As a result, while the communication permission flag is OFF or the medal insertion state is not set (NO in S3), the medal CPU 204a repeats the processing of step S3. For example, when the power is turned on, the main control board 200 performs initialization processing of the main control board 200 itself and the sub-control board 202, and then transmits a startup command (manufacturer code) to the medal CPU 204a. Also, since the VL connection signal is OFF immediately after the power is turned on, the medal insertion state is not set. Therefore, during this period, the fraud prevention signal is not output.

[0308] On the other hand, if the communication permission flag is ON and a medal insertion state is established (YES in S3), the medal CPU 204a establishes communication with the dedicated unit 350 and starts outputting an anti-fraud signal by transmitting a gaming machine information notification (S4). Furthermore, in response to the output of the anti-fraud signal, the medal CPU 204a starts the signal clock timer (S5). Thus, while the signal clock timer is timing, the setting of the anti-fraud signal is maintained, and the output of the anti-fraud signal continues. Here, an example was given in which the medal CPU 204a previously sets the anti-fraud signal to "game medal count clear detection" in bit 3 of gaming machine fraud 2 and sets a count value in the signal clock timer. When the communication permission flag is ON and a medal insertion state is established, i.e., when the start condition for the signal clock timer is satisfied, the signal clock timer starts counting and the anti-fraud signal is output. However, this is not limited to such a case. When the medal CPU 204a recognizes that the number of game medals has been cleared, it sets a medal count clear flag indicating that the number of game medals has been cleared, and when the condition for starting the signal clock timer is met, at that timing, provided that the medal count clear flag is set, it sets the game medal count clear detection in bit 3 of gaming machine fraud 2 as an anti-fraud signal, sets a count value in the signal clock timer, starts the signal clock timer, and outputs the anti-fraud signal.

[0309] Next, the medal CPU 204a determines whether the signal timing timer has timed 5 seconds (S6). As a result, if 5 seconds have not yet been reached (NO in S6), the medal CPU 204a repeats the processing of step S6. On the other hand, if 5 seconds have been timed (YES in S6), the medal CPU 204a resets the gaming medal count clear detection as an anti-fraud signal in bit 3 of gaming machine fraud 2 (S7). In this way, the output of the anti-fraud signal ends. This anti-fraud signal output processing may be performed within the use area of ​​the medal count control board 204, or, since this processing is security-related processing, it may be performed in an out-of-use area. By performing the anti-fraud signal output processing in the out-of-use area in this way, it is possible to make effective use of the use area.

[0310] In this way, the fraud prevention signal is generated, the token CPU 204a starts communication with the main CPU 200a, and after confirming connection with the dedicated unit 350 (a state in which tokens can be inserted), the signal timer counts a predetermined time, and while the predetermined time is counting, the fraud prevention signal is sent to the dedicated unit 350. This configuration makes it possible for the token CPU 204a to reliably ensure the duration of the output of the fraud prevention signal after successfully establishing communication with the main CPU 200a and the dedicated unit 350. In this way, fraud in the smart pachislot 100 can be reliably prevented.

[0311] Furthermore, by limiting the duration of the anti-fraud signal output to 5 seconds, the hall staff will no longer need to play the smart pachislot 100 once in order to stop the output of the setting change signal or the game medal count clear detection signal. This reduces the burden on the administrator who must make multiple smart pachislots 100 playable in a short period of time.

[0312] If the lower front door 106 is opened (an error occurs) while the fraud prevention signal is being output, and the machine is no longer in a state where medals can be inserted, the medal CPU 204a may reset the signal timing timer, which had been timing a predetermined time (for example, 5 seconds), and once again confirm that the communication permission flag is ON and that medals can be inserted, and then output a setting confirmation signal for the predetermined time. The medal CPU 204a may also save the count value of the signal timing timer at the time when the machine was no longer in a state where medals could be inserted, and when the power is turned on (when power is restored after a power outage), after confirming that the communication permission flag is ON and that medals can be inserted, resume timing from the saved count value of the signal timing timer and output the fraud prevention signal. In this way, it is possible to ensure that the fraud prevention signal continues to be output for at least the predetermined time. Also, here, an example has been described in which a door switch is provided on the lower front door 106 and the medal CPU 204a recognizes through the door switch that the lower front door 106 is open, but this is not limited to the above case. Alternatively, a door switch may be provided on the upper front door 104 and the medal CPU 204a may recognize through the door switch that the upper front door 104 is open, or door switches may be provided on both the upper front door 104 and the lower front door 106 and the medal CPU 204a may recognize through the door switch that both the upper front door 104 and the lower front door 106 are open. Furthermore, if the housing 102 is provided with a door other than the upper front door 104 and the lower front door 106, for example, a door with a projector, a door switch may be provided on such a door and the medal CPU 204a may recognize through the door switch that the door is open.

[0313] Furthermore, if a power outage (power cutoff) occurs while the fraud prevention signal is being output, the medal CPU 204a may reset the signal timing timer that has been timing a predetermined time (for example, 5 seconds), and after confirming that the communication permission flag has been turned ON again, output the fraud prevention signal to the dedicated unit 350 for a predetermined time. Furthermore, if the value of the signal timing timer can be saved in the event of a power outage, the medal CPU 204a may save the count value of the signal timing timer at the time of the power outage, and after confirming that the communication permission flag has been turned ON when the power is turned on (when the power is restored after the power outage), restart timing from the saved count value of the signal timing timer and output the fraud prevention signal to the dedicated unit 350.

[0314] Also, here, an example has been described in which the medal CPU 204a checks the medal insertion enabled state, which is a state in which play is possible, in order to check the connection with the dedicated unit 350. However, this is not the only case, and the medal CPU 204a may check the connection with the dedicated unit 350 by checking various information that is set on the condition that the VL connection signal is turned ON, or the VL connection signal itself.

[0315] In addition, the example described here is one in which the medal CPU 204a ensures the duration of the anti-fraud signal output by running the signal timer after confirming that the communication permission flag is ON and that medals can be inserted. However, this is not limiting. Alternatively, a signal timer may be provided in the main CPU 200a instead of the medal CPU 204a, and the main CPU 200a may ensure the duration of the anti-fraud signal output by running the signal timer after it becomes capable of sending a startup command and becomes capable of inserting medals. Specifically, when it becomes capable of sending a startup command or sends a startup command to the medal CPU 204a and becomes capable of inserting medals, the main CPU 200a starts outputting the anti-fraud signal (door open signal) and starts running the signal timer. Furthermore, the main CPU 200a stops outputting the anti-fraud signal when the signal timer reaches 5 seconds. 35 may be performed within the use area of ​​the main control board 200, or, since this is security-related processing, may be performed in the non-use area. By performing the output processing of the anti-tamper signal in the non-use area in this way, it becomes possible to make effective use of the use area.

[0316] Also, here we have given an example in which the medal CPU 204a starts the signal timing timer after confirming that the communication permission flag is ON and that a medal can be inserted, but this is not limited to this case, and the signal timing timer may also start when the communication permission flag is turned ON without confirming that a medal can be inserted.

[0317] Also, here we have given an example in which, in the smart pachislot 100, the medal CPU 204a generates an anti-fraud signal in response to detecting an abnormality, starts communication with the main CPU 200a, and after confirming connection with the dedicated unit 350, a predetermined time is counted, and the anti-fraud signal is continuously sent to the dedicated unit 350 while the predetermined time is being counted. However, this is not limited to such a case, and the frame CPU of the smart pachinko may also generate an anti-fraud signal in response to detecting an abnormality, start communication with the main CPU, and after confirming connection with the dedicated unit, a predetermined time is counted, and the anti-fraud signal is continuously sent to the dedicated unit while the predetermined time is being counted. Also, in the above example, in the smart pachislot 100, the main CPU 200a, instead of the medal CPU 204a, is able to send the startup command, and after the medal insertion state is reached, the signal timing timer is advanced to ensure the duration of the anti-fraud signal output. However, in the smart pachinko, the main CPU, instead of the frame CPU, is able to send the startup command, and after the medal insertion state is reached, the signal timing timer is advanced to ensure the duration of the anti-fraud signal output. Note that this type of anti-fraud signal output processing may be performed within the use area of ​​the main control board of the smart pachinko, or may be performed in an unused area.

[0318] (Monitoring illegal commands) Of the multiple types of commands (game medal insertion command, start lever press command, payout end command, one game end command, startup command, state transition command) sent from the main CPU 200a to the medal CPU 204a, some commands have a fixed transmission order (the order in which they should be received by the medal CPU 204a).

[0319] For example, a medal insertion command, a start lever press command, a payout end command, and a one-game end command are sequentially transmitted in response to a player's operations during one game. Specifically, when a player operates the bet switch 116 at the start of one game, the main CPU 200a transmits a medal insertion command to the medal CPU 204a. Next, when the player operates the start switch 118, the main CPU 200a transmits a start lever press command to the medal CPU 204a. Next, the rotation-controlled reels 110a, 110b, and 110c stop in response to the player's operation of the stop switches 120a, 120b, and 120c. When a winning decision is made, the main CPU 200a transmits a payout end command to the medal CPU 204a. Then, when the winning combination-related data is updated, the main CPU 200a transmits a one-game end command to the medal CPU 204a. In this manner, one game is completed.

[0320] However, betting can be performed by inserting electronic medals held in the medal holding unit through the operation of the bet switch 116, or by automatically inserting electronic medals based on the display of a replay combination on an active line. When an electronic medal is automatically inserted based on the display of a replay combination on an active line, the main CPU 200a does not transmit a game medal insertion command to the medal CPU 204a. Consequently, among the game medal insertion command, start lever press command, payout end command, and one game end command, the game medal insertion command is not necessarily transmitted from the main CPU 200a during one game. Therefore, the commands for which the transmission order of the main CPU 200a is fixed are the start lever press command, payout end command, and one game end command. The payout end command is transmitted even if the number of medals to be paid out is zero.

[0321] Here, the monitoring of command fraud targets three commands: a start lever press command, a payout end command, and a one-game end command, and determines whether the received commands are in a predetermined order. Specifically, when the medal CPU 204a receives one of the three commands (a limited number of commands), it determines whether the received command is a command that should have been received, and if it is different from the command that should have been received, it increments the error counter by 1. In this way, the medal CPU 204a counts the error counter when there is a risk of fraud, and when it reaches a predetermined value (e.g., 10), it determines that a communication error has occurred and notifies the communication error using a device such as the speaker 128. However, since communication errors are likely to occur during the initialization process for a predetermined period after power-on, updating of the error counter is prohibited to avoid unintended error notification.

[0322] Here, an example has been described in which the error counter is incremented by one when the order in which commands are received differs from the original order. However, the error counter is not limited to this case. For example, in addition to when the order in which commands are received differs from the original order, the error counter is incremented by one when the number of inserted coins is inconsistent, the number of payout coins is inconsistent, a command indicating that the reels 110 are spinning without a bet being placed is received, a command to insert a game medal is received after a start lever press command is received, a start lever press command is received again after a start lever press command is received, or the checksum in the command is abnormal. Here, the number of inserted coins is determined to be the total number of inserted coins included in the role ratio-related transmission information of the end-of-game command. The total number of inserted coins received in the previous game is stored, and if the result of adding the current number of inserted coins to the previous total number of inserted coins is equal to the current total number of inserted coins, it is determined to be consistent; if they differ, it is determined to be inconsistent. Similarly, the number of payout coins is determined by using the total payout coins included in the role ratio-related transmission information of the one game end command, and the total payout coins received in the previous game are stored, and if the result of adding the current payout coins to the previous total payout coins is equal to the current total payout coins, it is determined to be consistent, and if they are different, it is determined to be inconsistent. Also, in the case where a game medal insertion command is received after receiving a start lever press command, and in the case where a start lever press command is received again after receiving a start lever press command, when a start lever press command is received, information to that effect is stored, for example, by setting a flag, and when a payout end command is received, the information to the effect that a start lever press command has been received is cleared.In addition, if the order in which the commands are received differs from the original order, if the number of inserted coins is inconsistent, if the number of payout coins is inconsistent, if a command indicating that the reels 110 are spinning without a bet being placed is received, if a medal insertion command is received after a start lever press command is received, or if a start lever press command is received again after a start lever press command is received, the error counter is incremented, but the received command is considered valid and processing corresponding to that command is performed. On the other hand, if the checksum in the command is abnormal, the error counter is incremented and the received command is invalidated and discarded. Furthermore, if the error counter reaches a predetermined value, a communication error occurs, and the communication error is notified, the power must be turned back on to clear the error counter to resolve the communication error. The error counter may also be incremented if the number of inserted coins is outside a predetermined range (e.g., 1 to 3) or the number of payout coins is outside a predetermined range (e.g., 0 to 15). Also, here we have given an example in which the error counter is incremented when a game medal insertion command is received after receiving a start lever press command, and when a start lever press command is received again after receiving a start lever press command, but this is not limited to such cases. If a game medal insertion command is received after receiving a start lever press command, the medal CPU 204a may not process the game medal insertion command, and if a start lever press command is received again after receiving a start lever press command, the medal CPU 204a may not process the start lever press command received again.

[0323] 36 to 38 are flowcharts showing the flow of the command monitoring process. The command monitoring process is executed when the medal CPU 204a receives a command from the main CPU 200a. Note that FIG. 36 shows the case where a start lever press command is received, FIG. 37 shows the case where a payout end command is received, and FIG. 38 shows the case where a one game end command is received. Here, the process related to this embodiment will be explained, and processes unrelated to this embodiment will be omitted. The numerical values ​​of step S in these figures will be used only in the explanation of each figure.

[0324] As shown in Fig. 36, when a command is received from the main CPU 200a, the medal CPU 204a determines whether the received command is a start lever press command (S1). As a result, if the received command is not a start lever press command (NO in S1), the medal CPU 204a ends the command monitoring process for the start lever press command, and if it is a start lever press command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command (variable) is an identifier indicating a start lever press command (S2). Here, the next command is a variable (memory area) for holding the identifier of the command to be received next out of the three commands, the start lever press command, the payout end command, and the one game end command. As a result, if the identifier held in the next command is not an identifier indicating a start lever press command, i.e., if it is an identifier indicating a payout end command or an identifier indicating a one-game end command (NO in S2), the medal CPU 204a determines that the order in which the commands were received is different from the original order and increments the error counter by 1 (S3). If the identifier held in the next command is an identifier indicating a start lever press command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets the identifier indicating the payout end command as the command to be received next after the start lever press command (S4). Here, regardless of whether the received start lever press command is the command that should have been received originally, the medal CPU 204a sets the payout end command as the command to be received next after the start lever press command.

[0325] In this way, when a start lever press command is received, it is determined whether the identifier stored in the next command is an identifier indicating a start lever press command. Also, as will be described later, an identifier indicating a start lever press command is set in the next command when a one-game end command is received. In other words, when a start lever press command is received, the medal CPU 204a determines whether the previously received command is a one-game end command out of the three restricted commands, the start lever press command, the payout end command, and the one-game end command.

[0326] As shown in FIG. 37, when a command is received from the main CPU 200a, the medal CPU 204a determines whether the received command is a payout end command (S1). If the received command is not a payout end command (NO in S1), the medal CPU 204a terminates the command monitoring process for the payout end command. If the received command is a payout end command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command is an identifier indicating a payout end command (S2). If the identifier held in the next command is not an identifier indicating a payout end command, that is, an identifier indicating a one-game end command or an identifier indicating a start lever press command (NO in S2), the medal CPU 204a determines that the order in which the commands were received is different from the original order, and increments the error counter by 1 (S3). If the identifier held in the next command is an identifier indicating a payout end command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets an identifier indicating a one game end command as the command to be received next after the payout end command in the next command (S4). Here, regardless of whether the received payout end command is a command that should have been received originally, the one game end command is set as the command to be received next after the payout end command.

[0327] 38, when a command is received from the main CPU 200a, the medal CPU 204a determines whether the received command is a one-game end command (S1). If the received command is not a one-game end command (NO in S1), the medal CPU 204a terminates the command monitoring process for the one-game end command. If the received command is a one-game end command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command is an identifier indicating a one-game end command (S2). If the identifier held in the next command is not an identifier indicating a one-game end command, that is, if the identifier is an identifier indicating a start lever press command or an identifier indicating a payout end command (NO in S2), the medal CPU 204a determines that the order in which the commands were received is different from the original order, and increments the error counter by 1 (S3). If the identifier held in the next command is an identifier indicating a one game end command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets an identifier indicating a start lever press command as the command to be received next after the one game end command (S4). Here, regardless of whether the received one game end command is a command that should have been received, the start lever press command is set as the command to be received next after the one game end command.

[0328] In this way, when the medal CPU 204a receives a predetermined command from among the start lever press command, the payout end command, and the one game end command, it determines whether the identifier held in the next command is equal to the identifier indicating the received command. In other words, when the medal CPU 204a receives a predetermined command from among the start lever press command, the payout end command, and the one game end command, it determines whether the previously received command is the one game end command, the start lever press command, or the payout end command, respectively.

[0329] As described above, if a digital medal is automatically inserted based on the display of a replay combination on an active line at the start of a game, the main CPU 200a does not transmit a medal insertion command to the medal CPU 204a. In this case, the order of receiving the commands is "payout end command" → "one game end command" → "start lever press command," and the order of receiving the commands is maintained. However, if the player operates the bet switch 116 at the start of a game, the medal CPU 204a will receive the "game medal insertion command" between the "one game end command" and the "start lever press command," which could lead to the medal CPU 204a determining that the order of receiving the commands is incorrect.

[0330] Here, as explained using Figures 36 to 38, the objects for monitoring the order of reception are limited to three commands: a start lever press command, a payout end command, and a one-game end command. For example, suppose that a player operates the bet switch 116 at the start of one game, causing the medal CPU 204a to receive commands in the following order: "one-game end command" → "game medal insertion command" → "start lever press command." In this case, upon receiving the one-game end command, the medal CPU 204a sets, as the next command, an identifier indicating the start lever press command, which is the command to be received after the one-game end command, as shown in Figure 38. Next, the medal CPU 204a receives the game medal insertion command, but because the received game medal insertion command is not one of the three commands, a start lever press command, a payout end command, or a one-game end command, it does not determine or update the next command. Next, upon receiving the start lever press command, the medal CPU 204a determines whether the identifier held in the next command is an identifier indicating a start lever press command, as shown in FIG. 36. Since the next command holds an identifier indicating a start lever press command, the error counter is not updated. Therefore, no problem occurs even if the medal CPU 204a receives a "game medal insertion command" between the "one game end command" and the "start lever press command."

[0331] As described above, the main CPU 200a transmits the game medal insertion command, start lever press command, payout end command, one game end command, and startup command to the medal CPU 204a within the main loop, and transmits the state transition command within the timer interrupt to the medal CPU 204a. In this case, the medal CPU 204a receives the state transition command at the timing of the timer interrupt between the above three start lever press command, payout end command, and one game end command, and there is a risk that the medal CPU 204a will determine that the order of receiving the commands is incorrect.

[0332] Even in such a case, the command monitoring process only targets three commands: the start lever press command, the payout end command, and the one-game end command. Therefore, even if a state transition command is received between the start lever press command, the payout end command, and the one-game end command, the main CPU 200a does not execute the command monitoring process itself. In this way, the medal CPU 204a does not target commands other than the start lever press command, the payout end command, and the one-game end command in the command monitoring process, and only determines the order in which these three commands are received. Therefore, even if the medal CPU 204a receives a state transition command at the timing of a timer interrupt between the start lever press command, the payout end command, and the one-game end command, the error counter will not be updated.

[0333] This command monitoring process makes it possible to properly identify an error even if the command is tampered with through fraudulent activity, such as inserting an illegal board between the main control board 200 and the medal count control board 204.

[0334] Here, the medal CPU 204a receives a start lever press command, a payout end command, or a one-game end command as the second command, and determines whether the identifier stored in the next command is an identifier indicating the start lever press command, the payout end command, or the one-game end command, respectively. That is, whether the previously received command is a one-game end command, a start lever press command, or a payout end command as the first command. However, the commands to be determined are not limited to this case. It is sufficient if there are at least two commands whose reception order is predetermined, and the medal CPU 204a determines whether the first command and the second command are received in the predetermined reception order. In this case, the medal CPU 204a may determine that the received command among the limited number of commands is the first command when the medal CPU 204a receives the second command.

[0335] In addition to the command monitoring process described above, the medal CPU 204a also manages timeouts to confirm whether command transmission from the main CPU 200a to the medal CPU 204a is being performed stably. Specifically, the main CPU 200a transmits a transmission confirmation command at the timing of a timer interrupt (e.g., every 1.49 msec). The transmission confirmation command does not include an identifier or a checksum, and is, for example, a command configured with a one-byte fixed value "AAh" in which 1s and 0s are alternately arranged bit by bit. By periodically receiving such transmission confirmation commands, the medal CPU 204a confirms that command transmission is being performed stably. If the medal CPU 204a does not receive a transmission confirmation command that it should have received within a predetermined timeout (e.g., 100 msec), it clears information in the medal RAM 204c, such as a pointer, that is used when receiving each command, such as a game medal insertion command, a start lever press command, a payout end command, or a game end command. Here, since the transmission confirmation command is sent and received frequently, the information in the medal RAM 204c is simply cleared to take into consideration the effects of noise, etc. However, if a transmission confirmation command that should have been received is not received within a specified timeout, the error counter may be incremented by 1.

[0336] However, depending on the command, the time it takes to complete transmission of a single command may be longer than the timer interrupt period (e.g., 1.49 msec). For example, a single game end command or startup command may take more than 4 msec to complete transmission. In this case, the single game end command or startup command may collide with the transmission confirmation command.

[0337] Here, as will be described later, the main CPU 200a temporarily stores each command in the transmission FIFO 380 for serial transmission. Data is transmitted from the transmission FIFO 380 only at transmission-enabled timings (e.g., at 80 μsec intervals), but the main CPU 200a can set each command in the transmission FIFO 380 at once. In addition, the main CPU 200a inhibits timer interrupts while setting a one-game end command or a startup command in the transmission FIFO 380. With this configuration, the timing at which the main CPU 200a sets a one-game end command or a startup command in the transmission FIFO 380 does not overlap with the timing at which the main CPU 200a sets a transmission confirmation command in the transmission FIFO 380. Therefore, there is no collision between the one-game end command or the startup command and the transmission confirmation command.

[0338] However, if a transmission confirmation command is set after a game end command or a startup command is set, the transmission confirmation command will be output from the transmission FIFO 380 after the game end command or startup command. In this case, depending on the setting timing of the transmission FIFO 380, the transmission confirmation command will overlap after the game end command or startup command in the transmission FIFO 380, resulting in two or more transmission confirmation commands being output consecutively. In this case, the medal CPU 204a receives the transmission confirmation commands consecutively. However, even in such a case, the reception interval of the transmission confirmation commands averages the timer interrupt period, so the error counter is not updated.

[0339] By managing the timeout using such a transmission confirmation command, it is possible to properly identify an error even if the command is tampered with through fraudulent activity, such as inserting an illegal board between the main control board 200 and the medal count control board 204, or entering an illegal command by some means.

[0340] Here, the medal CPU 204a manages the timeout using a transmission confirmation command, but this is not limited to this case. Both the main CPU 200a and the medal CPU 204a may periodically output a transmission confirmation command, and the main CPU 200a may also manage the timeout using a transmission confirmation command (mutual management).

[0341] Furthermore, the means for checking whether command transmission from the main CPU 200a to the medal CPU 204a is being carried out stably is not limited to timeout management using a transmission confirmation command. For example, a command permission signal may be provided as a connection confirmation signal, and when either the main CPU 200a or the medal CPU 204a has turned the command permission signal OFF to prohibit command transmission, the other may clear information in the medal RAM 204c used when receiving each command, such as a pointer, if the other has sent a command while either the main CPU 200a or the medal CPU 204a has turned the command permission signal OFF to prohibit command transmission. Furthermore, when either the main CPU 200a or the medal CPU 204a has turned the command permission signal OFF to prohibit command transmission, the error counter may be updated, as with the transmission confirmation command.

[0342] Also, here, an example has been described in which a command is sent from the main CPU 200a as the first control unit to the medal CPU 204a as the second control unit in the smart pachislot 100. However, this is not limited to such a case, and the present invention can be applied to serial communication between various independent CPUs as the first control unit and the second control unit, for example, when sending and receiving commands between other boards within the smart pachislot 100.

[0343] Also, here, assuming that when a digitalized medal is automatically inserted based on the display of a replay role on an active line, the main CPU 200a does not transmit a gaming medal insertion command to the medal CPU 204a, three commands have been described as commands for which the transmission order of the main CPU 200a is fixed: a start lever press command, a payout end command, and a one-game end command. However, this is not limited to such a case; even when a digitalized medal is automatically inserted based on the display of a replay role on an active line, the main CPU 200a may transmit a gaming medal insertion command to the medal CPU 204a. In this case, the commands for which the transmission order of the main CPU 200a is fixed are four commands: a gaming medal insertion command, a start lever press command, a payout end command, and a one-game end command. In this case, when the main CPU 200a receives any of the four commands, namely, the game medal insertion command, the start lever press command, the payout end command, and the one game end command, it determines whether the received command is the command that should have been received, and if it is different from the command that should have been received, it increments the error counter by one.

[0344] Furthermore, the explanation here assumes that the payout end command is sent even when the payout number is zero, and lists three commands for which the main CPU 200a has a fixed transmission order: the start lever press command, the payout end command, and the one-game end command. However, this is not limited to this case. When the payout number is zero, the main CPU 200a may not send the payout end command to the medal CPU 204a. In this case, the commands for which the main CPU 200a has a fixed transmission order are the start lever press command and the one-game end command. In this case, when the main CPU 200a receives either the start lever press command or the one-game end command, it determines whether the received command is the command that should have been received, and if it is different from the command that should have been received, it increments the error counter by one. Furthermore, the main CPU 200a may not send a payout end command to the medal CPU 204a when the payout number is 0, and may send a medal insertion command to the medal CPU 204a when an electronic medal is automatically inserted based on the display of a replay role on an active line. In this case, the commands for which the main CPU 200a has a set transmission order are the medal insertion command, the start lever press command, and the one-game end command. In this case, when the main CPU 200a receives one of the three commands, the medal insertion command, the start lever press command, or the one-game end command, it determines whether the received command is the command it should have received, and if it is different from the command it should have received, it increments the error counter by one.

[0345] (Connection confirmation by VL connection signal) As described above, when checking the connection between the smart pachislot 100 and the dedicated unit 350, if the VL connection signal is ON, the smart pachislot 100 continues playing the game and accepts counting processing while play is possible. On the other hand, if the VL connection signal is OFF, the smart pachislot 100 executes game stop processing and restricts (prohibits) all of the following: betting electronic medals, operating the settlement switch 121, processing for game progress based on operating the start switch 118, and the counting processing described above. This is because an OFF VL connection signal can be determined to mean that the smart pachislot 100 is not properly connected to the dedicated unit 350, or that the power to the dedicated unit 350 is OFF.

[0346] However, even if the VL connection signal is ON—that is, even if the smart pachislot 100 and the dedicated unit 350 are properly connected and the dedicated unit 350 is recognized as powered ON—it may be better not to immediately execute the counting process. For example, when the VL connection signal is ON, communication between the main control board 200 and the medal count control board 204 is not established, or the communication connection is established but then disconnected. In this case, the counting process cannot be executed normally. Therefore, even if the smart pachislot 100 accepts operation of the counting switch 112 and transmits information to the dedicated unit 350, the counted medal count may be lost. Therefore, in a modified example of this embodiment, not only the VL connection signal but also the establishment status of communication between the main control board 200 and the medal count control board 204 is determined, and a decision is made as to whether to execute a game stop process. If communication is not established, a game stop process is executed, restricting game progress. Here, we have given an example of performing game stop processing in both cases where communication between the main control board 200 and the medal count control board 204 is not established when the VL connection signal is ON, and where communication is once established but then disconnected. However, this is not limited to such cases; game stop processing is performed when communication between the main control board 200 and the medal count control board 204 is not established when the VL connection signal is ON, but if communication is once established but then disconnected, the game stop processing may only restrict processing for game progress based on betting electronic medals, operation of the settlement switch 121, and operation of the start switch 118, and counting processing may remain possible.

[0347] 39 is a flowchart showing the communication specifications when the power is turned on. The numerical values ​​of step S in this figure will be used only in the explanation of this figure. For example, when the power is turned on to the smart pachislot 100, the main CPU 200a of the main control board 200 sends and receives predetermined commands (start-up command, reply command) to and from the medal CPU 204a of the medal count control board 204, and determines whether communication has been established.

[0348] First, the main CPU 200a sets its own register (S1), checks the backup from the previous power outage (S2), and transitions to a signal waiting state. In this waiting state, the main CPU 200a checks whether the power outage warning signal, which indicates that a power outage will occur after a predetermined time, is OFF and whether the command permission signal received from the medal count control board 204 is ON (S3). If the power outage warning signal is ON or the command permission signal is OFF (NO in S3), the main CPU 200a maintains the waiting state.

[0349] In parallel with this, the medal CPU 204a sets its own registers (S4), checks the backup from the previous power outage (S5), executes the startup initialization process (S6), and transitions to a startup command waiting state. In this startup command waiting state, the medal CPU 204a checks whether a startup command has been received (S7). If a startup command has been received (YES in S7), it checks whether the startup command is normal (S8). If a startup command has not been received (NO in S7) or if the startup command is abnormal (NO in S8), it maintains the startup command waiting state. Note that the startup command and reply command are composed of a serial signal consisting of a start bit, one byte (8 bits) of information indicating the command type, a stop bit, and a parity bit. Therefore, the medal CPU 204a determines that the startup command is normal if the command type indicates a startup command and the parity bit is normal.

[0350] If the power interruption warning signal is OFF and the command permission signal is ON (YES in S3), the main CPU 200a transmits a startup command to the medal CPU 204a (S9). Then, the main CPU 200a sets a communication timer (S10) and transitions to a state waiting for a reply command. In this state waiting for a reply command, the main CPU 200a checks whether a reply command has been received (S11). If a reply command has been received (YES in S11), the main CPU 200a checks whether the reply command is normal (S12). If a reply command has not been received (NO in S11) or if the reply command is abnormal (NO in S12), the main CPU 200a maintains the state waiting for a reply command. Note that the main CPU 200a determines that the reply command is normal if the command type indicates a reply command and the parity bit is normal.

[0351] ...

Claims

1. A gaming machine that can be connected to a specific unit that lends gaming value, a first control means for controlling the progress of a game; A second control means for managing game values ​​provided for games; A guide area between the outer rail and the inner rail, which guides the launched game ball to the game area; a ball return prevention mechanism that prevents the game ball from returning from the game area to the guide area; Equipped with The first control means restricting the progress of a game in the gaming machine when the connection state with the second control means is not connected; the information notified to the specific unit includes first information, second information, and third information; a priority level to be notified to the specific unit when notification timings of the first information, the second information, and the third information overlap is set in advance for the first information, the second information, and the third information; a relationship of priority among the first information, the second information, and the third information differs between a case where a predetermined condition is satisfied and a case where a predetermined condition is not satisfied; the ball return prevention mechanism has a displacement member that is displaceable between a first state, a second state, and a third state; the displacement member has a side surface portion facing the outer rail and a tip portion on a tip side of the side surface portion, The distance from the tip end to the outer rail is set to a specific distance, A game ball guided from the guide area to the game area is defined as a first game ball, If the game ball returning from the game area to the guide area is a second game ball, the first state is a state in which the specific distance is shorter than that in the second state, the second state is a state in which the specific distance is longer than that in the first state, The third state is a state of a gaming machine in which the first gaming ball is in contact with the side portion, the outer rail, and the second gaming ball, and the second gaming ball is in contact with the tip portion, the outer rail, and the first gaming ball, so that the specific distance is longer than in the first state and shorter than in the second state, and shorter than the distance from the lowest point of the second gaming ball to the outer rail.

2. A gaming machine that can be connected to a specific unit that lends gaming value, a first control means for controlling the progress of a game; A second control means for managing game values ​​provided for games; a substrate case that accommodates the substrate and has a first through hole; a cover member that covers at least a portion of the substrate case and has a second through hole formed therein; Equipped with The first control means restricting the progress of a game in the gaming machine when the connection state with the second control means is not connected; the information notified to the specific unit includes first information, second information, and third information; a priority level to be notified to the specific unit when notification timings of the first information, the second information, and the third information overlap is set in advance for the first information, the second information, and the third information; a relationship of priority among the first information, the second information, and the third information differs between a case where a predetermined condition is satisfied and a case where a predetermined condition is not satisfied; any type of screw among screws used in the gaming machine and provided above the first through hole cannot pass through the first through hole; the second through hole is capable of receiving at least one type of screw among screws used in the gaming machine and provided above the first through hole; the inside and outside of the board case are in communication with each other through the first through hole, and the first through hole functions as a heat dissipation hole; a space inside the cover member and a space outside the gaming machine are communicated with each other through the second through hole, and the second through hole functions as a heat dissipation hole; A gaming machine in which gaming balls cannot pass through the first through hole and the second through hole.

3. A gaming machine that can be connected to a specific unit that lends gaming value, a first control means for controlling the progress of a game; A second control means for managing game values ​​provided for games; a substrate on which predetermined electronic components are mounted; a substrate case that accommodates the substrate; Equipped with The first control means restricting the progress of a game in the gaming machine when the connection state with the second control means is not connected; the information notified to the specific unit includes first information, second information, and third information; a priority level to be notified to the specific unit when notification timings of the first information, the second information, and the third information overlap is set in advance for the first information, the second information, and the third information; a relationship of priority among the first information, the second information, and the third information differs between a case where a predetermined condition is satisfied and a case where a predetermined condition is not satisfied; An explosion-proof valve is formed on the top surface of the electronic component, a separation distance between the top surface of the electronic component and the top surface of the board case is longer than a distance from an outer periphery to a center of the top surface of the electronic component; a through hole is provided in a portion of the top surface of the board case that faces the top surface of the electronic component, The separation distance is longer than the length of a threaded portion of a screw that is used in the gaming machine and can be inserted into the through hole, A gaming machine in which the explosion-proof valve is visible from outside the circuit board case.

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