Display device

Abstract

To provide a display device capable of improving display quality.SOLUTION: A display device according to an embodiment includes a first substrate and a second substrate overlapping with the first substrate, a liquid crystal layer positioned between the first substrate and the second substrate and including a polymer dispersed liquid crystal, and a light-emitting element. The first substrate includes a first transparent substrate, a scan line, a signal line intersecting with the scan line, a switching element electrically connected to the scan line and the signal line, an organic insulating film overlapping with the scan line, the signal line, and the switching element and having an opening part, a pixel electrode overlapping with the opening part and electrically connected to the switching element, and a first orientation film overlapping with the organic insulating film and in contact with the liquid crystal layer. The second substrate includes a second transparent substrate and a second orientation film overlapping with the second transparent substrate and in contact with the liquid crystal layer. At least a part of a portion of the first orientation film that overlaps with the organic insulating film is in contact with the second orientation film.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] In recent years, display devices have been proposed that include a display panel having a polymer dispersed liquid crystal (PDLC) layer, a light source, etc. The polymer dispersed liquid crystal layer can be switched between a transparent state in which light is transmitted and a scattering state in which light is scattered, depending on the application of a voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153665 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of improving display quality. [Means for solving the problem]

[0005] A display device according to one embodiment includes a first substrate, a second substrate overlapping the first substrate, a liquid crystal layer between the first substrate and the second substrate, the liquid crystal layer including a polymer dispersed liquid crystal, and a light emitting element. The first substrate includes a first transparent substrate, scanning lines, signal lines intersecting the scanning lines, switching elements electrically connected to the scanning lines and the signal lines, an organic insulating film overlapping the scanning lines, the signal lines, and the switching elements and having an opening, a pixel electrode overlapping the opening and electrically connected to the switching elements, and a first alignment film overlapping the organic insulating film and in contact with the liquid crystal layer. The second substrate includes a second transparent substrate and a second alignment film overlapping the second transparent substrate and in contact with the liquid crystal layer. At least a part of the portion of the first alignment film overlapping the organic insulating film is in contact with the second alignment film. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view illustrating an example of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing the area near the light emitting module. [Diagram 3] FIG. 3 is a schematic plan view showing an example of a pixel. [Figure 4] FIG. 4 is a schematic plan view showing an example of a pixel electrode arranged in the pixel shown in FIG. [Diagram 5] FIG. 5 is a schematic plan view showing an example of a first substrate including the switching element shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an example of the first substrate taken along the line VI-VI shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an example of the first substrate taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an example of a display panel taken along line VIII-VIII shown in FIG. [Figure 9]FIG. 9 is a schematic cross-sectional view showing an example of a display panel taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a schematic plan view showing a region where the alignment film of the first substrate is in contact with the alignment film of the second substrate. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an example of a display panel included in a display device according to a comparative example. [Figure 12] FIG. 12 is a schematic cross-sectional view showing an example of a display panel included in a display device according to a comparative example. [Figure 13] FIG. 13 is a schematic cross-sectional view of a display panel according to the second embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of a display device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. Note that the disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0008] In this embodiment, a liquid crystal display device (so-called transparent display device) with high light transmission properties that uses a polymer dispersed liquid crystal is disclosed as an example of a display device. However, the configuration disclosed in this embodiment can also be applied to other types of display devices.

[0009] [First embodiment] Fig. 1 is a schematic plan view showing an example of a display device DSP according to this embodiment. In each figure including Fig. 1, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are shown to facilitate understanding as necessary. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z.

[0010] The first direction X, the second direction Y, and the third direction Z are mutually orthogonal, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In this embodiment, viewing the XY plane defined by the first direction X and the second direction Y is referred to as planar view.

[0011] The display device DSP includes a display panel PNL, a plurality of wiring boards 1, a plurality of IC chips 2, and a light emitting module 100.

[0012] 1, the display panel PNL has a rectangular shape that is elongated in the first direction X. The display panel PNL may have a rectangular shape that is elongated in the second direction Y, a square shape, or another polygonal shape, or another shape such as a circle or an ellipse.

[0013] The display panel PNL includes a first substrate SUB1, a second substrate SUB2 overlapping the first substrate SUB1, a liquid crystal layer LC including polymer dispersed liquid crystal, and a seal SE. The first substrate SUB1 and the second substrate SUB2 are formed in a flat plate shape along the XY plane.

[0014] The first substrate SUB1 and the second substrate SUB2 overlap in the third direction Z. The area where the first substrate SUB1 and the second substrate SUB2 overlap includes a display area DA in which an image is displayed.

[0015] The first substrate SUB1 includes a first transparent substrate 10. The first transparent substrate 10 has side surfaces 101 and 102 aligned along a first direction X, and side surfaces 103 and 104 aligned along a second direction Y. The side surfaces 101 and 102 are aligned in this order in the second direction Y. The side surfaces 103 and 104 are aligned in this order in the first direction X.

[0016] The second substrate SUB2 includes a second transparent substrate 20. The second transparent substrate 20 has side surfaces 201 and 202 along the first direction X and side surfaces 203 and 204 along the second direction Y.

[0017] The side surfaces 101, 102 and the side surfaces 201, 202 are side surfaces along the longer sides of the display panel PNL, and the side surfaces 103, 104 and the side surfaces 203, 204 are side surfaces along the shorter sides of the display panel PNL.

[0018] In the example shown in FIG. 1, side surface 102 overlaps side surface 202, side surface 103 overlaps side surface 203, and side surface 104 overlaps side surface 204, but these do not necessarily have to overlap.

[0019] The width of the first substrate SUB1 in the second direction Y is greater than the width of the second substrate SUB2 in the second direction Y. In other words, the side surface 201 does not overlap the side surface 101. The side surface 201 is located between the side surface 101 and the display area DA in the second direction Y.

[0020] The first substrate SUB1 has an extension portion Ex located between the side surface 101 and the side surface 201. The extension portion Ex corresponds to a portion of the first substrate SUB1 that extends in the direction opposite to the second direction Y from a portion that overlaps with the second substrate SUB2.

[0021] The wiring boards 1 and the IC chips 2 are mounted on the extending portion Ex. The wiring boards 1 are, for example, bendable flexible printed circuit boards. The IC chips 2 each have, for example, a built-in display driver that outputs signals required for image display. The IC chips 2 may be mounted on the wiring board 1.

[0022] 1, the multiple wiring boards 1 are arranged at intervals in the first direction X with respect to the display panel PNL. Note that the multiple wiring boards 1 may be a single wiring board extending in the first direction X.

[0023] 1, the multiple IC chips 2 are arranged at intervals in the first direction X with respect to the display panel PNL. Note that the multiple IC chips 2 may be a single IC chip extending in the first direction X.

[0024] The light emitting module 100 will be described in detail later, but the light emitting module 100 is disposed along the side surface 201 of the second transparent substrate 20. The light emitting module 100 overlaps the extension portion Ex in a plan view.

[0025] The seal SE bonds the first substrate SUB1 and the second substrate SUB2. The seal SE is formed in a frame shape. The seal SE surrounds the liquid crystal layer LC between the first substrate SUB1 and the second substrate SUB2.

[0026] The liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2. Such a liquid crystal layer LC is disposed across the area surrounded by the seal SE (including the display area DA) in a plan view.

[0027] 1, the liquid crystal layer LC is made of a polymer-dispersed liquid crystal including a polymer 31 and liquid crystal molecules 32. In one example, the polymer 31 is a liquid crystal polymer. The polymer 31 is formed in stripes extending along the first direction X and aligned in the second direction Y.

[0028] The liquid crystal molecules 32 are dispersed in the gaps between the polymer 31 and are oriented such that their major axes are aligned along the first direction X. Each of the polymer 31 and the liquid crystal molecules 32 has optical anisotropy or refractive index anisotropy. The responsiveness of the polymer 31 to an electric field is lower than the responsiveness of the liquid crystal molecules 32 to an electric field.

[0029] In one example, the alignment direction of the polymer 31 hardly changes regardless of the presence or absence of an electric field, whereas the alignment direction of the liquid crystal molecules 32 changes in response to the electric field when a high voltage equal to or higher than a threshold voltage is applied to the liquid crystal layer LC.

[0030] When no voltage is applied to the liquid crystal layer LC (initial orientation state), the optical axes of the polymer 31 and the liquid crystal molecules 32 are approximately parallel to each other, and light incident on the liquid crystal layer LC is transmitted through the liquid crystal layer LC with almost no scattering within the liquid crystal layer LC (transparent state).

[0031] When a voltage is applied to the liquid crystal layer LC, the orientation direction of the liquid crystal molecules 32 changes, and the optical axes of the polymer 31 and the liquid crystal molecules 32 cross each other. Therefore, light incident on the liquid crystal layer LC is scattered within the liquid crystal layer LC (scattered state). In other words, the liquid crystal layer LC can be switched between a transparent state and a scattering state depending on the voltage applied.

[0032] 2 is a schematic plan view showing an area near the light emitting module 100. The light emitting module 100 includes a plurality of light emitting elements 110 and a light guide 120. The plurality of light emitting elements 110 are aligned in a first direction X. The light guide 120 has a rod shape extending in the first direction X. The light guide 120 is located between the seal SE and the light emitting elements 110.

[0033] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. These pixels PX are indicated by dotted lines in the figure. Each of the pixels PX includes a pixel electrode PE, which is indicated by a solid-line square in the figure.

[0034] 2, each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and a capacitance CS. The switching element SW is formed of, for example, a thin film transistor (TFT), and is electrically connected to a scanning line G and a signal line S.

[0035] The scanning line G is electrically connected to the switching element SW in each of the pixels PX aligned in the first direction X. The signal line S is electrically connected to the switching element SW in each of the pixels PX aligned in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW.

[0036] The common electrode CE and the power supply line CL are disposed across the display area DA and its peripheral area. A predetermined voltage Vcom is applied to the common electrode CE. For example, a voltage having the same potential as that of the common electrode CE is applied to the power supply line CL.

[0037] Each of the pixel electrodes PE faces the common electrode CE in the third direction Z. In the display area DA, the liquid crystal layer LC (particularly, the liquid crystal molecules 32) is driven by an electric field generated between the pixel electrodes PE and the common electrode CE. A capacitance CS is formed, for example, between the power supply line CL and the pixel electrode PE.

[0038] Fig. 3 is a schematic plan view showing an example of a pixel PX. Fig. 3 shows a part of the configuration included in the first substrate SUB1. The first substrate SUB1 includes a plurality of scanning lines G, a plurality of signal lines S, a switching element SW, an insulating film IL, a power supply line CL, a metal line ML, and a connection electrode CN1.

[0039] The multiple scanning lines G each extend in a first direction X. The multiple signal lines S each extend in a second direction Y and intersect with the multiple scanning lines G. In this specification, a pixel PX corresponds to a region defined by two scanning lines G adjacent to each other in the second direction Y and two signal lines S adjacent to each other in the first direction X. The switching element SW is disposed near a portion where the scanning line G and the signal line S intersect.

[0040] The insulating film IL is formed in a lattice shape in each pixel PX. The insulating film IL overlaps the scanning lines G, the signal lines S, and the switching elements SW. The insulating film IL has an opening OP. In other words, the insulating film IL is formed in a bathtub shape.

[0041] The switching element SW includes a drain electrode DE extending into the opening OP. The connection electrode CN1 is formed in an island shape and is located in the opening OP. The connection electrode CN1 is electrically connected to one end of the drain electrode DE.

[0042] The power supply lines CL are disposed on the insulating film IL and are formed in a lattice shape surrounding the pixels PX. The power supply lines CL have a planar shape substantially equal to that of the insulating film IL. The power supply lines CL are spaced apart from the connection electrodes CN1.

[0043] The metal lines ML are disposed on the power supply lines CL and are formed in a lattice shape surrounding the pixels PX. The metal lines ML are formed, for example, to have a width smaller than that of the power supply lines CL and do not protrude from the power supply lines CL in a plan view. The power supply lines CL and the metal lines ML overlap the scanning lines G, the signal lines S, and the switching elements SW, respectively.

[0044] Fig. 4 is a schematic plan view showing an example of a pixel electrode PE arranged in the pixel PX shown in Fig. 3. The pixel electrode PE indicated by the dashed dotted line overlaps with the opening OP (shown in Fig. 3) of the insulating film IL.

[0045] The pixel electrode PE overlaps the connection electrode CN1 at the opening OP. An insulating film is interposed between the pixel electrode PE and the connection electrode CN1. A contact hole CH1 is formed in the insulating film. The pixel electrode PE contacts the connection electrode CN1 at the contact hole CH1. This allows the pixel electrode PE to be electrically connected to the switching element SW.

[0046] In Fig. 4, the light-shielding layer BM of the second substrate SUB2 is further indicated by dotted lines. The light-shielding layer BM is formed in a lattice shape. In a plan view, the light-shielding layer BM overlaps the power supply line CL, the switching element SW, a part of the connection electrode CN1, and the like. The light-shielding layer BM also overlaps the scanning line G, the signal line S, and the metal line ML shown in Fig. 3.

[0047] The light-shielding layer BM is formed to be larger than the scanning lines G, the signal lines S, and the switching elements SW in a plan view. In other words, the scanning lines G, the signal lines S, and the switching elements SW do not have any portions that protrude beyond the light-shielding layer BM in a plan view. The light-shielding layer BM has an opening AP that overlaps with the pixel electrode PE in a plan view.

[0048] Fig. 5 is a schematic plan view showing an example of the first substrate SUB1 including the switching element SW shown in Fig. 4. The switching element SW includes a semiconductor SC, a gate electrode GE integrated with the scanning line G, a source electrode SO integrated with the signal line S, a drain electrode DE, and an auxiliary gate electrode AG.

[0049] The semiconductor SC is, for example, an oxide semiconductor. The semiconductor SC may be a silicon-based semiconductor such as polycrystalline silicon or amorphous silicon. In the example shown in FIG 5, the auxiliary gate electrode AG overlaps the gate electrode GE and the semiconductor SC.

[0050] The semiconductor SC is located between the gate electrode GE and the auxiliary gate electrode AG. The auxiliary gate electrode AG further overlaps the scanning line G. A connection electrode CN2 is interposed between the scanning line G and the auxiliary gate electrode AG.

[0051] An insulating film is interposed between the scanning line G and the connection electrode CN2. A contact hole CH21 is formed in the insulating film. The connection electrode CN2 is in contact with the scanning line G at the contact hole CH21.

[0052] An insulating film is interposed between the connection electrode CN2 and the assist gate electrode AG. A contact hole CH22 is formed in the insulating film. The assist gate electrode AG is in contact with the connection electrode CN2 through the contact hole CH22.

[0053] As a result, the assist gate electrode AG, like the gate electrode GE, is electrically connected to the scanning line G. That is, the gate electrode GE and the assist gate electrode AG have the same potential as the scanning line G.

[0054] The source electrode SO and the drain electrode DE each extend along the second direction Y and are arranged at intervals in the first direction X. The source electrode SO is in contact with one end side of the semiconductor SC. The drain electrode DE is in contact with the other end side of the semiconductor SC.

[0055] One end of the drain electrode DE overlaps with the connection electrode CN3. An insulating film is interposed between the drain electrode DE and the connection electrode CN3. A contact hole CH3 is formed in the insulating film. The drain electrode DE contacts the connection electrode CN3 at the contact hole CH3.

[0056] The connection electrode CN1 indicated by the dashed line is in contact with the connection electrode CN3. This electrically connects the connection electrode CN1 to the switching element SW. The connection electrode CN1 is electrically connected to the pixel electrode PE shown in FIG. 4 through the contact hole CH1.

[0057] A power supply line CL indicated by a dashed line overlaps the gate electrode GE and the auxiliary gate electrode AG of the switching element SW. A metal line ML indicated by a dashed line overlaps the power supply line CL and also overlaps a part of the switching element SW.

[0058] Fig. 6 is a schematic cross-sectional view showing an example of the first substrate SUB1 along the line VI-VI shown in Fig. 5. The first substrate SUB1 includes a first transparent substrate 10, insulating films 11, 12, and 13, an insulating film IL, a switching element SW, a power supply line CL, a metal line ML, a pixel electrode PE, and an alignment film AL1 (first alignment film).

[0059] A gate electrode GE, which is integral with the scanning line G, is disposed on a first transparent substrate 10. An insulating film 11 covers the first transparent substrate 10 and the gate electrode GE. A semiconductor SC is disposed on the insulating film 11 and is located directly above the gate electrode GE.

[0060] A source electrode SO integral with the signal line S is disposed on the insulating film 11 and in contact with the semiconductor SC. A drain electrode DE is disposed on the insulating film 11 and in contact with the semiconductor SC.

[0061] The source electrode SO and the drain electrode DE are formed of, for example, the same metal material. The insulating film 12 covers the insulating film 11, the source electrode SO, and the drain electrode DE. The insulating film 12 is in contact with the semiconductor SC between the source electrode SO and the drain electrode DE.

[0062] The auxiliary gate electrode AG is disposed on the insulating film 12 and is located directly above the gate electrode GE and the semiconductor SC. The connection electrode CN3 is disposed on the insulating film 12. The connection electrode CN3 is in contact with the drain electrode DE through a contact hole CH3 formed in the insulating film 12.

[0063] The auxiliary gate electrode AG and the connection electrode CN3 are formed of, for example, the same metal material. The insulating film IL covers the auxiliary gate electrode AG. The connection electrode CN3 is located in the opening OP and is exposed from the insulating film IL.

[0064] The power supply line CL is disposed on the insulating film IL. The connection electrode CN1 is spaced apart from the power supply line CL. The connection electrode CN1 is disposed on the insulating film 12 in an opening OP of the insulating film IL.

[0065] The power supply line CL and the connection electrode CN1 are located substantially in the same layer and are formed collectively using the same material. The connection electrode CN1 is disposed on the connection electrode CN3.

[0066] The metal line ML is disposed on the power supply line CL. The power supply line CL, the metal line ML, and the connection electrode CN1 are covered with an insulating film 13. The insulating film 13 functions as a protective film that protects the power supply line CL, the metal line ML, and the connection electrode CN1.

[0067] The pixel electrode PE is disposed on the insulating film 13. The pixel electrode PE overlaps the opening OP. The pixel electrode PE is in contact with the connection electrode CN1 through a contact hole CH1 formed in the insulating film 13.

[0068] The alignment film AL1 covers the pixel electrode PE and the insulating film 13. A part of the insulating film 13 is located between the insulating film IL and the alignment film AL1. From another point of view, the alignment film AL1 overlaps the insulating film IL.

[0069] The insulating films 11, 12, and 13 are transparent inorganic insulating films such as silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating film IL is a transparent organic insulating film such as acrylic resin, etc. The power supply line CL, the connection electrode CN1, and the pixel electrode PE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0070] Fig. 7 is a schematic cross-sectional view showing an example of the first substrate SUB1 taken along line VII-VII shown in Fig. 5. The connection electrode CN2 is disposed on the insulating film 11. The connection electrode CN2 is in contact with the scanning line G through a contact hole CH21 formed in the insulating film 11.

[0071] The connection electrode CN2 is formed of, for example, the same metal material as the source electrode SO and the drain electrode DE. The insulating film 12 covers the insulating film 11, the connection electrode CN2, the source electrode SO, and the drain electrode DE. The auxiliary gate electrode AG is in contact with the connection electrode CN2 through a contact hole CH22 formed in the insulating film 12.

[0072] Fig. 8 is a schematic cross-sectional view showing an example of the display panel PNL along the line VIII-VIII shown in Fig. 5. Fig. 9 is a schematic cross-sectional view showing an example of the display panel PNL along the line IX-IX shown in Fig. 5. As shown in Fig. 8, the switching element SW is covered with an insulating film IL which is an organic insulating film. As shown in Fig. 9, the insulating film IL overlaps the scanning line G. Although Fig. 9 shows a cross section along the second direction Y including the scanning line G, a cross section along the first direction X including the signal line S is configured in the same manner.

[0073] 8 and 9, the second substrate SUB2 includes a second transparent substrate 20, a light-shielding layer BM, a common electrode CE, and an alignment film AL2 (second alignment film). The common electrode CE is a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The light-shielding layer BM is made of, for example, a metal material.

[0074] In relation to the first substrate SUB1, the light-shielding layer BM faces the switching elements SW etc. The light-shielding layer BM is located directly above the scanning lines G and signal lines S, and directly above the switching elements SW.

[0075] The light-shielding layer BM is located between the second transparent substrate 20 and the alignment film AL2. The common electrode CE is disposed across the pixels PX and covers the light-shielding layer BM. The common electrode CE is located between the light-shielding layer BM and the alignment film AL2.

[0076] The common electrode CE faces the pixel electrode PE across the liquid crystal layer LC at the opening OP. The common electrode CE is in contact with the light-shielding layer BM and is therefore electrically connected to the light-shielding layer BM. This reduces the resistance of the common electrode CE.

[0077] The alignment film AL2 covers the common electrode CE. In relation to the second transparent substrate 20, the alignment film AL2 overlaps the second transparent substrate 20. The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2.

[0078] The alignment films AL1 and AL2 are in contact with the liquid crystal layer LC, as shown in Figures 8 and 9. A transparent insulating film may be interposed between the light-shielding layer BM and the common electrode CE, or between the common electrode CE and the alignment film AL2.

[0079] As described above, the insulating film IL has a bathtub shape. The insulating film IL has an upper surface 51 facing the second substrate SUB2 and a plurality of side surfaces 52 connected to the upper surface 51, as shown in Fig. 8 and Fig. 9.

[0080] The side surfaces 52 define an opening OP. For example, the side surfaces 52 shown in Fig. 8 extend along the second direction Y, and the side surfaces 52 shown in Fig. 9 extend along the first direction X.

[0081] The insulating film 13 overlaps the upper surface 51 and the side surface 52. Specifically, the insulating film 13 faces the upper surface 51 with the power supply line CL and the metal wire ML interposed therebetween, and is in contact with the side surface 52.

[0082] The power supply line CL is located between the upper surface 51 and the insulating film 13. Specifically, the power supply line CL, which is a transparent electrode, is in contact with the upper surface 51 of the insulating film IL. The metal line ML is located between the power supply line CL and the insulating film 13 and is in contact with the insulating film 13. The metal line ML is electrically connected to the power supply line CL. Although not shown, a part of the power supply line CL is formed on the side surface 52, and the pixel electrode PE (a side portion 62 described later) and the power supply line CL overlap on the side surface 52 to form a capacitance CS shown in FIG. 2.

[0083] The pixel electrode PE is provided in the opening OP, and a part of it is provided along the side surface 52. Specifically, the pixel electrode PE has a main portion 61 and a side portion 62. The side portion 62 is formed integrally with the main portion 61. The main portion 61 is located in the opening OP. The side portion 62 faces the side surface 52 with the insulating film 13 interposed therebetween.

[0084] The side portion 62 has a tip portion 63. The tip portion 63 is spaced apart from the alignment film AL2, as shown in Figures 8 and 9. In other words, the tip portion 63 is not in contact with the alignment film AL2.

[0085] The tip portion 63 does not overlap the power supply line CL in the third direction Z. The tip portion 63 is located, for example, in the vicinity of the upper end of the side surface 52, but may be located in the vicinity of the lower end of the side surface 52 or in the vicinity of the center of the side surface 52.

[0086] At least a part of the portion of the alignment film AL1 that overlaps with the insulating film IL is in contact with the alignment film AL2. Since the alignment film AL1 is in contact with the alignment film AL2 in this manner, it is possible to suppress the formation of a gap where the liquid crystal layer LC is located above the upper surface 51 of the insulating film IL.

[0087] By forming the insulating film IL so that the alignment film AL1 is in contact with the alignment film AL2, a predetermined cell gap CG is formed between the first substrate SUB1 and the second substrate SUB2.

[0088] The cell gap CG corresponds to the distance from the alignment film AL1 to the alignment film AL2 at the opening OP along the third direction Z. The cell gap CG is, for example, about 1 μm to 4 μm.

[0089] The height H1 of the insulating film IL is approximately equal to the size of the cell gap. In one example, the height H1 is about 1 μm to 4 μm. The height H1 of the insulating film IL is set according to a desired cell gap CG.

[0090] Fig. 10 is a schematic plan view showing a region where the alignment film AL1 of the first substrate SUB1 contacts the alignment film AL2 of the second substrate SUB2. In Fig. 10, the portion of the alignment film AL1 that contacts the alignment film AL2 is indicated by a dashed line.

[0091] 10, the alignment film AL1 includes a first region A1, a second region A2, and a third region A3. The first region A1 includes a region overlapping with the scanning line G and extends along the first direction X. The second region A2 includes a region overlapping with the signal line S and extends along the second direction Y. The third region A3 is a region overlapping with the switching element SW.

[0092] The alignment film AL1 is in contact with the alignment film AL2 in, for example, the first region A1, the second region A2, and the third region A3. In other words, the alignment film AL1 is in contact with the alignment film AL2 in a lattice pattern.

[0093] The alignment film AL1 does not have to be in contact with the alignment film AL2 in each of the first region A1, the second region A2, and the third region A3. The alignment film AL1 may be in contact with the alignment film AL2 in any one or two of the first region A1, the second region A2, and the third region A3.

[0094] A width W1 of the first region A1 along the second direction Y is greater than, for example, a width WG of the scanning line G along the second direction Y. A width W2 of the second region A2 along the first direction X is greater than, for example, a width WS of the signal line S along the first direction X. These widths W1 and W2 may be greater than, for example, the widths of the power supply line CL and the metal line ML. The widths W1 and W2 may be smaller than, for example, the width of the light-shielding layer BM.

[0095] The display device DSP configured as above can improve the display quality. Specifically, in the display device DSP, at least a part of the portion of the alignment film AL1 that overlaps with the insulating film IL, which is an organic insulating film, is in contact with the alignment film AL2. This can suppress the formation of a gap where the liquid crystal layer LC is located above the upper surface 51 of the insulating film IL.

[0096] 11 and 12 are schematic cross-sectional views showing an example of a display panel PNL10 included in a display device DSP10 according to a comparative example. As shown in FIG. 11, the display panel PNL10 includes a spacer SP in the vicinity of the switching element SW.

[0097] The insulating film IL10 is an element corresponding to the insulating film IL in this embodiment. The spacer SP is located between the insulating film IL10 and the light-shielding layer BM. The spacer SP is provided under the common electrode CE and in contact with the alignment film AL1.

[0098] In the display panel PNL10, a cell gap CG is formed mainly by the spacers SP. The alignment film AL1 overlapping the insulating film IL10 is not in contact with the alignment film AL2, as shown in FIGS.

[0099] The height H2 of the insulating film IL10 in the comparative example is smaller than the height H1 of the insulating film IL in this embodiment. In other words, a gap 70 is formed above the insulating film IL10 as shown in FIGS.

[0100] The height H70 of the gap 70 is, for example, about 1.0 μm or more (in one example, about 1.0 μm to 1.5 μm). In the gap 70, a liquid crystal layer LC is positioned as shown in FIGS.

[0101] Here, it is assumed that in the manufacturing process of the display device DSP10, light L10 (e.g., UV) is irradiated from below the first transparent substrate 10 to form a polymer of the liquid crystal layer LC. A material that forms the liquid crystal layer LC (hereinafter, referred to as the "liquid crystal material") is positioned in the gap 70.

[0102] The gap 70 overlaps the scanning lines G and signal lines S made of a metal material in the third direction Z. This causes the irradiated light to not sufficiently reach the liquid crystal material overlapping the scanning lines G and signal lines S. As a result, an abnormality may occur in the portion of the liquid crystal layer LC located at the gap 70. The abnormality may be, for example, a defective alignment of liquid crystal molecules.

[0103] This may cause the light emitted from the light emitting module 100 to be unintentionally scattered in the portion. For example, as shown in Fig. 12, unevenness occurs due to scattering of light in the liquid crystal layer LC located in the gap 70. Such unevenness reduces the display quality of the display device DSP10.

[0104] In the display device DSP according to the present embodiment, the formation of gaps is suppressed in the portions overlapping the scanning lines G and the signal lines S. By suppressing the formation of gaps where the liquid crystal material is located, the liquid crystal material that is not hit by the irradiated light is less likely to occur in the manufacturing process, and the occurrence of abnormalities in the liquid crystal layer LC is suppressed. This makes it possible to suppress unintentional scattering of the light irradiated from the light emitting module 100 in the portions, thereby improving the display quality.

[0105] In this embodiment, since the cell gap CG is mainly formed by the insulating film IL, the display panel PNL does not have a spacer SP (shown in FIG. 11). Therefore, in the manufacturing process of the display device DSP, it is not necessary to provide a process for forming the spacer SP. In the display device DSP, the manufacturing process can be simplified compared to the display device DSP10 according to the comparative example. This makes it possible to reduce the cost of manufacturing the display device DSP.

[0106] In this embodiment, the alignment film AL1 is in contact with the alignment film AL2 in the first region A1, the second region A2, and the third region A3, thereby suppressing the formation of gaps in the portions between the alignment film AL1 and the alignment film AL2 that overlap the scanning lines G, the signal lines S, and the switching elements SW.

[0107] As a result, in the display device DSP, unintentional scattering of irradiated light can be suppressed, and thus display quality can be further improved. In the manufacturing process, the liquid crystal material located in the opening OP is disposed in each pixel PX by, for example, a drip method (ODF method).

[0108] The widths W1, W2 of the first region A1 and the second region A2 are larger than the widths WG, WS of the scanning lines G and the signal lines S, respectively, thereby suppressing the formation of gaps in the portions overlapping the scanning lines G and the signal lines S. This ensures that light is applied to the liquid crystal material in the manufacturing process, making it more difficult for abnormalities to occur in the liquid crystal layer LC.

[0109] As described above, according to this embodiment, it is possible to provide a display device DSP that is capable of improving display quality.

[0110] Next, other embodiments will be described. In the other embodiments described below, the same components as those in the first embodiment described above are given the same reference numerals as those in the first embodiment, and detailed descriptions thereof may be omitted or simplified.

[0111] [Second embodiment] 13 is a schematic cross-sectional view of a display panel PNL according to this embodiment. This embodiment differs from the first embodiment in that the first substrate SUB1 does not include the power supply lines CL and the metal lines ML.

[0112] The upper surface 51 of the insulating film IL, the insulating film 13, and the alignment film AL1 are stacked in this order in the third direction. The upper surface 51 of the insulating film IL is in contact with the insulating film 13 as shown in Fig. 13. The configuration of this embodiment can also provide the same effects as those of the first embodiment.

[0113] [Third embodiment] Next, another configuration example of the display device DSP will be described. Fig. 14 is a schematic cross-sectional view of the display device DSP according to this embodiment. Note that, regarding the display panel PNL, only the main parts are illustrated in a simplified manner.

[0114] The display panel PNL further includes a third transparent substrate 30. A major surface 30A of the third transparent substrate 30 faces the major surface 20B of the second transparent substrate 20 in the third direction Z.

[0115] The adhesive layer AD bonds the second transparent substrate 20 and the third transparent substrate 30. The third transparent substrate 30 is, for example, a glass substrate, but may be an insulating substrate such as a plastic substrate. The third transparent substrate 30 has a refractive index equivalent to that of the first transparent substrate 10 and the second transparent substrate 20. The adhesive layer AD has a refractive index equivalent to that of each of the second transparent substrate 20 and the third transparent substrate 30.

[0116] A side surface 301 of the third transparent substrate 30 is located directly above a side surface 201 of the second transparent substrate 20. The light emitting element 110 of the light emitting module 100 is electrically connected to the wiring substrate F. The light emitting element 110 is provided between the first substrate SUB1 and the wiring substrate F in the third direction Z.

[0117] The light guide 120 is provided in the second direction Y between the light emitting element 110 and the side surface 201 and between the light emitting element 110 and the side surface 301. The light guide 120 is adhered to the wiring substrate F by an adhesive layer AD1 and is adhered to the first substrate SUB1 by an adhesive layer AD2.

[0118] Next, the light L1 emitted from the light emitting element 110 will be described. The light emitting element 110 emits light L1 toward the light guide 120. The light L1 emitted from the light emitting element 110 propagates along the second direction Y, passes through the light guide 120, enters the second transparent substrate 20 from a side surface 201, and enters the third transparent substrate 30 from a side surface 301.

[0119] The light L1 incident on the second transparent substrate 20 and the third transparent substrate 30 propagates through the display panel PNL while being repeatedly reflected. The light L1 incident on the liquid crystal layer LC to which no voltage is applied passes through the liquid crystal layer LC with almost no scattering. The light L1 incident on the liquid crystal layer LC to which a voltage is applied is scattered by the liquid crystal layer LC. This scattered light SL is emitted from the display panel PNL and is visually recognized by the user as a display image.

[0120] Such a display device DSP can be observed from the main surface 10A side of the first transparent substrate 10, and can also be observed from the main surface 30B side of the third transparent substrate 30. Whether the display device DSP is observed from the main surface 10A side or from the main surface 30B side, the background of the display device DSP can be observed through the display device DSP.

[0121] The display panel PNL in the first embodiment or the display panel PNL in the second embodiment can be applied to the display device DSP according to this embodiment.

[0122] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.

[0123] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of each of the above-mentioned embodiments, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0124] Furthermore, with regard to other effects and advantages brought about by the aspects described in each of the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately conceived by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0125] 10...first transparent substrate, 11, 12, 13...insulating film, 20...second transparent substrate, 51...top surface, 52...side surface, 61...main portion, 62...side portion, 63...tip portion, 100...light-emitting module, 110...light-emitting element, 120...light-guiding body, A1...first region, A2...second region, A3...third region, AL1, AL2...alignment film, BM...light-shielding layer, CE...common electrode, CL...power supply line, DSP...display device, G...scanning line, IL...insulating film, LC...liquid crystal layer, ML...metal line, OP...opening, PE...pixel electrode, PNL...display panel, PX...pixel, S...signal line, SUB1...first substrate, SUB2...second substrate, SW...switching element.

Claims

1. A first substrate; a second substrate overlying the first substrate; a liquid crystal layer located between the first substrate and the second substrate, the liquid crystal layer including a polymer dispersed liquid crystal; A light emitting element, the first substrate comprises a first transparent substrate, scanning lines, signal lines intersecting the scanning lines, switching elements electrically connected to the scanning lines and the signal lines, an organic insulating film overlapping the scanning lines, the signal lines, and the switching elements and having an opening, a pixel electrode overlapping the opening and electrically connected to the switching elements, and a first alignment film overlapping the organic insulating film and in contact with the liquid crystal layer; the second substrate includes a second transparent substrate and a second alignment film overlapping the second transparent substrate and in contact with the liquid crystal layer; At least a part of the first alignment film that overlaps the organic insulating film is in contact with the second alignment film. Display device.

2. the first substrate further includes an inorganic insulating film located between the organic insulating film and the first alignment film, the organic insulating film has an upper surface facing the second substrate and a side surface connected to the upper surface and defining the opening, The inorganic insulating film overlaps the upper surface and the side surface. The display device according to claim 1 .

3. the first substrate further includes a power supply line located between the upper surface and the inorganic insulating film, and a metal line located between the power supply line and the inorganic insulating film and electrically connected to the power supply line; The display device according to claim 2 .

4. The pixel electrode has a side portion facing the side surface with the inorganic insulating film interposed therebetween. The display device according to claim 2 or 3.

5. The side portion has a tip portion spaced apart from the second alignment film. The display device according to claim 4.

6. the second substrate is located between the second transparent substrate and the second alignment film, and further includes a light-shielding layer overlapping the scanning lines, the signal lines, and the switching elements; The display device according to claim 1 .

7. the second substrate is located between the light-shielding layer and the second alignment film, and further includes a common electrode electrically connected to the light-shielding layer; The display device according to claim 6.

8. the first alignment film is in contact with the second alignment film in any one of a first region overlapping the scanning lines, a second region overlapping the signal lines, and a third region overlapping the switching elements; The display device according to claim 1 .

9. the first alignment film is in contact with the second alignment film in the first region, the second region, and the third region; The display device according to claim 8.

Images