Semiconductor memory device and method of manufacturing semiconductor memory device

The semiconductor memory device addresses positional deviations by incorporating a pillar with an electrically conductive channel layer and a step feature, ensuring continuous channel layers and improved performance.

JP2025039025APending Publication Date: 2025-03-21KIOXIA CORP
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Patent Information

Application Number
JP2023145759
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-09-08
Publication Date
2025-03-21

AI Technical Summary

Technical Problem

In semiconductor memory devices, positional deviations between the pillars penetrating the stacked body and the source line can lead to discontinuous channel layers, affecting device performance.

Method used

The semiconductor memory device includes a pillar with a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer, with the channel layer being electrically conductive on its side surfaces and having a cross-sectional area larger than the height of the third semiconductor layer, featuring a step at the interface between the first and third semiconductor layers.

Benefits of technology

This configuration suppresses the influence of positional deviations, ensuring continuous and effective channel layers, thereby enhancing the electrical characteristics and data erasing performance of the memory cells.

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Abstract

To suppress the effects of positional deviation between a portion of pillars penetrating a stacked body and a portion in a source line.SOLUTION: A semiconductor memory device according to an embodiment includes: a first semiconductor layer; a second semiconductor layer provided above the first semiconductor layer; a third semiconductor layer interposed between the first and second semiconductor layers; a stacked body which is provided above the second semiconductor layer and in which a plurality of conductive layers are stacked one by one while being separated from each other; and a pillar including a channel layer which extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body and reaches a predetermined depth of the first semiconductor layer. The channel layer is electrically connected to the third semiconductor layer on a side surface. The pillar has a cross-sectional area as viewed from the stacking direction which is larger at a height position of the first semiconductor layer than at a height position of the third semiconductor layer, and has a stepped portion at a height position of an interface between the first semiconductor layer and the third semiconductor layer.SELECTED DRAWING: Figure 2
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