Electric optical device and electronic device

Abstract

To achieve low power consumption while suppressing reduction in display quality caused by charges remaining at a drain node of a transistor for driving an OLED.SOLUTION: A pixel circuit 110 provided corresponding to a scan line 12 and a data line 14 has a transistor 121 and an OLED 130. The transistor 121 supplies current corresponding to voltage between a gate node and a source node to the OLED 130 during a light emission period (E), sets the data line 14 at potential Vini during an initialization period (A), sets the gate node of the transistor 121 at threshold equivalent potential during a compensation period (B), sets the gate node of the transistor 121 from the threshold equivalent potential to potential corresponding to the luminance of the OLED 130 during a writing period (C), and sets a drain node of the transistor 121 at potential equal to or more than the potential Vini to less than potential VBk during a drain set period (D).SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diode (hereinafter referred to as "OLED") elements have been proposed. In the electro-optical device, pixel circuits including the light-emitting elements and transistors that supply current to drive the light-emitting elements are provided in correspondence with the pixels of an image to be displayed, at intersections between scanning lines and data lines.

[0003] When an electro-optical device is miniaturized, a parasitic capacitance occurs in each part of the electro-optical device. If a parasitic capacitance occurs in the drain node of a transistor that drives a light-emitting element, the charge remaining in the parasitic capacitance flows to the light-emitting element, causing a decrease in display quality. Therefore, a technology has been proposed in which a reset potential is supplied to the drain node of the transistor via a data line before a current is supplied to the light-emitting element to cause it to emit light (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2023-50791 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, as with the technology described in Patent Document 1, when a reset potential is supplied to the drain node of a transistor via a data line, the potential amplitude of the data line becomes large, and it is not possible to reduce power consumption by charging and discharging the parasitic capacitance of the data line. Therefore, an object of the present invention is to provide a technology that achieves low power consumption while suppressing degradation of display quality caused by electric charges remaining in the drain node of a transistor that drives a light-emitting element. [Means for solving the problem]

[0006] In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a pixel circuit provided corresponding to a scanning line and a data line, the pixel circuit having a first transistor and a light-emitting element, the first transistor supplies a current to the light-emitting element corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor during an emission period, the data line is set to a first potential during an initialization period prior to the emission period, the gate node of the first transistor is set to a second potential corresponding to a threshold voltage of the first transistor during a compensation period after the initialization period and before the emission period, the gate node of the first transistor is set from the second potential to a third potential corresponding to the luminance of the light-emitting element during a first period after the compensation period and before the emission period, and the drain node of the first transistor is set to a fourth potential equal to or greater than the first potential and less than the third potential during a second period after the first period and before the emission period. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view of an electro-optical device according to a first embodiment. [Diagram 2] 1 is a block diagram showing an electrical configuration of an electro-optical device according to a first embodiment. [Diagram 3] FIG. 2 is a diagram showing a pixel circuit of the electro-optical device according to the first embodiment. [Figure 4] 4 is a timing chart showing the operation of the electro-optical device according to the first embodiment. [Diagram 5] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 6]5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 7] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 8] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 9] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 10] FIG. 4 is a diagram showing a potential range in a writing period in the first embodiment. [Figure 11] 5A and 5B are diagrams illustrating potential changes at various parts of the electro-optical device according to the first embodiment. [Figure 12] FIG. 11 is a block diagram showing an electrical configuration of an electro-optical device according to a second embodiment. [Figure 13] 10 is a timing chart showing the operation of the electro-optical device according to the second embodiment. [Figure 14] FIG. 11 is a block diagram showing an electrical configuration of an electro-optical device according to a third embodiment. [Figure 15] FIG. 13 is a diagram showing a pixel circuit of an electro-optical device according to a fourth embodiment. [Figure 16] 13 is a timing chart showing the operation of the electro-optical device according to the fourth embodiment. [Figure 17] FIG. 13 is a diagram showing a pixel circuit of an electro-optical device according to a fifth embodiment. [Figure 18] FIG. 13 is a diagram showing a pixel circuit of an electro-optical device according to a sixth embodiment. [Figure 19] 13 is a timing chart showing the operation of the electro-optical devices according to the fifth and sixth embodiments. [Figure 20] 10 is a timing chart showing the operation of an electro-optical device according to a modified example. [Figure 21] FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. [Figure 22] FIG. 2 is a diagram showing an optical configuration of a head mounted display. [Diagram 23] 10 is a timing chart showing the operation of an electro-optical device according to a comparative example. [Figure 24] 10A and 10B are diagrams illustrating the operation of an electro-optical device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, electro-optical devices according to embodiments will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are attached, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] First Embodiment FIG. 1 is a perspective view showing an electro-optical device 10 according to a first embodiment. The electro-optical device 10 is a micro display panel that displays an image in, for example, a head mounted display. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit for driving the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0011] In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of the light emitted from the OLED.

[0012] 2 is a block diagram showing the electrical configuration of the electro-optical device 10 according to the first embodiment. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an auxiliary circuit 60, n capacitive elements 70, an initialization circuit 80, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are provided along the X direction in the drawing, and n columns of data lines 14 are provided along the Y direction so as to be electrically insulated from each of the scanning lines 12. Here, m and n are integers of 2 or more.

[0013] In the display region 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure. An integer i between 1 and m is used to generally describe the scan lines 12. An integer j between 1 and n is used to generally describe the data lines 14.

[0014] The control circuit 30 controls each unit based on video data Vid and a synchronous signal Sync supplied from a host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, in 8 bits. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0015] In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one. The brightness characteristic indicated by the grayscale level in the video data Vid supplied from the host device does not necessarily match the luminance characteristic of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in the embodiment and outputs it as the video data Vdata. Therefore, the 10-bit video data Vdata also specifies a grayscale level. In other words, the video data Vdata specifies a grayscale level obtained by converting the grayscale level specified by the video data Vid.

[0016] For up-conversion, a look-up table is used that stores in advance the correspondence between, for example, 8 bits of input video data Vid and 10 bits of output video data Vdata. The control circuit 30 also generates various control signals to control each unit, which will be described in detail later.

[0017] The scanning line driving circuit 120 is a circuit for outputting various signals and driving the pixel circuits 110 arranged in m rows and n columns, row by row, according to the control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), mth scanning lines 12 in order. In general, the scanning line driving circuit 120 supplies a scanning signal / Gwr(i) to the i-th scanning line 12. The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), which will be described in detail later.

[0018] The data signal output circuit 50 is a circuit that outputs a signal of a voltage according to luminance to the pixel circuits 110 located in a row selected by the scanning line driving circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 in one-to-one correspondence with the n columns, the first latch circuit group 54 includes first latch circuits L1 in one-to-one correspondence with the n columns, and the second latch circuit group 56 includes second latch circuits L2 in one-to-one correspondence with the n columns. Also, the n DA conversion circuits 500 are in one-to-one correspondence with the n columns.

[0019] That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, and a DA conversion circuit 500 is provided corresponding to each example. Here, the selection circuit 520 of the jth column instructs the first latch circuit L1 of the jth column to select the video data of the jth column from the video data Vdata output from the control circuit 30, and the first latch circuit L1 of the jth column latches the video data Vdata according to the instruction. The second latch circuit L2 of the jth column outputs the video data Vdata latched by the first latch circuit L1 of the jth column to the DA conversion circuit 500 of the jth column in a writing period (C) described later according to the control of the control circuit 30.

[0020] The j-th column DA conversion circuit 500 converts the 10-bit video data Vdata output from the j-th column second latch circuit L2 into an analog signal and outputs it to the j-th column data signal output line 14c. In other words, the data signal output line 14c is provided in one-to-one correspondence with the data line 14, and the output terminal of the j-th column DA conversion circuit 500 is connected to the j-th column data signal output line 14c.

[0021] The auxiliary circuit 60 is a collection of transistors 62 provided in one-to-one correspondence with the data signal output lines 14c. The source node of the transistor 62 corresponding to the jth column is connected to a power supply line of potential Vref, and the drain node of the transistor 62 is connected to the jth data signal output line 14c. A control signal / Gref output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

[0022] The n capacitive elements 70 are provided in one-to-one correspondence with pairs of data signal output lines 14c and data lines 14. In particular, one end of the capacitive element 70 in the jth column is connected to the data signal output line 14c in the jth column, and the other end of the capacitive element 70 in the jth column is connected to the data line 14 in the jth column. The video data Vdata corresponds to a gradation level specified by the video data Vid, and the DA conversion circuit 500 converts the video data Vdata into an analog signal, which is supplied as a data signal to the data line 14 via the capacitive element 70. Therefore, the potential of the data signal supplied to the data line 14 corresponds to the gradation level specified by the video data Vid and the video data Vdata.

[0023] The initialization circuit 80 is a collection of pairs of transistors 82 , 84 and 86 provided in one-to-one correspondence with the data lines 14 . A source node of the transistor 82 corresponding to the j-th column is connected to a power supply line of potential Vel, and a drain node of the transistor 82 is connected to the data line 14 of the j-th column. A control signal / Drst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 82 in each column. The potential Vel is used as a high-level potential of the power supply voltage.

[0024] A source node of the transistor 84 corresponding to the j-th column is connected to a power supply line of potential Vini, and a drain node of the transistor 84 is connected to the j-th column data line 14. A control signal / Gini output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 84 in each column.

[0025] The source node of the transistor 86 corresponding to the j-th column is connected to a power supply line of the potential Vorst, and the drain node of the transistor 86 is connected to the data line 14 of the j-th column. A control signal / Grst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 86 in each column. The potential Vorst is, for example, the potential Gnd or a low potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED if power is supplied to the anode of the OLED. The potential Gnd is a ground potential, which is a reference potential of zero voltage.

[0026] In this embodiment, the control signals / Drst and / Grst are always at H level, so the transistors 82 and 86 in each column are always off. Therefore, in this embodiment, the transistors 82 and 86 have no electrical meaning. However, they are left for comparison with a comparative example described later.

[0027] A capacitance component parasitic on each data line 14 of each column. In the figure, the capacitance component is represented as a parasitic capacitance 72. From an electrical perspective, the parasitic capacitance 72 is represented as a capacitance element having one end connected to the data line 14 and the other end connected to a power supply line with a constant potential, for example, a potential Gnd. In addition, in the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are denoted as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is denoted as Vd(j).

[0028] 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the i row and j column as a representative.

[0029] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. In addition, the pixel circuits 110 in the i-th row are supplied with control signals / Gel(i-1) and / Gcmp(i-1) from the scanning line driving circuit 120 in addition to the scanning signal / Gwr(i-1) corresponding to the i-th row.

[0030] Control signal / Gel(i) is a generalized representation of control signals / Gel(1), / Gel(2), ..., / Gel(m-1), / Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, control signal / Gcmp(i) is a generalized representation of control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), / Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

[0031] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0032] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter in order, and is visually recognized by the observer. Note that the optical resonator is not shown. In addition, when the electro-optical device 10 simply displays a monochromatic image of light and dark only, the optical resonator and the color filter are omitted.

[0033] In transistor 121 of pixel circuit 110 in row i and column j, the gate node g is connected to the drain node of transistor 122, the source node s is connected to the power supply line 116 to which the potential Vel is supplied, and the drain node d is connected to the source node of transistor 123 and the source node of transistor 124. A capacitance component is parasitic on the drain node d of the transistor 121. In the figure, this capacitance component is represented as a parasitic capacitance 150. From an electrical perspective, the parasitic capacitance 150 is represented as a capacitance element having one end connected to the drain node d and the other end connected to a power supply line with a constant potential, for example, a potential Gnd.

[0034] One end of the capacitance element 140 is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. The other end of the capacitive element 140 may be connected to a power supply line of a different potential other than the power supply line 116 of the potential Vel, as long as the potential is kept substantially constant.

[0035] In the embodiment, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of a transistor is used as the capacitance element 140. Note that a parasitic capacitance of the gate node g of the transistor 121 may be used as the capacitance element 140, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used.

[0036] In the transistor 122 of the pixel circuit 110 in the i-th row and j-th column, a gate node is connected to the i-th row scanning line 12, and a source node is connected to the j-th column data line 14. In the transistor 123 of the pixel circuit 110 in the i-th row and j-th column, a control signal / Gcmp(i) is supplied to a gate node, and a drain node is connected to the j-th column data line 14. In the transistor 124 of the pixel circuit 110 in the i-th row and j-th column, a control signal / Gel(i) is supplied to a gate node, and a drain node is connected to the pixel electrode 131 which is the anode of the OLED 130.

[0037] In the transistors 122, 123, and 124, when the direction of current flow is reversed, the source node and the drain node are switched, but in this description, the source node and the drain node are as described above.

[0038] A potential Vct is supplied to the common electrode 133 that functions as the cathode of the OLED 130. Note that the potential Vct is, for example, the potential Gnd or a low potential close to the potential Gnd. In such a pixel circuit 110, a series connection of transistors 123 and 124 is provided in the path from the data line 14 to the pixel electrode 131, and a transistor 124 is provided between the drain node d of the transistor 121 and the pixel electrode 131.

[0039] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes even if the elements are not directly connected to each other. Although the pixel circuit 110 in the i-th row and j-th column has been described here, the pixel circuits 110 in the other rows and other columns have the same configuration.

[0040] The control circuit 30 controls driving of the pixel circuit 110 via the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120. For this reason, the control circuit 30, the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120 may be collectively referred to as a control circuit in a broad sense that controls the pixel circuit 110.

[0041] Next, the operation of the electro-optical device 10 will be described.

[0042] Fig. 4 is a timing chart for explaining the operation of the electro-optical device 10 according to the first embodiment. In detail, Fig. 4 is a timing chart showing the operation of one frame in the electro-optical device 10 and the operation of two consecutive horizontal scanning periods in that one frame.

[0043] In this description, this refers to one frame. One frame refers to the period required to display one frame of an image specified by the video data Vid. The time length of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal.

[0044] In the electro-optical device 10, in each frame (V), m scanning lines 12 are selected one by one in the order of 1st, 2nd, 3rd, ..., mth row and horizontally scanned. The period required for horizontal scanning of one row is the horizontal scanning period (H).

[0045] In this embodiment, the horizontal scanning period (H) is divided, in order of time, into an initialization period (A), a compensation period (B), a writing period (C), and a drain set period (D). In addition to the initialization period (A), the compensation period (B), the writing period (C), and the drain set period (D), the operation of the pixel circuit 110 further includes a light emission period (E).

[0046] The initialization period (A) is a period during which a potential Vini for turning on the transistor 121 is supplied to the gate node g via the data line 14. The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a potential corresponding to the threshold voltage of the transistor 121. The write period (C) is a period during which a potential corresponding to the gradation level is held (written) at the gate node g of the transistor 121, and more specifically, is a period during which the gate node g of the transistor 121 is changed from a potential corresponding to the threshold voltage by an amount corresponding to a voltage corresponding to the current flowing through the OLED 130. The drain set period (D) is a period during which the potential Vini is set to the drain node d of the transistor 121. The potential Vini set to the drain node d is held by the parasitic capacitance 150. The light emitting period (E) is a period for causing a current corresponding to the potential of the gate node g held in the writing period (C) to flow through the OLED 130 to emit light.

[0047] In this description, the "on state" of a transistor means that the source node and drain node of the transistor are electrically closed and in a low impedance state, and the "off state" of a transistor means that the source node and drain node are electrically open and in a high impedance state.

[0048] In this embodiment, the operation of each frame is common. Also, in one frame (V), the operation of each row in the horizontal scanning period (H) is common. Furthermore, the operation of the pixel circuits 110 in the 1st to nth columns of one row scanned in one horizontal scanning period (H) is common. Therefore, in the following, the operation of the pixel circuit 110 in the i-th row and j-th column during the horizontal scanning period (H) of the i-th row in each frame will be described as an example.

[0049] In one frame (V), in the initialization period (A) of each horizontal scanning period (H), the control signal / Gini is at L level, and the control signal / Gref is at L level, so that the transistors 84 in each column are turned on, and the transistors 62 in each column are turned on.

[0050] In addition, in the initialization period (A) of the horizontal scanning period (H) in the i-th row, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, and the control signal / Gel(i) is at H level. Therefore, in the initialization period (A), in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state.

[0051] Therefore, during the initialization period (A), as shown in FIG. 5, in the pixel circuit 110 in the i-th row and j-th column, the potential Vini is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 84, the j-th column data line 14, and the transistor 122, in that order.

[0052] In the initialization period (A), since the transistor 62 in each column is in an on state, the data signal output line 14c, that is, one end of the capacitive element 70, becomes the potential Vref. As described above, in the initialization period (A), the j-th column data line 14, that is, the other end of the capacitive element 70, is at the potential Vini. Therefore, in each column, the voltage across the capacitive element 70 becomes |Vref-Vini|, and one end of the parasitic capacitance 72 is held at the potential Vini. The potentials Vini and Vorst are Vini>Vorst This is the relationship.

[0053] In the compensation period (B) of each horizontal scanning period (H), the control signal / Gini changes to H level, and the control signal / Gref maintains L level. As a result, the transistors 84 in each column change to the OFF state, and the transistors 62 in each column maintain the ON state.

[0054] In the compensation period (B) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) maintains the H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0055] At the start of the compensation period (B), in the i-th row pixel circuit 110, the gate node g of the transistor 121 is at the potential Vini. When the transistor 123 is turned on while the gate node g is at the potential Vini, the transistor 121 is in a diode-connected state, that is, the gate node g and the drain node d are connected to each other.

[0056] 6, in the compensation period (B), the voltage between the gate node g and the source node s of the transistor 121 approaches (a voltage close to) the threshold voltage Vth of the transistor 121. That is, the potentials of the gate node g, the drain node d, and the data line 14 of the transistor 121 approach the threshold equivalent potential (Vel-Vth).

[0057] During the compensation period (B), the transistor 62 in each column maintains the on state, so that one end of the capacitance element 70 maintains the potential Vref. Also, during the compensation period (B), the other end of the capacitance element 70, which is the data line 14, approaches the threshold potential (Vel-Vth). Therefore, in each column, the voltage across the capacitive element 70 becomes |Vel-Vth-Vref|, and one end of the parasitic capacitance 72 is held at a potential equivalent to the threshold voltage (Vel-Vth).

[0058] In the writing period (C) of each horizontal scanning period (H), the control signal / Gini maintains the H level, and the control signal / Gref changes to the H level. As a result, the transistors 84 in each column maintain the off state, and the transistors 62 in each column change to the off state.

[0059] In the writing period (C) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the H level, and the control signal / Gel(i) maintains the H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

[0060] During the writing period (C), the transistors 62 of each column are turned off. The DA conversion circuit 500 of each column is supplied with 10-bit video data Vdata corresponding to the i-th row and column. Therefore, the DA conversion circuit 500 of the j-th column outputs a signal of a potential corresponding to the gradation level of the i-th row and j-th column to the data signal output line 14c.

[0061] 7, one end of the capacitive element 70 in the jth column rises from a potential Vref to a potential of a gradation level corresponding to the i-th row and the j-th column. This potential rise reaches the gate node g of the transistor 121 via the capacitive element 70, the data line 14, and the transistor 122 in this order.

[0062] The potential change amount of the gate node g in the writing period (C) is a value obtained by multiplying the potential rise amount at the data signal output line 14c, i.e., one end of the capacitance element 70, by the ratio of the capacitance value of the capacitance element 70 to the "composite capacitance value." The "composite capacitance value" here refers to the capacitance value of the composite capacitance of the capacitance element 70, the parasitic capacitance 72, and the capacitance element 140. Note that the capacitance value of the capacitance element 140 can be ignored if it is sufficiently small compared with the other capacitance values.

[0063] The potential changes of the data signal output line 14c and the data line 14 during the writing period (C) will be described with reference to FIG. The potential corresponding to the gradation level output by the DA conversion circuit 500 to the data signal output line 14c ranges from a potential Bk corresponding to the black level of the lowest gradation to a potential Wt corresponding to the white level of the highest gradation. The potential in this range is compressed to a range from a potential Vbk (≈Vel) to a potential Vwt slightly lower than the potential Vbk by the charge distribution by the capacitive element 70 and the parasitic capacitance 72, and reaches the data line 14 and the gate node g.

[0064] When the scanning signal / Gwr(i) becomes H level, the writing period (C) ends. In the pixel circuit 110 in the i-th row and j-th column, the transistor 122 is turned off, but the difference voltage between the potential of the gate node g and the potential Vel of the source node s is held in the capacitance element 140.

[0065] In this embodiment, after the end of the writing period (C), the drain set period (D) begins. During the drain set period (D) of each horizontal scanning period (H), the control signal / Gini changes to the L level, and the control signal / Gref maintains the H level. As a result, the transistors 84 in each column change to the ON state, and the transistors 62 in each column maintain the OFF state.

[0066] In the drain set period (D) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) changes to H level, the control signal / Gcmp(i) changes to L level, and the control signal / Gel(i) maintains H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0067] Therefore, during the drain set period (D), as shown in FIG. 8, in the pixel circuit 110 in the i-th row and j-th column, the potential Vini is supplied to the drain node d of the transistor 121 via the transistor 84, the j-th column data line 14, and the transistor 123 in that order. Therefore, during the drain set period (D), the drain node d, i.e., one end of the parasitic capacitance 150, is set to the potential Vini. As described above, the potential Vini is a potential that turns on the transistor 121 when supplied to the gate node g, and is lower than the potential Vel and higher than the potential Vorst.

[0068] In this embodiment, after the drain set period (D) ends, the light emission period (E) begins. In the light emission period (E) of the i-th row, the control signal / Gel(i) is inverted to the L level, so that the transistor 124 is turned on. 9, in the light emission period (E), a current Iel according to the potential of the gate node g held by the capacitance element 140 flows through the OLED 130 in the pixel circuit 110 in the i-th row and j-th column by the transistor 121. As a result, the OLED 130 emits light with a luminance according to the current Iel.

[0069] FIG. 23 is a timing chart for explaining the operation of a comparative example for explaining the superiority of the electro-optical device 10 according to the first embodiment. The configuration of the electro-optical device of the comparative example is the same as the configuration shown in Figures 2 and 3, but the control signals supplied from the control circuit 30 and the scanning line driving circuit 120 have waveforms as shown in Figure 23, unlike those in the first embodiment.

[0070] In the comparative example, the initialization period (A) is divided into three initialization periods (A1), (A2), and (A3). Among these, the initialization period (A1) is a period for setting the transistor 121 to an off state. The initialization period (A2) is a period for resetting the potential at the anode of the OLED 130, and the initialization period (A3) is a period for applying a potential Vini to the gate node g via the data line 14 to turn the transistor 121 to an on state at the beginning of the compensation period (B).

[0071] In the comparative example, in the initialization period (A1) of each horizontal scanning period (H), the control signal / Drst is at L level, the control signal / Gini is at H level, the control signal / Grst is at H level, and the control signal / Gref is at L level. As a result, the transistor 82 is turned on, the transistor 84 is turned off, the transistor 86 is turned off, and the transistor 62 is turned on.

[0072] In the comparative example, in the initialization period (A1) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, and the control signal / Gel(i) is at H level. As a result, in the pixel circuit 110, the transistor 122 is turned on, and the transistors 123 and 124 are turned off.

[0073] Therefore, in the comparative example, in the initialization period (A1), in the pixel circuit 110 in the i-th row, the potential Vel is supplied to the gate node g of the transistor 121 via the data line 14 and the transistor 122 in this order. When the potential Vel is supplied to the gate node g, the voltage between the gate node and the source node becomes zero, so that the transistor 121 is forcibly turned off. One end of the capacitance element 74 is fixed to the potential Vref.

[0074] In the comparative example, in the initialization period (A2) of each horizontal scanning period (H), the control signal / Drst changes to H level, the control signal / Gini maintains H level, the control signal / Grst changes to L level, and the control signal / Gref maintains L level. As a result, the transistor 82 changes to the OFF state, the transistor 84 maintains the OFF state, the transistor 86 changes to the ON state, and the transistor 62 maintains the ON state.

[0075] In the comparative example, in the initialization period (A2) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) changes to H level, the control signal / Gcmp(i) changes to L level, and the control signal / Gel(i) changes to L level. As a result, in the pixel circuit 110, the transistor 122 changes to the OFF state, and the transistors 123 and 124 change to the ON state.

[0076] Therefore, in the comparative example, in the i-th row pixel circuit 110 during the initialization period (A2), the potential Vorst is supplied to the pixel electrode 131, which is the anode of the OLED 130, via the data line 14, the transistors 123 and 124 in this order. When the potential Vorst is supplied to the pixel electrode 131, the OLED 130 is forcibly turned off. In addition, since the potential Vorst passes through the drain node d of the transistor 121, the charge remaining in the parasitic capacitance 150 is reset. One end of the capacitance element 74 is fixed to the potential Vref.

[0077] In the comparative example, the initialization period (A3), compensation period (B) and writing period (C) of the horizontal scanning period (H) in which the i-th row is selected are the same as the initialization period (A), compensation period (B) and writing period (C) in the first embodiment, in that order. That is, in the comparative example, during the horizontal scanning period (H) in which the i-th row is selected, during the initialization period (A3), the gate node g of the transistor 121 in the i-th row pixel circuit 110 is supplied with a potential Vini, during the compensation period (B), the gate node g approaches a threshold potential (Vel-Vth), and during the writing period (C), a potential corresponding to the gradation level is held at the gate node g of the transistor 121.

[0078] In the comparative example, in the drain set period (D) of each horizontal scanning period (H), the control signal / Drst is at H level, the control signal / Gini is at H level, the control signal / Grst is at H level, and the control signal / Gref is at H level. As a result, the transistor 82 is in the off state, the transistor 84 is in the off state, the transistor 86 is in the off state, and the transistor 62 is in the off state.

[0079] In the comparative example, in the drain set period (D) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at H level, the control signal / Gcmp(i) is at L, and the control signal / Gel(i) is at H level. Therefore, in the pixel circuit 110, the transistor 122 is in the off state, the transistor 123 is in the on state, and the transistor 124 is in the off state. During the drain set period (D), the control signal / Gref(i) continues to be at the H level from the write period (C), so the transistor 62 is in the off state.

[0080] Therefore, in the comparative example, in the pixel circuit 110 in the i-th row during the drain set period (D), as shown in FIG. 24, the potential held in the data line 14 and the parasitic capacitance 72 during the write period (C), i.e., the potential corresponding to the gradation level, is supplied to the drain node d of the transistor 121 via the transistor 123.

[0081] FIG. 11 is a diagram showing potential changes at various parts of the pixel circuit 110 of the electro-optical device 10 according to the first embodiment, in comparison with the comparative example. Here, the potential of the data line 14 is represented as Vdt, and the potential at the drain node d of the transistor 121 is represented as Vdr_d. This is an example in which the OLED 130 in the pixel circuit 110 is set to the black level of the lowest gradation. The potential change in the first embodiment is indicated by a solid line p, and the potential change in the comparative example is indicated by a dashed line q.

[0082] In this case, in the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini in the initialization period (A), approaches the threshold potential (Vel-Vth) in the compensation period (B), and becomes the potential Vbk corresponding to the black level in the writing period (C). Note that the potential Vbk is almost equal to the potential Vel, as described above. In the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini in the drain set period (D). Since the light emission period (E) is also the initialization period (A) in the next horizontal scanning period, in the first embodiment, the potential Vdt of the data line 14 becomes the potential Vini.

[0083] In the comparative example, the potential Vdt of the data line 14 becomes the potential Vini in the initialization period (A3) which is the end of the initialization period (A), approaches the threshold equivalent potential (Vel-Vth) in the compensation period (B), and becomes the potential Vbk in the writing period (C). Up to this point, it is the same as the first embodiment. In the comparative example, the potential Vdt of the data line 14 is maintained at the potential Vbk (≈Vel) according to the gradation level in the writing period (C) and in the drain set period (D). Note that in the comparative example, since the light emission period (E) is the initialization period (A1) in the next horizontal scanning period, the potential Vdt of the data line 14 is the potential Vel and hardly changes.

[0084] In the first embodiment, the potential Vdr_d at the drain node d of the transistor 121 approaches the threshold potential (Vel-Vth) in the same manner as the potential Vdt, since the transistor 123 is in the on state during the compensation period (B). In the first embodiment, when the transistor 123 changes to the off state at the end of the compensation period (B), the gate node g is approximately at the threshold potential (Vel-Vth), so the transistor 121 is turned on. As a result, the potential Vdr_d at the drain node d of the transistor 121 rises to the potential Vel. In the writing period (C), the gate node g rises from a potential equivalent to the threshold voltage (Vel-Vth) to a potential Vbk (≒Vel) equivalent to the black level. This potential rise is propagated to the drain node d via the parasitic capacitance between the gate node and the source node of the transistor 121. Therefore, in the write period (C), the potential Vdr_d at the drain node d of the transistor 121 further rises from the potential Vel. In the first embodiment, the potential Vdr_d at the drain node d becomes the potential Vini during the drain set period (D) due to the on state of the transistor 123. At the end of the drain set period (D) or the start of the light emission period (E), the transistor 123 changes from the on state to the off state, causing the potential Vdr_d at the drain node d to rise from the potential Vini. That is, the control signal / Gcmp(i) of the i-th row changes from the L level to the H level, and this potential rise is propagated to the drain node d via the parasitic capacitance between the gate node and the source node of the transistor 123, causing the potential Vdr_d to rise from the potential Vini.

[0085] In the comparative example, the potential Vdr_d at the drain node d of the transistor 121 approaches the threshold potential (Vel-Vth) during the compensation period (B), rises to the potential Vel at the end of the compensation period (B), and rises again to the potential Vbk (≈Vel) corresponding to the black level during the writing period (C). This is the same as in the first embodiment. In the comparative example, during the drain set period (D), the transistor 84 is off and the transistor 123 is on, so that the potential Vdr_d at the drain node d becomes equal to the potential Vbk (≈Vel) of the potential Vdt of the data line 14. At the end of the drain set period (D) or the start of the light emission period (E), the transistor 123 changes from the on state to the off state, causing the potential Vdr_d at the drain node d to rise from the potential Vbk (≈Vel).

[0086] When the OLED 130 in the pixel circuit 110 is set to the black level of the lowest gradation, in the drain set period (D), in the comparative example, the potential Vdr_d of the drain node d of the transistor 121 is approximately the potential Vel, and this potential Vel is held by the parasitic capacitance 150. That is, a charge remains in the parasitic capacitance 150. In this state, when the light emission period (E) is reached and the transistor 124 is changed to the on state, the charge remaining in the parasitic capacitance 150 flows into the OLED 130, causing the OLED 130 to emit a slight light. For this reason, in the comparative example, although it is desired to express the black level of the lowest gradation, the OLED 130 emits a slight light, preventing the realization of a high contrast ratio.

[0087] In contrast, in the first embodiment, when the OLED 130 is set to the black level of the lowest gradation, the potential Vdr_d of the drain node d of the transistor 121 is a potential ini lower than the potential Vel in the drain set period (D). Therefore, in the first embodiment, the charge remaining in the parasitic capacitance 150 is smaller than in the comparative example, so that even if the charge remaining in the parasitic capacitance 150 flows into the OLED 130 in the light emission period (E), the degree to which the OLED 130 emits light is smaller than in the comparative example. Therefore, in the first embodiment, a higher contrast ratio can be achieved than in the comparative example.

[0088] In the comparative example, when a black level is displayed, the potential Vdt of the data line 14 becomes a potential Vbk (≈Vel) in the drain set period (D), becomes a potential Vel in the initialization period (A1) of the next horizontal scanning period (H), becomes a potential Vorst in the initialization period (A2), and becomes a potential Vini in the initialization period (A3). That is, in the comparative example, the potential Vdt of the data line 14 drops from the potential Vel to the potential Vorst and then rises to the potential Vini from the drain set period (D) to the initialization period of the next horizontal scanning period. In contrast, in the first embodiment, the potential Vdt of the data line 14 is the potential Vini in the drain set period (D), and is also the potential Vini in the initialization period (A) of the next horizontal scanning period (H). That is, in the first embodiment, the potential Vdt of the data line 14 is constant at the potential Vini from the drain set period (D) to the initialization period of the next horizontal scanning period. Therefore, in the first embodiment, the power consumed by the parasitic capacitance 72 due to the potential amplitude of the data line 14 is reduced as compared to the comparative example.

[0089] In addition, in the technology described in the above-mentioned Patent Document 1, the potential Vorst is supplied to the drain node d of the transistor 121 during the period corresponding to the drain set period (D), whereas in the first embodiment, the potential Vini is higher than the potential Vorst. Therefore, when displaying a black level, the decrease in the potential Vdt of the data line 14 from the writing period (C) to the drain set period (D) is smaller in the first embodiment than in the technology described in Patent Document 1. In the technology described in Patent Document 1, when displaying a black level, the potential Vdt of the data line 14 becomes the potential Vorst in the drain set period (D), becomes the potential Vel in the initialization period (A1) of the next horizontal scanning period (H), becomes the potential Vorst in the initialization period (A2), and becomes the potential Vini in the initialization period (A3). In contrast, in the first embodiment, the potential Vdt of the data line 14 is constant at the potential Vini from the drain set period (D) to the initialization period of the next horizontal scanning period, as described above. Therefore, in the first embodiment, the power consumed by the parasitic capacitance 72 due to the potential amplitude of the data line 14 is reduced compared to not only the comparative example but also the technique described in Patent Document 1.

[0090] In the above-described first embodiment, when the potential Vini is supplied to the gate node g, it is necessary to turn on the transistor 121. For this reason, the potential Vini needs to be lower than the threshold potential (Vel-Vth) of the transistor 121. However, if the potential Vini is set low, it is necessary to set the compensation period (B) long in order to compensate for the variation in the threshold characteristics of all the transistors 121, which hinders the shortening of the horizontal scanning period associated with higher resolution. Furthermore, if the potential Vini is set low, the potential amplitude of the data line 14 increases, and the power consumed by the parasitic capacitance 72 increases, making it difficult to reduce power consumption. Furthermore, in order to bring the gate node g of the transistor 121 close to the ideal threshold equivalent potential (Vel-Vth) at the end of the compensation period (B), it is important to set the potential Vini supplied to the gate node g of the transistor 121 at the start of the compensation period (B). Thus, various constraints must be cleared when determining the potential Vini. In this way, if the potential Vini, which needs to clear various constraints, is set to the drain node in the drain set period (D), it may not be possible to sufficiently suppress weak light emission caused by the charge remaining in the parasitic capacitance 150 flowing into the OLED 130 at the beginning of the light emission period (E). Therefore, a second embodiment will be described in which a potential other than the potential Vini is used as the potential set to the drain node in the drain set period (D).

[0091] <Second embodiment> Fig. 12 is a block diagram showing an electrical configuration of an electro-optical device 10 according to a second embodiment. The electro-optical device 10 according to the second embodiment differs from the first embodiment shown in Fig. 2 in that transistors 85 are provided in one-to-one correspondence with the data lines 14 in an initialization circuit 80. A source node of the transistor 85 corresponding to the jth column is connected to a power supply line of potential Vini2, and a drain node of the transistor 85 is connected to the data line 14 of the jth column. A control signal / Gini2 output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 85 in each column. The potential Vini2 is higher than the potential Vini and lower than the potential Vbk.

[0092] FIG. 13 is a timing chart illustrating the operation of the electro-optical device 10 according to the second embodiment. The timing chart shown in Fig. 13 differs from Fig. 4 in that the control signal / Gini maintains the H level from the end of the writing period (C) to the end of the drain set period (D) and in that a control signal / Gini2 is added. The control signal / Gini2 becomes the L level during the drain set period (D) of each horizontal scanning period (H) in one frame (V) and becomes the H level during the other periods.

[0093] In the second embodiment, in the drain set period (D), instead of the transistor 84 being turned off in each column, the transistor 85 is turned on. Therefore, during the drain set period (D), although not specifically shown, in the pixel circuit 110 in the i-th row and j-th column, the potential Vini2 is supplied to the drain node d of the transistor 121 via the transistor 85, the j-th column data line 14, and the transistor 123 in that order.

[0094] Therefore, in the second embodiment, in the drain set period (D), the potential to be set at the drain node is the potential Vini2 separate from the potential Vini, so that the degree of freedom in setting the potentials Vini and Vini2 can be increased.

[0095] In the first or second embodiment, the potential Vref serves to fix the potential at one end of the capacitive element 70 when the potential of the data line 14, i.e., the potential at the other end of the capacitive element 70, fluctuates during the initialization period (A) and the compensation period (B). Therefore, a third embodiment will be described in which the potential to be set at the drain node during the drain set period (D) is a potential other than the potential Vini and is set to the potential Vref.

[0096] <Third embodiment> Fig. 14 is a block diagram showing the electrical configuration of the electro-optical device 10 according to the third embodiment. The electro-optical device 10 according to the third embodiment differs from the first embodiment shown in Fig. 2 in that transistors 87 are provided in one-to-one correspondence with the data lines 14 in the initialization circuit 80. A source node of the transistor 87 corresponding to the jth column is connected to a power supply line of potential Vref, and a drain node of the transistor 87 is connected to the jth column data line 14. A control signal / Gref2 output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 85 in each column. In the third embodiment, the control signal / Gref2 has the same waveform as the control signal / Gini2 in Fig. 13. Note that in the third embodiment, the control signal / Gini has the same waveform as in Fig. 13, not in Fig. 4.

[0097] In the third embodiment, in the drain set period (D), instead of the transistor 84 being turned off in each column, the transistor 87 is turned on. Therefore, during the drain set period (D), although not specifically shown, the potential Vref is supplied to the drain node d of the transistor 121 in the pixel circuit 110 in the i-th row and j-th column via the transistor 87, the j-th column data line 14, and the transistor 123 in that order.

[0098] Therefore, in the third embodiment, the potential to be set at the drain node during the drain set period (D) is not the potential Vini but the potential Vref, so that the degree of freedom in setting the potential Vini can be increased. Also, in the third embodiment, compared to the second embodiment, there is no need to generate a separate potential Vini2, so that the circuit configuration for generating the potential can be simplified. In the third embodiment, the potential Vref is set to be equal to or higher than the potential Vini and lower than the potential Vbk.

[0099] In the first to third embodiments, the initialization circuit 80 is configured to supply a potential to be set to the drain node during the drain set period (D), but the potential may be supplied by an element other than the initialization circuit 80, specifically, a separate element in the pixel circuit 110. Therefore, a fourth embodiment will be described in which the pixel circuit 110 itself supplies the potential to be set at the drain node during the drain set period (D). The fourth embodiment is different from the first embodiment in the configuration of the pixel circuit.

[0100] <Fourth embodiment> Fig. 15 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a fourth embodiment. The pixel circuit 110 according to the fourth embodiment differs from the first embodiment shown in Fig. 3 in that a transistor 126 is provided that electrically connects the drain node d of the transistor 121 and the power supply line of the potential Vini2 during the drain set period (D). A control signal / Gini2(i) output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 126 in the pixel circuits 110 in the i-th row. That is, the control signal / Gini2(i) is supplied for each row.

[0101] FIG. 16 is a timing chart showing the operation of the electro-optical device 10 according to the fourth embodiment, in particular the waveforms of the control signal / Gini2(i-1) in the (i-1)th row and the control signal / Gini2(i) in the i-th row. As shown in the figure, in the drain set period (D) of the horizontal scanning period (H) in the i-th row, the control signal / Gini2(i) becomes L level and the control signal / Gcmp(i) becomes H level. Note that in the fourth embodiment, the control signal / Gini maintains the H level from the end of the writing period (C) to the end of the drain set period (D), which is the same as the second embodiment shown in FIG.

[0102] In the fourth embodiment, in the drain set period (D) of the horizontal scanning period (H) in the i-th row, the transistor 123 is turned off and the transistor 126 is turned on. Therefore, in the drain set period (D), although not particularly shown, in the pixel circuit 110 in the i-th row and j-th column, the potential Vini2 is supplied to the drain node d of the transistor 121 via the transistor 126.

[0103] Therefore, in the fourth embodiment, during the drain set period (D), unlike the first to third embodiments, the potential to be set to the drain node is supplied without passing through the data line 14, thereby reducing the power consumed by charging and discharging the data line 14 (parasitic capacitance 72). Moreover, in the fourth embodiment, the drain set period (D) of the horizontal scanning period (H) in the i-th row can be executed independently of the other rows. In addition, in the fourth embodiment, the drain set period (D) of the horizontal scanning period (H) in the i-th row can be executed in parallel with the writing period (C). In the fourth embodiment, when the drain set period (D) and the writing period (C) are executed in parallel, the compensation period (B) can be made longer accordingly, or the horizontal scanning period (H) can be shortened to achieve higher resolution.

[0104] 16, for example, the scanning signal / Gwr(i) may be changed from L level to H level in the drain set period (D) of the horizontal scanning period (H) in the i-th row. In this configuration, the writing period (C) is executed in parallel until the middle of the drain set period (D). In this configuration, when the transistor 122 changes from an on state to an off state, the transistor 126 is in an on state. This suppresses the influence caused when the transistor 122 changes to an off state. Specifically, this influence is a phenomenon in which the potential of the drain node of the transistor 122 (the gate node g of the transistor 121) increases due to feed-through by the transistor 122, and further, the potential increase fluctuates the potential of the drain node d via a parasitic capacitance between the gate node and drain node of the transistor 121.

[0105] In the fourth embodiment, the potential to be set to the drain node d in the drain set period (D) is supplied via the transistor 126 provided separately in the pixel circuit 110, but the present invention is not limited to such a configuration. In short, any configuration may be used as long as it reduces the charge remaining in the parasitic capacitance 150 before the light emission period (E). Therefore, a fifth and sixth embodiments will be described in which the charge remaining in the parasitic capacitance 150 before the light emission period (E) is reduced by an element other than the transistor 126.

[0106] <Fifth embodiment> Fig. 17 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a fifth embodiment. The pixel circuit 110 according to the fifth embodiment differs from the first embodiment shown in Fig. 3 in that a capacitive element 161 is provided between the drain node d of the transistor 121 and a discharge control line 170. In detail, one electrode of the capacitive element 161 is connected to the drain node d of the transistor 121, and the other electrode is connected to the discharge control line 170. In the fifth embodiment, the capacitive element 161 is a metal capacitor having a MIM (Metal Insulator Metal) structure in which an insulating layer is sandwiched between different conductive layers on a semiconductor substrate. The discharge control lines 170 of the pixel circuits 110 in the i-th row are commonly supplied with a control signal / Ds(i) output from the control circuit 30. That is, the control signal / Ds(i) is supplied for each row.

[0107] Sixth embodiment Fig. 18 is a diagram showing a pixel circuit 110 of an electro-optical device 10 according to a sixth embodiment. The pixel circuit 110 according to the fifth embodiment differs from the fifth embodiment shown in Fig. 17 in that the capacitive element 161 is replaced with a capacitive element 162. In detail, the capacitive element 162 is a MOS capacitor having one electrode, which is a source node and a drain node, connected to a drain node d of the transistor 121, and the other electrode connected to a gate node. That is, the capacitive element 162 is formed by sandwiching the gate insulating layer of the transistor between the semiconductor layer (lower electrode) and the gate electrode layer (upper electrode) of the transistor. In the sixth embodiment, similarly to the fifth embodiment, the control signal / Ds(i) output from the control circuit 30 is commonly supplied to the discharge control lines 170 of the pixel circuits 110 in the i-th row.

[0108] FIG. 19 is a timing chart showing the operation of the electro-optical device 10 according to the fifth or sixth embodiment, in particular the waveforms of the control signal / Ds(i-1) in the (i-1)th row and the control signal D / s(i) in the i-th row. As shown in the figure, the control signal D / s(i) for the i-th row becomes H level at the start of the horizontal scanning period (H) for the i-th row, and at the start of the drain set period (D), the potential of the drain node d decreases as the control signal D / s(i) drops from H level to L level, thereby reducing the charge remaining in the parasitic capacitance 150.

[0109] <Modifications and Applications> In the above-described first to sixth embodiments (hereinafter referred to as "embodiments, etc."), various modifications or applications are possible as follows.

[0110] In the embodiment, the initialization period (A) to the drain set period (D) are contained within one horizontal scanning period (H) as shown in (1) of Fig. 20, but the drain set period (D) does not need to be contained within the one horizontal scanning period (H). Specifically, the initialization period (A), the compensation period (B) and the writing period (C) need to be contained within one horizontal scanning period (H), but the drain set period (D) may be after the one horizontal scanning period and before the light emission period (E) as shown in (2) of Fig. 20. In this way, by placing the drain set period (D) after one horizontal scanning period, the period that needs to be contained in the horizontal scanning period (H), particularly the compensation period (B), can be made longer, or the horizontal scanning period (H) can be shortened to achieve higher resolution.

[0111] The reason why the drain set period (D) is executed after the write period (C) in the embodiment etc. will be described. When the write period (C) ends in the horizontal scanning period (H) of the i-th row, the transistor 122 changes from the on state to the off state, specifically, the potential of the scanning signal / Gwr(i) rises from the L level to the H level. The potential rise propagates through the parasitic capacitance between the gate node and drain node of the transistor 122, and raises the potential of the drain node of the transistor 122, i.e., the gate node g of the transistor 121. The potential rise at the gate node g of the transistor 121 propagates through the parasitic capacitance between the gate node and drain node of the transistor 121, and raises the potential of the drain node d of the transistor 121. Therefore, it is efficient to execute the drain set period (D) after the drain node d has risen in potential at the end of the write period (C).

[0112] In the embodiment and the like, the transistors 82 and 86 are provided for the purpose of explanation in comparison with the comparative example, but as described above, they are not necessary in the embodiment and the like, and may be omitted.

[0113] In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14. In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500, but the present invention is not limited to this.

[0114] The channel types of the transistors 64, (82), 84, 85, (86), 87, 121 to 126, etc. are not limited to those in the embodiment, etc. Furthermore, the channels of these transistors, etc. may be changed as appropriate, or may be replaced with transmission gates as appropriate.

[0115] <Electronic equipment> Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

[0116] FIG. 21 is a diagram showing the appearance of a head mounted display, and FIG. 22 is a diagram showing the optical configuration thereof. First, as shown in Fig. 21, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. As shown in Fig. 22, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure). The image display surface of the electro-optical device 10L is disposed to the left in FIG. 22. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0117] In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0118] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, display units of smart watches and wearable devices, light bulbs of projection projectors, and the like, in addition to the head mounted display 300.

[0119] <Additional Notes> From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

[0120] An electro-optical device according to one embodiment (embodiment 1) includes a pixel circuit arranged corresponding to a scanning line and a data line, the pixel circuit having a first transistor and a light-emitting element, the first transistor supplies a current to the light-emitting element corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor during an emission period, the data line is set to a first potential during an initialization period prior to the emission period, the gate node of the first transistor is set to a second potential corresponding to the threshold voltage of the first transistor during a compensation period after the initialization period and before the emission period, the gate node of the first transistor is set to a third potential from the second potential corresponding to the luminance of the light-emitting element during a first period after the compensation period and before the emission period, and the drain node of the first transistor is set to a fourth potential greater than or equal to the first potential and less than the third potential during a second period after the first period and before the emission period.

[0121] The electro-optical device according to the first aspect prevents the charge remaining in the parasitic capacitance at the drain node of the first transistor from flowing into the light-emitting element during the light-emitting period, thereby suppressing weak light emission caused by the flow of charge and making it easier to achieve a high contrast ratio. The transistor 121 is an example of a first transistor. In the first embodiment, the potential Vini is an example of the first potential and the fourth potential. The threshold equivalent potential (Vel-Vth) at the end of the compensation period (B) is an example of the second potential. The writing period (C) is an example of the first period. The potential Vbk supplied to the gate node g of the transistor 121 in the writing period (C) is an example of the third potential. The drain set period (D) is an example of the second period. In the initialization period, the gate node of the first transistor is preferably at the first potential.

[0122] In an electro-optical device according to a specific aspect 2 of aspect 1, the fourth potential is the same as the first potential. In the electro-optical device according to aspect 2, the fourth potential is also used as the first potential, which simplifies the circuit that generates the potential.

[0123] In an electro-optical device according to a specific aspect 3 of aspect 1, the fourth potential is higher than the first potential. When the gate node of the first transistor is at the first potential during the initialization period and at the second potential corresponding to the threshold voltage during the compensation period, various constraints are imposed on the first potential. In the electro-optical device according to aspect 3, a potential separate from the first potential is used as the fourth potential, which increases the degree of freedom in setting the fourth potential. The potential Vini2 in the second embodiment or the potential Vref in the third embodiment is an example of the fourth potential.

[0124] In the electro-optical device according to a fourth specific example of the first example, the drain node of the first transistor is set to the fourth potential via the data line during the second period. The electro-optical device according to a fifth specific aspect of the first aspect includes a second transistor that electrically connects the fourth potential supply line and the drain node of the first transistor during the second period.

[0125] The electro-optical device according to a sixth specific aspect of the first aspect includes a capacitive element having one electrode connected to the drain node of the first transistor and the other electrode connected to a discharge control line. In the electro-optical device according to a seventh specific example of the sixth example, the capacitive element is a metal capacitor. The capacitive element 161 is an example of a metal capacitor. In the electro-optical device according to an eighth specific aspect of the sixth aspect, the capacitive element is a MOS capacitor. The capacitance element 162 is an example of a MOS capacitance.

[0126] An electronic device according to a ninth aspect includes the electro-optical device according to any one of the first to eighth aspects. [Explanation of symbols]

[0127] 10...electro-optical device, 12...scanning line, 14...data line, 14c...data signal output line, 30...control circuit, 50...data signal output circuit, 60...auxiliary circuit, 62...transistor, 70...capacitive element, 72, 150...parasitic capacitance, 80...initialization circuit, 82, 84, 85, 86, 87...transistor, 110...pixel circuit, 120...scanning line driving circuit, 121 to 124, 126...transistor, 130...OLED, 161, 162...capacitive element, 170...discharge control line.

Claims

1. The pixel circuit includes a pixel circuit provided in correspondence with the scanning line and the data line, the pixel circuit includes a first transistor and a light emitting element; The first transistor is supplying a current corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor to the light emitting element during a light emitting period; In an initialization period prior to the light emission period, The data line is set to a first potential; In a compensation period after the initialization period and before the light emission period, a gate node of the first transistor at a second potential corresponding to a threshold voltage of the first transistor; In a first period after the compensation period and before the light emission period, A gate node of the first transistor is changed from the second potential to a third potential corresponding to a luminance of the light-emitting element; In a second period after the first period and before the light emitting period, The drain node of the first transistor is set to a fourth potential that is equal to or higher than the first potential and is lower than the third potential. Electro-optical device.

2. The fourth potential is the same as the first potential.

2. The electro-optical device according to claim 1.

3. The fourth potential is higher than the first potential.

2. The electro-optical device according to claim 1.

4. During the second period, the drain node of the first transistor is set to the fourth potential via the data line.

2. The electro-optical device according to claim 1.

5. a second transistor that electrically connects the fourth potential supply line and the drain node of the first transistor during the second period; 2. The electro-optical device according to claim 1.

6. A capacitance element having one electrode connected to the drain node of the first transistor and the other electrode connected to a discharge control line.

2. The electro-optical device according to claim 1.

7. The capacitive element is Metal capacity 7. The electro-optical device according to claim 6.

8. The capacitive element is It is a MOS capacitor.

7. The electro-optical device according to claim 6.

9. 9. An electronic apparatus comprising the electro-optical device according to claim 1.

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