Display device and control method

Abstract

To provide a display device capable of reducing power consumption during display caused by a low refresh rate while preventing deterioration of an image quality during display caused by a high refresh rate.SOLUTION: A display device comprises: a plurality of scanning lines GL0, ... GLN disposed in parallel in a display region 21H; a first scanning line drive circuit 71 connected to the plurality of scanning lines in one end GLa of the plurality of scanning lines in an extension direction outside of the display region and supplying voltage to the plurality of scanning lines; a second scanning line drive circuit 72 connected to the other end GLb of the plurality of scanning lines in the extension direction outside of the display region and supplying voltage to the plurality of scanning lines; and a control circuit. The control circuit alternately drives the first and second scanning line drive circuits one by one on a predetermined frame basis when a refresh rate in display according to a video signal is a first refresh rate, and drives both the first and second scanning line drive circuits when the refresh rate is a second refresh rate that is higher than the first refresh rate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a display device and a control method. [Background technology]

[0002] As the frame of a liquid crystal display panel becomes narrower, there is a demand for a smaller scanning line driving circuit. Therefore, the output capacity of the scanning line driving circuit tends to become smaller. On the other hand, there is a demand for driving the display at a high refresh rate for use in videos, games, and the like. If the output capacity of the scanning line driving circuit becomes smaller with the miniaturization, there is a risk of image quality deteriorating at a high refresh rate. Japanese Patent Application Laid-Open No. 2012-78127 (hereinafter, Patent Document 1) discloses a substrate in which two gate driving circuits are provided in one TFT array region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-78127 A Summary of the Invention

[0004] There is a demand for preventing degradation of image quality when displaying at a high refresh rate, while reducing power consumption when displaying at a low refresh rate.

[0005] According to one embodiment, a display device includes a plurality of scanning lines arranged side by side within a display area, a first scanning line driving circuit arranged outside the display area, connected to the plurality of scanning lines at one end in the extension direction of the plurality of scanning lines, and supplying a voltage to the plurality of scanning lines, a second scanning line driving circuit arranged outside the display area, connected to the plurality of scanning lines at the other end in the extension direction of the plurality of scanning lines, and supplying a voltage to the plurality of scanning lines, and a control circuit. The control circuit is configured to drive the first scanning line driving circuit and the second scanning line driving circuit alternately one by one for each predetermined frame when a refresh rate of an image displayed according to a video signal is a first refresh rate, and to drive both the first scanning line driving circuit and the second scanning line driving circuit when a second refresh rate higher than the first refresh rate is a second refresh rate.

[0006] Further details will be described in the following embodiments. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a TFT substrate included in a liquid crystal display panel provided in a display device. [Diagram 3] FIG. 3 is a schematic diagram of a control device provided in the display device. [Figure 4] FIG. 4 is a schematic diagram of a GOUT control unit included in a scanning line driving circuit provided in the control device. [Diagram 5] FIG. 5 is a flowchart showing an example of the flow of a control method for a liquid crystal display panel according to an embodiment. [Figure 6] FIG. 6 is a schematic diagram showing the timing at which scan line signals are supplied to a plurality of scan lines at a high refresh rate. [Figure 7] FIG. 7 is a schematic diagram showing the timing at which scan line signals are supplied to a plurality of scan lines at a low refresh rate. [Figure 8]FIG. 8 is a diagram for explaining the relationship between the scanning line signal from the first scanning line driving circuit and the voltages measured at one end and the other end of the scanning line to which a gate-on voltage is applied, at a high refresh rate and a low refresh rate, respectively, in the control method of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <1. Overview of the display device and control method> (1) A display device according to an embodiment includes a plurality of scanning lines arranged side by side within a display area, a first scanning line driving circuit arranged outside the display area, connected to the plurality of scanning lines at one end in the extension direction of the plurality of scanning lines, and supplying a voltage to the plurality of scanning lines, a second scanning line driving circuit arranged outside the display area, connected to the plurality of scanning lines at the other end in the extension direction of the plurality of scanning lines, and supplying a voltage to the plurality of scanning lines, and a control circuit. The control circuit is configured to drive the first scanning line driving circuit and the second scanning line driving circuit alternately one by one for each predetermined frame when a refresh rate of an image displayed in accordance with a video signal is a first refresh rate, and to drive both the first scanning line driving circuit and the second scanning line driving circuit when a second refresh rate higher than the first refresh rate is set.

[0009] In the display device according to the embodiment, the control circuit drives both the first scanning line drive circuit and the second scanning line drive circuit at the second refresh rate, so that voltages are supplied to the multiple scanning lines from both ends by both the first scanning line drive circuit and the second scanning line drive circuit, thereby allowing a sufficient voltage to be supplied to all the scanning lines, and images can be displayed with high display quality.

[0010] In addition, the control circuit alternately drives the first scanning line drive circuit and the second scanning line drive circuit one at a time for each predetermined frame at the first refresh rate, so that at the first refresh rate, half of the scanning line drive circuits at the second refresh rate stop driving. Therefore, this control method achieves both high image quality and low power consumption at a high refresh rate.

[0011] In addition, in the configuration according to this embodiment, the first scanning line driving circuit and the second scanning line driving circuit are alternately driven for a predetermined number of frames at the first refresh rate, which prevents the same voltage from being continuously applied to the switching elements in the scanning line driving circuit, as compared with a case where only one of the first scanning line driving circuit and the second scanning line driving circuit is driven for a long period of time at the first refresh rate while the other is stopped, thereby suppressing a shift in the threshold of the switching elements.

[0012] (2) In the display device of (1), preferably, the control circuit is further configured to determine whether the refresh rate is the first refresh rate or the second refresh rate based on synchronization signal information for the video signal, thereby making it possible to switch between controls for each refresh rate according to the video signal.

[0013] (3) Preferably, in the display device of (1) or (2), alternately driving the first scanning line drive circuit and the second scanning line drive circuit includes supplying a gate-on voltage to the scanning line for a longer time when the refresh rate of an image displayed according to a video signal is the first refresh rate than the time when the first scanning line drive circuit and the second scanning line drive circuit supply the gate-on voltage to the scanning line at the second refresh rate. As a result, at the first refresh rate, the gate-on voltage is applied only from one end of the scanning line, but the supply time of the gate-on voltage is long, so that the entire scanning line can be sufficiently charged. As a result, a high-quality display can be realized even when displaying at the first refresh rate.

[0014] (4) Preferably, in the display device described in any one of (1) to (3), the first scanning line drive circuit and the second scanning line drive circuit each include a switch arranged in a voltage supply path to the scanning line, and driving the first scanning line drive circuit and the second scanning line drive circuit alternately, one at a time, for each predetermined frame includes turning on a switch in one of the first scanning line drive circuit and the second scanning line drive circuit and turning off a switch in the other of the first scanning line drive circuit and the second scanning line drive circuit, for each predetermined frame.

[0015] As a result, at the first refresh rate, the first scanning line drive circuit and the second scanning line drive circuit alternate between a state in which the gate-on voltage is supplied to the scanning line and a state in which the gate-on voltage is not supplied to the scanning line for each predetermined frame. When the switch is turned off, the supply of the gate-on voltage from the scanning line drive circuit on the other side to the scanning line is cut off, and the scanning line is placed in a high impedance state. This maintains the gate-on voltage supplied to the scanning line from the scanning line drive circuit on the one side whose switch is turned on. This ensures the display quality at the first refresh rate.

[0016] (5) A control method according to an embodiment is a control method for a liquid crystal display panel having a plurality of scanning lines arranged side by side within a display area, and first and second scanning line drive circuits arranged outside the display area and supplying a voltage to the plurality of scanning lines. The first scanning line drive circuit is connected to the plurality of scanning lines at one end in the extension direction of the plurality of scanning lines, and the second scanning line drive circuit is connected to the plurality of scanning lines at the other end in the extension direction of the plurality of scanning lines. The control method includes driving the first scanning line drive circuit and the second scanning line drive circuit alternately one at a time for each predetermined frame when a refresh rate of an image displayed according to a video signal is a first refresh rate, and driving both the first scanning line drive circuit and the second scanning line drive circuit when a second refresh rate higher than the first refresh rate is a second refresh rate. This realizes a balance between image quality and low power consumption at a high refresh rate in the display device.

[0017] <2. Examples of display devices and control methods> [First embodiment] 1 is a schematic cross-sectional view showing an example of the configuration of a display device 100 according to this embodiment. The display device 100 includes a liquid crystal display panel 10 and a control device 50. The liquid crystal display panel 10 includes a TFT (Thin Film Transistor) substrate 20 that is a glass substrate, a color filter (CF) substrate 30 that is an opposing substrate, and a liquid crystal layer 40 between the TFT substrate 20 and the CF substrate 30. The control device 50 includes a signal line driving circuit (source driver) 60, a first scanning line driving circuit (gate driver) 71 (see FIGS. 2 and 3), a second scanning line driving circuit 72 (see FIGS. 2 and 3), and a display controller 80.

[0018] 2 is a schematic diagram of the TFT substrate 20. The TFT substrate 20 includes a substrate 21 and a plurality of (for example, N+1) scanning lines (gate bus lines) GL0, GL1, GL2, ... GLN. The scanning lines GL0, GL1, GL2, ... GLN are also referred to as scanning lines GL. The TFT substrate 20 also includes a plurality of signal lines (source bus lines) SL and a plurality of pixels PX. The substrate 21 includes a display region 21H and a non-display region (frame region) 21G which is a region other than the display region 21H. The non-display region 21G is disposed on the outer periphery of the display region 21H, and is preferably disposed so as to surround the periphery of the display region 21H.

[0019] A plurality of scanning lines GL, a plurality of signal lines SL, and a plurality of pixels PX are arranged in a display region 21H. In detail, the plurality of scanning lines GL extend in a first direction, which is the row direction in the figure, and are arranged at a predetermined interval in a second direction perpendicular to the first direction, which is the column direction in the figure. The plurality of scanning lines GL are arranged in the second direction from one end (for example, the upper end of FIG. 2) in the order of scanning lines GL0, GL1, GL2, ... GLN.

[0020] The signal lines SL extend in the second direction and are arranged at a predetermined interval in the first direction. The pixels PX are arranged in an area surrounded by a pair of adjacent scanning lines GL and a pair of adjacent signal lines SL. The pixels PX are arranged two-dimensionally in the first and second directions.

[0021] The pixel PX includes a pixel electrode PE and a switching element SW. The switching element SW is, for example, a three-terminal element, and a scanning line GL, a signal line SL, and a pixel electrode PE are connected to three terminals, respectively. The switching element SW is, for example, a TFT. The gate electrode of the TFT is connected to the scanning line GL, the source electrode is connected to the signal line SL, and the drain electrode is connected to the pixel electrode PE. Each scanning line GL is connected to the gate electrode of the TFT of the pixel PX arranged in the first direction among the multiple pixels PX. Also, each signal line SL is connected to the source electrode of the TFT of the pixel PX arranged in the second direction among the multiple pixels PX.

[0022] In the non-display area 21G, a signal line driving circuit 60, a first scanning line driving circuit 71, and a second scanning line driving circuit 72 are arranged. The first scanning line driving circuit 71 is arranged on one end GLa side of the scanning line GL and connected to the one end GLa, and the second scanning line driving circuit 72 is arranged on the other end GLb side of the scanning line GL and connected to the other end GLb. The signal line driving circuit 60 is connected to the signal line SL. As an example, two signal line driving circuits 60, one on the left side and one on the right side, are arranged in the non-display area 21G and are respectively connected to the left half signal line SL and the right half signal line SL. The signal line driving circuit 60, the first scanning line driving circuit 71, and the second scanning line driving circuit 72 are connected to the display controller 80 via a flexible printed circuit (FPC) 90. As an example, two FPCs 90 are provided on the left and right sides, respectively connecting the first scanning line driving circuit 71, the left signal line driving circuit 60, and the display controller 80, and the second scanning line driving circuit 72, the right signal line driving circuit 60, and the display controller 80.

[0023] 3 is a schematic diagram of the control device 50. The control device 50 receives a video signal Dp from the host device 200, and controls the driving of the scanning lines GL and signal lines SL of the liquid crystal display panel 10. The host device 200 is a device equipped with the display device 100, and is composed of one or more computers including a processor 201 such as a CPU (Central Processing Unit), for example.

[0024] The display controller 80 is a control circuit that controls the display on the liquid crystal display panel 10. The display controller 80 receives a control signal Dc and a video signal Dp from the host device 200. The control signal Dc includes synchronization signal information for the video signal Dp. The synchronization signal information includes basic clock frequency information, resolution information, vertical blanking interval information, and horizontal blanking interval information. The display controller 80 generates a frame signal Dg and a display data signal Dd from the video signal Dp. The frame signal Dg is a signal that indicates the start point of each frame, and is a signal for synchronizing the timing at which the scanning line driving circuits 71 and 72 output a gate signal (a gate-on voltage GHi or a gate-off voltage GLo, described later) to the scanning line GL.

[0025] The display device 100 can display images at a plurality of refresh rates. The plurality of refresh rates include a low refresh rate (first refresh rate) and a high refresh rate (second refresh rate) higher than the first refresh rate. The combination of the first refresh rate and the second refresh rate is arbitrary. As an example, the first refresh rate may be 30 Hz, and the second refresh rate may be 60 Hz. As another example, the first refresh rate may be 60 Hz, and the second refresh rate may be 120 Hz. As another example, the first refresh rate may be 30 Hz or 60 Hz, and the second refresh rate may be 120 Hz. As another example, the first refresh rate may be 30 Hz, and the second refresh rate may be 60 Hz or 120 Hz. Note that each of the above rate values ​​is an example, and may be arbitrary.

[0026] The display controller 80 analyzes basic clock frequency information, resolution information, and blanking interval information included in the control signal Dc, and determines the refresh rate when displaying an image according to the video signal Dp. The display controller 80 outputs a scanning line switching signal (hereinafter, GOUT control signal) Ds according to the result of the refresh rate determination. The display controller 80 also outputs a display data signal Dd to the signal line drive circuit 60 according to the result of the refresh rate determination. The display data signal Dd is supplied (written) to the pixel PX by the signal line drive circuit 60.

[0027] The display controller 80 outputs a frame signal Dg and a GOUT control signal Ds to the scanning line driving circuits 71 and 72. At this time, the display controller 80 outputs different GOUT control signals Ds to the scanning line driving circuits 71 and 72 depending on the result of the determination of the refresh rate.

[0028] The GOUT control signal Ds is a signal for controlling the driving of the first scanning line driving circuit 71 and the second scanning line driving circuit 72, and is, for example, an enable signal. The enable signal switches between a high level and a low level. When the determination result of the refresh rate is a high refresh rate, the display controller 80 outputs a high-level GOUT control signal Ds to both the scanning line driving circuits 71 and 72.

[0029] When the determination result of the refresh rate is a low refresh rate, the display controller 80 outputs a high-level GOUT control signal Ds to one of the scanning line driving circuits 71 and 72 and a low-level GOUT control signal Ds to the other. Of the scanning line driving circuits 71 and 72, the one to which the high-level GOUT control signal Ds is applied supplies a scanning line signal to be described later to the scanning line, and the other to which the low-level GOUT control signal Ds is applied stops. The display controller 80 repeats a state (first state) in which the first scanning line driving circuit 71 outputs a high-level GOUT control signal Ds to output a low-level GOUT control signal Ds to the second scanning line driving circuit 72 at a predetermined timing, and a state (second state) in which the second scanning line driving circuit 72 outputs a high-level GOUT control signal Ds to output a low-level GOUT control signal Ds to the first scanning line driving circuit 71. The predetermined timing is, for example, every frame indicated by a frame signal Dg generated from a video signal Dp.

[0030] The scanning line driving circuits 71 and 72 receive a frame signal Dg from the display controller 80, and apply scanning line signals (gate signals) to the multiple scanning lines GL based on the frame signal Dg. In detail, the first scanning line driving circuit 71 applies scanning line signals LGn0, LGn1, LGn2, ... LGnN from one end GLa side to each of the scanning lines GL0, GL1, GL2, ... GLN. The second scanning line driving circuit 72 applies scanning line signals RGn0, RGn1, RGn2, ... RGnN from the other end GLb side to each of the scanning lines GL0, GL1, GL2, ... GLN.

[0031] The scanning line signal is a voltage applied to the scanning line GL, and the scanning line signals LGn0, LGn1, LGn2, ... LGnN are voltages that the first scanning line driving circuit 71 applies to the scanning lines GL0, GL1, GL2, ... GLN from one end GLa, and the scanning line signals RGn0, RGn1, RGn2, ... RGnN are voltages that the second scanning line driving circuit 72 applies to the scanning lines GL0, GL1, GL2, ... GLN from the other end GLb. The scanning line signals LGn0, LGn1, LGn2, ... LGnN are also referred to as the scanning line signal LGn, and the scanning line signals RGn0, RGn1, RGn2, ... RGnN are also referred to as the scanning line signal RGn. The scanning line signals LGn and RGn are either a gate-on voltage GHi or a gate-off voltage GLo. The scanning line driving circuits 71 and 72 receive a gate-on voltage GHi and a gate-off voltage GLo from a power supply circuit (not shown) and apply them to the scanning lines GL.

[0032] The TFT (switching element SW of the pixel PX) is in the ON state while a gate-on voltage GHi is applied to the gate electrode from the scanning line GL. The TFT is in the OFF state while a gate-off voltage GLo lower than the gate-on voltage GHi is applied. The ON state of the TFT indicates a state in which a display data signal Dd can be supplied to the pixel PX by the signal line driving circuit 60.

[0033] Applying the scanning line signal to the scanning lines GL based on the frame signal Dg means that the scanning line driving circuits 71 and 72 apply the gate-on voltage GHi to the multiple scanning lines GL in sequence based on the frame signal Dg, and apply the gate-off voltage GLo to the other scanning lines GL. As a result, the display data signal Dd output based on the video signal Dp is written to the pixels PX in sequence by the signal line driving circuit 60.

[0034] The scanning line driving circuits 71 and 72 each have a GOUT control unit 73. Fig. 4 is a schematic configuration diagram of the GOUT control unit 73. The GOUT control unit 73 includes a switch 731L which is a TFT arranged in a connection path between the first scanning line driving circuit 71 and each one end GLa of the multiple scanning lines GL, and a switch 731R which is a TFT arranged in a connection path between the second scanning line driving circuit 72 and each other end GLb. The switches 731L and 731R are collectively referred to as switch 731.

[0035] The switch 731 is switched on and off according to a GOUT control signal Ds from the display controller 80. That is, the switch 731 is switched on when the GOUT control signal Ds is at a high level, and switched off when the GOUT control signal Ds is at a low level. When the GOUT control signal Ds output to the first scanning line driving circuit 71 is at a high level, the switch 731L is switched on. When the GOUT control signal output to the second scanning line driving circuit 72 is at a high level, the switch 731R is switched on. This switches the application of the scanning line signals in each of the scanning line driving circuits 71 and 72. When the switch 731 is switched on, the scanning line driving circuits 71 and 72 are electrically connected to the multiple scanning lines GL. Therefore, the gate-on voltage GHi or the gate-off voltage GLo applied from the scanning line driving circuits 71 and 72 according to the frame signal Dg is supplied to each of the multiple scanning lines GL.

[0036] When the switch 731 is turned off, the scanning line driving circuits 71 and 72 are disconnected from the multiple scanning lines GL. Therefore, all of the multiple scanning lines GL are in a high impedance state (Hi-Z). The high impedance state of the scanning lines GL means that the output from the scanning line driving circuits 71 and 72 is in an electrically open state. At this time, the gate-on voltage GHi or the gate-off voltage GLo applied from the scanning line driving circuits 71 and 72 in accordance with the frame signal Dg is not supplied to any of the multiple scanning lines GL. In other words, the scanning line driving circuits 71 and 72 with the switch 731 turned off do not apply a voltage to any of the multiple scanning lines GL.

[0037] Specifically, in the first state, the gate-on voltage GHi or the gate-off voltage GLo applied by the first scanning line driving circuit 71 based on the frame signal Dg is supplied to each of the multiple scanning lines GL from one end GLa. Since the second scanning line driving circuit 72 is disconnected from the multiple scanning lines GL, no voltage is applied to any of the multiple scanning lines from the other end GLb.

[0038] In the second state, the gate-on voltage GHi or the gate-off voltage GLo applied by the second scanning line driving circuit 72 based on the frame signal Dg is supplied to each of the multiple scanning lines GL from the other end GLb. Since the first scanning line driving circuit 71 is disconnected from the multiple scanning lines GL, no voltage is applied to any of the multiple scanning lines from the one end GLa.

[0039] 5 is a flowchart showing an example of the flow of a control method for the liquid crystal display panel 10 according to the present embodiment. When the display controller 80 receives a control signal Dc and a video signal Dp from the host device 200 (YES in step S101), the display controller 80 generates a frame signal Dg and a display data signal Dd from the video signal Dp (step S103). The display controller 80 outputs the generated frame signal Dg to both the first scanning line driving circuit 71 and the second scanning line driving circuit 72 (step S104).

[0040] The display controller 80 analyzes the control signal Dc and determines the refresh rate when displaying an image according to the video signal Dp (step S105). If the refresh rate is the high refresh rate (NO in step S107), the display controller 80 outputs a high-level GOUT control signal Ds to both the first scanning line driving circuit 71 and the second scanning line driving circuit 72 (step S109).

[0041] If the refresh rate is a low refresh rate (YES in step S107), the display controller 80 outputs a high-level GOUT control signal Ds to one scanning line drive circuit, and outputs a low-level GOUT control signal Ds to the other scanning line drive circuit (step S111). In detail, in step S111, the display controller 80 outputs a GOUT control signal Ds to each scanning line drive circuit at a level opposite to the level of the GOUT control signal Ds output to each scanning line drive circuit in the immediately preceding frame. As a result, in the case of a low refresh rate, the GOUT control signal Ds is output alternately at a high level and a low level to the first scanning line drive circuit 71 and the second scanning line drive circuit 72.

[0042] Fig. 6 and Fig. 7 are schematic diagrams showing the timing at which scanning line signals are supplied to a plurality of scanning lines GL. Fig. 6 is a schematic diagram showing the timing at a high refresh rate, and Fig. 7 is a schematic diagram showing the timing at a low refresh rate. In Fig. 6 and Fig. 7, the horizontal direction represents the passage of time. Fig. 6 and Fig. 7 are timing diagrams showing the relationship between signals S1 to S3 (and signals S4 and S5 in Fig. 7), scanning line signals LGn0, LGn1, LGn2, ... LGnN, and scanning line signals RGn0, RGn1, RGn2, ... RGnN.

[0043] Signal S1 represents a video signal Dp from the host device 200. In Fig. 6 and Fig. 7, an example is shown in which the control device 50 receives the video signal Dp from the host device 200 for each frame, from frames F1 to F5. At a high refresh rate (Fig. 6), one frame corresponds to, for example, 120 Hz. At a low refresh rate (Fig. 7), one frame corresponds to, for example, 30 Hz.

[0044] The signal S2 represents a frame signal Dg generated from the video signal Dp. The frame signal Dg of each of the frames F1 to F5 represents the start point of each frame.

[0045] A signal S3 is a display data signal Dd, and indicates the timing at which it is supplied to the pixel PX by the signal line drive circuit 60. The display data signal Dd is supplied to the pixel PX by the signal line drive circuit 60 in response to each of the frame signals Dg of the frames F1 to F5.

[0046] At a high refresh rate (FIG. 6), in each frame, the gate-on voltage GHi is sequentially supplied to the scanning line GL from both the first scanning line driving circuit 71 and the second scanning line driving circuit 72. That is, at a high refresh rate, the gate-on voltage GHi is applied to the scanning line GL from both ends by each of the scanning line driving circuits 71 and 72 for each frame.

[0047] Due to the resistance component and parasitic capacitance component of the scanning line GL, the voltage waveform is disturbed and a delay occurs in the signal at a position far from the end of the scanning line GL connected to the scanning line driving circuit. Therefore, the time during which the TFT connected to the scanning line GL is maintained in the on state may be shortened. However, when the scanning line driving circuits 71 and 72 each supply the gate-on voltage GHi to the scanning line GL from both ends at a high refresh rate, a sufficient voltage is supplied to the entire scanning line GL, and the gate-on voltage GHi is easily applied to each TFT. As a result, the display device 100 can display images with high display quality in response to a high refresh rate.

[0048] At the time of a low refresh rate (FIG. 7), signals S4 and S5 represent the GOUT control signal Ds. The signal S4 represents the GOUT control signal Ds that the display controller 80 outputs to the first scanning line driving circuit 71. The signal S5 represents the GOUT control signal Ds that the display controller 80 outputs to the second scanning line driving circuit 72. In this example, the signal S4 is at a high level and the signal S5 is at a low level in frame F1, the signal S4 is at a low level and the signal S5 is at a high level in frame F2, the signal S4 is at a high level and the signal S5 is at a low level in frame F3, and so on are repeated alternately.

[0049] During a low refresh rate, in frame F1, the second scanning line driving circuit 72 does not apply the scanning line signals RGn0, RGn1, RGn2, ... RGnN to any of the multiple scanning lines GL in accordance with a low-level signal S5, and all of the multiple scanning lines GL are in a high impedance state (Hi-Z). On the other hand, the first scanning line driving circuit 71 sequentially supplies a gate-on voltage GHi to the multiple scanning lines GL in accordance with a high-level signal S4, and supplies a gate-off voltage GLo at other times.

[0050] In frame F2, the first scanning line driving circuit 71 does not apply the scanning line signals LGn0, LGn1, LGn2, ... LGnN to any of the multiple scanning lines GL in response to the low level signal S4, resulting in a high impedance state. Meanwhile, the second scanning line driving circuit 72 sequentially supplies the gate-on voltage GHi to the multiple scanning lines GL in response to the high level signal S5, and supplies the gate-off voltage GLo at other times.

[0051] In frames F3 and F5, the voltage is applied in the same state as in frame F1, and in frame F4, the voltage is applied in the same state as in frame F2. Therefore, in the case of a low refresh rate, the first scanning line driving circuit 71 and the second scanning line driving circuit 72 are driven one by one for each frame. As a result, at the time of a low refresh rate, half of the scanning line driving circuits are stopped from driving, so that the power of the stopped scanning line driving circuits can be reduced. As a result, energy saving is realized compared to the case where both are driven.

[0052] As a comparative example of reducing power by stopping the driving of one of the scanning line driving circuits, a control method of stopping the driving of only one of the first scanning line driving circuit 71 and the second scanning line driving circuit 72 and driving only the other is considered. In the control method according to this comparative example, either an on voltage or an off voltage is constantly applied to the switch 731 of the scanning line driving circuit that is stopped and the transistors that constitute the scanning line output circuit. Therefore, the threshold shift of the switch 731 of the scanning line driving circuit that is stopped and the transistors that constitute the scanning line output circuit is larger than that of the switch 731 of the scanning line driving circuit that is driven and the transistors that constitute the scanning line output circuit.

[0053] In contrast, in the control method according to the present embodiment, during a low refresh rate, voltages are alternately supplied to the scanning lines GL from the first scanning line driving circuit 71 and the second scanning line driving circuit 72. This causes voltages to be alternately applied to the switches 731 of the first scanning line driving circuit 71 and the second scanning line driving circuit 72. As a result, the shift in the threshold value is suppressed.

[0054] If one scanning line driving circuit supplies a gate-off voltage GLo from one end in accordance with the GOUT control signal Ds at a low refresh rate, the gate-on voltage GHi is not sufficiently supplied to the entire scanning line GL even if the other scanning line driving circuit supplies a gate-on voltage GHi from the other end. In this regard, in the control method according to the present embodiment, the switch 731 of the scanning line driving circuits 71 and 72 is turned on and off in accordance with the GOUT control signal Ds, so that the end of the scanning line GL to which no voltage is supplied is electrically opened. Therefore, in the control method according to the present embodiment, the gate-on voltage GHi is sufficiently supplied to the entire scanning line GL compared to the control in which the gate-off voltage GLo is supplied from one end in accordance with the GOUT control signal Ds at a low refresh rate. Therefore, the display quality at a low refresh rate can be ensured. [Second embodiment] In the control method according to the second embodiment, the display controller 80 makes the time (application time) for supplying the gate-on voltage GHi in each of the first scanning line driving circuit 71 and the second scanning line driving circuit 72 longer at the time of the low refresh rate than the application time of the gate-on voltage GHi at the time of the high refresh rate. This is because at the time of the low refresh rate, it is possible to set the horizontal period longer than at the time of the high refresh rate.

[0055] The control method according to the second embodiment includes, for example, sending a control signal Dg1 from the display controller 80 to each of the first scanning line drive circuit 71 and the second scanning line drive circuit 72, which increases the application time of the gate-on voltage GHi. That is, for example, the display controller 80 outputs a frame signal Dg at a high refresh rate, and outputs the frame signal Dg and the control signal Dg1 at a low refresh rate. The control signal Dg1 is a control signal that increases the application time of the gate-on voltage GHi.

[0056] 8 is a diagram for explaining the relationship between the scanning line signal LGn from the first scanning line driving circuit 71 and the voltages measured at one end GLa and the other end GLb of the scanning line GL to which the gate-on voltage GHi is applied, respectively, at a high refresh rate and a low refresh rate, in the control method according to the second embodiment. Waveform E is a schematic diagram of the waveform of the scanning line signal LGn at a high refresh rate, and waveform F is a schematic diagram of the waveform of the scanning line signal LGn at a low refresh rate. Waveform A is a schematic diagram of the voltage waveform measured at one end GLa of the scanning line GL at a high refresh rate, waveform B is a schematic diagram of the voltage waveform measured at the other end GLb of the scanning line GL at a high refresh rate, waveform C is a schematic diagram of the voltage waveform measured at one end GLa of the scanning line GL at a low refresh rate, and waveform D is a schematic diagram of the voltage waveform measured at the other end GLb of the scanning line GL at a low refresh rate. In FIG. 8, the horizontal axis represents time (t) and the vertical axis represents voltage (V).

[0057] The voltage value Vt is the threshold voltage at which the TFT of the pixel PX is turned on. When the gate-on voltage GHi is applied to the scanning line GL and the voltage value applied to the gate electrode of the TFT reaches the voltage value Vt, the TFT is turned on. The TFT is maintained in the on state while the voltage value applied to the gate electrode is above the voltage value Vt. When the application of the gate-on voltage GHi to the scanning line GL is terminated and the voltage value falls below the voltage value Vt, the TFT transitions to the off state. The period during which the TFT is maintained in the on state is also referred to as the on time.

[0058] As shown by comparing the waveforms A and B and the waveforms C and D, the pulse shape of the scanning line signal LGn is maintained at a position close to the first scanning line driving circuit 71, but due to the resistance component and parasitic capacitance component of the scanning line GL, the voltage applied to the gate electrode of the TFT does not steeply follow the rising edge of the scanning line signal LGn at a position far from the first scanning line driving circuit 71, and it takes time to reach the threshold voltage Vt. Therefore, the on-time t3 of the waveform B at a position far from the first scanning line driving circuit 71 is shorter than the on-time t1 of the waveform A at a position close to the first scanning line driving circuit 71. Also, the on-time t4 of the waveform D at a position far from the first scanning line driving circuit 71 is shorter than the on-time t2 of the waveform C at a position close to the first scanning line driving circuit 71.

[0059] In the control method according to the second embodiment, the application time H2 of the gate-on voltage GHi at a low refresh rate is longer than the application time H1 of the gate-on voltage GHi at a high refresh rate (H1 <H2)。

[0060] At this time, as can be seen from waveforms C and D, a sufficient TFT on time can be ensured even at a position on the scanning line GL far from the first scanning line driving circuit 71. As a result, a sufficient pixel writing time can be ensured even at a position far from the first scanning line driving circuit 71, and display quality can be ensured. [Third embodiment] The switching of the driving between the first scanning line driving circuit 71 and the second scanning line driving circuit 72 at the time of the low refresh rate is not limited to every frame. As another example, it may be every arbitrary frame. For example, the driving between the first scanning line driving circuit 71 and the second scanning line driving circuit 72 may be switched every two frames.

[0061] The display controller 80 according to the third embodiment has a counter (not shown) as an example, and counts the number of frame signals Dg. When the counted number of frame signals Dg reaches a number stored in advance as the number of drive switching between the first scanning line drive circuit 71 and the second scanning line drive circuit 72, the display controller 80 outputs a high-level GOUT control signal Ds to a scanning line drive circuit on the opposite side to the scanning line drive circuit that output the high-level GOUT control signal Ds in the previous frame.

[0062] <3. Notes> The present invention is not limited to the above-described embodiment, and various modifications are possible. [Explanation of symbols]

[0063] 10: liquid crystal display panel, 21G: non-display area, 21H: display area, 50: control device, 71: first scanning line drive circuit, 72: second scanning line drive circuit, 73: GOUT control section, 80: display controller (control circuit), 100: display device, 731, 731L, 731R: switches, Dg: frame signal, Dp: video signal, Ds: GOUT control signal, GHi: gate-on voltage, GL, GL0, GL1, GL2,: scanning lines, GLa: one end, GLb: other end, GLo: gate-off voltage

Claims

1. A plurality of scanning lines arranged side by side within a display area; a first scanning line driving circuit arranged outside the display area, connected to the plurality of scanning lines at one end in an extension direction of the plurality of scanning lines, and supplying a voltage to the plurality of scanning lines; a second scanning line driving circuit that is disposed outside the display area, is connected to the plurality of scanning lines at the other end in the extension direction of the plurality of scanning lines, and supplies a voltage to the plurality of scanning lines; A control circuit, The control circuit is configured to alternately drive the first scanning line drive circuit and the second scanning line drive circuit one by one for each predetermined frame when a refresh rate of an image displayed in accordance with a video signal is a first refresh rate, and to drive both the first scanning line drive circuit and the second scanning line drive circuit when a refresh rate of an image displayed in accordance with a video signal is a second refresh rate higher than the first refresh rate. Display device.

2. The control circuit is further configured to determine whether the refresh rate is the first refresh rate or the second refresh rate based on synchronization signal information for the video signal. The display device according to claim 1 .

3. Driving the first scanning line drive circuit and the second scanning line drive circuit alternately includes, when a refresh rate of an image displayed according to a video signal is the first refresh rate, causing the first scanning line drive circuit and the second scanning line drive circuit to supply a gate-on voltage to the scanning line for a time longer than a time for which the first scanning line drive circuit and the second scanning line drive circuit supply a gate-on voltage to the scanning line when the refresh rate is the second refresh rate. The display device according to claim 1 .

4. the first scanning line driving circuit and the second scanning line driving circuit each include a switch disposed in a voltage supply path to the scanning line; Driving the first scanning line drive circuit and the second scanning line drive circuit alternately one by one for each of the predetermined frames includes turning on the switch in one of the first scanning line drive circuit and the second scanning line drive circuit and turning off the switch in the other of the first scanning line drive circuit and the second scanning line drive circuit for each of the predetermined frames. The display device according to claim 1 .

5. A method for controlling a liquid crystal display panel having a plurality of scanning lines arranged side by side within a display area, and first and second scanning line drive circuits arranged outside the display area and supplying voltages to the plurality of scanning lines, comprising: the first scanning line driving circuit is connected to the plurality of scanning lines at one end in an extension direction of the plurality of scanning lines; the second scanning line driving circuit is connected to the plurality of scanning lines at the other end in the extension direction of the plurality of scanning lines, When a refresh rate of an image to be displayed in accordance with a video signal is a first refresh rate, the first scanning line drive circuit and the second scanning line drive circuit are alternately driven one by one for each predetermined frame, and when a refresh rate of an image to be displayed in accordance with a video signal is a second refresh rate higher than the first refresh rate, both the first scanning line drive circuit and the second scanning line drive circuit are driven. Control methods.

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