Synchronized System-on-Chip Telemetry Aggregation and Buffering

Abstract

Embodiments of the present disclosure include techniques for synchronized telemetry aggregation and buffering in a system-on-chip (SoC). A first set of telemetry data associated with the operation of a plurality of processor cores of the SoC during a first epoch is received. A second set of telemetry data associated with the operation of the plurality of processor cores during a second epoch is received. The first set of telemetry data is determined to correspond to an incomplete set of telemetry data for the first epoch. As a result of the determination, a message is transmitted to one or more controllers of the plurality of processor cores to modify an operation associated with telemetry data collection.

Description

Technical Field

[0001] This disclosure relates to computing systems. More particularly, this disclosure relates to techniques for aggregating and buffering telemetry data for system-on-chips.

Background Art

[0002] Some system-on-chip (SoC) designs implement the design using many processor cores.

Summary of the Invention

[0003] In such designs, it may be beneficial to monitor the telemetry parameters of processor cores to capture raw information for various purposes. Tracking telemetry data, and the timing between telemetry data sets, is a difficult and complex problem. The high sampling rates used in modern SoCs may make it difficult to detect missing telemetry data, or imbalances within the telemetry data storage. Moreover, it may become difficult to determine which processor core is associated with the telemetry data, and which processor core is responsible for errors associated with the telemetry data.

Brief Description of the Drawings

[0004]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Figure 10

DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. Such examples and details are not to be construed as overly limiting the elements of the claims or the claimed subject matter as a whole. The claimed subject matter can, singly or in combination, include some or all of the features in these examples, and can further include modifications and equivalents of the features and techniques described herein, which will be apparent to those skilled in the art based on the language of the different claims.

[0006] Embodiments herein relate to techniques for synchronizing telemetry data obtained in connection with the operation of multiple processor elements of a system-on-chip (SoC). In an SoC with multiple processing elements, monitoring various telemetry parameters of the processing elements can capture raw information that can be used, as non-limiting examples, for system management, error detection, and determination of discovery methods of operation. The present disclosure provides techniques implemented via hardware and software to generate independent streams of telemetry from the processing elements, align the telemetry data received during a given measurement epoch, and implement one or more data structures for processing the telemetry data. Embodiments of the present disclosure also provide support for high sampling rates and handling of telemetry data for overlapping measurement epochs. Features of the present disclosure enable detection of missing data, detection of overrun conditions, and establishment of a synchronization state for telemetry.

[0007] As used herein, the term "epoch" refers to the period during which temporally related local telemetry data from all tiles or cores of a system-on-chip architecture is received and stored by a telemetry processing engine.

[0008] FIG. 1 illustrates a system-on-chip (SoC) architecture 100 that provides telemetry data aggregation and buffering according to one or more embodiments. The SoC architecture 100 includes a plurality of mesh nodes 102-1, 102-2, ... 102-N (collectively "mesh nodes 102"), and a plurality of channels 104 for communicating telemetry data between adjacent nodes of the mesh nodes 102. Each of the mesh nodes 102 is associated with a set of processor cores or processing elements 106-1, 106-2, ... 106-N (collectively "processor cores 106") where telemetry data is collected. For example, the set of processor cores 106 associated with mesh node 102-1 excludes the set of processor cores 106 associated with mesh node 102-2 from each other.

[0009] The SoC architecture 100 also includes a plurality of tile sensor controllers 108, each associated with an individual node of the mesh nodes 102. Each tile sensor controller 108 is associated with and can process telemetry data for a set of processor cores 106 of a single node of the mesh nodes 102. Each tile sensor controller 108 receives measurements of one or more telemetry parameters (e.g., temperature, voltage, current) for the associated node and its processor cores 106, generates telemetry data based on the received measurements, and provides the telemetry data to the associated mesh node 102 and its processor cores 106. In some embodiments, the tile sensor controller 108 can control or initiate adjustments that affect the telemetry parameters. For example, the tile sensor controller 108 can adjust the current, clock frequency, or voltage applied to the processor core 106 in response to determining that the temperature, current, or voltage of the processor core 106 has exceeded a specified threshold. As used herein, the term "tile" refers to an aggregate of one or more processor cores, a telemetry data sampling device, and a telemetry data router associated with a single mesh node of the mesh nodes 102. Further explanation of tiles is provided with respect to FIG. 3 and elsewhere in this specification.

[0010] The SoC architecture 100 further includes a telemetry processing engine 110 that receives telemetry data 112 including telemetry data 114 collected by some or all of the mesh nodes 102 during a given epoch. A subset of the mesh nodes 102 receives telemetry data 114 from one or more mesh nodes and transmits the received telemetry data, along with its own telemetry data, to other mesh nodes. The telemetry processing engine 110 receives telemetry data 112 from a designated node among the mesh nodes 102 as a result of the telemetry data 114 being transmitted through the mesh nodes 102. The mesh node 102-9 is a node assigned from among the plurality of mesh nodes 102 to provide the telemetry data 112 to the telemetry processing engine 110.

[0011] The mesh nodes 102 can communicate with each other via channels 104 to determine how telemetry data is transmitted through the mesh nodes 102. During a given epoch, a set of adjacent nodes can be designated to which an individual node among the mesh nodes 102 will receive telemetry data 114. Another adjacent node is designated to which the individual node will send its telemetry data 114, along with the telemetry data received from the set of adjacent nodes during a given epoch. The telemetry data 114 generated for each mesh node 102 includes sensor data indicating measured temperature, voltage, and / or current associated with a set of associated processor cores 106. The telemetry data 114 generated for each mesh node 102 includes, in some embodiments, performance data indicating the performance level at which the associated set of processor cores 106 is operable, and / or consumption data indicating the power consumption level of the associated set of processor cores 106.

[0012] As a specific non-limiting example, mesh node 102-1 generates telemetry data 114-1 for that set of processor cores 106 and sends the telemetry data 114-1 to adjacent mesh node 102-4. Mesh node 102-4 also generates telemetry data 114-4 for that associated set of processor cores 106 and sends the telemetry data 114-4 to adjacent mesh node 102-7. Mesh node 102-4 can also send the telemetry data 114-1 received from mesh node 102-1 to mesh node 102-7. Mesh node 102-7 generates telemetry data 114-7 for that associated set of processor cores 106 and sends the telemetry data 114-7 to adjacent mesh node 102-8. Mesh node 102-7 can also send the telemetry data 114-4 and / or telemetry data 114-1 received from mesh node 102-4 to adjacent mesh node 102-8. Mesh node 102-8 generates telemetry data 114-8 for that associated set of processor cores 106 and sends the telemetry data 114-8 to mesh node 102-9. Mesh node 102-8 can also send the telemetry data 114-1, 114-4, 114-7, and / or 114-8 received from adjacent mesh nodes 102-7 and 102-5 to mesh node 102-9. Mesh node 102-9 can also receive the telemetry data 114-2 generated by mesh node 102-2, the telemetry data 114-3 generated by mesh node 102-3, and / or the telemetry data 114-6 generated by mesh node 102-6 from adjacent mesh node 102-6. Mesh node 102-6 sends the telemetry data 114-2, 114-3, and / or 114-6 to mesh node 102-9.

[0013] The generated telemetry data 114 for the mesh node 102 may, from time to time, be received by the mesh node 102-9 and sent to the telemetry processing engine 110. Thus, the telemetry data 112 can include a series of telemetry data 114 that may arrive at the mesh node 102-9 in a random order. The introduction of mesh network traffic on the channel 104 other than the telemetry data 114 can cause further variations when the telemetry data 112 is received by the telemetry processing engine 110.

[0014] The telemetry processing engine 110 includes a telemetry memory bridge 116 that receives the telemetry data 112 and a telemetry control memory 118 for storing the telemetry data 112. The telemetry processing engine 110 also includes a system control processor 120 communicatively coupled to the telemetry memory bridge 116 and the telemetry control memory 118. The system control processor 120 is configured to manage the power applied to and / or consumed by the processor core 106 and other aspects of the mesh node 102. The system control processor 120 is also responsible for controlling various aspects of the sensor and telemetry capture devices, such as synchronization, sensor setup, sensor error handling, firmware updates, and telemetry gathering. The telemetry processing engine 110 can include an administrative control processor 122 communicatively coupled to the telemetry memory bridge 116 and the telemetry control memory 118.

[0015] The telemetry memory bridge 116 includes logic (e.g., programmable logic, wired-connected logic) that causes the telemetry memory bridge 116 to be implemented as described herein. The telemetry memory bridge 116 is configured to parse the telemetry data 112, track the status of the telemetry data 114 included in the telemetry data 112 for individual epochs, and store the parsed telemetry data 124 in the telemetry control memory 118. The telemetry memory bridge 116 is also configured to manage data objects associated with the telemetry data 114 and perform error handling related to the telemetry data 114. The telemetry data bridge 116 is configured to generate an error status 125 based on the parsed telemetry data 124. Generation of the error status 125 can include, by way of non-limiting example, generating an interrupt, a control signal, a message, or a modification to a status register.

[0016] The telemetry control memory 118 comprises a volatile memory (e.g., random access memory) including a set of data structures for storing the parsed telemetry data 124. More specifically, the telemetry control memory 118 includes a set of circular buffers for storing the parsed telemetry data 114. In some embodiments, the set of circular buffers includes different circular buffers for each type of telemetry data. For example, a first circular buffer may be configured to store temperature data, a second circular buffer may be configured to store voltage data, and a third circular buffer may be configured to store current data. In some embodiments, the circular buffers can have different attributes specific to the type of telemetry data. One circular buffer, for example, may have a different size than another circular buffer. One circular buffer may be configured to store an array of entries for a given processor core, while another circular buffer may be configured to store a single entry for the same processor core. In some embodiments, the telemetry control memory 118 is an error correction coded memory macro operating at a specified frequency (e.g., 600 MHz, 800 MHz).

[0017] In some embodiments, the telemetry control memory 118 includes a plurality of ports through which memory locations within the telemetry control memory 118 can be accessed. The plurality of ports of the telemetry memory bridge 116 can include a first set of ports through which the telemetry memory bridge 116 can access the telemetry control memory 118. The plurality of ports of the telemetry memory bridge 116 can include a second set of ports through which the system control processor 120 and / or the management control processor 122 can access the telemetry control memory 118. The telemetry processing engine 110 can include a second set of ports and an interconnect system 129, such as a utility bus, coupled to the system control processor 120 and / or the management control processor 122. The system control processor 120 and / or the management control processor 122 can read telemetry data stored in the telemetry control memory 118 via the interconnect system 129. The telemetry memory bridge 116 can write telemetry data to the telemetry control memory 118 via the first set of ports, while the system control processor 120 and / or the management control processor 122 are reading telemetry data from the telemetry control memory 118 via the second set of ports. In some embodiments, the system control processor 120 and the management control processor 122 can access the telemetry control memory 118 via the same one or more ports of the second set of ports.

[0018] The system control processor 120 is configured to track the status of the received telemetry data 114 and handle errors associated with the telemetry data 114. The system control processor 120 can send a message or an interrupt to the tile sensor controller 108 to improve the detected error. The system control processor 120 can also send a message 126 (e.g., a control signal, an interrupt, an instruction) to the tile sensor controller 108 to adjust various telemetry parameters based on the received telemetry data 114. The management control processor 122 can manage the pointers of the circular buffer and track the parsed telemetry data 124 stored in the telemetry control memory 118. The management control processor 122 is connected to the telemetry control memory 118 (e.g., via a utility bus) and can access the telemetry data stored in the telemetry control memory 118 based on the pointers in the telemetry memory bridge 116.

[0019] In some embodiments, the message 126 can include a sensor trigger signal that can transition the tile sensor controller 108 for one or more of the mesh nodes 102 between a first mode in which telemetry data collection is enabled and a second mode in which telemetry data collection is disabled. In some embodiments, the sensor trigger signal can be specific to the type of telemetry data. For example, the message 126 can include a first trigger message associated with enabling / disabling temperature telemetry data collection, a second trigger message associated with enabling / disabling voltage telemetry data collection, and a third trigger message associated with enabling / disabling current telemetry data collection. Further explanation of the sensor trigger is provided with respect to FIG. 2 and elsewhere in this specification.

[0020] Each of the mesh nodes 102 is a cross-point or router that supports connections to two or more channels 104. In some embodiments, the mesh nodes 102 can have a two-dimensional arrangement with rows and / or columns. In some embodiments, the two-dimensional arrangement of the mesh nodes 102 can be a lattice structure in which vertically adjacent and horizontally adjacent nodes are spaced at equal distances. The mesh nodes 102 can be arranged along a single dimension or in a geometric pattern in some embodiments. The mesh nodes 102 can include one or more types of nodes, such as, by way of non-limiting example, coherent nodes, non-coherent nodes, home nodes, subordinate nodes, request nodes, and diverse nodes.

[0021] Each of the channels 104 can include one or more communication channels or sub-channels that connect adjacent nodes. In embodiments where an individual channel 104 includes multiple sub-channels, each of the channels 104 can include various types of communication sub-channels, such as, by way of non-limiting example, request channels, response channels, data channels, and snoop channels. The mesh nodes 102 and channels 104 can comprise a coherent mesh network for facilitating communication between the mesh nodes 102 and conveying data. The mesh nodes 102 can communicate and / or convey data according to one or more suitable communication protocols, such as the coherent hub interface (CHI) protocol or the AXI4 stream protocol. In some embodiments, the channel is at least part of a processor utility bus, such as an advanced microcontroller bus utilizing the advanced extensible interface bus protocol.

[0022] In some embodiments, the SoC architecture 100 can include a telemetry analysis engine 130 that includes one or more control processors for analyzing telemetry data. The management control processor 122 reads telemetry data 124 stored in a set of buffers in the telemetry control memory 118, as described below with respect to FIGS. 5A through 5C. The management control processor 122 can send the read telemetry data 128 to the telemetry analysis engine 130. The telemetry analysis engine 130 can control the operating characteristics of the processor core 106 based on the received telemetry data 128. In some embodiments, the telemetry analysis engine 130 can be part of the telemetry processing engine 110.

[0023] FIG. 2 illustrates a sub-architecture 200 of an example of the SoC architecture 100 according to one or more embodiments. The sub-architecture 200 includes a tile sensor controller 202 corresponding to the tile sensor controller 108 of FIG. 1. The tile sensor controller 202 includes a voltage and / or temperature (VT) controller 204, a current telemetry controller 206, and a data arbiter 208. The VT telemetry controller 204 supports a voltage monitor 210 and / or a temperature sensor hub 212. The current telemetry controller 206 supports one or more current meters 214, a sample processor 216, and / or a dynamic voltage and frequency scaling (DVFS) engine 218. The voltage monitor 210 and / or the temperature sensor hub 212 can be included as part of the VT telemetry controller 204, or can be placed external to and communicatively coupled to the VT telemetry controller 204. The current meter 214, the sample processor 216, and / or the DVFS engine 218 can be included as part of the current telemetry controller 206, or can be placed external to and communicatively coupled to the current telemetry controller 206.

[0024] The VT telemetry controller 204 receives voltage measurement values from a voltage monitor 210 regarding the operating voltage applied to the processor core 106. In some embodiments, as described below with respect to FIG. 3, the received voltage measurement values can include measurement values of other components within the tile. As further described below with respect to FIG. 3, the VT telemetry controller 204 also receives temperature measurement values from a temperature sensor hub 212, and the temperature measurement values indicate the temperature measured at one or more points within the tile.

[0025] The VT telemetry controller 204 generates a data packet including data regarding the acquired voltage and temperature measurement values, and sends the data packet to the data arbiter 208. More specifically, the VT telemetry controller 204 generates and sends a voltage data packet 220 including data indicating the voltage measurement values acquired by the voltage monitor 210. The VT telemetry controller 204 also generates and sends a temperature data packet 222 including data indicating the temperature measurement values acquired by the temperature sensor hub 212. In some embodiments, the VT telemetry controller 204 is configured to control the voltage applied to the processor core 106 (or other components of the tile), or to control other aspects that can affect the temperature at points within the tile. In some embodiments, the VT telemetry controller 204 is configured to send signals to other components that use signals to at least partially control the voltage or affect the temperature at points within the tile. In some embodiments, the voltage applied to the processor core 106 may be controlled by one or more devices external to the VT telemetry controller 204 - for example, the DVFS engine 218 can control the voltage applied to the individual processor cores 106.

[0026] The current telemetry controller 206 receives the current measurement values acquired by the current meter 214. The acquired current measurement values can include a set of current measurement values of the current applied to the individual cores of the set of processor cores 106. For example, the current meter 214 can include a first current meter for measuring the current of the first processor core, and can include a second current meter for measuring the current of the second processor core. In some embodiments, the current meter 214 includes one or more on-die current meters (ODCMs). In some embodiments, the sample processor 216 generates statistical data regarding the current measurement values acquired by the current meter 214. For example, the sample processor 216 can determine, as a non-limiting example, the average current, median current, maximum current, or minimum current of the current measurement values over a given period. The current telemetry controller 206 generates a current data packet 224 that includes data indicating the current measurement values acquired by the current meter 214 and / or statistical data regarding the acquired current measurement values, and sends it to the data arbiter 208.

[0027] The DVFS engine 218 can control the frequency and / or voltage applied to individual cores of the set of processor cores 106. The DVFS engine 218 can also monitor and / or control one or more states of the processor cores 106, such as the power consumption of individual cores, or the performance level of individual cores. In some embodiments, the DVFS engine 218 can send messages or control signals that control the operating characteristics of individual cores to other components. Non-limiting examples of such components include voltage regulators (e.g., load dropout regulators), current regulators (e.g., constant current regulators), and switches or frequency regulators (e.g., phase-locked loops). In some embodiments, the current telemetry controller 206 includes one or more current controllers 219 configured to control the current applied to the processor cores 106 (or other components of the tile), or to control other aspects that can affect the current applied to components within the tile. The one or more current controllers 219 can include a plurality of current controllers, each configured to control the current applied to an individual processing core of the processing cores 106.

[0028] In some embodiments, the current telemetry controller 206 sends state or message data packets 226 regarding various parameters or states measured, detected, or otherwise observed by the DVFS engine 218 to the data arbiter 208. For example, the state data packet 226 can include data regarding the power consumption and / or performance level of individual processor cores 106. The state data of the state data packet 226 may be stored in the telemetry control memory 118.

[0029] Data packets sent by the VT telemetry controller 204 and / or the current telemetry controller 206 can have a defined format. For example, the temperature data packet 222 can include an array of temperature measurement data, with each element of the array indicating the temperature measurement value at a specific point on the tile. As another example, the current data packet 224 can include an array of current measurement data, with each element being specific to an individual processor core 106. In some embodiments, the VT telemetry controller 204 and / or the current telemetry controller 206 can include a timestamp indicating the time at which the measurement was received or sent to the data arbiter 208.

[0030] The data arbiter 208 includes logic (e.g., programmable logic, logic connected by wiring) for determining the order in which simultaneously received data packets will be transmitted to the channel 228 of the SoC architecture 100, and the channel 228 corresponds to one of the channels 104 described with respect to FIG. 1. The data arbiter 208 can transmit the data packet 230 to a mesh network router 232 communicatively coupled to the channel 228. The mesh network router 232 will be described in detail below with respect to FIG. 3. The data arbiter 208 can include memory for temporary storage of data packets received from the VT telemetry controller 204 and the current telemetry controller 206.

[0031] In some embodiments, data arbiter 208 can forward data packets 230 to channel 228 in the order in which they are received - e.g., according to a first-in, first-out (FIFO) technique. In some embodiments, data arbiter 208 can forward data packets 230 to channel 228 according to the priority associated with the type of data packet. By way of example, data arbiter 208 can include logic that indicates that current data packets 224 have the highest priority, voltage data packets 220 have the second highest priority, temperature data packets 222 have the third highest priority, and status data packets 226 have the lowest priority.

[0032] Sub-architecture 200 can include an interconnect device 234 configured to send message 236 to VT telemetry controller 204 and / or send message 238 to current telemetry controller 206. In some embodiments, interconnect device 234 is a mesh network interconnect device and may be connected to one or more sub-channels of channel 104. Interconnect device 234 may be communicatively coupled to system control processor 120 as described with respect to FIG. 1 and elsewhere in this specification. In such embodiments, one or more of messages 126 may be sent to tile sensor controller 108 via interconnect device 234. Interconnect device 234 can send messages from system control processor 120 to VT telemetry controller 204 and / or current telemetry controller 206 of a particular one of tile sensor controllers 202 associated with a particular one of mesh nodes 102 based on the received data packets.

[0033] Message 236 and / or 238 may be generated as a result of the detection of one or more specified situations by the system control processor 120. Each of message 236 and / or message 238 can cause the VT telemetry controller 204 or the current telemetry controller 206 to perform one or more improvement actions. The improvement actions can include re-initializing or adjusting the operations of the voltage monitor 210, the temperature sensor hub 212, the current meter 214, the sample processor 216, or the DVFS engine 218. For example, the improvement actions can include adjusting the sampling rate of the voltage monitor 210, the temperature sensor hub 212, the current meter 214, the sample processor 216, and / or the DVFS engine 218. As another example, the improvement actions can cause the VT telemetry controller 204 or the current telemetry controller 206 to reset or synchronize one or more devices to align the measurement values in the same epoch.

[0034] Each of message 236 and / or 238 can be reset or re-initialized in relation to the synchronization process to the VT telemetry controller 204 and / or the current telemetry controller 206. The synchronization process can include the receipt of message 126 that causes message 236 or message 238 to be sent to the interconnect device 234 by two or more tile sensor controllers 108 of the mesh node 102.

[0035] In some embodiments, the sub-architecture 200 includes a sensor trigger 240 that transitions the VT telemetry controller 204 and / or the current telemetry controller 206 to operate between a first mode in which telemetry data collection is enabled and a second mode in which telemetry data collection is disabled. The tile sensor controller 202, the VT telemetry controller 204, the current telemetry controller 206, and / or their component elements can enable / disable telemetry data collection based on one or more logic states associated with the sensor trigger 240.

[0036] In some embodiments, the sensor trigger 240 includes a memory (e.g., RAM, register) having a set of bits having one or more values corresponding to the telemetry collection state of the tile sensor controllers 108, 202, the VT telemetry controller 204, and / or the current telemetry controller 206. Each value of the set of bits may be controlled based on a message 242 initiated by the system control processor 120 (e.g., via the interconnect device 234). In some embodiments, the set of bits of the sensor trigger 240 can include a first set of bits for enabling / disabling temperature telemetry data collection associated with the VT telemetry controller 204, a second set of bits for enabling / disabling voltage telemetry data collection associated with the VT telemetry controller 204, and / or a third set of bits for enabling / disabling current telemetry data collection associated with the current telemetry controller 206. In some embodiments, the set of bits of the sensor trigger 240 can include a single bit for enabling / disabling all telemetry data collection associated with each tile sensor controller 202.

[0037] The tile sensor controller 202, VT telemetry controller 204, current telemetry controller 206, and / or its component elements can transition from a first mode to a second mode in response to detecting one or more changes (e.g., from binary zero (0) to binary one (1)) in a set of bits associated with the sensor trigger 240 from a first value to a second value. The tile sensor controller 202, VT telemetry controller 204, current telemetry controller 206, and / or its component elements can transition from the second mode to the first mode in response to detecting one or more changes (e.g., from binary one (1) to binary zero (0)) in a set of bits associated with the sensor trigger 240 from a second value to a first value.

[0038] In some embodiments, the sensor trigger 240 includes logic (e.g., programmable logic, wired logic) configured to send a message 244 to the VT telemetry controller 204 to enable / disable temperature telemetry data collection and / or voltage telemetry data collection associated with the VT telemetry controller 204. In some embodiments, the sensor trigger 240 includes logic (e.g., programmable logic, wired logic) configured to send a message 246 to the current telemetry controller 206 to enable / disable current telemetry data collection and / or status data collection associated with the current telemetry controller 206. In some embodiments, the message 244 and the message 246 may be a single message that enables / disables telemetry data collection associated with the tile sensor controllers 108, 202.

[0039] The tile sensor controller 202, VT telemetry controller 204, current telemetry controller 206, and / or its component elements can transition from a first mode to a second mode in response to receiving message 244 and / or message 246 that provide an instruction or control signal to invalidate telemetry data collection. The tile sensor controller 202, VT telemetry controller 204, current telemetry controller 206, and / or its component elements can transition from the second mode to the first mode in response to receiving message 244 and / or message 246 that provide an instruction or control signal to validate telemetry data collection.

[0040] The tile sensor controller 202, VT telemetry controller 204, current telemetry controller 206, and / or its component elements can start, stop, or restart telemetry data collection based on a defined event. For example, the VT telemetry controller 204 and current telemetry controller 206 can initiate the first transition from a second mode (invalidated telemetry collection) to a first mode (validated telemetry collection) based on sensor trigger 240. The VT telemetry controller 204 and / or current telemetry controller 206 can begin collecting telemetry data for the second time after the first time in response to detecting a signal edge in a clock signal or other named signal. The same principle can equally apply to invalidating telemetry data collection.

[0041] In response to receiving a sensor trigger 240 signal that enables telemetry data collection, the telemetry resources begin collecting telemetry data contemporaneously or as nearly simultaneously as possible. For example, in response to receiving messages 244 and 246, the VT controller 204 and the current telemetry controller 206 can each begin collecting telemetry data immediately or upon detection of the same event (e.g., a rising edge of a clock). As another example, two or more tile sensor controllers 202 of the mesh node 102 can begin collecting telemetry data immediately or upon detection of the same event. Beginning telemetry data collection contemporaneously or simultaneously helps to facilitate the temporal alignment of telemetry data sampling and serves to reduce the length of the epoch period.

[0042] Each of the tile sensor controllers 202 is configured in some embodiments to detect some locally occurring errors related to, for example, temperature, voltage, and / or current telemetry data collection. The tile sensor controller 202 can be configured to detect, for example, sampling errors associated with one or more analog-to-digital converters involved in collecting telemetry data. The tile sensor controller 202 can generate an interrupt provided to the system control processor 120, and the system control processor 120 can initiate corrective actions to resolve or correct the local errors detected by the corresponding tile sensor controller 202.

[0043] FIG. 3 illustrates a mesh network tile 300 of an example associated with a single mesh node of the SoC architecture of FIG. 1 according to one or more embodiments. Tile 300 includes a first processor core 302-1, a second processor core 302-2, a first memory device 304-1, and a second memory device 304-2. Processor cores 302-1 and 302-2 (collectively "processor cores 302") correspond to a set of processor cores 106 as described with respect to FIG. 1 and elsewhere in this specification.

[0044] Memory devices 304-1 and 304-2 (collectively "memory devices 304") each include one or more types of volatile memory for storing data packets. More particularly, memory devices 304 include cache memory (e.g., L3 cache memory) and can include static random access memory (SRAM), dynamic random access memory (DRAM), and / or double data rate (DDR) memory. In some embodiments, memory devices 304 can each include logic (e.g., programmable logic, wired logic) configured to process and execute requests to read and / or write data to the memory. In some embodiments, memory devices 304-1 and 304-2 receive and store telemetry data associated with processor cores 302-1 and 302-2. In some embodiments, memory devices 304 receive and store data packets associated with processor cores of other tiles.

[0045] Tile 300 includes a tile sensor controller 306-1 coupled to processor core 302-1 and a tile sensor controller 306-2 coupled to processor core 302-2. Tile sensor controllers 306-1 and 306-2 correspond to the tile sensor controller 202 discussed with respect to FIG. 2. Tile 300 also includes a plurality of temperature sensors 308 integrated with or attached to processor core 302 and memory device 304. In FIG. 3, two temperature sensors measure the temperature at each location of processor core 302 and a single temperature sensor measures the temperature at each location of memory device 304. In some embodiments, there may be a different number of temperature sensors in tile 300 provided at locations different from those shown. Tile sensor controllers 306-1 and 306-2 can each receive message 236 and / or 238 in connection with the implementation of improvement actions, as described with respect to FIG. 2 and elsewhere in this specification.

[0046] In some embodiments, a current controller is associated with or included in each core 302. The current controller for each core 302 is configured to selectively adjust the current consumed by the individual core 302 based on, for example, instructions or control signals provided by telemetry analysis engine 130. The current controller for each core 302 may also be configured to generate time information, such as a timestamp, indicating the time at which an individual current measurement was acquired. The time information may be provided to tile sensor controller 306 by each current controller. In some embodiments, the adjustment of the current consumed by the individual core 302 is controlled by a DVFS engine 218 associated with the individual core 302 based on a current measurement by current meter 214.

[0047] Tile 300 also includes a mesh network router 310 configured to receive telemetry data from routers of other tiles. The mesh network router 310 routes the telemetry data received from other tiles. In some embodiments, the mesh network router 310 can obtain the telemetry data stored in the memory device 304-1 and / or the memory device 304-2, and send the obtained telemetry data to adjacent tiles within the mesh node network.

[0048] As a specific non-limiting example illustrating the operation of the mesh network router 310 during a given epoch, the mesh node 102-8 in FIG. 1 can include tile 300. The mesh network router 310 can, for the first time, receive a data packet including telemetry data associated with the processor core 302 from one or both of the tile sensor controllers 306. The mesh network router 310 can, for the second time after the first time, receive a set of data packets 312-1 including telemetry data from the mesh node 102-5 via the channel 314-1. The mesh network router 310 can, for the third time after the second time, receive a set of data packets 312-2 including telemetry data from the mesh node 102-7 via the channel 314-2. The mesh network router 310 sends a set of data packets 316 corresponding to the telemetry data associated with the processor core 302-1 and / or the processor core 302-2 to adjacent tiles within the network of the mesh node 102. The mesh network router 310 also sends the sets of data packets 312-1 and 312-2 to adjacent tiles. In some embodiments, the mesh network router 310 can send the telemetry data to adjacent tiles in the order in which the telemetry data becomes available to the mesh network router 310.

[0049] The mesh network routers 310 of the mesh nodes 102 in the SoC architecture 100 communicate with each other to determine how data packets will be routed so that they reach the telemetry processing engine 110. The mesh network routers 310 communicate to determine a first set of adjacent mesh nodes to which individual mesh nodes will send data packets. The mesh network routers 310 also communicate to determine a second set of adjacent mesh nodes to which each individual mesh node will receive data packets. As shown in the SoC architecture 100, the mesh nodes 102 cooperate with each other to cause the data packets to be transmitted to the assigned mesh node (mesh node 102-9 in this example) that will provide the telemetry data 112 to the telemetry processing engine 110.

[0050] The mesh network routers 310 can sometimes convey different routes for data packets over time. The set of routes shown in FIG. 1, for example, can be established during a first epoch. The mesh network routers 310 can determine different sets of routes for data packets. In some embodiments, the adjacent mesh nodes to which a given mesh network router 310 sends telemetry data can change from one epoch to another. In some embodiments, the adjacent nodes to which a given mesh network router 310 sends telemetry data can be static and remain unchanged from a first epoch to a second epoch.

[0051] The problems associated with the foregoing framework are that data packets can arrive at the telemetry memory bridge 116 in an order different from the order in which they were sent by the mesh network router 310 or the order generated by the tile sensor controller 108. Factors that affect the receipt of data packets by the telemetry processing engine 110 include, as non-limiting examples, the physical location of tiles within the mesh network, traffic on channel 114, the sampling rates of various telemetry data, and / or DVFS engine traffic.

[0052] FIG. 4A illustrates a timeline 400A of an example of a first set of telemetry epochs of telemetry data received by a telemetry processing engine according to one or more embodiments. The timeline 400A includes a first epoch 402A, a second epoch 404A, and a third epoch 406A. In the case of the timeline 400A, the SoC architecture 100 is susceptible to a first set of circumstances. The first set of circumstances is accompanied, for example, by a first sampling rate at which the tile sensor controller 108 acquires telemetry data. As a result of the first set of circumstances, each epoch is completed before the next epoch begins. The timeline 400A includes, for example, a period 408 between the first epoch 402A and the second epoch 404A during which telemetry data is not received by the telemetry processing engine 110. In some implementations, as a result of detecting the period 408, the telemetry processing engine 110 can increase the sampling rate at which telemetry data is acquired by the tile sensor controller 108.

[0053] Figure 4B illustrates a timeline 400B of a second set of telemetry epochs of telemetry data received by a telemetry processing engine, according to one or more embodiments. The timeline 400B includes a first epoch 402B, a second epoch 404B, and a third epoch 406B. In the case of the timeline 400B, the SoC architecture 100 is susceptible to a second set of circumstances. The second set of circumstances is associated with, for example, a second sampling rate at which the tile sensor controller 108 acquires telemetry data, and the second sampling rate is faster than the first sampling rate discussed with respect to FIG. 4A. As a result of the second set of circumstances, the second epoch 404B begins immediately after the first epoch 402B, and the third epoch 404C begins immediately after the second epoch 404B. For example, there is a very small period 408 between adjacent epochs within the timeline 400B, or there is no period 408.

[0054] Figure 4C illustrates a timeline 400C of a third set of telemetry epochs of telemetry data received by a telemetry processing engine, according to one or more embodiments. The timeline 400C includes a first epoch 402C, a second epoch 404C, and a third epoch 406C. In the case of the timeline 400C, the SoC architecture 100 is susceptible to a third set of circumstances. The third set of circumstances is associated with, for example, a third sampling rate at which the tile sensor controller 108 acquires telemetry data, and the third sampling rate is faster than the second sampling rate discussed with respect to FIG. 4B. As a result of the third set of circumstances, the second epoch 404C begins before the first epoch 402C is complete, and the third epoch 406C begins before the second epoch 404C is complete. Circumstances that affect the occurrence of the next epoch with respect to the current epoch include the sampling rate, the congestion of telemetry data in the SoC architecture, and the processing speed of various components in the SoC architecture 100.

[0055] Referring back to FIG. 1, the parameters of the SoC architecture 100 can be controlled to regulate the occurrence of the next epoch for the current epoch. The system control processor 120 and / or the management control processor 122 can generate an interrupt in response to detecting the occurrence of various situations or errors associated with the telemetry data or its collection. In some implementations, the presence of various error conditions can be detected where an incomplete set of telemetry data is acquired during a given epoch. In some embodiments, the telemetry memory bridge 116 can detect the presence of one or more of the error conditions described herein and generate an error status 125, such as an interrupt, that is provided to or otherwise observable by the sensor control processor 120 and / or the management control processor 122.

[0056] In response to detecting an error condition, the telemetry memory bridge 116 can generate an error status 125 that causes the system control processor 120 to adjust the operation of one or more of the tile sensors 108. The first error condition corresponds to a situation where a first set of telemetry data for a first epoch is received, a second set of telemetry data for a second epoch is received, and telemetry data for a third epoch is received, but the first set of telemetry data is incomplete. The second error condition corresponds to a situation where a complete second set of telemetry data for a second epoch is received, but the first set of telemetry data for a first epoch prior to the second epoch is incomplete. The system control processor 120 can issue a first sensor trigger signal message that temporarily disables telemetry data collection for one or more types of telemetry data at the tile sensors 108, 202. The system control processor 120 can issue a second sensor trigger signal message that re-enables or restarts telemetry data collection for one or more types of telemetry data at the tile sensors 108, 202.

[0057] The telemetry memory bridge 116 can detect the presence of a third error condition where the write pointer should match the read pointer's position by incrementing the write pointer for a given circular buffer. In response to detecting the third error condition, the telemetry memory bridge 116 can generate an interrupt to adjust the operation of one or more of the tile sensors controllers 108. By generating the interrupt, the administrative control processor 122 or the system control processor 120 can send a message 126 to one or more of the tile sensors controllers 108.

[0058] In some embodiments, the message 126 can cause the tile sensors controller 108 to adjust the sampling rate of one or more types of telemetry data. For example, as a result of detecting the situation described with respect to FIG. 4C, the message 126 may be sent to one or more of the tile sensors controllers 108 to synchronize the telemetry data by resetting or re-initializing the voltage monitor 210, the temperature sensor hub 212, or the current meter 214. As a result of detecting a buffer overflow situation where the position of the write pointer should match the position of the read pointer by incrementing the write pointer, the message 126 may be sent to one or more of the tile sensors controllers 108 to reduce the sampling rate for one or more types of telemetry data. In some implementations, in response to detecting a buffer overflow situation, the system control processor 120 can reset the write pointer and the read pointer to the initial position of the buffer.

[0059] FIG. 5A illustrates a first circular buffer 500A storing telemetry data of a first type according to one or more embodiments. The type of telemetry data stored in the first circular buffer 500A corresponds to temperature measurements associated with tile 300 of the SoC architecture 100. The first buffer 500A includes a first plurality of entries 502A that identify the epochs with which the telemetry data is associated. The first buffer 500A also includes a second plurality of entries 504A for storing the received telemetry data.

[0060] The first buffer 500A has a size configured to store telemetry data for a number I of epochs and a number N of temperature entries for each of the epochs. More specifically, a subset of the temperature telemetry entries 506-1 for the first epoch has a number N of temperature telemetry data entries, where the number N corresponds to the number of mesh nodes 102 in the SoC architecture 100. As a specific non-limiting example, the number N for the SoC architecture 100 shown in FIG. 1 is 9, but the number N may vary based on the design of the SoC architecture 100. In some embodiments, each entry in the second plurality of entries 504A is configured to store an array of temperature telemetry data entries. Referring to FIG. 3, for example, each entry in the second plurality of entries 504A includes six instances of temperature telemetry data, each of the six instances corresponding to a temperature measurement by one of six temperature sensors 308. The size of the first buffer 500A (e.g., the number I of epochs) may be selected based on the sampling rate or range of sampling rates of the temperature telemetry data and / or the number of temperature sensors.

[0061] The first buffer 500A contains or is associated with a plurality of data objects. The first data object is a read pointer 508A that specifies a set of entries in the first buffer 500A that are to be read next by the system control processor 120, the management control processor 122, and / or other entities of the SoC architecture 100 or associated with the SoC architecture 100. The read pointer 508A can point to the first entry within a set of temperature telemetry data entries 506 that are to be read. The first entry can include time information associated with the set of entries, as discussed below. In response to the temperature telemetry data being read from the set of entries indicated by the read pointer 508A (e.g., associated with the temperature telemetry data of tile 300 of mesh node 102-1), the position of the read pointer 508A is updated to point to the next subset of temperature telemetry data - in this case, updated to point to the first entry within a subset of the temperature telemetry data entries 506-2 for tile 102-2 in the second epoch.

[0062] The second data object is a write pointer 510A that specifies a set of second entries 504A in the first buffer 500A into which the temperature telemetry data is to be written next. The write pointer 510A can point to the first entry within the set of entries that are to be written. In response to all of the temperature telemetry data being written into the subset of temperature telemetry entries 506-2 associated with the write pointer 510A, the position of the write pointer 510A is updated to point to the next subset of temperature telemetry entries 506-3 (not shown). In some embodiments, the write pointer 510A may be updated by the telemetry memory bridge 116.

[0063] In the first buffer 500A, after all the entries within the current subset of the entries associated with the read pointer 508A have been read, the read pointer 508A is advanced to the next subset of the temperature telemetry entries. For example, after the telemetry data has been read from any entry within the subset of entry 506-1, the read pointer 508A may be updated from the first entry within the subset of entry 506-1 to the first entry within the subset of entry 506-2. In some embodiments, the management control processor 122 advances the read pointer 508A to the next subset of entry 506.

[0064] After all the entries within the set of entries associated with the write pointer 510A have been written, the write pointer 510A is advanced to the next set of the temperature telemetry entries. For example, after the temperature telemetry data has been written to all the entries within the subset of entry 506-2, the write pointer 510A may be updated from the first entry within the subset of entry 506-2 to the first entry within the subset of entry 506-3 (not shown). In some embodiments, the telemetry memory bridge 116 advances the write pointer 510A to the next subset of entry 506.

[0065] As a result of reading the telemetry data within the last entry (e.g., the entry for the temperature of tile N in epoch I) in the first buffer 500A, the position of the read pointer 508A is returned to the first entry (e.g., the entry for tile 1 in the first epoch) in the first buffer 500A. As a result of writing the telemetry data to the last remaining empty entry within the subset of the temperature telemetry entry 506-M, the position of the write pointer 510A is returned to the subset of the temperature telemetry entry 506-1 (e.g., the entry for tile 1 in the first epoch) in the first buffer 500A.

[0066] The telemetry processing engine 110 is configured to detect various buffer error situations associated with the first buffer 500A. The telemetry memory bridge 116 can detect a buffer overflow situation in response to a determination that advancing the write pointer 510A should position the write pointer 510A at the same set of entries as the read pointer 508A. Detection of the overflow situation can include, for example, an attempt by the telemetry memory bridge 116 to write an entry to the same set of telemetry data entries 506 pointed to by the read pointer 508A. As a result of detecting the buffer overflow situation, the telemetry memory bridge 116 can generate an interrupt, which is provided to and / or detected by the system control processor 120 and / or the management control processor 122. In response to registering the buffer overflow situation, in some implementations, the management control processor 122 can reset the position of the read pointer 508A and / or the position of the write pointer 510A to the initial position of the first buffer 500A. In connection with the buffer overflow situation, the system control processor 120 can adjust the operation of one or more tile sensor controllers 202, such as by re-initializing the controller and / or the sensor to sample temperature telemetry data at a different sampling rate.

[0067] In some embodiments, the telemetry memory bridge 116 generates a timestamp 511A or other time information indicating the time at which the first one or more entries in a subset of the temperature telemetry entries 506 were received. It is noted that a subset of the temperature telemetry entries 506 for a given epoch may not necessarily be received in a continuous order or all at once. The telemetry memory bridge 116 includes the timestamp 511A in a second entry 504A of a first buffer 500A within the telemetry control memory 118. For example, a first timestamp 511A may be included in a subset of the temperature telemetry entry 506-1 of the first epoch, a second timestamp 513A may be included in a subset of the temperature telemetry entry 506-2 of the second epoch, and so on. In some embodiments, the timestamp may be included as a respective unique entry within the second entry 504A. In some embodiments, the tile sensor controller 108 of the mesh node 102 can append a timestamp to the beginning of the temperature telemetry data, which is then transmitted via channel 104 to the telemetry memory bridge 116.

[0068] In some embodiments, the temperature telemetry data can include an address or identifier associated with the tile or mesh node where the temperature telemetry data was generated. The telemetry memory bridge 116 compares the address with the addresses of tiles 0, 1,... N and stores the temperature telemetry data in the first buffer 500A based on a match between the addresses. In the case of a subset of the temperature telemetry entry 506-1, the telemetry memory bridge 116 can receive telemetry data 114-2 including temperature telemetry data associated with the mesh node 102-2 (see FIG. 1). Based on the address or identifier within the telemetry data 114-2, the telemetry memory bridge 116 writes the temperature telemetry data to the tile 2 temperature location within the first buffer 500A for the subset of the temperature telemetry entry 506-1.

[0069] FIG. 5B illustrates a second circular buffer 500B storing second type of telemetry data according to one or more embodiments. The type of telemetry data stored in the second circular buffer 500B corresponds to voltage measurements associated with tile 300 of the SoC architecture 100. The second buffer 500B includes a first plurality of entries 502B that identify the epochs with which the telemetry data is associated. The second buffer 500B also includes a second plurality of entries 504B for storing the received telemetry data.

[0070] The second buffer 500B has a size configured to store telemetry data for a number J of epochs and a number N of voltage entries for each of the epochs. More specifically, a subset of the voltage telemetry entries 512-1 for the first epoch has a number N of voltage telemetry data entries, where the number N corresponds to the number of mesh nodes 102 in the SoC architecture 100. The second buffer 500B has the same size as the first buffer 500A in some embodiments. In some embodiments, each entry within the second plurality of entries 504B is configured to store an array of voltage telemetry data entries. In some embodiments, the voltage telemetry data stored in the voltage telemetry data entries can represent the voltage observed or measured by the voltage monitor 210. The size of the second buffer 500B (e.g., the number J of epochs) may be selected based on the sampling rate or range of sampling rates of the voltage telemetry data.

[0071] The second buffer 500B contains or is associated with a plurality of data objects. The first data object is a read pointer 508B that specifies an entry within the second buffer 500B that is to be next read by the system control processor 120, the management control processor 122, and / or other entities of the SoC architecture 100 or associated with the SoC architecture 100. The read pointer 508B can point to the first entry within a set of voltage telemetry data entries 512 that are to be read. The first entry can include time information associated with the set of entries, as discussed below. In response to voltage telemetry data being read from the set of entries indicated by the read pointer 508B (e.g., associated with the voltage telemetry data of tile 300 of mesh node 102-1), the position of the read pointer 508B is updated to point to the next subset of voltage telemetry data - in this case, updated to point to the first entry within a subset of entries 512-2 of voltage telemetry data for tile 102-2 in the second epoch.

[0072] The second data object is a write pointer 510B that specifies a set of second entries 504B within the second buffer 500B into which voltage telemetry data is to be next written. The write pointer 510B can point to the first entry within the set of entries that are to be written. In response to all of the voltage telemetry data being written to the subset of voltage telemetry entries 512-2 associated with the write pointer 510B, the position of the write pointer 510B is updated to point to a subset of voltage telemetry entries 512-3 (not shown). The write pointer 510B may be updated by the telemetry memory bridge 116 in some embodiments.

[0073] In the second buffer 500B, after all the entries within the current subset of the entries associated with the read pointer 508B have been read, the read pointer 508B is advanced to the next subset of entries. For example, after telemetry data has been read from every entry within the subset of entry 512-1, the read pointer 508B may be updated from the first entry within the subset of entry 512-1 to the first entry within the subset of entry 512-2. In some embodiments, the management control processor 122 advances the read pointer 508B to the next subset of entry 512.

[0074] After all the entries within the set of entries associated with the write pointer 510B have been written, the write pointer 510B is advanced to the next set of voltage telemetry entries. For example, after voltage telemetry data has been written to every entry within the subset of entry 512-2, the write pointer 510B may be updated from the first entry within the subset of entry 512-2 to the first entry within the subset of entry 512-3 (not shown). In some embodiments, the telemetry memory bridge 116 is configured to advance the write pointer 510B.

[0075] As a result of reading the telemetry data within the last entry (e.g., the entry for tile N voltage of epoch J) within the second buffer 500B, the position of the read pointer 508B is returned to the first entry (e.g., the entry for tile 1 of the first epoch) within the second buffer 500B. As a result of writing the telemetry data to the last remaining empty entry within the subset of voltage telemetry entry 512-M, the position of the write pointer 510B is returned to the subset of voltage telemetry entry 512-1 (e.g., the entry for tile 1 of the first epoch) within the second buffer 500B.

[0076] The telemetry processing engine 110 is configured to detect various buffer error situations associated with the second buffer 500B. In response to a determination that advancing the write pointer 510B should position the write pointer 510B at the same set of entries as the read pointer 508B, the telemetry memory bridge 116 can detect a buffer overflow situation. Detection of the overflow situation can include, for example, an attempt by the telemetry memory bridge 116 to write an entry to the same set of telemetry data entries 512 pointed to by the read pointer 508B. As a result of detecting the buffer overflow situation, the telemetry memory bridge 116 can generate an interrupt, which is provided to and / or detected by the system control processor 120 and / or the management control processor 122. In response to registering the buffer overflow situation, in some implementations, the management control processor 122 can reset the position of the read pointer 508B and / or the position of the write pointer 510B to the initial position of the first buffer 500B. In connection with the buffer overflow situation, the system control processor 120 can adjust the operation of one or more tile sensor controllers 202, such as by re-initializing the controller and / or the sensor to sample the voltage telemetry data at a different sampling rate.

[0077] In some embodiments, the telemetry memory bridge 116 generates a timestamp 511B or other time information indicating the time at which the first one or more entries in a subset of the voltage telemetry entries 512 were received. It is noted that a subset of the voltage telemetry entries 512 for a given epoch may not necessarily be received in consecutive order or all at once. The telemetry memory bridge 116 includes the timestamp 511B in a second entry 504B of a second buffer 500B within the telemetry control memory 118. For example, a first timestamp may be included in a subset of the voltage telemetry entries 512-1 of the first epoch, a second timestamp may be included in a subset of the voltage telemetry entries 512-2 of the second epoch, and so on. In some embodiments, the timestamp 511B may be included as a separate entry within the second entry 504B. In some embodiments, the tile sensor controller 108 of the mesh node 102 can append a timestamp to the beginning of the voltage telemetry data, which is then transmitted via channel 104 to the telemetry memory bridge 116.

[0078] In some embodiments, the voltage telemetry data can include an address or identifier associated with the tile or mesh node where the voltage telemetry data was generated. The telemetry memory bridge 116 compares the address to the addresses of tiles 0, 1,...N and stores the voltage telemetry data in the second buffer 500B based on a match between the addresses. In the case of a subset of the voltage telemetry entries 512-1, the telemetry memory bridge 116 can receive telemetry data 114-2 including voltage telemetry data associated with the mesh node 102-2 (see FIG. 1). Based on the address or identifier within the telemetry data 114-2, the telemetry memory bridge 116 writes the voltage telemetry data to the tile 2 voltage location within the second buffer 500B for the subset of the voltage telemetry entries 512-1.

[0079] FIG. 5C illustrates a third circular buffer 500C storing third type of telemetry data according to one or more embodiments. The type of telemetry data stored in the third circular buffer 500C corresponds to measurements associated with tile 300 of the SoC architecture 100. The third buffer 500C includes a first plurality of entries 502C that identify an epoch with which the telemetry data is associated. The third buffer 500C also includes a second plurality of entries 504C for storing received current telemetry data.

[0080] The third buffer 500C has a size configured to store telemetry data for several K epochs and, for each epoch, several 2N current entries. More specifically, a first subset of the current telemetry entries 514-1 for the first epoch has several 2N current telemetry data entries, where the number N corresponds to the number of mesh nodes 102 in the SoC architecture 100. In some embodiments, the number of current telemetry data entries for a given epoch is based on the number of processor cores 106 associated with each of the mesh nodes 102. For example, if the number of processor cores 106 associated with each mesh node 102 is 4, the number of current telemetry data entries for a given epoch is 4N. The size of the third buffer 500C (e.g., the number K of epochs) may be selected based on the sampling rate of the current telemetry data and / or the number of processor cores 106 in tile 300.

[0081] In some embodiments, the current telemetry data stored in the current telemetry data entry can represent the current observed or measured by the current meter 214. In some embodiments, the current telemetry data stored in the current telemetry data entry can represent a statistical value generated by the sample processor 216 based on a plurality of current measurements obtained by the current meter 214 over a given period. As described herein, the statistical value may be, by way of non-limiting example, an average value, a median value, a maximum value, or a minimum value.

[0082] The third buffer 500C contains or is associated with a plurality of data objects. The first data object is a read pointer 508C that specifies an entry in the third buffer 500C that is to be read next by the system control processor 120, the management control processor 122, and / or another entity of the SoC architecture 100 or associated with the SoC architecture 100. The read pointer 508C can indicate the first entry within a set of current telemetry data entries 514 that are to be read. In response to the current telemetry data being read from the set of entries indicated by the read pointer 508C (e.g., associated with the current telemetry data of tile 300 of mesh node 102-1), the position of the read pointer 508C may be updated to indicate the next subset of current telemetry data - in this case, updated to indicate the first entry within a subset of current telemetry data entries 514-2 for tile 102-2 in the second epoch.

[0083] In some embodiments, the first entry within a subset of entries 514 can include time information associated with the set of entries. In some embodiments, each current telemetry data entry within the plurality of entries 504C includes or can reference (e.g., via a pointer) time information associated with the current telemetry data entry. In such embodiments, the current meter 214 in the current telemetry controller 206 can generate time information indicating the time at which the current telemetry data was acquired and can include the time information along with the current telemetry data.

[0084] The second data object is a write pointer 510C that specifies a set of second entries 504C within a third buffer 500C where current telemetry data will next be written. The write pointer 510C can indicate the first entry within the set of entries to be written. In response to all of the current telemetry data being written to a subset of the current telemetry entries 514-2 associated with the write pointer 510C, the position of the write pointer 510C is updated to indicate the next subset of current telemetry entries 514-3 (not shown). The write pointer 510C may, in some embodiments, be updated by the telemetry memory bridge 116.

[0085] In the third buffer 500C, the read pointer 508C is advanced to the next subset of entries after all of the entries within the current subset of entries associated with the read pointer 508C have been read. For example, the read pointer 508C may be updated from the first entry within the subset of entries 514-1 to the first entry within the subset of entries 514-2 after telemetry data has been read from any of the entries within the subset of entries 514-1. In some embodiments, the management control processor 122 advances the read pointer 508C to the next subset of entries 514.

[0086] The write pointer 510C is advanced to the next set of current telemetry entries after all of the entries within the set of entries associated with the write pointer 510C have been written. For example, the write pointer 510C may be updated from the first entry within the subset of entries 514-2 to the first entry within the subset of entries 514-3 (not shown) after current telemetry data has been written to all of the entries within the subset of entries 514-2. In some embodiments, the telemetry memory bridge 116 is configured to advance the write pointer 510C.

[0087] As a result of reading the telemetry data in the last entry in the third buffer 500C (e.g., the entry for tile N current of epoch K), the position of the read pointer 508C is returned to the first entry in the third buffer 500C (e.g., the entry for tile 1 of the first epoch). As a result of writing the telemetry data to the last remaining empty entry within a subset of the current telemetry entries 514-M, the position of the write pointer 510C is returned to a subset of the current telemetry entries 514-1 in the third buffer 500C (e.g., the entry for tile 1 of the first epoch).

[0088] The telemetry processing engine 110 is configured to detect various buffer error situations associated with the third buffer 500C. The telemetry memory bridge 116 can detect a buffer overflow situation in response to a determination that advancing the write pointer 510C should position the write pointer 510C at the same set of entries as the read pointer 508C. Detection of the overflow situation can include, for example, an attempt by the telemetry memory bridge 116 to write an entry to the same set of telemetry data entries 506 pointed to by the read pointer 508C. As a result of detecting the buffer overflow situation, the telemetry memory bridge 116 can generate an interrupt, which is provided to and / or detected by the system control processor 120 and / or the management control processor 122. In response to registering the buffer overflow situation, in some implementations, the management control processor 122 can reset the position of the read pointer 508C and / or the position of the write pointer 510C to the initial position of the first buffer 500C. In connection with the buffer overflow situation, the system control processor 120 can adjust the operation of one or more tile sensor controllers 202, such as by re-initializing the controller and / or sensor to sample the current telemetry data at a different rate.

[0089] In some embodiments, the telemetry memory bridge 116 generates a timestamp 511C or other time information indicating the time at which one or more first entries among a subset of the current telemetry entries 514 were received. It is noted that a subset of the current telemetry entries 514 for a given epoch may not necessarily be received in a consecutive order or all at once. The telemetry memory bridge 116 includes the timestamp 511C in a second entry 504C of a third buffer 500C within the telemetry control memory 118. For example, a first timestamp may be included in a subset of the current telemetry entry 514-1 for the first epoch, a second timestamp may be included in a subset of the current telemetry entry 514-2 for the second epoch, and so on. In some embodiments, the timestamp 511C may be included as a separate entry within the second entry 504C.

[0090] As described with respect to FIG. 3, a current controller may be associated with or included in each core 302. In some embodiments, each current controller can generate a timestamp for an individual current measurement. Each individual current telemetry data may include a timestamp indicating the time at which the current measurement was acquired, or the timestamp may be associated with each individual current telemetry data. For example, the current telemetry data for the first core within a subset of the current telemetry entry 514-1 can have a first timestamp, the current telemetry data for the second core within a subset of the current telemetry entry 514-1 can have a second timestamp, and the current telemetry data for the Nth core within a subset of the current telemetry entry 514-1 can have an Nth timestamp.

[0091] In some embodiments, the current telemetry data can include an address or identifier associated with the tile or mesh node where the current telemetry data was generated. The telemetry memory bridge 116 compares the address to the addresses of tiles 0, 1, ... N and stores the current telemetry data in the third buffer 500C based on a match between the addresses. In the case of a subset of the current telemetry entries 514-1, the telemetry memory bridge 116 can receive telemetry data 114-1, including the current telemetry data associated with core 1 of mesh node 102-2 (see FIGS. 1 and 3). Based on the address or identifier within the telemetry data 114-1, the telemetry memory bridge 116 writes the current telemetry data to the current location of core 1 within the third buffer 500C for the subset of the current telemetry entries 514-1.

[0092] FIG. 6A illustrates a set of status registers 600A for tracking telemetry data received by the telemetry memory bridge 116 over multiple epochs, according to one or more embodiments. The telemetry memory bridge 116 of the SoC architecture 100 stores and maintains a set of status registers for tracking the telemetry data received by the telemetry memory bridge 116. The status register 600A is represented as a table having rows and columns, which is provided for ease of explanation, and the status register 600A may be implemented as one or more arrays, data structures, or data objects in various embodiments.

[0093] The status register 600A includes a set of entries 602-1 for the tile corresponding to the first mesh node of the SoC architecture 100, a set of entries 602-2 for the tile corresponding to the second mesh node of the SoC architecture 100, a set of entries 602-3 for the tile corresponding to the third mesh node of the SoC architecture 100, up to a set of entries 602-N for the Nth mesh node of the SoC architecture 100. Referring specifically to the SoC architecture 100 shown in FIG. 1, for example, the Nth mesh node should be the ninth mesh node 102-9.

[0094] The status register 600A also includes a set of statuses for the types of telemetry data acquired during the first epoch, and a set of statuses for the types of telemetry data acquired during the second epoch. The set of statuses includes the tile temperature status 604-A for the first epoch, the tile temperature status 604-B for the second epoch, the tile voltage status 606-A for the first epoch, the tile voltage status 606-B for the second epoch, the tile current status 608-A of the first processor core (e.g., the processor core 302-1 in FIG. 3) during the first epoch, the tile current status 608-B of the first processor core during the second epoch, the tile current status 610-A of the second processor core (e.g., the processor core 302-2 in FIG. 3) during the first epoch, and the tile current status 610-B of the second processor core during the second epoch.

[0095] Each status register stores a bit that indicates whether the specified type of telemetry data is stored, has not yet been read, and the write pointer has not been advanced. During operation, the telemetry memory bridge 116 updates the value of the bit in response to receiving all of the telemetry data corresponding to the telemetry type during a given epoch. For example, the tile temperature status 604-A, tile voltage status 606-A, tile current status 608-A, and tile current status 610-A correspond to the status of the telemetry data for the first epoch, while the tile temperature status 604-B, tile voltage status 606-B, tile current status 608-B, and tile current status 610-B correspond to the status of the telemetry data for the second epoch.

[0096] As a result of storing the telemetry data in one of the circular buffers 500, the telemetry memory bridge 116 updates the corresponding bit in the status register. For example, as a result of receiving the temperature telemetry data of the mesh node 102-1 and storing this in a subset of the temperature telemetry entry 506-1 of the first buffer 500A, the telemetry memory bridge 116 can update the bit TA_1 of the tile temperature status 604-A from binary zero (0) to binary one (1). As a result of detecting that all of the status bits for the tile temperature status 604-A of the first epoch have been set to binary one (1), the telemetry memory bridge 116 can clear the status register for the tile temperature status 604-A (for example, by updating the bit TA_1 of the tile temperature status 604-A from binary one (1) back to zero (0)), and can advance the write pointer 510A from the current set of entries to the next subset of the temperature telemetry entry 506. The same principle applies to the other status bits 606, 608, and 610 in the status register 600A.

[0097] Telemetry memory bridge 116 can advance the write pointer 510 (see FIGS. 5A to 5C) of a given buffer 500 to the next subset of entries as a result of determining that telemetry data has been received and written to every entry within the current subset of entries. Telemetry memory bridge 116 updates the status registers for each telemetry type and for a given epoch as a result of receiving telemetry data of a designated type. Telemetry memory bridge 116 can, for example, receive temperature telemetry data associated with tile 1 and as a result update status TA_1 from binary value zero (0) to 1 (1). In response to receiving temperature telemetry data for each tile in a given epoch and updating status bit 604-A to binary value 1 (1), telemetry memory bridge 116 resets the value of status bit 604-A to binary zero (0) and increments write pointer 510A from the current subset of entries (e.g., subset 506-2) to the next subset of entries (e.g., subset 506-3).

[0098] Telemetry memory bridge 116 can detect an overrun error situation in response to a determination that (i) one or more of the status bits for a telemetry type of a first epoch (e.g., temperature status bit 604-A) are set to a first value indicating that telemetry data has not yet been received for one or more mesh nodes 102, and (ii) all of the status bits for the same telemetry type of a second epoch (e.g., temperature status bit 604-B) are set to a second value indicating that all telemetry data has been received for the mesh nodes. As a result of detecting the presence of an overrun error situation, telemetry memory bridge 116 can generate an interrupt that is provided to and / or detectable by system control processor 120 and / or management control processor 122.

[0099] As a more detailed example, the telemetry memory bridge 116 can detect the occurrence of an overrun error for tile 1 as a result of detecting that (i) the temperature status bit TA_1 has a binary value of zero (0), and simultaneously, (ii) all of the status register 604-B has transitioned to a binary value of one (1). In response to detecting the overrun error, the telemetry memory bridge 116 can generate an interrupt that causes the system control processor 120 and / or the management control processor 122 to perform one or more corrective actions. Such corrective actions can include sending a message 126 that causes the tile sensor controller 202 for mesh node 102-1 to modify the operation of the temperature sensor hub 212, or resetting the read pointer 508. Modifying the operation of the temperature sensor hub 212 can include reducing the sample rate of the temperature measurements or re-initializing the temperature sensor hub 212. This principle also applies to tile voltage statuses 606-A and 606-B, and tile current statuses 608 and 610.

[0100] A plurality of pointers 611 are associated with the status register 600A. The pointers may be provided for each type of telemetry data, and each type of telemetry data includes a pair of status bits. For example, in the case of the first tile 602-1 (corresponding to the mesh node 102-1), there are a pointer 611 and two temperature status bits TA_1 and TA_2. The temperature status bit TA_1 initially has a binary value of zero (0). The pointer 611 points to the temperature status bit TA_1 at the start of the first epoch. The start of an epoch, in some embodiments, corresponds to the time when time information (e.g., timestamp 611A, timestamp 511A) is generated and stored in the circular buffer, as described with respect to FIGS. 5A, 5B, and 5C. Those skilled in the art will understand that various factors (e.g., the location of the mesh node with respect to the designated mesh node 102-9, data traffic on the mesh network) affect the timing and / or order in which the telemetry data arrives at the telemetry processing engine 110. Thus, the start or end of an epoch may be marked by different types of telemetry data or by telemetry from different mesh nodes. Each of the plurality of pointers 611 corresponds to a memory location that stores the address of one of the status register bits within the status register 600A.

[0101] After the start of the first epoch, temperature telemetry data of the mesh node 102-1 is received and stored in the tile 1 temperature location within the set of temperature telemetry entries 506-1 of the first circular buffer 500A. In connection with storing the temperature telemetry data in the set of temperature telemetry entries 506-1, the telemetry memory bridge 116 updates the value of the temperature status bit TA_1 (pointed to by the pointer 611) from zero (0) to one (1). The telemetry memory bridge 116 can also advance the write pointer 510A to the next subset of the temperature telemetry data entry 506 (e.g., advance the write pointer 510A from the timestamp within the subset 506-1 to the subset 506-2).

[0102] During the first epoch, the telemetry memory bridge 116 detects that all the entries within the set of temperature telemetry entries 506-1 are filled in connection with the determination that all of the tile temperature status 604-A have the value one (1). In response to determining that the set of temperature telemetry entries 506-1 is filled with telemetry data, the telemetry memory bridge 116 resets each value of the tile temperature status 604-A to zero (0).

[0103] For the second epoch following the first epoch, the telemetry memory bridge 116 adjusts so that the pointer 611 points to the status bit TB_1. In the second epoch, temperature telemetry data of the mesh node 102-1 is received and stored in the tile 1 temperature location within the set of temperature telemetry entries 506-2 of the first circular buffer 500A. In connection with storing the temperature telemetry data in the set of temperature telemetry entries 506-2, the telemetry memory bridge 116 updates the value of the temperature status bit TB_1 (pointed to by the pointer 611) from zero (0) to one (1). The temperature memory bridge 116 also adjusts so that the pointer 611 points to the status bit TA_1 again.

[0104] During the second epoch, the telemetry memory bridge 116 detects that all of the entries within the set of temperature telemetry entries 506-2 are satisfied in connection with the determination that all of the tile temperature statuses 604-B have the value 1 (one). In response to determining that the set of temperature telemetry entries 506-2 is filled with telemetry data, the telemetry memory bridge 116 resets each value of the tile temperature status 604-B to zero (0).

[0105] FIG. 6B illustrates an example set of mask registers 600B for tracking the telemetry activation status of mesh node 102, or whether telemetry data collection has been activated for a particular telemetry type. The telemetry memory bridge 116 can utilize the mask register 600B in connection with tracking telemetry data status using the status register 600A as described elsewhere herein, or in connection with determining whether to issue a message 126 to modify the operation of telemetry data collection. The mask register 600B is represented as a table having rows and columns, which is provided for ease of explanation, and the mask register 600B may be implemented as one or more arrays, data structures, or data objects in various embodiments.

[0106] The mask register 600B includes a set of mask entries 612-1 for the tile corresponding to the first mesh node of the SoC architecture 100, a set of mask entries 612-2 for the tile corresponding to the second mesh node of the SoC architecture 100, a set of mask entries 612-3 for the tile corresponding to the third mesh node of the SoC architecture 100, up to a set of mask entries 612-N for the tile corresponding to the Nth mesh node of the SoC architecture 100. Specifically referring to the SoC architecture 100 shown in FIG. 1, for example, the Nth mesh node should be the ninth mesh node 102-9.

[0107] Mask register 600B also includes a set of masks for all types of telemetry data. The set of masks includes a tile temperature mask 614 for temperature telemetry, a tile voltage mask 616 for voltage telemetry, a tile current mask 618-1 for current telemetry of the first processor core (e.g., processor core 302-1 in FIG. 3), and a tile current mask 618-2 for current telemetry of the second processor core (e.g., processor core 302-2 in FIG. 3).

[0108] In some embodiments, telemetry memory bridge 116 implements a tile mask register to determine whether to generate an interrupt. For example, telemetry memory bridge 116 can determine, based on status register 600A, that voltage telemetry data has not been received in the current epoch and the next epoch (e.g., that entries VA_3 and VB_3 both have zero values), as indicated by tile voltage statuses 606-A and 606-B of mesh node 102-3. Even before generating an interrupt or error message, however, telemetry memory bridge 116 can reference the tile voltage mask status associated with mesh node 102-3 and detect that status mask VM_3 has a value (e.g., 1) indicating that the processor core 106 associated with mesh node 102-3 is inactive or disabled for voltage telemetry processing. As a result, telemetry memory bridge 116 does not generate an interrupt if there is no voltage telemetry data for the current epoch and / or the next epoch.

[0109] In some embodiments, the telemetry memory bridge 116 can perform a set of logical operations involving one or more of the status mask registers 600B in connection with determining whether all telemetry data of a particular type was received during a given epoch. As a specific example, the tile voltage status mask VM_1 for tile 300 associated with mesh node 102-1 can have a value indicating that the processor core 106 of mesh node 102-1 is inactive during a given epoch or is not susceptible to the effects of voltage telemetry data collection during the given epoch. The value of status mask VM_1 in such a scenario can be the binary value 1(1). The value of the tile voltage status register VA_1 can have the binary value zero (0) for the same given epoch indicating that voltage telemetry data was not received from mesh node 102-1. The telemetry memory bridge 116 can perform a logical OR operation using status mask VM_1 and status register VA_1 to obtain a result of the binary value 1(1). In some embodiments, the voltage status register VA_1 may be updated based on the status mask VM_1. The telemetry memory bridge 116, as a result of the status mask, may thus not generate an interrupt if there is no voltage telemetry data from mesh node 102-1 during a given epoch.

[0110] FIG. 7 illustrates a method 700 for synchronizing telemetry aggregation and buffering in the SoC architecture of FIG. 1 according to one or more embodiments. Method 700 can be implemented by one or more of the entities described herein, such as the telemetry memory bridge 116, the system control processor 120, and / or the management control processor 122. Specific features described with respect to FIG. 7 are discussed in more detail elsewhere in this specification and, thus, further explanation thereof is omitted for brevity.

[0111] Method 700 includes, at 702, receiving a first set of telemetry data associated with the operation of a plurality of processor cores of a SoC. The first set of telemetry data can be transmitted by one of a plurality of mesh network routers each associated with one of the mesh nodes 102, as described with respect to FIGS. 2 and 3 and elsewhere in this specification. The first set of telemetry data can include data generated by a plurality of tile sensor controllers (e.g., tile sensor controllers 204, 206, 306) corresponding to a subset of the mesh nodes 102. The first set of telemetry data can correspond, as a non-limiting example, to telemetry data 114-8, 114-5, or 114-7 of FIG. 1.

[0112] Method 700 also includes, at 704, receiving a second set of telemetry data associated with the operation of a plurality of processor cores of a SoC. The second set of telemetry data can be transmitted by one of a plurality of mesh network routers each associated with one of the mesh nodes 102, as described with respect to FIGS. 2 and 3 and elsewhere in this specification. The second set of telemetry data can include data generated by a plurality of tile sensor controllers (e.g., tile sensor controllers 204, 206, 306) corresponding to a subset of the mesh nodes 102. The second set of telemetry data can correspond, as a non-limiting example, to telemetry data 114-6, 114-3, or 114-2 of FIG. 1.

[0113] Method 700 further includes, at 706, determining that, during a second period, a first set of telemetry data corresponds to an incomplete set of telemetry data for a first epoch of telemetry data collection that includes the first period. Telemetry memory bridge 116 can detect a set of situations correlated with the incomplete set of telemetry data. The incomplete set of data is, more particularly, a set of data that does not include all of the telemetry data entries of a single subset of the telemetry data entries shown in FIGS. 5A, 5B, and 5C. For example, the incomplete set may be a set of temperature telemetry data that does not include all of a first subset of temperature entry 506-1. The incomplete set may be a set of voltage telemetry data that does not include all of a first subset of voltage telemetry entry 512-1. The incomplete set may be a set of current telemetry data that does not include all of a first subset of current telemetry entry 514-1. Further explanation regarding 706 is provided below with respect to FIG. 8.

[0114] Method 700 includes, at 708, transmitting a first set of messages to one or more controllers of a plurality of processor cores to modify operations associated with telemetry data collection. The messages transmitted at 708 correspond to message 126 sent to one or more tile sensor controllers 108 of SoC architecture 100. The messages transmitted at 708 include, in some embodiments, message 236 sent to VT telemetry controller 204 and / or message 238 sent to current telemetry controller 206. In some embodiments, the first set of messages transmitted at 708 includes message 242 that causes sensor trigger 240 to abort telemetry data collection by VT controller 204 and / or current controller 206 (e.g., as a result of issuing message 244 and / or message 246). The messages sent at 708 can cause one or more improvement actions to be implemented at tile temperature controller 108, VT telemetry controller 204, and / or current telemetry controller 206 that received the messages. The improvement actions implemented can include resetting or synchronizing one or more devices to align measurements in future epochs. Tile temperature controller 108, VT telemetry controller 204, and / or current telemetry controller 206 that received the messages can initiate telemetry data collection based on the same event, such as a ready signal or handshake issued over utility bus or channel 104.

[0115] Method 700 can include, at 710, transmitting a second set of messages to one or more controllers of a plurality of processor cores to modify operations associated with telemetry data collection. The messages transmitted at 710 correspond to messages 126 sent to one or more tile sensor controllers 108 of SoC architecture 100. The second set of messages causes one or more tile controllers 108 that receive the second set of messages to restart or reinitialize telemetry data collection. In some embodiments, the second set of messages transmitted at 710 can include a message 242 that causes sensor trigger 240 to issue commands to VT controller 204 and / or current controller 206 to command VT controller 204 and / or current controller 206 to restart telemetry data collection. In some embodiments, the second set of messages may be transmitted at 710 as a result of detecting that telemetry data collection was successfully aborted in response to the transmission of the first set of messages at 708. In some embodiments, instead of transmitting the second set of messages, one or more of tile sensor controllers 108 can detect that telemetry data collection has been aborted, and in response, can restart telemetry data collection.

[0116] Determining at 706 can involve utilization of status register 600A and / or mask register 600B. FIG. 8 shows a method 800 for determining error status associated with collecting telemetry data, according to one or more embodiments. Method 800 can be implemented by one or more entities described herein, such as telemetry memory bridge 116, system control processor 120, and / or management control processor 122. All or part of method 800 may be implemented in connection with determining at 706 when, during a second period, a first set of telemetry data corresponds to an incomplete set of telemetry data for a first epoch of telemetry data collection that includes a first period. The start of an epoch, in some embodiments, corresponds to the time at which time information (e.g., timestamp 511A, timestamp 513A) is generated and stored in a circular buffer, as described with respect to FIGS. 5A, 5B, and 5C.

[0117] Method 800 includes, at 802, storing a first set of telemetry data for a first epoch in a first section of a circular buffer. For example, telemetry memory bridge 116 can store a first set of telemetry data received at 702 over a first period in telemetry control memory 118. In some embodiments, the first set of telemetry data can include various types of telemetry data, such as temperature telemetry data, voltage telemetry data, current telemetry data, and / or status telemetry data. The first set of telemetry data stored at 802 is an incomplete set of data. For example, the first set of telemetry data may not include a subset of telemetry data entries for every memory location in temperature telemetry entry 506-1.

[0118] As a result of not storing a complete set of telemetry data at 802, one or more associated status bits within status register 600A can have a value of binary zero (0). Continuing with the previous example, telemetry memory bridge 116 may not receive temperature telemetry data for tile 1 temperature during the first epoch. Thus, the subset of temperature telemetry entry 506-1 is incomplete, and the tile temperature status TA_1 has a value of binary zero (0).

[0119] Storing a first set of telemetry data at 802 can include storing various types of telemetry data in various circular buffers. Telemetry memory bridge 116 can store temperature telemetry data in a first circular buffer 500A, voltage telemetry data in a second circular buffer 500B, and current telemetry data in a third circular buffer 500C. Storing a first set of telemetry data at 802 can include storing telemetry data associated with a given mesh node 102 in a particular section of the circular buffer. For example, telemetry data associated with mesh node 102-2 may be stored in the tile 2 temperature location of the subset of temperature telemetry entry 506-1 shown in FIG. 5A, corresponding to one or more memory addresses within telemetry control memory 118.

[0120] Method 800 further includes, at 804, storing a second set of telemetry data for a second epoch in a second section of the circular buffer. In some examples, the second set of telemetry data stored at 804 may be an incomplete set of data. As an example, the second set of telemetry data may not include telemetry data entries for any memory locations within a subset of temperature telemetry entries 506-2. The second set of telemetry stored at 804 may correspond to a second set of telemetry data received over a second period that is different from the second period at 702 and may be stored in telemetry control memory 118. Telemetry memory bridge 116 can update pointer 511 to indicate the next status bit within status register 600A, as described with respect to FIG. 6A.

[0121] In some embodiments, the second set of telemetry data can also include various types of telemetry data, such as temperature telemetry data, voltage telemetry data, current telemetry data, and / or status telemetry data. Storing the second set of telemetry data at 804 can include storing various types of telemetry data in various circular buffers. Telemetry memory bridge 116 can store temperature telemetry data in a first circular buffer 500A, voltage telemetry data in a second circular buffer 500B, and current telemetry data in a third circular buffer 500C. Storing the second set of telemetry data at 804 can include storing telemetry data associated with a given mesh node 102 in a particular section of the circular buffer. For example, telemetry data associated with mesh node 102-2 may be stored in the tile 2 temperature location of the subset of temperature telemetry entries 506-2 shown in FIG. 5A.

[0122] Method 800 can also include, at 806, receiving a third set of telemetry data for a third epoch. Continuing with the non-limiting example at 804, the telemetry memory bridge 116 can receive temperature telemetry data for the third time, after which the first telemetry data for the second epoch was received. The telemetry memory bridge 116 can receive temperature telemetry data associated with a third timestamp after a second timestamp of a subset of temperature telemetry entries 506-2+.

[0123] Method 800 can include, at 808, detecting an error based on a determination that the first set of telemetry data is an incomplete set of data. The error detected at 808 can correspond to a first error condition that the first set of telemetry data is an incomplete set of data when the third set of telemetry data is received at 806. The telemetry memory bridge 116 can determine that, when the third set of telemetry data is received at 806, the tile status bits for a particular type of telemetry data in the first epoch include one or more binary values of zero (0) and one or more binary values of one (1).

[0124] As an example, for the third time, the tile temperature status bit 604-A in the status register 600A can include one or more status bit zeros (0). For the third time, the tile temperature status bit 604-B can have a value of zero (0) as a result of the telemetry memory bridge 116 determining that the second set of telemetry data received at 804 is a complete set of telemetry data and resetting the value 1(1) to zero (0). Detecting an error at 808 corresponds to the situation where the write pointer 510 indicates a subset of the telemetry data two epochs after the third set of telemetry data was received at 806. In such a situation, data missing from the first set of telemetry data received at 702 may be lost, or the sampling rate may be set too high for the type of telemetry data.

[0125] In some examples, the detection of an error at 808 can be specific to the status bit. For example, the tile temperature status bit TA_1 may be set to zero (0) to indicate that temperature telemetry data for the first tile 602-1 was not received during the first epoch. For the third time, the telemetry memory bridge 116 can receive temperature telemetry data for the first tile 602-1 associated with a third timestamp after the second timestamp associated with the second set of data received at 704 of method 700. The telemetry memory bridge 116 can refer to the fact that the temperature status bit TA_1 of the first tile 602-1 still has a value of zero (0) indicating that the telemetry memory bridge 116 is still waiting for the temperature telemetry data of the tile 602-1 during the first epoch. Thus, the telemetry memory bridge 116 can detect the first error situation based on the zero (0) value of the temperature status bit TA_1.

[0126] The error detected at 808 may correspond to a second error condition determined by the telemetry memory bridge 116 that the first set of telemetry data stored at 802 is still an incomplete set of telemetry data when the telemetry data was received at 806 during the third epoch. During or at the end of the second epoch, for example, the telemetry memory bridge 116 can determine that all of the tile temperature status bits 604-B have a binary value of 1(1) indicating that the second set of temperature telemetry data during the second epoch is complete. In response, the telemetry memory bridge 116 adjusts the value of the tile temperature status bits 604-B to zero (0). Referring to the tile temperature status bits 604-A, the telemetry memory bridge 116 determines that one or more status bits having a value of zero (0) indicating that the first set of telemetry data stored at 802 is still incomplete are included in the tile temperature status bits 604-A. While the tile temperature status bits 604-A include one or more binary zero (0) values, in response to receiving the temperature telemetry data of the third epoch, the telemetry memory bridge 116 detects the presence of the second error condition based on the determination that the first set of the tile temperature status bits 604-A is incomplete when the third set of temperature telemetry data is received.

[0127] In response to detecting an error at 808, method 800 includes, at 810, generating an error status. Generating an error status at 810 (e.g., generating error status 125_) can include transmitting a message indicating the error to system control processor 120 and / or management control processor 122 via telemetry memory bridge 116. Generating an error status at 810 can include, in some embodiments, updating status bits monitored by system control processor 120 and / or management control processor 122 to different values. Generating an error status at 810 can include generating an interrupt detected by system control processor 120 and / or management control processor 122. Generating an error status at 810 can cause telemetry processing engine 110 to transmit one or more messages 126 as described herein. Generating an error message at 810 can include resetting the positions of the read and write pointers associated with the circular buffer as a result of determining that the first set of telemetry data corresponds to an incomplete set.

[0128] In connection with or in response to generating an error status at 810, telemetry processing engine 110 can re-initialize telemetry data collection, reset the read and write pointers of buffer 500, and re-initialize communication with management control processor 122. Telemetry processing engine 110 can then re-assert sensor trigger 240 to restart telemetry data collection again (e.g., via sending message 242).

[0129] Based on whether the error detected at 808 is a first error condition or a second error condition, different improvement actions can be implemented or commanded. For example, as a result of detecting the first error condition, message 126 sent by system control processor 122 can cause tile sensor controllers 108, 202 to adjust the sampling rate associated with one or more types of telemetry data. As another example, as a result of detecting the second error condition, message 126 can cause tile sensor controllers 108, 202 to synchronize telemetry data collection according to signal trigger 240 and, in some embodiments, based on a defined signal event (e.g., a signal edge). As a more detailed example, message 126 can cause VT telemetry controller 204 to re-initialize temperature sensor hub 212 and / or temperature sensor 308 to begin capturing temperature telemetry data at a clock signal edge or a trigger signal.

[0130] Figure 9 shows a method 900 for managing a status register in connection with receiving telemetry data during successive epochs, according to one or more embodiments. Method 900 can be implemented by one or more entities described herein, such as telemetry memory bridge 116, system control processor 120, and / or management control processor 122.

[0131] Method 900 includes, at 902, storing a first set of telemetry data in a first section of a circular buffer. For example, telemetry memory bridge 116 can store the first set of telemetry data received at 702 in telemetry control memory 118. In some embodiments, the first set of telemetry data can include various types of telemetry data, such as temperature telemetry data, voltage telemetry data, current telemetry data, and / or status telemetry data. Storing the first set of telemetry data at 902 can include storing various types of telemetry data in various circular buffers. Telemetry memory bridge 116 can store temperature telemetry data in a first circular buffer 500A, voltage telemetry data in a second circular buffer 500B, and current telemetry data in a third circular buffer 500C. Storing the first set of telemetry data at 902 can include storing telemetry data associated with a given mesh node 102 in a specific section of the circular buffer. For example, telemetry data associated with mesh node 102-2 may be stored in the tile 2 temperature location of a subset of temperature telemetry entries 506-1 shown in FIG. 5A that correspond to one or more memory addresses within telemetry control memory 118.

[0132] Method 900 also includes, in relation to storing the first set of telemetry data in the first section at 902, at 904, updating a first status bit in a status register. Continuing with the non-limiting example at 902, in relation to storing telemetry data in the tile 2 temperature location of a subset of temperature telemetry entries 506-1, telemetry memory bridge 116 can update the tile temperature status TA_2 of tile 602-2 from a binary value zero (0) to a binary value one (1).

[0133] In some implementations, one or more of the processor cores 106 associated with the mesh nodes 102 may be disabled or operated without sending telemetry data. At the start of an epoch, the telemetry memory bridge 116 can perform a set of logical operations to obtain results used to determine whether an error condition exists. For example, the telemetry memory bridge 116 can perform a set of logical operations using as operands the value of the status mask bits in the status mask register 600B and the value of the corresponding status bits in the status register 600A. As a more detailed non-limiting example, to determine the result associated with the tile voltage status VA_1 of tile 602-1, the telemetry memory bridge 116 can perform a logical OR operation using as operands (i) the value of the voltage mask VM_1 of the first mask entry 612-1 for the first tile, and (ii) the value of the status register VA_1. Obtaining a zero (0) value for this result should indicate that the voltage telemetry data for the first tile 602-1 in the first epoch is incomplete, while obtaining a one (1) value for this result should indicate that the voltage telemetry data for the first tile 602-1 in the first epoch is complete or masked, as described with respect to FIG. 6B and elsewhere in this specification.

[0134] In some embodiments, the telemetry memory bridge 116 can update the value of one or more status bits based on the value of an associated mask register bit. For example, at the beginning of an epoch, the telemetry memory bridge 116 can refer to the mask register 600B and update the corresponding status bit in the status register 600A for each mask bit in the mask register 600B. For example, the mask bit TM_3 may be set to a binary value 1(1) indicating that the processor core 106 associated with the mesh node 102-3 is disabled or operating without sending telemetry data. In response to detecting that the mask bit TM_3 has a value of binary 1(1), the telemetry memory bridge 116 can update the value pointed to by the pointer 611 associated with the tile temperature status bit 604 of the third tile 602-3. More specifically, the telemetry memory bridge 116 can update the value of the status bit TA_3 from a binary value zero (0) to a binary value 1(1). As a result of the foregoing operations, an error status may not be generated when the processor core 106 is disabled or operating without sending telemetry data.

[0135] In some implementations, the first set of telemetry data received over a first period may be a complete set of data in which the telemetry data is stored in every entry within the first subset of the temperature entry 506-1, as described with respect to 702. In such a situation, all of the status bits (e.g., tile temperature status 604-A) for a given set of status registers during an epoch have a binary value 1(1). As a result of detecting that a given set of status registers has a value of 1(1), method 900 includes, at 906, resetting the value of the first status bit (e.g., tile temperature status 604-A) back to a binary value zero (0).

[0136] Method 900 further includes, at 908, storing a second set of telemetry data in a second section of the circular buffer. For example, the telemetry memory bridge 116 can store the second set of telemetry data received at 702 in the telemetry control memory 118. In some embodiments, the second set of telemetry data can include various types of telemetry data such as temperature telemetry data, voltage telemetry data, current telemetry data, and / or status telemetry data. Storing the second set of telemetry data at 908 can include storing various types of telemetry data in various circular buffers. The telemetry memory bridge 116 can store temperature telemetry data in the first circular buffer 500A, voltage telemetry data in the second circular buffer 500B, and current telemetry data in the third circular buffer 500C. Storing the second set of telemetry data at 908 can include storing the telemetry data associated with a given mesh node 102 in a specific section of the circular buffer. For example, the telemetry data associated with mesh node 102-2 may be stored in the tile 2 temperature location of a subset of the temperature telemetry entry 506-2 shown in FIG. 5A.

[0137] Method 900 also includes, in relation to storing a first set of telemetry data in a first section at 908, at 910, updating a second status bit in the status register. Continuing with the non-limiting example at 908, in relation to storing telemetry data in the tile 2 temperature location of a subset of the temperature telemetry entry 506-2, the telemetry memory bridge 116 can update the tile temperature status TB_2 of tile 602-2 from the binary value zero (0) to the binary value one (1).

[0138] The second set of telemetry data received over the second period can be a complete set of data where the telemetry data is stored in any entry within the second subset of temperature entry 506-2. As a result of detecting that a given set of status registers has a value of one (1), method 900 includes, at 912, resetting the value of the second status bit (e.g., tile temperature status 604-B) back to the binary value zero (0).

[0139] Example computer system FIG. 10 depicts a simplified block diagram of an example computer system 1000 according to a particular embodiment. Computer system 1000 can be used to execute any of the computing devices, systems, or servers described in the foregoing disclosure. As shown in FIG. 10, computer system 1000 includes one or more processors 1002 that communicate with several peripheral devices via an interconnection system 1004. These peripheral devices include data storage 1006 (comprising memory 1008 and file storage subsystem 1100), user interface input device 1012, user interface output device 1014, and network interface subsystem 1016.

[0140] Interconnection system 1004 can provide a mechanism for communicating the various components and subsystems of computer system 1000 with each other as intended. Although interconnection system 1004 is shown schematically as a single bus, alternative embodiments of the bus subsystem can utilize multiple buses.

[0141] The network interface subsystem 1016 can serve as an interface for communicating data between the computer system 1000 and other computer systems or networks. Embodiments of the network interface subsystem 1016 can include, for example, Ethernet cards, Wi-Fi and / or cellular adapters, modems (telephone, satellite, cable, ISDN, etc.), digital subscriber line (DSL) units, and / or the like.

[0142] The user interface input device 1012 can include a keyboard, a pointing device (e.g., a mouse, trackball, touchpad, etc.), a touch screen incorporated in a display, an audio input device (e.g., a voice recognition system, a microphone, etc.), and other types of input devices. In general, the use of the term "input device" is intended to include all possible types of devices and mechanisms for inputting information into the computer system 1000.

[0143] The user interface output device 1014 can include a display subsystem, a printer, or a non-display device such as an audio output device, etc. The display subsystem can be, for example, a flat panel device such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) display. In general, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computer system 1000.

[0144] The data storage 1006 includes the memory 1008 and the file / disk storage subsystem 1010. The subsystems 1018 and 1020 represent non-transitory computer-readable storage media capable of storing program code and / or data that provide the functions of the embodiments of the present disclosure.

[0145] Memory 1008 includes several memories, including a main random access memory (RAM) 1018 for storing instructions and data during program execution, and a read-only memory (ROM) 1020 in which fixed instructions are stored. File storage subsystem 1010 can provide persistent (i.e., non-volatile) storage for programs and data files, and can include magnetic or solid-state hard disk drives, optical drives with associated removable media (e.g., CD-ROMs, DVDs, Blu-ray, etc.), removable flash memory-based drives or cards, and / or other types of storage media known in the art.

[0146] It should be understood that computer system 1000 is illustrative, and many other configurations are possible with more or fewer components than system 1000. Further embodiments The embodiments disclosed herein may be combined with other embodiments disclosed herein to create additional embodiments. The embodiments disclosed herein include receiving a first set of telemetry data associated with the operation of a plurality of processor cores of a system-on-chip (SoC) during a first epoch for telemetry data collection, receiving a second set of telemetry data associated with the operation of the plurality of processor cores during a second epoch for telemetry data collection, determining that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch, and transmitting a message to one or more controllers of the plurality of processor cores to modify operations associated with telemetry data collection as a result of determining that the first set of telemetry data corresponds to an incomplete set.

[0147] In some embodiments, the defined situation is an epoch overlap situation where a first epoch partially overlaps with a second epoch for telemetry data collection. In some embodiments, the message includes an instruction to modify the state of the trigger signal, and the collection of telemetry data for one or more of the plurality of processor cores is enabled or disabled based on the state.

[0148] In some embodiments, the method includes receiving a third set of telemetry data associated with the operation of a plurality of processor cores during a third epoch for telemetry data collection, and determining that one or more telemetry data instances of the first epoch are missing when the third set of telemetry data is received.

[0149] In some embodiments, the method includes storing a first set of telemetry data in a first section of a circular buffer, storing a second set of telemetry data in a second section of the circular buffer, updating a first status bit of a first plurality of status bits associated with a first epoch in a status register in relation to storing the first set of telemetry data in the first section, and updating a second status bit of a second plurality of status bits associated with a second epoch in the status register in relation to storing the second set of telemetry data in the second section, wherein determining that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second plurality of status bits to the defined state.

[0150] In some embodiments, the method comprises determining that a second set of telemetry data corresponds to a complete set of telemetry data for a second epoch of telemetry data collection, the second epoch being different from the first epoch and the determination being in response to a determination that the second epoch ends before receiving a complete first set of telemetry data for the first epoch, and transmitting a message.

[0151] In some embodiments, a first set of telemetry data and a second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and the method comprises updating a first bit of a status register and a second bit of the status register in response to receiving the first set of telemetry data, the first bit corresponding to the first type of telemetry data and the second bit corresponding to the second type of telemetry data; and updating a third bit of the status register and a fourth bit of the status register in response to receiving the second set of telemetry data, the third bit corresponding to the first type of telemetry data and the fourth bit corresponding to the second type of telemetry data.

[0152] Embodiments of the present disclosure include a telemetry memory bridge configured to receive a first set of telemetry data associated with the operation of a plurality of processor cores of a system-on-chip (SoC) during a first epoch for telemetry data collection, receive a second set of telemetry data associated with the operation of the plurality of processor cores during a second epoch for telemetry data collection, store the first set of telemetry data and the second set of telemetry data in a memory, determine that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch, and generate an error status as a result of the determination that the first set of telemetry data corresponds to an incomplete set of telemetry data. The system includes one or more control processors configured to detect the error status and transmit a message to one or more controllers of the plurality of processor cores to modify an operation associated with telemetry data collection as a result of the detected error status.

[0153] In some embodiments, the specified situation is an epoch overlap situation in which the first epoch partially overlaps with the second epoch for telemetry data collection. In some embodiments, the telemetry memory bridge is configured to receive a third set of telemetry data associated with the operation of the plurality of processor cores during a third epoch for telemetry data collection and determine that one or more telemetry data instances of the first epoch are missing when the third set of telemetry data is received.

[0154] In some embodiments, the telemetry memory bridge stores a first set of telemetry data in a first section of a circular buffer, stores a second set of telemetry data in a second section of the circular buffer, updates a first status bit of a first plurality of status bits associated with a first epoch in a status register in connection with storing the first set of telemetry data in the first section, and updates a second status bit of a second plurality of status bits associated with a second epoch in the status register in connection with storing the second set of telemetry data in the second section, wherein the determination that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second plurality of status bits to a defined state.

[0155] In some embodiments, the telemetry memory bridge determines that a second set of telemetry data corresponds to a complete set of telemetry data for a second epoch of telemetry data collection, wherein the second epoch is different from the first epoch and the determination is in response to the determination that the second epoch has ended prior to the first epoch and a message has been transmitted.

[0156] In some embodiments, a first set of telemetry data and a second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and the telemetry memory bridge is configured to update a first bit of a status register and a second bit of the status register in response to receiving the first set of telemetry data, wherein the first bit corresponds to the first type of telemetry data and the second bit corresponds to the second type of telemetry data, and to update a third bit of the status register and a fourth bit of the status register in response to receiving the second set of telemetry data, wherein the third bit corresponds to the first type of telemetry data and the fourth bit corresponds to the second type of telemetry data.

[0157] In some embodiments, the message includes an instruction to modify the state of a trigger signal, and collection of telemetry data for one or more of a plurality of processor cores is enabled or disabled based on the state.

[0158] Embodiments of the present disclosure include a system-on-chip comprising a plurality of processor cores, a memory, a telemetry memory bridge coupled to the memory, a control processor communicatively coupled to the telemetry memory bridge, and a plurality of mesh network routers each configured to route telemetry data associated with one or more of the processor cores to the telemetry memory bridge. The telemetry memory bridge is configured to receive a first set of telemetry data associated with the operation of a plurality of processor cores of a system-on-chip (SoC) during a first epoch for telemetry data collection, wherein the first set of telemetry data is transmitted by a mesh network router among the plurality of mesh network routers; receive a second set of telemetry data associated with the operation of the plurality of processor cores during a second epoch for telemetry data collection, wherein the second set of telemetry data is transmitted by the mesh network router; store the first set of telemetry data and the second set of telemetry data in the memory; determine that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch; and generate an error status as a result of the determination that the first set of telemetry data corresponds to an incomplete set of telemetry data. The control processor is configured to detect the error status and transmit a message to one or more controllers of the plurality of processor cores to modify an operation associated with telemetry data collection.

[0159] In some embodiments, the telemetry memory bridge includes a status register having a first plurality of status bits associated with a first epoch and a second plurality of status bits associated with a second epoch, the telemetry memory bridge being configured to update a first status bit of the first plurality of status bits in response to receiving a first set of telemetry data and to update a second status bit of the second plurality of status bits in response to receiving a second set of telemetry data, the control processor being configured to determine that the first set of telemetry data corresponds to an incomplete set in response to a transition of the second plurality of status bits to a defined state, and to perform the updating.

[0160] In some embodiments, the telemetry memory bridge includes a mask register having a first mask bit associated with a first processor core of a plurality of processor cores and a second mask bit associated with a second processor core of the plurality of processor cores, the telemetry memory bridge being configured to determine a first result associated with a first status bit based on a value of the first mask bit and to determine a second result associated with a second status bit based on a value of the second mask bit, the determination that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch being based on the first result or the second result.

[0161] In some embodiments, the defined situation is an epoch overlap situation in which the first epoch partially overlaps the second epoch for telemetry data collection. In some embodiments, the telemetry memory bridge is configured to receive a third set of telemetry data associated with the operation of a plurality of processor cores during a third epoch for telemetry data collection, and to determine that one or more telemetry data instances of the first epoch are missing when the third set of telemetry data is received.

[0162] In some embodiments, the telemetry memory bridge is configured to determine that a second set of telemetry data corresponds to a complete set of telemetry data for a second epoch for telemetry data collection, the second epoch being different from the first epoch and the transmission of messages being in response to a determination that the second epoch ends before the first epoch.

[0163] The above description illustrates various embodiments of the present disclosure, along with examples of how aspects of these embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the flexibility and advantages of the present disclosure as defined by the following claims. For example, although specific embodiments have been described with respect to specific process flows and steps, it should be apparent to those skilled in the art that the scope of the present disclosure is not strictly limited to the described flows and steps. Steps described as sequential may be executed in parallel, the order of steps may be changed, and steps may be modified, combined, added, or omitted. As another example, although specific embodiments have been described using a specific combination of hardware and software, it should be recognized that other combinations of hardware and software are possible, and that specific operations described as being implemented in software may also be implemented in hardware, and vice versa.

[0164] The specification and drawings should therefore be regarded in an illustrative rather than a restrictive sense. Other arrangements, embodiments, implementations, and equivalents will be apparent to those skilled in the art and may be employed without departing from the spirit and scope of the disclosure as described in the following claims.

Claims

1. Memory and It is a telemetry memory bridge, During the first epoch for telemetry data collection, a first set of telemetry data associated with the operation of multiple processor cores of the system-on-a-chip (SoC) is received, During a second epoch for telemetry data collection, a second set of telemetry data associated with the operation of the plurality of processor cores is received, The first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and in response to receiving the first set of telemetry data, the first bit corresponds to the first type of telemetry data and the second bit corresponds to the second type of telemetry data, and the update is as follows: The first set of telemetry data and the second set of telemetry data are stored in the memory, It is determined that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch, As a result of the determination that the first set of telemetry data corresponds to an incomplete set of telemetry data, an error status is generated. A telemetry memory bridge configured to perform the following: One or more control processors, To detect the aforementioned error status, As a result of detecting the aforementioned error status, a message is transmitted to one or more controllers of the plurality of processor cores in order to correct the operation associated with telemetry data collection, thereby improving the error situation associated with telemetry data production. One or more control processors configured to perform the following: A system that includes this.

2. The system according to claim 1, wherein the defined situation is an epoch overlap situation in which the first epoch partially overlaps with a second epoch for telemetry data collection.

3. The system according to claim 1, wherein the telemetry memory bridge is During a third epoch for telemetry data collection, a third set of telemetry data associated with the operation of the plurality of processor cores is received, When the third set of telemetry data is received, it is determined that one or more telemetry data instances from the first epoch are missing. A system configured to perform the following actions.

4. The system according to claim 1, wherein the telemetry memory bridge is The first set of telemetry data is stored in the first section of the circular buffer, The second set of telemetry data is stored in the second section of the circular buffer, In connection with storing the first set of telemetry data in the first section, the first status bit among a plurality of first status bits associated with the first epoch in the status register is updated, A system configured to update a second status bit of a second set of status bits associated with the second epoch in the status register, in connection with storing the second set of telemetry data in the second section, wherein the decision that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second set of status bits to a predetermined state.

5. The system according to claim 1, wherein the telemetry memory bridge is The determination that the second set of telemetry data corresponds to the complete set of telemetry data for a second epoch for telemetry data collection, the second epoch being different from the first epoch, and the transmission of the message is in response to the determination that the second epoch is completed before the first epoch. A system configured to perform the following actions.

6. The system according to claim 1, wherein the first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and the telemetry memory bridge is Updating the third bit and the fourth bit of the status register in response to receiving the second set of telemetry data, wherein the third bit corresponds to the first type of telemetry data and the fourth bit corresponds to the second type of telemetry data. A system configured to perform the following actions.

7. The system according to claim 1, wherein the message includes an instruction for modifying the state of a trigger signal, and the collection of telemetry data for one or more processor cores among the plurality of processor cores is enabled or disabled based on the state.

8. The steps include receiving a first set of telemetry data associated with the operation of multiple processor cores of a system-on-a-chip (SoC) during a first epoch for telemetry data collection, The steps include receiving a second set of telemetry data associated with the operation of the plurality of processor cores during a second epoch for telemetry data collection, The first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and the step of updating a first bit and a second bit of the status register in response to receiving the first set of telemetry data, wherein the first bit corresponds to the first type of telemetry data and the second bit corresponds to the second type of telemetry data, The steps include determining that the first set of telemetry data corresponds to an incomplete set of telemetry data for the first epoch, As a result of determining that the first set of telemetry data corresponds to an incomplete set, a message is transmitted to one or more controllers of the plurality of processor cores in order to correct the operation associated with telemetry data collection, thereby improving the error situation associated with telemetry data production. A method that includes this.

9. A method according to claim 8, wherein the defined situation is an epoch overlap situation in which the first epoch partially overlaps with a second epoch for telemetry data collection.

10. The method according to claim 8, The steps include receiving a third set of telemetry data associated with the operation of the plurality of processor cores during a third epoch for telemetry data collection, When the third set of telemetry data is received, the step of determining that one or more telemetry data instances from the first epoch are missing. A method that includes this.

11. The method according to claim 8, The steps include storing the first set of telemetry data in a first section of a circular buffer, The steps include storing the second set of telemetry data in the second section of the circular buffer, In connection with storing the first set of telemetry data in the first section, the steps include updating a first status bit among a plurality of first status bits associated with the first epoch in the status register, In connection with storing the second set of telemetry data in the second section, the step of updating a second status bit among a second set of status bits associated with the second epoch in the status register, wherein the determination that the first set of telemetry data corresponds to an incomplete set is in response to a transition of the second set of status bits to a predetermined state, and A method that includes this.

12. The method according to claim 8, The step of determining that the second set of telemetry data corresponds to a complete set of telemetry data for a second epoch for telemetry data collection, wherein the second epoch, unlike the first epoch, is in response to the determination that the transmission of the message is completed before the first complete set of telemetry data for the first epoch is received. A method that includes this.

13. The method according to claim 8, wherein the first set of telemetry data and the second set of telemetry data include a first type of telemetry data and a second type of telemetry data, and the method is Steps of updating a first bit and a second bit of a status register in response to receiving the first set of telemetry data, wherein the first bit corresponds to the first type of telemetry data and the second bit corresponds to the second type of telemetry data, Steps to update a third bit and a fourth bit of the status register in response to receiving the second set of telemetry data, wherein the third bit corresponds to the first type of telemetry data and the fourth bit corresponds to the second type of telemetry data. A method that includes this.

14. A method according to claim 8, wherein the message includes an instruction for modifying the state of a trigger signal, and the collection of telemetry data for one or more processor cores among the plurality of processor cores is enabled or disabled based on the state.

Images