Apparatus using lap tracking to address data overflow

Abstract

The device includes a circular buffer, which contains a fixed number of entries and allows for data overflow while maintaining the most recently stored entries in order. The circular buffer can be used as a return address stack used in a processor to push / pop return addresses for subroutine calls. Additional circuitry dynamically links the entries to maintain a last-in, first-out stack. A system return pointer tracks the next entry to be returned when an entry is read. When data is pushed into an entry in the circular buffer, the entry stores a pointer to the entry relative to the previous system return pointer. By tracking the previous system return pointer with the pushed entry, the dynamically linked entry can skip previously popped intervening entries and track the order of recently written, unpopped entries without having to maintain separate free and used lists.

Description

[Technical Field] 【0001】 Priority application This application claims priority to U.S. Patent Application No. 17 / 816,513, filed August 1, 2022, entitled "AN APPARATUS EMPLOYING WRAP TRACKING FOR ADDRESSING DATA OVERFLOW," which is incorporated herein by reference in its entirety. 【0002】 The techniques of this disclosure relate generally to data buffer overflows, and more particularly to an efficient apparatus for addressing data buffer overflows in computer microarchitectures. [Background technology] 【0003】 Computer software programming constructs include subroutines for grouping together sets of instructions that are frequently called to perform a task or operation. When a program containing a call to a subroutine is compiled, the compiled program will include a call instruction to the subroutine that jumps to the program address of the subroutine. The compiler will also include an instruction in the subroutine that is a return instruction to terminate the subroutine when its execution is complete. When a processor executes a subroutine, the processor must determine a program return address to return to when the return instruction is processed. In the context of computer microarchitecture, conventional processors utilize a return address stack (RAS) to track return addresses resulting from subroutine calls, so that the processor can determine which program address to return to after the subroutine's execution is complete. When the processor encounters a call instruction to a subroutine, the processor adds or pushes the return address to the RAS. Thus, when the processor encounters a return instruction, the processor reads or pops the return address from the RAS and then returns to executing instructions beginning at the return address. 【0004】 A RAS system is a fixed data buffer utilized to hold return addresses from call-type instructions. Because a return address stack system includes a fixed RAS structure in memory, programs executed by a processor can sometimes cause the RAS to overflow, or in other words, write more information to the return address stack than the stack can physically store. Traditional return address stack systems may or may not address overflow situations. However, due to today's deep processor pipelines and their use of predictive instruction fetching, computer architecture designs must also address managing return addresses when a branch instruction is deemed mispredicted by the processor. 【0005】 Some conventional approaches for RAS systems completely eliminate overflow situations. These approaches limit the number of new entries to be added to the RAS, which, under overflow conditions, results in inconsistencies between the added entries due to the specific call and return addresses returned by the RAS. Therefore, these conventional RAS systems have defined their fixed RAS to be increasingly large so as to delay but not prevent data overflow. In addition, for a branch instruction misprediction, all entries in these conventional RAS systems are reset, or in other words, flushed, thereby losing any history of the return address. Other conventional RAS systems that address data overflow situations utilize tracking systems for valid / invalid entries in the RAS. These conventional tracking systems include a checkpoint table to save the state of the RAS for each call-type instruction. Specifically, before writing an entry to the RAS for a call-type instruction, the tracking system in those conventional RAS systems performs a content addressable memory (CAM) lookup on the checkpoint table each time a call-type instruction is received to ensure that the next RAS entry to be returned has previously been retired or committed. If the entry has previously been retired or committed, the entry is available. Otherwise, those conventional approaches must find an available entry in a separately managed free list of entries and manage the order of the list of valid entries. The CAM lookup consumes energy and impacts system performance. Summary of the Invention [Problem to be solved by the invention] 【0006】 To conserve processing power and improve performance, there is a need for more efficient data devices that can handle data overflow while reducing overhead such as that caused by CAM lookups. [Means for solving the problem] 【0007】 Aspects disclosed in the detailed description include an apparatus that uses wrap tracking to address data overflow. In one example, the apparatus includes a circular buffer that includes a fixed number of entries for data storage and allows data overflow to occur while maintaining the most recently stored data entries in order. For example, the circular buffer may be used as a return address stack (RAS) buffer used to push and pop return addresses for subroutine calls in a processor. In an exemplary aspect, entries in the circular buffer are statically linked in the forward direction and dynamically linked in the backward direction. Entries are written or pushed in the forward direction, while entries are read or popped in the backward direction. Additional circuitry is utilized to manage the dynamic linking in the backward direction. A system return pointer tracks the next entry to be returned when an entry is to be read. When data is pushed into an entry in the circular buffer, the entry stores a pointer to the entry relative to the previous system return pointer. By tracking previous system return pointers in pushed entries, the backward-linked buffer skips over intervening entries that were previously popped, and thus can dynamically track the order of recently written, unpopped entries without having to maintain separate free and used lists in the circular buffer. 【0008】 In another exemplary embodiment, the apparatus is further used as a return address stack (RAS) having a processor pipeline that uses predictive fetching of instructions. In this example, entries are written to and read from the RAS circular buffer speculatively. When using a return address stack system according to the present disclosure with predictive fetching, the RAS system will also efficiently manage the retirement or commitment of call-type instructions and return instructions. For example, this exemplary embodiment will address the retirement of a return instruction whose associated data entry in the RAS has already returned. If the return instruction was part of a correctly predicted branch, the entry associated with the committed return instruction will have already returned and may have been overwritten by a subsequent call instruction, thereby eliminating the need for further processing of the entry for the commit signal. In another embodiment, each entry includes a global wrap count value to track the particular circular iteration (i.e., loop count) of the circular buffer at which the entry is written to the buffer. The global wrap count value is configured to be written with the iteration count of the circular buffer at the time the entry is written. By utilizing the copied global wrap count in the circular buffer entry, the RAS system can track whether the entry associated with the retiring / committing of the return instruction has been overwritten and is therefore available, thus eliminating the need to reset the entry associated with the retired instruction. By dynamically linking the return address with the global wrap counter mechanism, the RAS system of the present disclosure tracks whether an entry has been overwritten without requiring a CAM search of the checkpoint buffer to find the appropriate entry that needs to be retired and without managing valid / invalid bits to determine whether the appropriate entry has been overwritten. 【0009】 Other aspects of the present disclosure will include how this novel approach addresses restoring the state of the RAS for a misprediction of a call-type instruction prior to speculatively writing the RAS entry associated with the call-type instruction. 【0010】 Data buffer overflows can generally occur in many use cases. In general, data buffer overflows can occur anywhere there is a fixed size buffer and the demand to add more entries to the data buffer exceeds the fixed buffer size and the demand to consume entries. Aspects of the examples disclosed herein are generally applicable to addressing data buffer overflows. 【0011】 In this regard, one exemplary aspect provides an apparatus including a circular buffer. The apparatus also includes a return pointer register, a global wrap group register, and a buffer manager circuit. The circular buffer includes a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, and each entry among the fixed number of entries includes a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to and a second field configured to store a link to a next entry to return upon a read request after the entry is read from the circular buffer. The return pointer register is configured to track a most recently added data entry among the fixed number of entries. The global wrap group register is configured to store a value representing the number of iterations in which the circular buffer has been written. The buffer manager circuit is configured to, in response to a write request, determine a next available entry among the fixed number of entries, update the local wrap group field of the next available entry to the value of the global wrap group register, and update the second field of the next available entry to the value of the return pointer register. 【0012】 In another exemplary aspect, a method for managing a LIFO system is provided. The method includes establishing a circular buffer. The circular buffer includes a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, and each entry among the fixed number of entries includes a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to and a second field configured to store a link to a next entry to return upon a read request after the entry is read from the circular buffer. The method further includes establishing a return pointer register configured to track a most recently added data entry among the fixed number of entries and establishing a global wrap group register configured to store a value representing the number of iterations in which the circular buffer has been written. In response to a write request, the method includes determining a next available entry among the fixed number of entries, updating the local wrap group field of the next available entry to the value of the global wrap group register, and updating the second field of the next available entry to the value of the return pointer register. 【0013】 In another aspect, a non-transitory computer-readable medium having computer-executable instructions stored thereon is provided that, when executed by a processor, cause the processor to establish a circular buffer, the circular buffer including a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, wherein an entry among the fixed number of entries includes a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to and a second field configured to store a link to the next entry to return on a read request after the entry is read from the circular buffer. The computer-executable instructions also cause the processor to establish a return pointer register configured to track a most recently added data entry among the fixed number of entries and to establish a global wrap group register configured to store a value representing the number of iterations in which the circular buffer has been written. In response to a write request, the computer-executable instructions cause the processor to determine a next available entry of the fixed number of entries, update a local wrap group field of the next available entry to the value of the global wrap group register, and update a second field of the next available entry to the value of the return pointer register. [Brief explanation of the drawings] 【0014】 [Figure 1] FIG. 1 is a block diagram of an initialization state of an exemplary last-in-first-out (LIFO) system including a circular buffer that uses wrap tracking to handle data overflow. [Figure 2] FIG. 2 is a block diagram of the state of the LIFO system of FIG. 1 after two write requests. [Figure 3] FIG. 3 is a block diagram of the state of the LIFO system of FIG. 2 after a read request. [Figure 4]FIG. 4 is a block diagram of the state of the LIFO system of FIG. 3 after each entry in the circular buffer has been written. [Figure 5] FIG. 5 is a block diagram of the state of the LIFO system of FIG. 4 after the first entry in the circular buffer has been overwritten without being returned. [Figure 6] FIG. 1 is a block diagram of an exemplary processor-based system including a central processing unit (CPU) including instruction processing circuitry and a RAS system configured to use wrap tracking to address data overflow and instruction mispredictions. [Figure 7] FIG. 7 is a block diagram of the state of the RAS system of FIG. 6 after the first entry in the RAS buffer has been overwritten. [Figure 8] FIG. 7 is a block diagram of the state of the RAS system of FIG. 6 when a commit signal for a return instruction is received. [Figure 9] 7 is a block diagram illustrating the state of the RAS system of FIG. 6 when a conditional branch instruction is determined to be mispredicted. [Figure 10] 11 is a flow chart for the operation of a buffer manager circuit that maintains the order of recent entries in a circular buffer, including but not limited to the circular buffers of FIGS. 1-5 and the RAS systems of FIGS. 6-10. [Figure 11] FIG. 10 is a block diagram of an exemplary processor-based system that may include a LIFO system, such as the LIFO systems shown in FIGS. 1 and 6, where the LIFO system includes a buffer manager circuit configured to utilize at least wrap tracking to address data overflow while maintaining the most recently written entries. DETAILED DESCRIPTION OF THE INVENTION 【0015】 Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. 【0016】 Aspects disclosed in the detailed description include a circular buffer that uses wrap tracking to address data overflow. In one example, the circular buffer is a fixed-size circular buffer containing a fixed number of entries for data storage, which allows data overflow to occur while maintaining the most recently stored data entries in order. For example, the circular buffer may be used as a return address stack (RAS) buffer used to push and pop return addresses for subroutine calls in a processor. In an exemplary aspect, entries in the circular buffer are statically linked in the forward direction and dynamically linked in the backward direction. Entries are written or pushed in the forward direction, while entries are read or popped in the backward direction. Additional circuitry is utilized to manage the dynamic linking in the backward direction. A system return pointer tracks the next entry to be returned when an entry is to be read. In other words, the system return pointer tracks the entry most recently added to the circular buffer. When data is pushed into an entry in the circular buffer, the entry stores a pointer to the entry for the previous system return pointer. By tracking the previous system return pointer in the pushed entry, the backward-linked buffer skips over intervening entries that were previously popped, and thus can dynamically track the order of recently written, unpopped entries without having to maintain separate free and used lists within the circular buffer. In another exemplary aspect, the circular buffer is also used in a processor pipeline that uses predictive fetching of instructions. In this example, entries are written to the RAS and entries are read from the RAS speculatively.When using a return address stack system according to the present disclosure in conjunction with predictive fetching, the RAS system will also efficiently manage the retirement or commitment of call-type instructions and return instructions. For example, this exemplary embodiment will address the retirement of a return instruction whose associated data entry in the RAS has already returned. If the return instruction was part of a correctly predicted branch, the entry associated with the committed return instruction will have already returned and may have been overwritten by a subsequent call instruction, thereby eliminating the need for further processing of the entry for the commit signal. In another embodiment, each entry includes a global wrap count value to track the particular circular iteration (i.e., loop count) of the circular buffer at which the entry is written to the buffer. The global wrap count value is configured to be written with the iteration count of the circular buffer at the time the entry is written. By utilizing the copied global wrap count in the circular buffer entries, the RAS system can track whether an entry associated with the retirement / commit of a return instruction has been overwritten and is therefore available, thereby eliminating the need to reset the entry associated with the retired instruction. By dynamically linking the return address with a global wrap counter mechanism, the RAS system of the present disclosure tracks whether an entry has been overwritten without requiring a CAM search of the checkpoint buffer to find the appropriate entry that needs to be retired, and without managing valid / invalid bits to determine whether the appropriate entry has been overwritten. 【0017】 1-5 illustrate various states of an exemplary last-in, first-out (LIFO) system according to the present disclosure based on a particular set of write and read requests. Through this progression, an exemplary operation of LIFO system 2 can be understood in that it advantageously allows entries to be overwritten while maintaining a list of most recently written entries. FIGS. 6-10 illustrate an example of a LIFO system deployed in conjunction with an instruction processing system. Before describing the example instruction processing system of FIGS. 6-10, FIGS. 1-5 are first described below. 【0018】 In this regard, FIG. 1 is a block diagram of an exemplary LIFO system 2 in an initialization state 3 during initialization, according to one example of the present disclosure. As shown in FIG. 1, the LIFO system 2 includes a buffer manager circuit 4 and a circular buffer circuit 6, also referred to herein as a “circular buffer 6.” The circular buffer 6 is used to store entries and return individual entries as needed. The circular buffer 6 may be used as a return address stack, as described with respect to FIGS. 6-9. The circular buffer 6 includes eight entries 8A-8H. The buffer manager circuit 4 includes a global wrap group register 10 that stores a value representing the number of iterations that the entries 8A-8H of the circular buffer 6 have been written to so far. The buffer manager circuit 4 also includes a return pointer register 12 that stores the address of one of the entries 8A-8H to indicate the particular entry to return upon a read request. As will be shown later in the description, the return pointer register 12 will contain the entry most recently added to the circular buffer circuit 6. At initialization, the global wrap group register 10 and the return pointer register 12 are set to 0. For illustrative purposes, the size of the circular buffer 6 is set to eight entries, but it should be noted that the concepts described herein can be easily extended to various sizes. Also, it should be noted that while the circuits and registers described herein are implemented in hardware, they can also be implemented in software logic and software variables. 【0019】 In this example, buffer manager circuit 4 also includes a head pointer register 14 that stores the address of one of entries 8A-8H to indicate the beginning of the list in circular buffer 6, and a tail pointer register 16 that stores the address of one of entries 8A-8H to indicate the end of the list in circular buffer 6. At initialization, head pointer register 14 is set to the address of entry 8A, and tail pointer register 16 is set to the address of entry 8H. Buffer manager circuit 4 may also include a call pointer register 18 that stores the address of one of entries 8A-8H to indicate the entry in circular buffer 6 to write to upon the next write request. The write request may be the result of a subroutine call instruction. At initialization, call pointer register 18 and return pointer register 12 are set to the address of entry 8A. 【0020】 Entries 8A-8H include next fields 22A-22H, data fields 24A-24H, backward link fields 26A-26H, and local wrap group fields 28A-28H. Next field 22 contains the address of the next forward entry in circular buffer 6. As shown in FIG. 1, next field 22A of entry 8A contains the address of entry 8B, next field 22B of entry 8B contains the address of entry 8C, and so on up to entry 8H, linking the entries clockwise in a circular fashion. Thus, next fields 22A-22H statically link entries 8A-8H in the forward direction. 【0021】 Data fields 24A-24H contain the data to be returned when the respective entry is read. Data fields 24A-24H are initialized to zero, but in this example will eventually contain the data that will be read as a result of a read request. Data fields 24A-24H can contain any type of data, including values and addresses. Backward link fields 26A-26H are initially set to zero. During a write request, the backward link field of the written entry will contain the address of the next entry to be returned after the written entry has been returned. As will be explained later, backward link fields 26A-26H will form a list of entries to be read during a series of read requests. Local wrap group fields 28A-28H are initialized to zero and contain the iteration number at which the respective entry was written. As will be explained later, local wrap group field 28A will be assigned the current value of global wrap group register 10 at the time the respective entry 8A-8H was written as a result of a write request. 【0022】 2 is a block diagram of a state 200 of the LIFO system 2 of FIG. 1 after two write requests, a first write request 202 and a second write request 204. In response to the first write request 202, the buffer manager circuit 4 writes to entry 8A, also known as “entry #0,” because entry 8A was where the call pointer register 18 pointed at during initialization. Specifically, the buffer manager circuit 4 writes “d1” to the data field 24A, writes a 0 to the backward link field 26A because this was the first entry written after initialization, and writes a 0 to the local wrap group field 28H because this was the value of the global wrap group register 10 immediately before entry 8A received the first write request 202. 2, after writing to entry 8A in response to first write request 202, buffer manager circuit 4 will advance call pointer register 18 by copying the address from next field 22A to contain the address of entry 8B, the next entry to be written. Also, although not shown in FIG. 2, after writing first write request 202, buffer manager circuit 4 will set return pointer register 12 to contain the address of entry 8A, since entry 8A will be returned if a read request is received by buffer manager circuit 4 prior to a subsequent write request. 【0023】 In response to the second write request 204, buffer manager circuit 4 writes to entry 8B, specifically, writes “d2” to data field 24B, writes the address of entry 8A to backward link field 26B because that was the value of return pointer register 12 after processing first write request 202, and writes 0 to local wrap group field 28H because that was the value of global wrap group register 10 immediately before entry 8A received the write request. After writing to entry 8B in response to second write request 204, buffer manager circuit 4 will advance call pointer register 18 by copying the address from next field 22B to include the address of entry 8C, the next entry to be written. Also, after writing to entry 8B in response to second write request 204, buffer manager circuit 4 will set return pointer register 12 to include the address of entry 8B because entry 8B will be returned if a read request is received by buffer manager circuit 4 prior to a subsequent write request. As can be seen in FIG. 2, the entries between the call pointer register 18 and the tail pointer register 16 are available to be written. 【0024】 FIG. 3 is a block diagram of a state 300 of the LIFO system 2 of FIG. 2 after a read request 302. In response to the read request 302, the buffer manager circuit 4 reads the address pointed to by the return pointer register 12, which was entry 8B (see FIG. 2), and returns the value of "d2" from entry 8B. Also, in response to the read request, the buffer manager circuit 4 sets the return pointer register 12 to the address of entry 8A by copying the backward link field 26B to the return pointer register 12. From the description of FIGS. 1-3, the LIFO operation can be recognized in that the most recently written entry is returned from the buffer of the two written entries 8A and 8B. 【0025】 FIG. 4 is a block diagram of a state 400 of the LIFO system 2 of FIG. 3 after each entry in the circular buffer has been written by the buffer manager circuit 4 according to the list of write and read requests 402. Following the same operations described for the buffer manager circuit 4 for the write and read requests of FIGS. 2-3, FIG. 4 shows the state of each of the entries 8A-8H and the buffer manager circuit 4 after processing the last write request in the list of write and read requests 402. Note that all data fields of entries 8A-8H have been filled with data associated with the write requests in the list of write and read requests 402. There were two read requests: read request 302, which corresponds to returning entry 8B (see FIG. 3), and read request 404, which corresponds to returning entry 8F. Note that due to those read requests and the subsequent write request, entries 8B and 8F are not referenced in any of the backward link fields of entries 8A-8H. As can be seen in FIG. 4, the path of backward-linked entries starting with the entry pointed to by the return pointer register 12 or entry 8H tracks the list of entries most recently written to the circular buffer 6 that have not been returned. 【0026】 When processing the last write request and before the entry is written, buffer manager circuit 4 checks whether current call pointer register 18 is equal to current tail pointer register 16. In this case, because current call pointer register 18 is equal to current tail pointer register 16, buffer manager circuit 4 advances head pointer register 14 and tail pointer register 16 by one entry to point to entries 8B and 8A, respectively. Buffer manager circuit 4 also increments global wrap group register 10 because the next entry to be written is entry 8A and this is the second time entry 8A is being written. Logically, buffer manager circuit 4 increments current global wrap group register 10 when it is equal to the local wrap group field of the entry pointed to by updated tail pointer register 16. In other words, global wrap group register 10 is incremented each time the first entry 8A is overwritten. To process the write request, buffer manager circuit 4 also advances call pointer register 18 and return pointer register 12 as described in FIG. 2. 【0027】 FIG. 5 is a block diagram of a state 500 of the LIFO system of FIG. 4 after the first entry in the circular buffer has been overwritten. Because the state of LIFO system 2 is shown in FIG. 4, FIG. 5 shows the state after read request 502 and write request 504 have been processed by buffer manager circuit 4. Similar to the description of FIG. 3, in response to read request 502, buffer manager circuit 4 read entry 8H and assigned return pointer register 12 to entry 8G (not shown in FIG. 5). In response to write request 504, buffer manager circuit 4 updated entry 8A, assigning data field 24A to "d9" and copying local wrap group field 28A from global wrap group register 10. Buffer manager circuit 4 also copied backward link field 26A from return pointer register 12, which was entry 8G (prior to processing write request 504), so that the entry's backward path excludes entry 8H, which was read from the previous read request 502. Buffer manager circuit 4 advanced both the read pointer register and the call pointer register by one entry to point to entries 8A and 8B, respectively. When writing this overwritten entry, the global wrap group register is not incremented because the local wrap group field of the newly allocated tail pointer register, entry 8B, is not equal to the global wrap group register. 【0028】 FIG. 6 is a block diagram of an exemplary processor-based system including an instruction processing system 600, a central processing unit (CPU) system 602, and a RAS system 604. As described in more detail below, the RAS system 604 is configured to use wrap tracking to address data overflow and instruction mispredictions. For example, the RAS system 604 may use at least a LIFO system including a fixed number of entries 605(1)..605(n), similar to the LIFO system 2 of FIGS. 1-5. FIGS. 7-10 illustrate an exemplary operation of a LIFO system used as the RAS system 604 in the processor-based system of FIG. 6. Before describing the RAS system 604 of FIG. 6, other elements of the CPU system 602 of FIG. 6 are first described below. 【0029】 The CPU system 602 may be provided in a system-on-chip (SoC) 606, as an example. In this regard, instructions 608 are fetched from an instruction memory 616 by an instruction fetch circuit 610 provided in a front-end instruction stage 614F of the instruction processing system 600. The instruction memory 616 may be provided in or part of a system memory within the CPU system 602, as an example. An instruction cache 618 may also be provided in the CPU system 602 to cache the instructions 608 from the instruction memory 616 to reduce latency in the instruction fetch circuit 610 fetching the instructions 608. The instruction fetch circuit 610 passes the instructions 608 as fetched instructions 608F down one or more instruction pipelines I0-I1 within the instruction processing system 600 to be preprocessed before reaching an execution circuit 620 within a back-end instruction stage 614B within the instruction processing system 600 where the fetched instructions 608F are executed. N The instruction pipelines I0 to I N are provided across different processing circuits or stages of the instruction processing system 600 to be preprocessed and process the fetched instructions 608F in a series of steps that are executed simultaneously to increase throughput prior to execution of the fetched instructions 608F in the execution circuitry 620. 【0030】 6, a prediction circuit 622 (e.g., a branch prediction circuit) is also provided in the front-end instruction stage 614F to speculate or predict target addresses for control flow fetched instructions 608F, such as conditional branch instructions. The prediction of the target address by the prediction circuit 622 is used by the instruction fetch circuit 610 to determine the next fetched instruction 608F to be fetched based on the predicted target address. The front-end instruction stage 614F of the instruction processing system 600 in this example also includes an instruction decode circuit 624. The instruction decode circuit 624 is configured to decode the fetched instructions 608F fetched by the instruction fetch circuit 610 into decoded instructions 608D to determine the type of instruction 608 and the action required, which determines which instruction pipeline IO-I the fetched instruction 608F will be sent to. N 7-9, including its operation in response to these signals from instruction decode circuit 624. In addition, instruction decode circuit 624 signals RAS system 604 about various types of instructions, including call instructions, return instructions, and conditional branch instructions. Instruction decode circuit 624 sends a write signal 625 for call instructions, a read signal 627 for return instructions, and a notify signal for conditional branch instructions to RAS system 604. The operation of RAS system 604 in response to these signals is further described with respect to the description of FIGS. 7-9, including its operation in response to these signals from instruction decode circuit 624. 【0031】 Continuing to refer to FIG. 6, in this example, the decoded instruction 608D is then passed through the instruction pipeline I0-I1. N6. The fetched instructions 608F are placed in one or more of the registers 614A, 614B, and 614C, and then provided to a register access circuit 626 in the back-end instruction stage 614B of the instruction processing system 600. The register access circuit 626 is configured to determine whether any register names in the decoded instruction 608D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing of the instruction 608. The instruction processing system 600 of Figure 6 is capable of processing the fetched instructions 608F out-of-order, if possible, to achieve better throughput performance and parallelism. However, the number of logical (i.e., architectural) registers provided in the CPU system 602 may be limited. 【0032】 In this regard, register access circuitry 626 is provided in the back-end instruction stage 614B of instruction processing system 600. Register access circuitry 626 is configured to invoke a register map table (RMT) to rename logical source register operands and / or write destination register operands of instruction 608 to available physical registers in a physical register file (PRF). 【0033】 To extract a larger number of instructions 608 that can be executed independently and out of order for improved performance, it may be desirable to enable the CPU system 602 of FIG. 6 to have visibility into a larger number of future instructions 608 (i.e., an instruction window). 【0034】 In this regard, the instruction processing system 600 includes a register access (RACC) circuit 646. The RACC circuit 646 controls the instruction pipeline I0-I1 prior to the dispatch circuit 648. NThe RACC circuit 646 is configured to provide a value generated from the executed instruction 608E as a source register operand of the instruction 608 to be executed. Also, in the instruction processing system 600 of FIG. 6, the dispatch circuit 648 is provided in the instruction pipelines I0 to I1 after the RACC circuit 646 in the back-end instruction stage 614B. N The decoded instruction 608D is provided in the back-end instruction stage 614B. The dispatch circuit 648 is configured to dispatch the decoded instruction 608D to the execution circuit 620 to be executed when all source register operands for the decoded instruction 608D are available. The execution circuit 620 and the writeback circuit 650 are provided in the back-end instruction stage 614B. The execution circuit 620 signals to the RAS system 604 when call, return, and conditional branch instructions are committed to memory. Additionally, the execution circuit 620 will send a mispredict signal 652 to the RAS system 604 when it determines that a predictively prefetched instruction is mispredicted. This situation will arise, for example, when the prediction circuit 622 selects one of multiple paths for the instruction from a conditional branch instruction prior to resolution of the branch condition, and subsequent resolution of the branch condition determines an alternate path for the instruction. The RAS system 604 is further described with respect to the description of FIGS. 7-9, including its operation in response to these signals from the execution circuit 620. 【0035】 FIG. 7 is a block diagram of a state 700 of the RAS system 604 of FIG. 6 after the first entry in the RAS 754 has been overwritten. The RAS 754 includes eight entries 756A-756H. The RAS system 604 also includes a buffer manager circuit 758. The buffer manager circuit 758 includes a global wrap group register 760 that stores a value representing the number of iterations that the entries 756A-756H of the RAS 754 have been written to. The buffer manager circuit 758 also includes a return pointer register 762 that stores the address of one of the entries 756A-756H to indicate the particular entry to return upon a read request, which in this embodiment is a read signal 627 from the instruction decode circuit 624 resulting from decoding a return instruction. For illustrative purposes, the size of the RAS 754 is fixed at eight entries, but it should be noted that the concepts described herein can be easily extended to various sizes. Also, note that although the registers and circuits are implemented in hardware, they could also be implemented in software logic and software variables. 【0036】 Buffer manager circuit 758 may also include a head pointer register 764 that stores the address of one of entries 756A-756H to indicate the beginning of the list in RAS 754, and a tail pointer register 766 that stores the address of one of entries 756A-756H to indicate the end of the list in RAS 754. Buffer manager circuit 758 may also include a call pointer register 768 that stores the address of one of entries 756A-756H to indicate the entry in RAS 754 to write to in response to the next write request, which in this embodiment is write signal 625 from instruction decode circuit 624 resulting from decoding a subroutine call instruction. 【0037】 Entries 756A-756H include next fields 770A-770H, data fields 772A-772H, backward link fields 774A-774H, and local wrap group fields 776A-776H. Next field 770 contains the address of the next forward entry in RAS 754 (shown as "Next #1" in FIG. 7). As shown in FIG. 7, next field 770A of entry 756A contains the address of entry 756B, next field 770B of entry 756B contains the address of entry 756C, and so on up to entry 756H, linking the entries in a circular clockwise direction. Thus, next fields 770A-770H statically link entries 756A-756H in the forward direction. 【0038】 Data fields 772A-772H contain the return address to be returned when the respective entry is read. Backward link fields 774A-774H store the address of the next entry to be returned after the current entry is read. On a write request, the backward link field 774 of the written entry will contain the address of the next entry to be returned after the written entry is returned. As will be explained later, backward link fields 774A-774H will form a list of entries to be read on a series of read requests. Local wrap group fields 776A-776H contain the value of the global wrap group register 760 at the time the respective entry 756 was written, which reflects the number of iterations RAS 754 was written to. 【0039】 The buffer manager circuit 758 also includes a branch instruction buffer 778. The branch instruction buffer 778 maintains a snapshot of the state of the RAS system 604 in response to processing a read, write, or notify signal from the instruction decode circuit 624. As will be further explained with respect to the disclosure of FIGS. 8-9 , the buffer manager circuit 758 will utilize the information stored in the branch instruction buffer 778 to advantageously manage the RAS system 604 when receiving a commit signal, also known as a retire signal, from the execution circuit 620 and to advantageously restore the state of the RAS system 604 in response to a misprediction signal 652. Specifically, the buffer manager circuit 758 writes a new line to the branch instruction buffer for each of these signals. The buffer manager circuit 758 writes the state of the call pointer register 768, the return pointer register 762, and the global wrap group register 760 immediately before processing a particular signal. The buffer manager circuit 758 also writes whether the received signal mapped to a call instruction, a return instruction, or a conditional branch instruction. For example, buffer manager circuit 758 wrote data to row 780 in response to receiving write signal 625 from instruction decode circuit 624 after decoding instruction CALL1. Additionally, buffer manager circuit 758 wrote data to row 782 in response to receiving read signal 627 from instruction decode circuit 624 after decoding instruction RET2. Furthermore, buffer manager circuit 758 wrote data to row 784 in response to receiving a notification signal for a conditional branch instruction (e.g., branch on equality (BEQ) for two registers). 【0040】 State 700 of RAS system 604 is the result of buffer manager circuit 758 processing signals resulting from sequence of instructions 781. Sequence of instructions 781 is similar to list of write and read requests 402 of FIG. 5. As a result, the states of entries 756A-756H are similar to the states of entries 8A-8H, except for the data fields. As noted above, data fields 772A-772H contain the return addresses of the associated calling subroutines. Also, because sequence of instructions 781 and list of write and read requests 402 both overwrote the first entries in RAS 754 and circular buffer 6, respectively, the states of the global wrap group register, return pointer register, call pointer register, head pointer register, and tail pointer register are the same between FIG. 5 and FIG. 7. 【0041】 See row 780. Row 780 was written when a write request for CALL1 was received. The data for that write request was written to entry 756A (the data shown in FIG. 7 for entry 756A is the data after processing the write signal 625 associated with CALL9). When a read signal 627 for RET2 was received, buffer manager circuit 758 returned the address stored in data field 772A. However, when a write signal 625 for CALL9 was received, buffer manager circuit 758 overwrote entry 756A, including data field 772A, with the return address for CALL9 ("C9RA"), overwrote backward link field 774A to point to entry 756G, and overwrote local wrap group field 776A with the value of global wrap group register 760. 【0042】 8 is a block diagram of a state 800 of the RAS system 604 of FIG. 6 when a commit signal for a return instruction 802 is processed by the buffer manager circuit 758. As will be explained next, the state 700 prior to receiving the commit signal for RET2 is equivalent to the state 800 after the buffer manager circuit 758 has processed the commit signal. In other words, updates to registers 760, 762, or 768 are avoided with respect to the commit signal. 【0043】 The execution circuit 620 sends a commit signal to the RAS system 604 when an instruction completes processing in the instruction processing system 600. Commit signals for instructions are received in the same order as the instruction sequence. The buffer manager circuit 758 may maintain a register whose value allows the buffer manager circuit 758 to index into a row of the branch instruction buffer 778. Thus, the buffer manager circuit 758 directly accesses the row of the branch instruction buffer 778 associated with the instruction for which the commit signal was received. In FIG. 8 , the buffer manager circuit 758 directly indexes into row 782, which was written when RET2 was received. The buffer manager circuit 758 uses value 804 as an index into the RAS 754 to locate entry 756B. By comparing the wrap group field 806 in the branch instruction buffer 778 with the local wrap group field 776B, the buffer manager circuit 758 determines that entry 756B has not been overwritten because these fields are equal and therefore entry 756B is eligible to be retired. If the local wrap group field 776B was not equal to the wrap group field 806, the buffer manager circuit 758 would have determined that the entry had been overwritten and was not eligible to be retired. In either case, because the RAS system 604 allows overwriting, the RAS system 604 advantageously does not need to perform any reset of fields in the entry in response to a commit signal, nor does it need to change the state of registers (762, 764, 766, and 768), unlike conventional approaches for RAS systems. 【0044】 9 is a block diagram illustrating the state 900 of the RAS system when it is determined that conditional branch instruction BEQ 902 is mispredicted. Because instruction processing system 600 is a predictive fetch system, the transmission of read and write signals 627 and 625, respectively, to RAS system 604 occurs prior to determining whether the associated instruction was correctly predicted. The resolution of whether an instruction was correctly predicted occurs in execution circuitry 620. If execution circuitry 620 determines whether an instruction was mispredicted, it must flush back-end instruction stage 614B of all instructions resulting from the mispredicted instruction and send a mispredict signal to RAS system 604 so that RAS system 604 can reset itself. 9, in response to the misprediction signal 652, the buffer manager circuit 758 directly accesses row 904 in the branch instruction buffer 778 and resets the call pointer register 768 to entry 756G referenced by the CALL field of row 904 and resets the return pointer register 762 to entry 756E referenced by the RET field of row 904. The buffer manager circuit 758 may reset the subsequent row of the branch instruction buffer 778 or simply reset the register whose value enables the buffer manager circuit 758 to index to the next available row of the branch instruction buffer 778. This advantageous approach to managing the RAS system 604 conserves energy. 【0045】 FIG. 10 is a flowchart 1000 for operations 1002A-D of a buffer manager circuit (4 and 758) that utilizes wrap tracking to enable data overwrite and maintain the order of recent entries, in accordance with the present disclosure. As described above with respect to FIGS. 1-5, buffer manager circuit 4 manages the state of the LIFO system to allow entries to be overwritten while keeping the most recent entries in order. As described above with respect to FIGS. 6-9, buffer manager circuit 758 includes all the functionality of buffer manager circuit 4, but also includes functionality for managing the state of a LIFO system used as a RAS system with a predictive instruction fetch processing system. Thus, operations 1002A-B are performed by both buffer manager circuits 4 and 758. Operations 1002C-D are performed by buffer manager circuit 758 only. 【0046】 Writing an entry to a LIFO structure, e.g., circular buffer 6 or 754, begins at block 1004. In block 1004, the method dynamically links the written entry in the LIFO structure to the previous valid entry to be returned after the written entry by setting the backward link entry field in the written entry. In block 1006, the write operation sets the local wrap group field of the written entry to the global wrap group number. In optional block 1008, the write operation checkpoints the state of the LIFO structure if the LIFO structure is deployed in the RAS system. In doing so, the checkpoint information will include the cause of the write, the entry pointed to by the call pointer, and the entry pointed to by the read pointer. Optional block 1008 is executed by buffer manager circuit 758 as the LIFO structure is deployed in RAS system 604. In block 1010, the write operation determines whether to update the global wrap group if the next entry to be written starts a new iteration of writing entries in the LIFO structure. In block 1012, the write operation increments the call pointer and the read pointer of the LIFO structure. 【0047】 Reading an entry from a LIFO structure, for example, circular buffer 6 or 754, begins at block 1014. At block 1014, the read operation returns data from the entry in the LIFO structure pointed to by the read pointer. At block 1016, the read operation sets the return pointer to the previous backward link entry field of the entry that was read. 【0048】 Committing instructions in a predictive instruction processing system begins at block 1018. At block 1018, the commit operation recognizes an overflow when the entry associated with the commit signal includes a local wrap group number that is different from the global wrap group. 【0049】 Mispredicting an instruction in a predicted instruction processing system begins at block 1020. The mispredict operation retrieves a checkpointed entry associated with the mispredicted instruction. At block 1022, the mispredict operation restores a call pointer and a read pointer to the retrieved checkpointed entry. 【0050】 A circular buffer using lap tracking to address data overflow according to aspects disclosed herein may be provided in or incorporated into any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 【0051】 In this regard, FIG. 11 is an example of a processor-based system 1100 that may include a LIFO system 1102, such as the LIFO systems shown in FIGS. 1 and 6, including a buffer manager circuit 1108 configured to utilize at least wrap tracking to address data overflow while maintaining recently written entries, according to aspects disclosed herein. For example, the LIFO system 1102 may include the previously described buffer manager circuit 4, 758 of FIGS. 1 and 7. In this example, the processor-based system 1100 includes a processor 1104 including one or more CPUs 1106 and a cache memory 1107. Each CPU 1106 includes the LIFO system 1102, which may be, for example, the RAS system 604 of FIGS. 6 and 7. The RAS system 604 includes a buffer manager circuit 758 and a branch instruction buffer 778 for addressing resetting the state of the RAS system 604 for the misprediction signal 652, according to aspects disclosed herein. 【0052】 11 , the CPU 1106 can issue memory access requests via a system bus 1110. The memory access requests issued by the CPU 1106 via the system bus 1110 can be routed to a memory controller 1112 in a memory system 1114 that includes one or more memory arrays 1116. Although not shown in FIG. 11 , multiple system buses 1110 can be provided, with each system bus 1110 constituting a different fabric. For example, the CPU 1106 can communicate bus transaction requests to the memory system 1114 as an example of a slave device. 【0053】 Other master and slave devices may be connected to the system bus 1110. As shown in FIG. 11, these devices may include a memory system 1114, one or more input devices 1118, one or more output devices 1120, one or more network interface devices 1122, and one or more display controllers 1124. The input devices 1118 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 1120 may include any type of output device, including, but not limited to, audio indicators, video indicators, and other visual indicators. The network interface device 1122 may be any device configured to enable the exchange of data with a network 1126, including a modem. The network 1126 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device 1122 may be configured to support any type of desired communication protocol. 【0054】 The CPU 1106 may also be configured to access a display controller 1124 via the system bus 1110 to control information sent to one or more displays 1128. The display controller 1124 sends information to be displayed to the display 1128 via one or more video processors 1130, which process the information to be displayed into a format suitable for the display 1128. The display 1128 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. 【0055】 Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium, and that any such instructions are executed by a processor or other processing device, or a combination of both. The CPU 602 described herein may, by way of example, be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. 【0056】 The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). 【0057】 Aspects disclosed herein may be embodied in hardware or in instructions stored in hardware and may reside in, for example, a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server. 【0058】 It should also be noted that the operational steps described in any of the exemplary aspects herein are set forth to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps described in an exemplary aspect may be combined. It should be understood that the operational steps shown in the flowchart diagrams may be subject to many different variations, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 【0059】 The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 【0060】 Example implementations are described in the following numbered aspects / clauses. 1. A circular buffer, the circular buffer comprising: a circular buffer including a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, wherein an entry among the fixed number of entries includes a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to, and a second field configured to store a link to a next entry to return on a read request after the entry has been read from the circular buffer, wherein one of the fixed number of entries is a first entry and one of the fixed number of entries is a most recently added entry; a return pointer register configured to track the most recently added entry among a fixed number of entries; a global wrap group register configured to store a value representing the number of iterations the circular buffer has been written to; In response to a write request, determining a next available entry from the fixed number of entries; updating the local wrap group field of the next available entry to the value of the global wrap group register; updating the second field of the next available entry to the value in the return pointer register; a buffer manager circuit configured to: An apparatus comprising: 2. The apparatus of clause 1, wherein the buffer manager circuitry is further configured to update a return pointer register to the value of the second field of the entry in response to a read request. 3. The apparatus of clause 1, wherein the buffer manager circuitry is further configured to increment a global wrap group register in response to overwriting the first entry. 4. The apparatus of clause 2 or 3, further including a branch instruction buffer, wherein the buffer manager circuit is further configured to store the state of the return pointer register and the global wrap group register in the branch instruction buffer in response to a read or write request. 5. The apparatus of clause 4, wherein the buffer manager circuit is further configured to restore a return pointer register and a global wrap group register from the branch instruction buffer in response to the misprediction signal. 6. The apparatus of clause 4 or 5, wherein the buffer manager circuit is further configured to recognize whether an entry has been previously overwritten by being configured to compare a local wrap group field of the entry with a global wrap group register in response to a commit signal associated with the entry. 7. Establishing a circular buffer, the circular buffer comprising: comprising a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, each of the fixed number of entries comprising a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to, and a second field configured to store a link to a next entry to return on a read request after the entry has been read from the circular buffer, wherein one of the fixed number of entries is a first entry and one of the fixed number of entries is a most recently added entry; establishing a return pointer register configured to track a most recently added entry among a fixed number of entries; establishing a global wrap group register configured to store a value representing the number of iterations the circular buffer has been written to; In response to a write request, determining a next available entry from the fixed number of entries; updating the local wrap group field of the next available entry to the value of the global wrap group register; updating a second field of the next available entry to the value of the return pointer register; A method comprising: 8. updating a return pointer register to the value of the second field of the entry in response to the read request. The method of clause 7 further includes: 9. Incrementing a global wrap group register in response to overwriting the first entry. The method of clause 7 or 8, further including: 10. Storing the state of the return pointer register and the global wrap group register in response to a read or write request. The method of clause 9 further includes: 11. Restoring a return pointer register and a global wrap group register in response to a misprediction signal. The method of clause 10 further includes: 12. Recognizing whether an entry has been previously overwritten by comparing a local wrap group field of the entry with a global wrap group register in response to a commit signal associated with the entry. The method of clause 10 further includes: 13. A non-transitory computer-readable medium having stored thereon computer-executable instructions, the computer-executable instructions, when executed by a processor, causing the processor to: Establishing a circular buffer, the circular buffer comprising: establishing a circular buffer including a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, each entry among the fixed number of entries including a local wrap group field configured to identify which iteration of writing the circular buffer the entry was last written to, and a second field configured to store a link to a next entry to return on a read request after the entry has been read from the circular buffer, wherein one of the fixed number of entries is a first entry and one of the fixed number of entries is a most recently added entry; establishing a return pointer register configured to track a most recently added entry among a fixed number of entries; establishing a global wrap group register configured to store a value representing the number of iterations the circular buffer has been written to; In response to a write request, determining a next available entry from the fixed number of entries; updating the local wrap group field of the next available entry to the value of the global wrap group register; updating the second field of the next available entry to the value in the return pointer register; A non-transitory computer-readable medium for causing 14. The non-transitory computer-readable medium of clause 13, wherein the computer-executable instructions, when executed by a processor, further cause the processor to, in response to a read request, update a return pointer register to the value of the second field of the entry. 15. The non-transitory computer-readable medium of clause 13 or 14, wherein the computer-executable instructions, when executed by a processor, further cause the processor to increment a global wrap group register in response to overwriting the first entry. 16. The non-transitory computer-readable medium of clauses 13 to 15, wherein the computer-executable instructions, when executed by a processor, further cause the processor to store the state of a return pointer register and a global wrap group register in response to a read or write request. 17. The non-transitory computer-readable medium of clause 16, wherein the computer-executable instructions, when executed by a processor, further cause the processor to restore a return pointer register and a global wrap group register in response to a misprediction signal. 18. The non-transitory computer-readable medium of clause 16 or 17, wherein the computer-executable instructions, when executed by a processor, further cause the processor to recognize whether the entry has been previously overwritten by comparing a local wrap group field of the entry with a global wrap group register in response to a commit signal associated with the entry. [Explanation of symbols] 【0061】 2. LIFO system 3 Initialization state 4 Buffer Manager Circuit 6 Circular buffer circuit, circular buffer 8A~8H Entry 10 Global Wrap Group Register 12 Return Pointer Register 14 Head Pointer Register 16 Tail Pointer Register 18 Call Pointer Register 22, 22A~22H Next Field 24A~24H Data Field 26A~26H Backward Link Field 28A~28H Local Lap Group Field 200 Status 202 First Write Request 204 Second write request 300 Status 302 Read Request 400 Status 402 List of write and read requests 404 Read Request 500 Status 502 Read Request 504 Write Request 600 Command Processing System 602 Central Processing Unit (CPU) System, CPU System 604 RAS System 605(1)..605(n) entries 606 System on Chip (SoC) 608 command 608D Decoded Instructions 608F Instruction fetched 610 Instruction fetch circuit 614B Back-end instruction stage 614F Front-end instruction stage 616 instruction memory 618 instruction cache 620 Execution Circuit 622 Prediction Circuit 624 Instruction Decoding Circuit 625 Write Signal 626 Register Access Circuit 627 Read Signal 646 Register Access (RACC) Circuit, RACC Circuit 648 Dispatch Circuit 650 Write-back circuit 652 Misprediction Signal 700 Status 754 RAS 756, 756A~756H entries 758 Buffer Manager Circuit 760 Global Wrap Group Register, Register 762 Return Pointer Register, Register 764 Head Pointer Register, Register 766 Tail Pointer Register, Register 768 Call Pointer Register, Register 770A~770H Next Field 772A~772H Data field 774A~774H Backward link field 776A~776H Local Lap Group Field 778 Branch Instruction Buffer 781 Sequence of Instructions 782 lines 800 Status 802 Return Command 804 value 806 Rap Group Field 900 Status 902 Conditional branch instruction BEQ Line 904 1000 Flowchart 1002A~1002D operation 1100 processor-based systems 1102 LIFO system 1104 processor 1106 CPU 1108 Buffer Manager Circuit 1110 System Bus 1112 Memory Controller 1114 Memory System 1116 Memory Array 1118 Input Devices 1120 output device 1122 Network Interface Device 1124 Display Controller 1126 Network 1128 Display 1130 Video Processor I0~I N instruction pipeline

Claims

[Claim 1] A device for performing wrap tracking to address data overflow in a circular buffer, It includes a buffer manager circuit, and the buffer manager circuit is Receiving a write request and, In response to the aforementioned write request, Determining the next available entry from a fixed number of entries in a circular buffer, wherein the circular buffer is The system includes a fixed number of entries statically linked in a first direction in which data is written to the circular buffer, and each entry includes a local wrap group field configured to identify which iteration of writing to the circular buffer the entry was last written to, and a second field configured to store a link to the next entry to be returned when a read request is made after the entry has been read from the circular buffer, and it is determined that one of the fixed number of entries is the first entry, and one of the fixed number of entries is the most recently added entry. Updating the local wrap group field of the next available entry to the value of the global wrap group register, wherein the global wrap group register is configured to store a value representing the number of iterations to which the circular buffer has been written. Updating the second field of the next available entry in the return pointer register, wherein the return pointer register is configured to store a value representing the number of iterations to which the circular buffer has been written. A device configured to perform the following actions. [Claim 2] The apparatus according to claim 1, wherein the buffer manager circuit is further configured to update the return pointer register with the value of the second field of the entry in response to a read request. [Claim 3] The apparatus according to claim 1, wherein the buffer manager circuit is further configured to increment the global wrap group register in response to overwriting the first entry. [Claim 4] The apparatus according to claim 3, wherein the buffer manager circuit is further configured to store the states of the return pointer register and the global wrap group register in a branch instruction buffer in response to a read request or a write request. [Claim 5] The apparatus according to claim 4, wherein the buffer manager circuit is further configured to restore the return pointer register and the global wrap group register from the branch instruction buffer in response to a misprediction signal. [Claim 6] The apparatus according to claim 4, wherein the buffer manager circuit is further configured to recognize whether an entry has been previously overwritten by comparing the local wrap group field of the entry with the global wrap group register in response to a commit signal associated with the entry. [Claim 7] A method for performing wrap tracking to address data overflow in a circular buffer, The steps include receiving a write request and In response to the aforementioned write request, A step of determining the next available entry from a fixed number of entries in a circular buffer, wherein the circular buffer is A step of determining that a fixed number of entries are statically linked in a first direction in which data is written to the circular buffer, and each entry of the fixed number of entries includes a local wrap group field configured to identify which iteration of writing to the circular buffer the entry was last written to, and a second field configured to store a link to the next entry to be returned when a read request is made after the entry has been read from the circular buffer, and one of the fixed number of entries is the first entry, and one of the fixed number of entries is the most recently added entry, A step of updating the local wrap group field of the next available entry to the value of a global wrap group register, wherein the global wrap group register is configured to identify which iteration of the circular buffer was last written to, and the global wrap group register is configured to store a value representing the number of iterations to which the circular buffer was written. A step of updating the second field of the next available entry in a return pointer register, wherein the return pointer register is configured to track the most recently added entry among the fixed number of entries. Methods that include... [Claim 8] Steps to update the return pointer register with the value of the second field of the entry in response to a read request. The method according to claim 7, further comprising: [Claim 9] Steps to increment the global wrap group register in response to overwriting the first entry: The method according to claim 7, further comprising: [Claim 10] Steps to store the state of the return pointer register and the global wrap group register in response to a read or write request. The method according to claim 9, further comprising: [Claim 11] Steps to restore the return pointer register and the global wrap group register in response to the erroneous prediction signal. The method according to claim 10, further comprising: [Claim 12] In response to a commit signal associated with the entry, the step of determining whether the entry has been previously overwritten is to compare the local wrap group field of the entry with the global wrap group register. The method according to claim 10, further comprising: [Claim 13] A computer program that includes instructions for carrying out the method described in any one of claims 7 to 12 when executed by the apparatus described in claim 1.

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