Method, apparatus, and article of manufacture for improving the performance of networks operating in multiple frequency bands

Abstract

The example apparatus (200) includes interface circuitry (212), a memory (218) configured to store machine-readable instructions (220), and a processing circuitry (202) configured to at least one of instantiate or execute the machine-readable instructions. The example processing circuitry is configured to at least one of instantiate or execute the machine-readable instructions to determine connectivity criteria for a first device that is synchronized with a second device and to transmit the connectivity criteria via the interface circuitry (212) to a third device with which the first device is not synchronized. The example processing circuitry is also configured to at least one of instantiate or execute the machine-readable instructions to transmit a second communication to the first device to synchronize the first device with the third device based on a first communication from the third device.

Description

[Technical Field]

[0001] This description relates generally to wireless communications, and more particularly to methods, apparatus, and articles of manufacture for improving performance of networks operating in multiple frequency bands. [Background technology]

[0002] The Institute of Electrical and Electronics Engineers (IEEE) 802.15.4 is a technical standard that defines the operation of low-rate wireless personal area networks (LR-WPANs). IEEE 802.15.4 is the basis for the Zigbee, Thread, and Wi-SUN specifications, each of which further extends the standard by developing upper layers not specified in IEEE 802.15.4. Most deployments of IEEE 802.15.4-based technologies use an asynchronous, non-beaconing mode of personal area network (PAN) operation in the global 2.4 gigahertz (GHz) industrial, scientific, and medical (ISM) radio frequency (RF) band. Zigbee and Thread are examples of common mesh network technologies based on this mode of operation. PAN operation is also implemented in Internet of Things (IoT) networks. Summary of the Invention

[0003] For methods, apparatus, and articles of manufacture for improving performance of a network operating in multiple frequency bands, an example apparatus includes interface circuitry, a memory configured to store machine-readable instructions, and a processing circuitry configured to at least one of instantiate or execute the machine-readable instructions. The example processing circuitry is configured to at least one of instantiate or execute the machine-readable instructions to determine a connectivity metric for a first device synchronized with a second device and to cause the connectivity metric to be transmitted, via the interface circuitry, to a third device with which the first device is not synchronized. The example processing circuitry is also configured to at least one of instantiate or execute the machine-readable instructions to cause the first device to transmit a second communication to synchronize the first device with the third device based on a first communication from the third device. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example network including devices capable of communicating in multiple frequency bands.

[0005] [Figure 2] 2 is a block diagram of an example implementation of a parent device in the network of FIG. 1.

[0006] [Figure 3] 2 is a block diagram of an example implementation of a child device in the network of FIG. 1.

[0007] [Figure 4] 2 is a timing diagram illustrating example channel hopping in the network of FIG. 1 for example parent devices with different dwell times.

[0008] [Figure 5]2 is a timing diagram illustrating example channel hopping in the network of FIG. 1 for an example child device in a sleep mode of operation and an example parent device.

[0009] [Figure 6] 3 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the parent device of FIG. 2 to perform channel hopping across multiple frequency bands.

[0010] [Figure 7] 3 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the parent device of FIG. 2 to perform channel hopping in the base frequency band.

[0011] [Figure 8] 4 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the child device of FIG. 3 to synchronize with an example parent device.

[0012] [Figure 9] 4 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the child device of FIG. 3 to perform coordinated sampled listening using channel hopping.

[0013] [Figure 10] 3 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the parent device of FIG. 2 to utilize alternative frequency bands to assist parental selection for a child device.

[0014] [Figure 11] 3 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the parent device of FIG. 2 to use alternative frequency bands to assist parental selection for a child device.

[0015] [Figure 12] 4 is a flowchart representing example machine-readable instructions and / or example operations that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the child device of FIG. 3 to select a parent device.

[0016] [Figure 13] FIG. 12 is a block diagram of an example processing circuitry platform including processing circuitry configured to execute, instantiate, and / or perform the example machine-readable instructions and / or example operations of FIGS. 6, 7, 10, and / or 11 to implement the parent device of FIG. 2.

[0017] [Figure 14] 13 is a block diagram of an example processing circuitry platform including processing circuitry configured to execute, instantiate, and / or perform the example machine-readable instructions and / or example operations of FIGS. 8, 9, and / or 12 to implement the child device of FIG. 3.

[0018] [Figure 15] 15 is a block diagram of an example implementation of the processing circuitry of FIG. 13 and / or the processing circuitry of FIG. 14.

[0019] [Figure 16] 15 is a block diagram of another example implementation of the processing circuitry of FIG. 13 and / or the processing circuitry of FIG. 14.

[0020] [Figure 17]1 is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, and / or firmware (e.g., corresponding to the example machine-readable instructions of FIGS. 6, 7, 8, 9, 10, 11, and / or 12) to client devices associated with end users and / or consumers (e.g., for license, sale, and / or use), retailers (e.g., for sale, resale, license, and / or sublicense), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in distributed products to retailers and / or other end users, such as direct sales customers).

[0021] The same reference numerals or other reference designators are used to refer to the same or similar (functionally and / or structurally) features. DETAILED DESCRIPTION OF THE INVENTION

[0022] The drawings are not necessarily drawn to scale. Generally, like reference numbers and their descriptions in the drawings refer to the same or similar parts. Although the drawings show regions with complete lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or irregular.

[0023] In addition to the widely used 2.4 GHz spectrum, it may be desirable to operate in the sub-1 GHz RF spectrum (e.g., radio frequencies below 1 GHz). For example, operating in the sub-1 GHz spectrum and the 2.4 GHz spectrum may enable longer links (e.g., long-distance propagation) within the network, more robust links over media such as concrete, and avoid the congested 2.4 GHz band. It may also be desirable to maintain existing operation in the 2.4 GHz RF spectrum. For example, operating in the 2.4 GHz band may maintain a global ISM operating mode and increase the ubiquity of 2.4 GHz solutions. Additional exemplary details of operating in the sub-1 GHz and 2.4 GHz spectrum may be found in commonly assigned U.S. Patent Application No. 2023 / 0052555, entitled "Device and Method for Asynchronous and Synchronous Wireless Communication Utilizing a Single Radio," filed August 10, 2022, which is incorporated herein by reference in its entirety. [Patent Document 1] U.S. Patent Application No. 2023 / 0052555

[0024] However, operating a single network across two RF bands using a single radio poses challenges in most IEEE 802.15.4 implementations. One challenge posed by sub-1 GHz operation is the duty cycle obligations (e.g., channel hopping) specified by certain regional RF regulatory agencies (e.g., the Federal Communications Commission (FCC)). For example, if a device is operating below a threshold bandwidth (e.g., less than 400 kHz bandwidth) and above a threshold power (e.g., greater than 30 dBm), the FCC requires channel hopping across at least 50 channels. An exemplary frequency band may be divided into one or more channels, where a channel refers to a frequency range within a frequency band. Existing channel hopping techniques are limited to a single frequency range. Existing channel hopping techniques also require all coordinators (e.g., routers, gateways, etc.) that are part of the network to support the same frequency band. Existing channel hopping techniques also impose a high computational burden on the coordinator to synchronize with neighboring devices. For example, existing channel hopping techniques require the coordinator to maintain synchronization information for all neighboring devices, which may exceed 50 devices in a real-world network.

[0025] Furthermore, existing channel hopping techniques complicate device operation by requiring all coordinators in the network to periodically transmit data on all channels to allow child devices in the network to select a parent device with which one or more child devices potentially have a stronger connection. Furthermore, existing channel hopping techniques do not support Coordinated Sampled Listening (CSL). CSL is a feature of IEEE 802.15.4 that enables low-power child devices to shift from a sleep mode to a wake mode of operation at specific periodic instances synchronized with a parent device. For example, a parent device can schedule data exchanges with child devices at specific periodic instances. However, existing channel hopping techniques do not support this feature of IEEE 802.15.4. Furthermore, existing channel hopping techniques do not support the discovery of other devices operating in different frequency bands. For example, a child device operating according to existing CSL techniques cannot discover other devices that may operate in a different frequency band from the child device.

[0026] The examples described herein enable channel hopping in the sub-1 GHz band (e.g., to enable range-extending links) while reducing (e.g., minimizing) changes to operation at 2.4 GHz (to enable reuse of existing software stacks for 2.4 GHz operation). For example, the methods, apparatus, and articles of manufacture described herein handle multiple frequency bands as part of a channel hopping sequence. The examples described herein also reduce the computational burden on synchronizing devices by synchronizing channel hopping in a subnetwork (e.g., without synchronizing a device with all neighboring devices). The examples described herein also enable frequency hopping using CSL. The examples described herein also utilize overlapping channel hopping sequences between parent devices to assist a child device in selecting a parent device that potentially has a stronger connection with the child device. The examples described herein also utilize alternative frequency bands supported by the parent device to enable selection of a parent device that potentially has a stronger connection with the child device.

[0027] 1 is a block diagram of an example network 100 including devices capable of communicating in multiple frequency bands. For example, network 100 includes devices operating in the sub-1 GHz frequency band and devices operating in the 2.4 GHz frequency band. In the example of FIG. 1, network 100 includes an example gateway 102 and a first example dual-band router 104. A and a second exemplary dual-band router 104 B an exemplary single-band router 106; and a first exemplary endpoint device 108. A and a second example endpoint device 108 B and a third example endpoint device 108 C and a fourth example endpoint device 108 D and a fifth example endpoint device 110 A and a sixth exemplary endpoint device 110 Band a seventh exemplary endpoint device 110 C and an eighth example endpoint device 110 D and,

[0028] In the illustrated example of Figure 1, network 100 includes one or more parent devices and one or more child devices. Exemplary parent devices are devices that direct data packets between devices and / or networks. For example, parent devices include gateways and routers. Exemplary child devices are devices that are synchronized with a parent device. For example, child devices include endpoint devices and internal routers (e.g., routers synchronized with gateways).

[0029] In the illustrated example of FIG. 1, the gateway 102 is connected to the Internet, a first dual-band router 104 A , the second dual-band router 104 B , and a single-band router 106. In the example of FIG. 1, the gateway 102 includes one or more protocol translators, one or more impedance matchers, one or more rate converters, one or more fault isolators, and / or one or more signal translators. In the example of FIG. 1, the gateway 102 operates in a single frequency band. For example, the gateway 102 operates in the 2.4 GHz frequency band. In the example of FIG. 1, the gateway 102 is connected to the Internet, a first dual-band router 104, A , the second dual-band router 104 B , and single-band router 106. For example, gateway 102 allows data packets to flow from network 100 to the Internet. Thus, in the example of FIG. 1, gateway 102 directs data packets between first dual-band router 104 and A , the second dual-band router 104 B , and acts as a parent device to the single-band router 106 .

[0030] In the illustrated example of FIG. 1, the first dual-band router 104 A The gateway 102, the single-band router 106, and the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A , and the sixth endpoint device 110 B In the example of FIG. 1, the first dual-band router 104 A includes software and / or hardware circuitry. For example, the first dual-band router 104 A The first dual-band router 104 may include routing software running on a central processing unit (CPU). A includes one or more application specific integrated circuits (ASICs). In the example of FIG. 1, the first dual-band router 104 A The first dual-band router 104 operates in multiple frequency bands. A can operate in the sub-1 GHz frequency band and the 2.4 GHz frequency band. In the example of FIG. 1, the first dual-band router 104 A The first dual-band router 104 A For example, the first dual-band router 104 uses the base frequency band as the frequency band in which it operates for the synchronous operation mode. A In an exemplary synchronous operation mode, the first dual-band router 104 A and the first dual-band router 104 A The child devices synchronize their channel hopping. Also, in the example of FIG. 1, the first dual-band router 104 A The first dual-band router 104 A For example, the first dual-band router 104 may use an alternative frequency band as the frequency band in which it operates for the asynchronous operation mode. A In the exemplary asynchronous operation mode, the first dual-band router 104 utilizes the 2.4 GHz frequency band as an alternative frequency band.A and the first dual-band router 104 A Child devices may not synchronize with the channel hopping.

[0031] In the illustrated example of FIG. 1, the first dual-band router 104 A gateway 102, single-band router 106, and first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A , and the sixth endpoint device 110 B For example, the first dual-band router 104 A The gateway 102, the single-band router 106, and the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A , and the sixth endpoint device 110 B The first dual-band router 104 utilizes information contained in a routing table and / or routing policy to direct data packets between certain endpoint devices. A the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A , and the sixth endpoint device 110 B to other devices in the network 100. In some examples, the first dual-band router 104 A The first dual-band router 104 A and a second dual-band router 104 B Utilizing the alternative frequency bands supported by the second dual-band router 104 B In the example of FIG. 1, the first dual-band router 104 A the first endpoint device 108A , the second endpoint device 108 B , the fifth endpoint device 110 A , and the sixth endpoint device 110 B Acts as a parent device for

[0032] In the illustrated example of FIG. 1, the second dual-band router 104 B The gateway 102, the single-band router 106, and the seventh endpoint device 110 C , and an eighth endpoint device 110 D In the example of FIG. 1, the second dual-band router 104 B includes software and / or hardware circuitry. For example, the second dual-band router 104 B Additionally or alternatively, the second dual-band router 104 includes routing software running on a CPU. B In the example of FIG. 1, the second dual-band router 104 B The second dual-band router 104 operates in multiple frequency bands. B can operate in the sub-1 GHz frequency band and the 2.4 GHz frequency band. In the example of FIG. 1, the second dual-band router 104 B The second dual-band router 104 B For example, the second dual-band router 104 uses the base frequency band as the operating frequency band for the synchronous operation mode. B In an exemplary synchronous mode of operation, the second dual-band router 104 utilizes the sub-1 GHz frequency band as its base frequency band. B and a second dual-band router 104 B The child devices synchronize their channel hopping. Also, in the example of FIG. 1, the second dual-band router 104 B The second dual-band router 104 BFor example, the second dual-band router 104 may use an alternative frequency band as the frequency band in which it operates for the asynchronous operation mode. B In the exemplary asynchronous mode of operation, the second dual-band router 104 utilizes the 2.4 GHz frequency band as an alternative frequency band. B and a second dual-band router 104 B child devices may not synchronize their channel hopping.

[0033] In the illustrated example of FIG. 1, the second dual-band router 104 B gateway 102, single-band router 106, and seventh endpoint device 110. C and an eighth endpoint device 110 D For example, the second dual-band router 104 B gateway 102, single-band router 106, and seventh endpoint device 110. C and an eighth endpoint device 110 D The second dual-band router 104 utilizes information contained in the routing tables and / or routing policies to direct data packets between certain endpoint devices. B the seventh endpoint device 110 C and an eighth endpoint device 110 D to other devices in the network 100. In some examples, the second dual-band router 104 B The second dual-band router 104 B and the first dual-band router 104 A The first dual-band router 104 utilizes the alternative frequency bands supported by A In the example of FIG. 1, the second dual-band router 104 B the seventh endpoint device 110 C and an eighth endpoint device 110 DActs as a parent device for

[0034] In the illustrated example of FIG. 1, the single-band router 106 is connected to the gateway 102, the first dual-band router 104, and A , the second dual-band router 104 B , the third endpoint device 108 C , and a fourth endpoint device 108 D 1, the single-band router 106 includes software and / or hardware circuitry. For example, the single-band router 106 includes routing software running on a CPU. Additionally or alternatively, the single-band router 106 includes one or more ASICs. In the example of FIG. 1, the single-band router 106 operates in a single frequency band. For example, the single-band router 106 operates in the 2.4 GHz frequency band. In the example of FIG. 1, the single-band router 106 is coupled to the gateway 102, the first dual-band router 104, and the second dual-band router 106. A , the second dual-band router 104 B , and a third endpoint device 108 C and a fourth endpoint device 108 D For example, the single-band router 106 may be connected to the gateway 102, the first dual-band router 104, or the second dual-band router 104. A , the second dual-band router 104 B , and a third endpoint device 108 C and a fourth endpoint device 108 D The single-band router 106 therefore utilizes information contained in the routing table and / or routing policy to direct data packets between certain endpoint devices among the third endpoint device 108. C and a fourth endpoint device 108 Dto other devices in the network 100. In the example of FIG. 1, the single-band router 106 connects to a third endpoint device 108 C and a fourth endpoint device 108 D Acts as a parent device for

[0035] In the illustrated example of FIG. 1, the first endpoint device 108 A and the second endpoint device 108 B The first dual-band router 104 A Also, a third endpoint device 108 C and a fourth endpoint device 108 D is coupled to the single-band router 106. In the example of FIG. 1, the first endpoint device 108 A , the second endpoint device 108 B , the third endpoint device 108 C , and a fourth endpoint device 108 D In the example of FIG. 1, the first endpoint device 108 A , the second endpoint device 108 B , the third endpoint device 108 C , and / or the fourth endpoint device 108 D One or more of may be implemented by, among others, a smart speaker, a smart plug, a smart tap (e.g., a smart faucet), a contact sensor (e.g., to detect whether a window or door is open), a smart light.

[0036] In the illustrated example of FIG. 1, the fifth endpoint device 110 A and a sixth endpoint device 110 B The first dual-band router 104 A and a seventh endpoint device 110 C and an eighth endpoint device 110 DThe second dual-band router 104 B In the example of FIG. 1, the fifth endpoint device 110 A , the sixth endpoint device 110 B , the seventh endpoint device 110 C , and an eighth endpoint device 110 D In the example of FIG. 1, the fifth endpoint device 110 A , the sixth endpoint device 110 B , the seventh endpoint device 110 C , and / or the eighth endpoint device 110 D One or more of may be implemented by, among others, a smart speaker, a smart plug, a smart tap (e.g., a smart faucet), a contact sensor (e.g., for detecting whether a window or door is open), a smart light.

[0037] In the illustrated example of FIG. 1 , when joining network 100, a child device transmits a discovery request to one or more parent devices in network 100 (e.g., first dual-band router 104A, second dual-band router 104B, and single-band router 106). In response to receiving the discovery request, the parent device transmits a response including synchronization information used by potential child devices to synchronize with the parent device. Thus, in response to the discovery request, a child device attempting to join network 100 may receive multiple responses from potential parent devices. After the child device synchronizes with the parent device, the parent device transmits timing elements (e.g., timing packets) to the child device, with each data packet and / or acknowledgment packet being sent to the child device. An example timing element includes information identifying the time elapsed since the parent device last channel hopped.

[0038] In the illustrated example of FIG. 1 , channel hopping in network 100 is limited to sub-networks of network 100. For example, a child device operating in a sub-1 GHz frequency band synchronizes to the channel hopping schedule of a parent device with which the child device is synchronized. In this manner, the child device stores synchronization information for the parent device with which the child device is synchronized. The parent device may also store synchronization information for nearby peer devices and / or child devices, although this is not required. In the example of FIG. 1 , the fifth endpoint device 110 A and a sixth endpoint device 110 B The first dual-band router 104 A Also, in the example of FIG. 1, the seventh endpoint device 110 C and an eighth endpoint device 110 D The second dual-band router 104 B In some examples, the child device also stores synchronization information for one or more candidate parent devices with which the child device did not synchronize. In this way, the child device may be able to synchronize with other candidate parent devices at different times.

[0039] 1, all child devices synchronize to a given sub-1 GHz compatible parent device, which channel hops on a synchronized schedule, but each of a group of such devices channel hops on a different schedule, allowing for frequency diversity across the sub-networks of network 100. For example, in the example of FIG. A and a second dual-band router 104 B The first dual-band router 104 operates in a different channel hopping sequence. For example, the first dual-band router 104 operates in the sub-1 GHz frequency band. A and a second dual-band router 104 BThe sub-networks do not interfere with each other, thus improving frequency diversity within the network 100.

[0040] 2 is a block diagram of an example implementation of a parent device 200 in the network 100 of FIG. 1. For example, the first dual-band router 104 A and a second dual-band router 104 B may be implemented by parent device 200. In the example of FIG. 2, parent device 200 includes exemplary processing circuitry 202. The example processing circuitry 202 of FIG. 2 includes exemplary communications control circuitry 204, exemplary channel timing circuitry 206, and exemplary counter circuitry 208. The example parent device 200 of FIG. 2 also includes an antenna 210 and exemplary interface circuitry 212. The example interface circuitry 212 includes exemplary transmitter circuitry 214 and exemplary receiver circuitry 216. Also in the example of FIG. 2, parent device 200 includes exemplary memory 218. The example memory 218 includes exemplary instructions 220.

[0041] In the example of FIG. 2 , parent device 200 may be instantiated (e.g., instantiated, made to have any length of time, materialized, implemented, etc.) by a processing circuit element, such as a central processing unit (CPU), executing a first instruction. Additionally or alternatively, parent device 200 of FIG. 2 may be instantiated (e.g., instantiated, made to have any length of time, materialized, implemented, etc.) by (1) an application-specific integrated circuit (ASIC) and / or (2) a field-programmable gate array (FPGA) structured and / or configured in response to execution of a second instruction to perform operations corresponding to the first instruction. Thus, it should be understood that some or all of the circuit elements of FIG. 2 may be instantiated at the same or different times. Some or all of the circuit elements of FIG. 2 may be instantiated, for example, in one or more threads executing concurrently in hardware and / or serially in hardware. Also, in some examples, some or all of the circuit elements of FIG. 2 may be implemented by microprocessor circuit elements that execute instructions and / or FPGA circuit elements that perform operations to implement one or more virtual machines and / or containers.

[0042] In the depicted example of Figure 2, processing circuitry 202 is coupled to interface circuitry 212 and memory 218. For example, processing circuitry 202 is coupled to transmitter circuitry 214, receiver circuitry 216, and memory 218. In the example of Figure 2, processing circuitry 202 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In some examples, processing circuitry 202 is instantiated by the processing circuitry executing a parent instruction and / or is configured to perform operations such as those represented by the flowcharts of Figures 6, 7, 10, and / or 11.

[0043] In the illustrated example of FIG. 2, communications control circuitry 204 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 2, communications control circuitry 204 monitors network 100 for one or more discovery requests from candidate child devices. For example, before a candidate child device synchronizes with parent device 200, the candidate child device transmits a discovery request to parent device 200. As described below, the discovery request identifies a particular channel on which the interface circuitry of the candidate child device will be tuned for a predetermined period of time. In the example of FIG. 2, based on receiving the discovery request, communications control circuitry 204 causes transmitter circuitry 214 to transmit a response to the discovery request on the channel identified in the discovery request.

[0044] 2, the response to the discovery request includes synchronization information. The example synchronization information includes data identifying the number of channels on which communications control circuitry 204 tunes interface circuitry 212, a pseudo-random number sequence on which communications control circuitry 204 hops between channels, two or more dwell times (e.g., 50 milliseconds (ms), 250 ms, etc.) that channel timing circuitry 206 uses to program counter circuitry 208, and the time period after which channel timing circuitry 206 alternates between dwell times (e.g., DWELL_TIME_SWITCH parameter). The exemplary synchronization information also includes data identifying a base frequency band (e.g., a sub-1 GHz frequency band) of parent device 200, an alternate frequency band (e.g., a 2.4 GHz band) of parent device 200, a period of time after which communications control circuitry 204 switches from the base frequency band to the alternate frequency band (e.g., a FREQ_SWITCH_CHANNEL_PARAMETER), and a period of time after which communications control circuitry 204 switches from the alternate frequency band to the base frequency band (e.g., an ALT_FREQ_SLOT_RANGE). The exemplary synchronization information may be formatted as shown in Table 1 below. [Table 1]

[0045] 2, the FREQ_SWITCH_CHANNEL_PARAMETER and ALT_FREQ_SLOT_RANGE parameters are measured in slots. In the examples described herein, a slot represents a period of time dedicated to a channel. For example, a slot is of duration equal to the dwell time. By including the FREQ_SWITCH_CHANNEL_PARAMETER and ALT_FREQ_SLOT_RANGE parameters in the synchronization information, the communications control circuitry 204 enables child devices synchronized to the parent device 200 to follow channel hopping sequences across multiple frequency bands (e.g., both the sub-1 GHz frequency band and the 2.4 GHz frequency band).

[0046] 2 , the example synchronization information in Table 1 indicates to the child device that every 50 slots, parent device 200 switches interface circuitry 212 from being tuned to the base frequency band to being tuned to the alternate frequency band, and remains at the alternate frequency band for 10 slots. In the example of Table 1, the base frequency band is a sub-1 GHz frequency band utilized for the synchronous mode of operation, and the alternate frequency band is 2.4 GHz utilized for the asynchronous mode of operation. Example sub-1 GHz frequency bands include the 915 megahertz (MHz) frequency band (which may be applicable in areas defined by the FCC), the 868 MHz frequency band (which may be applicable in areas defined by regulations complying with standards defined by the European Telecommunications Standards Institute (ETSI)), and the 470 MHz frequency band (which may be applicable in areas defined by the Ministry of Industry and Information Technology of the People's Republic of China). The example synchronization information in Table 1 also indicates to the child device that at the end of 10 slots (e.g., at the end of ALT_FREQ_SLOT_RANGE), parent device 200 will switch interface circuitry 212 from being tuned to the 2.4 GHz frequency band to being tuned to the sub-1 GHz frequency band. In the example of FIG. 2, once communications control circuitry 204 selects a channel (e.g., in the sub-1 GHz frequency band or the 2.4 GHz frequency band), communications control circuitry 204 follows the hopping sequence for each channel, even if uninterrupted. For example, in the example synchronization information in Table 1, slot number 65 will be the same channel as per the selected hopping sequence, regardless of whether a switch to the 2.4 GHz frequency band occurred in slot 50.

[0047] In the illustrated example of FIG. 2 , the pseudorandom sequence identified in the synchronization information identifies N+M channels, where N represents the number of slots dedicated to channels in the sub-1 GHz frequency band and M represents the number of slots dedicated to channels in the 2.4 GHz frequency band. Therefore, channel hopping using N+M slots indicates that there are M slots dedicated to the 2.4 GHz frequency band and (NM) slots dedicated to the sub-1 GHz frequency band. As described above, when the communications control circuitry 204 tunes the interface circuitry 212 to a channel in the sub-1 GHz frequency band, the communications control circuitry 204 continues to operate the interface circuitry 212 in the sub-1 GHz frequency band and channel hops to another channel in the sub-1 GHz frequency band after the dwell time expires. Also, in the example of FIG. 2 , when the communications control circuitry 204 tunes the interface circuitry 212 to a channel in the 2.4 GHz frequency band, the communications control circuitry 204 does not follow the channel hopping sequence. 2, communications control circuitry 204 causes interface circuitry 212 to remain tuned to a single channel for the number of slots specified by the ALT_FREQ_SLOT_RANGE parameter. For example, channel hopping may not be required by RF regulatory agencies in certain regions when a device is operating in the 2.4 GHz frequency band. Thus, when parent device 200 is operating in the 2.4 GHz frequency band, parent device 200 is considered to be operating in an asynchronous mode of operation. In an additional or alternative example, communications control circuitry 204 implements channel hopping in the 2.4 GHz frequency band.

[0048] In the illustrated example of FIG. 2 , after the child device synchronizes with the parent device 200 (e.g., using synchronization information), the communications control circuitry 204 and the channel timing circuitry 206 perform channel hopping in the base frequency band of the parent device 200. In the example of FIG. 2 , in accordance with the synchronization information, the communications control circuitry 204 tunes the interface circuitry 212 to a channel and operates within the channel for a dwell time. For example, based on a pseudo-random number sequence identified in the synchronization information, the communications control circuitry 204 calculates the channel to which the interface circuitry 212 should be tuned. Also, for example, the communications control circuitry 204 communicates (e.g., exchanges data) with the child device within the channel for the dwell time. In the example of FIG. 2 , based on the expiration of the dwell time, the communications control circuitry 204 determines whether the data exchange in the first channel has expired. For example, for a child device utilizing CSL, if the child device and parent device 200 are exchanging data when the dwell time expires, communication control circuitry 204 maintains the current adjustment of interface circuitry 212 until the data exchange is complete (e.g., until communication control circuitry 204 receives an acknowledgment packet from the child device and / or transmits an acknowledgment packet to the child device).

[0049] In the illustrated example of FIG. 2, parent device 200 may cooperate with other parent devices in network 100 to assist a child device in selecting a parent device with which the child device has a stronger connection. For example, when a child device is synchronized with parent device 200, there may be candidate parent devices that have a stronger connection with the child device than parent device 200. In this manner, parent device 200 may cooperate with candidate parent devices to notify the child device of the existence of candidate parent devices. Similarly, parent device 200 may receive communications from other parent devices indicating candidate child devices with which parent device 200 may have a stronger connection. In some examples, communication control circuitry 204 is instantiated by processing circuitry executing communication control instructions and / or configured to perform operations such as those represented by the flowcharts of FIGS. 6, 7, 10, and / or 11.

[0050] In the illustrated example of FIG. 2, the channel timing circuit element 206 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 2, the channel timing circuit element 206 controls the counter circuit element 208. For example, the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to track dwell times of the parent device 200. For example, the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to count down from a dwell time identified in the synchronization information. Additionally or alternatively, the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to count up from a dwell time identified in the synchronization information. In the example of FIG. 2, the channel timing circuit element 206 determines whether one or more dwell times have expired. For example, the channel timing circuit element 206 determines whether one or more counters have counted down from a predetermined value. Additionally or alternatively, channel timing circuitry 206 determines whether one or more counters have counted up from a predetermined value.

[0051] In the illustrated example of FIG. 2 , the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to track the number of utilized slots for each dwell time of the parent device 200. For example, the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to count down from a DWELL_TIME_SWITCH parameter identified in the synchronization information. Additionally or alternatively, the channel timing circuit element 206 configures one or more counters of the counter circuit element 208 to count up to a DWELL_TIME_SWITCH parameter identified in the synchronization information. In the example of FIG. 2 , the channel timing circuit element 206 determines whether the DWELL_TIME_SWITCH period has expired. For example, the channel timing circuit element 206 determines whether one or more counters have counted down from a predetermined value. Additionally or alternatively, the channel timing circuit element 206 determines whether one or more counters have counted up to a predetermined value. Based on channel timing circuitry 206 determining that the DWELL_TIME_SWITCH period has expired, channel timing circuitry 206 utilizes the second dwell time. For example, channel timing circuitry 206 sets one or more counters of counter circuitry 208 to track the second dwell time. In this manner, channel timing circuitry 206 advantageously enables a child device to select a parent device with which the child device may have a stronger connection.

[0052] For example, once a child device is synchronized to parent device 200, it may be advantageous for the child device to switch to another parent device with which the child device has a stronger connection, if such a parent device is available. If the entire network operates on a single channel (e.g., does not implement channel hopping), the child device may detect different parent devices. However, if the network implements channel hopping (e.g., network 100), different parent devices may be hopping on different channels. Thus, without adjustment, existing channel hopping techniques make it unlikely that different parent devices are transmitting on the same channel as the parent device with which the child device is synchronized. Advantageously, by utilizing different dwell times in the channel hopping sequence, channel timing circuitry 206 increases the likelihood that a child device will detect a parent device with which it may have a stronger connection. For example, FIG. 4 illustrates an example in which different parent devices utilize different dwell times. As described below, utilizing different dwell times between parent devices increases the likelihood that two independent parent devices hopping on different sequences will have a common, overlapping channel. In some examples, channel timing circuitry 206 is instantiated by processing circuitry executing channel timing instructions and / or configured to perform operations such as those represented by the flowcharts of FIGS. 6 and / or 7.

[0053] 2, counter circuit element 208 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 2, counter circuit element 208 includes one or more counters for tracking one or more dwell times, which are the period (in terms of slots) after which parent device 200 switches interface circuit element 212 from a base frequency band (e.g., a sub-1 GHz frequency band) to an alternative frequency band (e.g., a 2.4 GHz frequency band), the period (in terms of slots) after which parent device 200 switches interface circuit element 212 from an alternative frequency band to the base frequency band, and / or the period (in terms of slots) after which channel timing circuit element 206 alternates dwell times. In some examples, counter circuit element 208 is instantiated and / or configured to perform operations by processing circuit element executing counter instructions.

[0054] In some examples, parent device 200 includes a means for processing. For example, the means for processing may be implemented by processing circuitry 202. In some examples, processing circuitry 202 may be instantiated by a processing circuitry such as example processing circuitry 1312 of FIG. 13 . For example, processing circuit element 202 may be instantiated by example microprocessor 1500 of FIG. 15 executing machine-executable instructions such as those implemented by at least blocks 604, 606, 608, 610, 612, 614, 616, and 618 of FIG. 6, at least blocks 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, and 726 of FIG. 7, at least blocks 1002, 1004, 1006, 1008, and 1010 of FIG. 10, and / or at least blocks 1104, 1106, 1108, 1110, and 1114 of FIG. 11. In some examples, processing circuitry 202 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or the FPGA circuitry 1600 of FIG. 16 that is configured and / or structured to perform operations corresponding to machine-readable instructions. Additionally or alternatively, processing circuitry 202 may be instantiated by any other combination of hardware, software, and / or firmware. For example, processing circuitry 202 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other configurations are suitable as well.

[0055] In some examples, the means for processing includes means for controlling communications. For example, the means for controlling communications may be implemented by communications control circuitry 204. In some examples, communications control circuitry 204 may be instantiated by processing circuitry such as example processing circuitry 1312 of FIG. 13. For example, communications control circuitry 204 may be instantiated by example microprocessor 1500 of FIG. 15 executing machine-executable instructions such as those implemented by at least blocks 604, 610, 612, 616, and 618 of FIG. 6, at least blocks 702, 704, 708, 710, 714, 718, 722, and 726 of FIG. 7, at least blocks 1002, 1004, 1006, 1008, and 1010 of FIG. 10, and / or at least blocks 1104, 1106, 1108, 1110, and 1114 of FIG. 11. In some examples, the communications control circuitry 204 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or the FPGA circuitry 1600 of FIG. 16 configured and / or structured to perform operations corresponding to machine-readable instructions. Additionally or alternatively, the communications control circuitry 204 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the communications control circuitry 204 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are suitable as well.

[0056] In some examples, the means for processing includes means for controlling timing. For example, the means for controlling timing may be implemented by channel timing circuitry 206. In some examples, channel timing circuitry 206 may be instantiated by a processing circuitry, such as example processing circuitry 1312 of FIG. 13. For example, channel timing circuitry 206 may be instantiated by example microprocessor 1500 of FIG. 15, which executes machine-executable instructions, such as those implemented by at least blocks 608 and 614 of FIG. 6 and / or at least blocks 706, 712, 716, 720, and 724 of FIG. 7. In some examples, channel timing circuitry 206 may be instantiated by hardware logic circuitry, which may be implemented by ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, channel timing circuitry 206 may be instantiated by any other combination of hardware, software, and / or firmware. For example, channel timing circuitry 206 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other configurations are suitable as well.

[0057] In the illustrated example of Figure 2, antenna 210 is coupled to transmitter circuitry 214 and receiver circuitry 216. In the example of Figure 2, antenna 210 may be implemented by a monopole antenna, a dipole antenna, an array antenna, a large loop antenna, a traveling wave antenna, or an aperture antenna, among others. In the example of Figure 2, antenna 210 emits signals into and detects signals from the environment in which parent device 200 is located.

[0058] In the illustrated example of FIG. 2 , interface circuitry 212 is coupled to processing circuitry 202 and antenna 210. In some examples, interface circuitry 212 is implemented by one or more transmitters and one or more receivers. Additionally or alternatively, interface circuitry 212 is implemented by one or more transceivers. As noted above, in the illustrated example of FIG. 2 , interface circuitry 212 includes transmitter circuitry 214 and receiver circuitry 216. In the illustrated example of FIG. 2 , transmitter circuitry 214 is coupled to processing circuitry 202 and antenna 210. The example transmitter circuitry 214 of FIG. 2 is implemented by physical layer circuitry. For example, transmitter circuitry 214 includes physical coding sublayer circuitry and physical medium dependent layer circuitry. In the illustrated example of FIG. 2 , receiver circuitry 216 is coupled to processing circuitry 202 and antenna 210. 2 is implemented by physical layer circuitry, e.g., receiver circuitry 216 includes physical coding sublayer circuitry and physical media dependent layer circuitry.

[0059] In the illustrated example of FIG. 2, memory 218 is coupled to processing circuit element 202. The example memory 218 of FIG. 2 is configured to store data. For example, memory 218 can store one or more files that indicate synchronization information, information communicated in discovery requests from candidate child devices, information communicated from one or more parent devices, one or more connectivity criteria for child devices synchronized with parent device 200, and / or any other values. Memory 218 also stores one or more files that indicate instructions 220. For example, instructions 220 may be implemented by the machine-readable instructions of FIG. 6, FIG. 7, FIG. 10, and / or FIG. 11. In the example of FIG. 2, memory 218 may be implemented by volatile memory (e.g., synchronous dynamic random access memory (SDRAM), DRAM, RAMBUS dynamic random access memory (RDRAM), etc.) and / or non-volatile memory (e.g., flash memory). The example memory 218 may additionally or alternatively be implemented with one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDDR), etc.

[0060] In additional or alternative examples, the illustrated memory 218 may be implemented by one or more mass storage devices, such as a hard disk drive, a compact disk drive, a digital versatile disk drive, a solid state disk drive, etc. In the illustrated example, memory 218 is shown as a single database, but memory 218 may be implemented by any number and / or type of databases. Also, the data stored in memory 218 may be in any data format, such as, for example, binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc.

[0061] 3 is a block diagram of an example implementation of a child device 300 in the network 100 of FIG. A , the second endpoint device 108 B , the third endpoint device 108C , the fourth endpoint device 108 D , the fifth endpoint device 110 A , the sixth endpoint device 110 B , the seventh endpoint device 110 C , and an eighth endpoint device 110 D may be implemented by the child device 300. In the example of Figure 3, the child device 300 includes exemplary processing circuitry 302. The example processing circuitry 302 of Figure 3 includes exemplary communications control circuitry 304, exemplary channel timing circuitry 306, and exemplary counter circuitry 308. The example child device 300 of Figure 3 also includes an antenna 310 and exemplary interface circuitry 312. The example interface circuitry 312 includes exemplary transmitter circuitry 314 and exemplary receiver circuitry 316. Also in the example of Figure 3, the child device 300 includes exemplary memory 318. The example memory 318 includes exemplary instructions 320.

[0062] In the example of FIG. 3 , child device 300 may be instantiated (e.g., instantiated, made to have any length of time, materialized, implemented, etc.) by processing circuitry, such as a CPU, executing a first instruction. Additionally or alternatively, child device 300 of FIG. 3 may be instantiated (e.g., instantiated, made to have any length of time, materialized, implemented, etc.) by (1) an ASIC and / or (2) an FPGA structured and / or configured in response to execution of a second instruction to perform operations corresponding to the first instruction. Thus, it should be understood that some or all of the circuitry of FIG. 3 may be instantiated at the same or different times. Some or all of the circuitry of FIG. 3 may be instantiated, for example, in one or more threads executing simultaneously on hardware and / or serially on hardware. Also, in some examples, some or all of the circuitry of FIG. 3 may be implemented by microprocessor circuitry and / or FPGA circuitry executing instructions to perform operations to implement one or more virtual machines and / or containers.

[0063] In the depicted example of Figure 3, processing circuitry 302 is coupled to interface circuitry 312 and memory 318. For example, processing circuitry 302 is coupled to transmitter circuitry 314, receiver circuitry 316, and memory 318. In the example of Figure 3, processing circuitry 302 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In some examples, processing circuitry 302 is instantiated by the processing circuitry executing a parent instruction and / or is configured to perform operations such as those represented by the flowcharts of Figures 8, 9, and / or 12.

[0064] In the illustrated example of FIG. 3 , the communications control circuitry 304 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 3 , the communications control circuitry 304 searches the network for one or more candidate parent devices. For example, the communications control circuitry 304 transmits one or more discovery requests. In the example of FIG. 3 , the communications control circuitry 304 repeatedly transmits the one or more discovery requests on all channels supported by the child device 300. In this manner, at least one channel overlaps with the channel on which the candidate parent device is tuned. The example discovery request includes information identifying the channel on which the communications control circuitry 304 tunes the interface circuitry 312 for a predetermined period of time. In this manner, after receiving the discovery request, when the candidate parent device is tuned to the channel identified in the discovery request, the candidate parent device transmits a response to the discovery request that includes synchronization information.

[0065] In the illustrated example of FIG. 3 , after the child device 300 (e.g., receiver circuitry 316) receives one or more responses to one or more discovery requests, the communications control circuitry 304 selects one or more candidate parent devices with which the child device 300 will synchronize. For example, the communications control circuitry 304 selects the candidate parent device with the strongest connectivity to the child device 300 from among the one or more candidate parent devices. In the example of FIG. 3 , the communications control circuitry 304 calculates a received signal strength indicator (RSSI) value for each candidate parent device from which the child device 300 receives a response and selects the candidate parent device with the highest RSSI value. The strength of connectivity may also be measured in terms of bit error rate (BER), link quality indicator (LQI), among other connectivity metrics. In the example of FIG. 3 , the communications control circuitry 304 causes the synchronization information of the selected candidate parent devices to be stored in memory 318.

[0066] In the illustrated example of FIG. 3 , based on the synchronization information, the processing circuitry 302 synchronizes channel hopping with the selected parent device. For example, the communications control circuitry 304 and the channel timing circuitry 306 perform channel hopping according to the synchronization information. For example, based on the synchronization information, the communications control circuitry 304 tunes the interface circuitry 312 to a channel and operates within the channel for a dwell time. Also, based on, for example, a pseudo-random number sequence identified in the synchronization information, the communications control circuitry 304 calculates the channel to which the interface circuitry 312 should be tuned. In the example of FIG. 3 , the communications control circuitry 304 communicates (e.g., performs one or more data exchanges) with the parent device within the channel for the dwell time.

[0067] In the illustrated example of FIG. 3 , child device 300 may utilize CSL. For example, when the parent device is not communicating with child device 300, communication control circuitry 304 places child device 300 in a sleep mode of operation. For example, to place child device 300 in the sleep mode of operation, communication control circuitry 304 turns off interface circuitry 312. At a specific time, communication control circuitry 304 places child device 300 in a wake mode of operation. For example, to place child device 300 in the wake mode of operation, communication control circuitry 304 turns on interface circuitry 312. Also, at a specific time, communication control circuitry 304 tunes interface circuitry 312 to a channel on which the parent device is expected to operate and operates within the channel. In the example of FIG. 3 , communication control circuitry 304 determines whether data exchange on the channel has ended based on the expiration of a dwell time. For example, if the child device 300 is using a CSL and the child device 300 and the parent device are exchanging data when the dwell time expires, the communication control circuitry 304 maintains the current adjustment of the interface circuitry 312 until the data exchange is complete (e.g., until the communication control circuitry 304 receives an acknowledgment packet from the parent device and / or transmits an acknowledgment packet to the parent device).

[0068] In the illustrated example of FIG. 3 , a parent device with which child device 300 is synchronized may inform child device 300 of another parent device with which child device 300 has a stronger connection. For example, when child device 300 is synchronized with a first parent device, the first parent device may inform child device 300 of a second parent device with which child device 300 has a stronger connection than the first parent device. Based on receiving such notification from the first parent device, communication control circuitry 304 causes a discovery request to be transmitted to the second parent device and synchronizes with the second parent device after receiving a response from the second parent device. In some examples, communication control circuitry 304 is instantiated by processing circuitry executing communication control instructions and / or configured to perform operations such as those represented by the flowcharts of FIGS. 8 , 9 , and / or 12 .

[0069] In the illustrated example of FIG. 3 , the channel timing circuit element 306 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 3 , the channel timing circuit element 306 controls the counter circuit element 308. For example, the channel timing circuit element 306 configures one or more counters of the counter circuit element 308 to track the dwell time of the parent device to which the child device 300 is synchronized. For example, the channel timing circuit element 306 configures one or more counters of the counter circuit element 308 to count down from the dwell time identified in the synchronization information. Additionally or alternatively, the channel timing circuit element 306 configures one or more counters of the counter circuit element 308 to count up to the dwell time identified in the synchronization information. In the example of FIG. 3 , the channel timing circuit element 306 determines whether one or more dwell times have expired. For example, the channel timing circuit element 306 determines whether one or more counters have counted down from a predetermined value. Additionally or alternatively, channel timing circuitry 306 determines whether one or more counters have counted up to a predetermined value.

[0070] In the illustrated example of FIG. 3 , the channel timing circuitry 306 configures one or more counters of the counter circuitry 308 to track the number of utilized slots for each dwell time of the parent device to which the child device 300 is synchronized. For example, the channel timing circuitry 306 configures one or more counters of the counter circuitry 308 to count down from a DWELL_TIME_SWITCH parameter identified in the synchronization information. Additionally or alternatively, the channel timing circuitry 306 configures one or more counters of the counter circuitry 308 to count up to a DWELL_TIME_SWITCH parameter identified in the synchronization information. In the example of FIG. 3 , the channel timing circuitry 306 determines whether the DWELL_TIME_SWITCH period has expired. For example, the channel timing circuitry 306 determines whether one or more counters have counted down from a predetermined value. Additionally or alternatively, the channel timing circuitry 306 determines whether one or more counters have counted up to a predetermined value.

[0071] In the illustrated example of FIG. 3 , based on channel timing circuitry 306 determining that the DWELL_TIME_SWITCH period has expired, channel timing circuitry 306 utilizes a second dwell time. For example, channel timing circuitry 306 sets one or more counters of counter circuitry 308 to track the second dwell time. As described above, other parent devices (e.g., parent devices to which child device 300 is not synchronized) utilize different dwell times than the parent. In this manner, child device 300 can detect and connect to other parent devices if the other parent device has stronger connectivity with child device 300. In some examples, channel timing circuitry 306 is instantiated by processing circuitry executing channel timing instructions and / or configured to perform operations such as those represented by the flowcharts of FIGS. 8 and / or 9 .

[0072] 3, counter circuitry 308 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In the example of FIG. 3, counter circuitry 308 includes one or more counters to track one or more dwell times, which are the period (in terms of slots) after which the parent device switches from the base frequency band (e.g., a sub-1 GHz frequency band) to the alternate frequency band (e.g., a 2.4 GHz frequency band), the period (in terms of slots) after which the parent device switches from the alternate frequency band to the base frequency band, and / or the period (in terms of slots) after which the channel timing circuitry 306 alternates dwell times. In some examples, counter circuitry 308 is instantiated and / or configured to perform operations by processing circuitry executing counter instructions.

[0073] In some examples, the child device 300 includes a means for processing. For example, the means for processing may be implemented by processing circuitry 302. In some examples, the processing circuitry 302 may be instantiated by a processing circuitry such as the example processing circuitry 1412 of FIG. 14. For example, the processing circuitry 302 may be instantiated by the example microprocessor 1500 of FIG. 15, which executes machine-executable instructions such as those implemented by at least blocks 802, 806, 808, 810, 812, 814, 816, 818, and 820 of FIG. 8, at least blocks 902, 904, 906, 908, 910, 912, 914, and 916 of FIG. 9, and / or at least blocks 1204 and 1208 of FIG. 12. In some examples, processing circuitry 302 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or the FPGA circuitry 1600 of FIG. 16 configured and / or structured to perform operations corresponding to machine-readable instructions. Additionally or alternatively, processing circuitry 302 may be instantiated by any other combination of hardware, software, and / or firmware. For example, processing circuitry 302 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other configurations are suitable as well.

[0074] In some examples, the means for processing includes means for controlling communications. For example, the means for controlling communications may be implemented by communications control circuitry 304. In some examples, communications control circuitry 304 may be instantiated by processing circuitry such as example processing circuitry 1412 of FIG. 14. For example, communications control circuitry 304 may be instantiated by example microprocessor 1500 of FIG. 15 executing machine-executable instructions such as those implemented by at least blocks 802, 806, 812, 814, 818, and 820 of FIG. 8, at least blocks 902, 908, 910, 914, and 916 of FIG. 9, and / or at least blocks 1204 and 1208 of FIG. 12. In some examples, communications control circuitry 304 may be instantiated by hardware logic circuitry, which may be implemented by ASIC, XPU, or FPGA circuitry 1600 of FIG. 16 configured and / or structured to perform operations corresponding to machine-readable instructions. Additionally or alternatively, the communications control circuitry 304 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the communications control circuitry 304 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other configurations are suitable as well.

[0075] In some examples, the means for processing includes means for controlling timing. For example, the means for controlling timing may be implemented by channel timing circuitry 306. In some examples, channel timing circuitry 306 may be instantiated by a processing circuitry, such as example processing circuitry 1412 of FIG. 14. For example, channel timing circuitry 306 may be instantiated by example microprocessor 1500 of FIG. 15, which executes machine-executable instructions, such as those implemented by at least blocks 810 and 816 of FIG. 8 and / or at least blocks 904, 906, and 912 of FIG. 9. In some examples, channel timing circuitry 306 may be instantiated by hardware logic circuitry, which may be implemented by ASIC, XPU, or FPGA circuitry 1600 of FIG. 16, configured and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, channel timing circuitry 306 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the channel timing circuitry 306 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other configurations are equally suitable.

[0076] In the illustrated example of Figure 3, antenna 310 is coupled to transmitter circuitry 314 and receiver circuitry 316. In the example of Figure 3, antenna 310 may be implemented by a monopole antenna, a dipole antenna, an array antenna, a large loop antenna, a traveling wave antenna, or an aperture antenna, among others. In the example of Figure 3, antenna 310 emits signals into and detects signals from the environment in which child device 300 is located.

[0077] In the illustrated example of FIG. 3 , interface circuitry 312 is coupled to processing circuitry 302 and antenna 310. In some examples, interface circuitry 312 is implemented by one or more transmitters and one or more receivers. Additionally or alternatively, interface circuitry 312 is implemented by one or more transceivers. As noted above, in the example of FIG. 3 , interface circuitry 312 includes transmitter circuitry 314 and receiver circuitry 316. In the example of FIG. 3 , transmitter circuitry 314 is coupled to processing circuitry 302 and antenna 310. The example transmitter circuitry 314 of FIG. 3 is implemented by physical layer circuitry. For example, transmitter circuitry 314 includes physical coding sublayer circuitry and physical medium dependent layer circuitry. In the example of FIG. 3 , receiver circuitry 316 is coupled to processing circuitry 302 and antenna 310. The example receiver circuitry 316 of FIG. 3 is implemented by physical layer circuitry. For example, receiver circuitry 316 includes physical coding sublayer circuitry and physical media dependent layer circuitry.

[0078] In the illustrated example of FIG. 3, memory 318 is coupled to processing circuit element 302. The example memory 318 of FIG. 3 is configured to store data. For example, memory 318 can store one or more files that indicate synchronization information for a parent device with which a child device is synchronized, information communicated in a discovery request from child device 300, one or more connectivity criteria for one or more candidate parent devices, and / or any other values. Memory 318 also stores one or more files that indicate instructions 320. For example, instructions 320 may be implemented by the machine-readable instructions of FIG. 8, FIG. 9, and / or FIG. 12. In the example of FIG. 3, memory 318 may be implemented by volatile memory (e.g., SDRAM, DRAM, RDRAM, etc.) and / or non-volatile memory (e.g., flash memory). The example memory 318 may additionally or alternatively be implemented by one or more DDR, such as DDR, DDR2, DDR3, DDR4, mDDR, etc.

[0079] In additional or alternative examples, the illustrated memory 318 may be implemented by one or more mass storage devices, such as a hard disk drive, a compact disk drive, a digital versatile disk drive, a solid state disk drive, etc. In the illustrated example, memory 318 is shown as a single database, but memory 318 may be implemented by any number and / or type of databases. Additionally, the data stored in memory 318 may be in any data format, such as, for example, binary data, comma-separated data, tab-separated data, SQL structures, etc.

[0080] FIG. 4 is a timing diagram 400 illustrating example channel hopping in the network 100 of FIG. 1, for example, for example parent devices having different dwell times. In the example of FIG. 4, an example child device 402 is synchronized with a first example parent device 404. Also in the example of FIG. 4, the child device 402 is not synchronized with a second example parent device 406. In the example of FIG. 4, the first parent device 404 and the second parent device 406 utilize different dwell times. In this manner, the channel hopping sequence of the first parent device 404 overlaps with the channel hopping sequence of the second parent device 406. As a result of the different dwell times, the likelihood that the child device 402 is tuned to the same channel as the second parent device 406 increases. For example, a first example slot 408 of the channel hopping sequence of the first parent device 404 overlaps with a second example slot 410 of the channel hopping sequence of the second parent device 406. Also, during the first slot 408, the receiver circuitry of the child device 402 is tuned to channel "4," and during the second slot 410, the transmitter circuitry of the second parent device 406 is tuned to channel "4." Thus, during the overlapping period of the first slot 408 in the second slot 410, the child device 402 can detect communications from the second parent device 406 and determine whether the child device 402 has a stronger connection with the second parent device 406 than with the first parent device 404.

[0081] Additionally, by dynamically varying the dwell time through the channel hopping sequence, the exemplary parent device further increases the likelihood that a child device will detect a communication from a parent device with which it is not synchronized. For example, each parent device may include a DWELL_TIME_SWITCH parameter that defines the period (in terms of slots) after which each parent device will alternate dwell times. For example, the exemplary synchronization information illustrated in Table 1 above indicates that a parent device (e.g., parent device 200) will alternate between 50 milliseconds and 250 milliseconds every 50 slots. In the example of Table 1, the parent device (e.g., parent device 200) utilizes a 50 millisecond dwell time for slots 0-49, 100-149, 200-249, etc., and a 250 millisecond dwell time for slots 50-99, 150-199, etc. The number of dwell times utilized by a parent device can vary from two different dwell times to any N different dwell times.

[0082] 5 is a timing diagram 500 illustrating example channel hopping in the network 100 of FIG. 1 for an example child device 502 and an example parent device 504 in a sleep mode of operation. In the example of FIG. 5, the child device 502 is synchronized with the parent device 504, and the child device 502 utilizes CSL. For example, during periods when the child device 502 is not scheduled to exchange data with the parent device 504, the child device 502 switches from a wake mode of operation to a sleep mode of operation (e.g., turns off interface circuitry in the child device 502). Also, during periods when the child device 502 is scheduled to exchange data with the parent device 504, the child device 502 switches from a sleep mode of operation to a wake mode of operation (e.g., turns on interface circuitry in the child device 502).

[0083] 5, when the child device 502 switches to a wake mode of operation, the child device 502 tunes to a particular channel on which the parent device 504 is expected to operate. For example, if the child device 502 receives data during the example scheduled wake operation period 506, the child device 502 tunes its receiver circuitry to the channel on which the transmitter circuitry of the parent device 504 is expected to operate. Also, for example, if the child device 502 transmits data during the example scheduled wake operation period 506, the child device 502 tunes its transmitter circuitry to the channel on which the receiver circuitry of the parent device 504 is expected to operate.

[0084] 5, if the example data exchange 508 between the child device 502 and the parent device 504 exceeds the duration (e.g., slot duration) of the scheduled wake period 506, the child device 502 and the parent device 504 continue to operate on the channel to which the devices (e.g., the child device 502 and the parent device 504) were tuned at the start of the scheduled wake period 506. In this manner, the example data exchange 508 during the scheduled wake period 506 occurs on the same channel. In other words, the child device 502 and the parent device 504 may be configured to communicate on a single channel throughout the data exchange 508 that occurs during the scheduled wake period 506. Also, in the illustrated example of FIG. 5, if the start of the scheduled wake period 506 is within a threshold amount of time of a transition on the channel of the parent device 504, the child device 502 and the parent device 504 may be configured to utilize the next channel in the channel hopping sequence for the scheduled wake period 506. In such examples, child device 502 and parent device 504 may be configured to communicate on the next channel during the scheduled wake period 506 based on (e.g., in response to) determining that the scheduled transition to the next channel will occur in less than a threshold amount of time from the start of the scheduled wake period 506. In this manner, the examples described herein enable channel hopping with CSL-compatible devices.

[0085] Although an example manner of implementing parent device 200 of Figure 2 is illustrated in Figure 2, one or more of the elements, processes, and / or devices shown in Figure 2 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Also, although an example manner of implementing child device 300 of Figure 3 is illustrated in Figure 3, one or more of the elements, processes, and / or devices illustrated in Figure 3 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Additionally, the example processing circuitry 202, example communications control circuitry 204, example channel timing circuitry 206, example counter circuitry 208, example antenna 210, example interface circuitry 212, example transmitter circuitry 214, example receiver circuitry 216, example memory 218 of FIG. 2, and / or more generally the example parent device 200, and / or the example processing circuitry 302, example communications control circuitry 304, example channel timing circuitry 306, example counter circuitry 308, example antenna 310, example interface circuitry 312, example transmitter circuitry 314, example receiver circuitry 316, example memory 318, and / or more generally the example child device 300 of FIG. 3 may be implemented in hardware alone or in hardware in combination with software and / or firmware. Thus, for example, any of the example communications control circuitry 204, example channel timing circuitry 206, example counter circuitry 208, and / or more generally, the example processing circuitry 202 of FIG. 2 and / or the example communications control circuitry 304, example channel timing circuitry 306, example counter circuitry 308, and / or more generally, the example processing circuitry 302 of FIG. 3 may be implemented by processing circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs) such as FPGAs.Also, the example parent device 200 of Figure 2 may include one or more elements, processes, and / or devices in addition to or instead of those shown in Figure 2, and / or may include more than one of any or all of the illustrated elements, processes, and devices. Also, the example child device 300 of Figure 3 may include one or more elements, processes, and / or devices in addition to or instead of those shown in Figure 3, and / or may include more than one of any or all of the illustrated elements, processes, and devices.

[0086] Flowcharts representing example machine-readable instructions that may be executed by processing circuitry (e.g., instructions to cause a processing circuitry) to implement and / or instantiate parent device 200 of Figure 2 and / or that represent example operations that may be performed by processing circuitry to implement and / or instantiate parent device 200 of Figure 2 are shown in Figures 6, 7, 10, and / or 11. Flowcharts representing example machine-readable instructions that may be executed by processing circuitry (e.g., instructions to cause a processing circuitry) to implement and / or instantiate child device 300 of Figure 3 and / or that represent example operations that may be performed by processing circuitry to implement and / or instantiate child device 300 of Figure 3 are also shown in Figures 8, 9, and / or 12. The machine-readable instructions may be one or more executable programs or portions of one or more executable programs for execution by a processing circuitry, such as processing circuitry 1312 shown in exemplary processing circuitry platform 1300 described hereinafter in connection with FIG. 13 or processing circuitry 1412 shown in exemplary processing circuitry platform 1400 described hereinafter in connection with FIG. 14, and / or may be one or more functions or portions of functions performed by the exemplary processing circuitry (e.g., FPGA) described hereinafter in connection with FIG. 15 and / or FIG. 16. In some examples, the machine-readable instructions cause an operation, task, etc. to be performed and / or carried out in an automated manner in the real world. As used herein, "automated" means without human involvement.

[0087] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disk, a compact disk (CD), a digital versatile disk (DVD), etc.), a redundant array of independent disks (RAID), registers, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable medium may program and / or be executed by processing circuitry located in one or more hardware devices, although the program in its entirety and / or portions thereof may alternatively be executed and / or instantiated by one or more hardware devices other than the processing circuitry and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an end-point client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an end-point client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media.Also, although the example program is described with reference to the flowcharts depicted in FIGS. 6, 7, 10, and / or 11, many other ways of implementing the example parent device 200 of FIG. 2 may alternatively be used. Also, although the example program is described with reference to the flowcharts depicted in FIGS. 8, 9, and / or 12, many other ways of implementing the example child device 300 of FIG. 3 may alternatively be used. For example, the order of execution of the flowchart blocks may be changed, and / or some of the described blocks may be modified, eliminated, or combined. Additionally or alternatively, any or all of the flowchart blocks may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware. The processing circuitry may be distributed across different network locations and / or may be local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). For example, the processing circuitry may be a CPU and / or FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.An example XPU may be implemented by a heterogeneous computing system that includes multiple types of processing circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more network processing units (NPUs), one or more DSPs, etc., and / or any combination thereof) and orchestration techniques (e.g., application programming interfaces (APIs)) that can assign computing tasks to any of the multiple types of processing circuitry that are suitable and available to perform the computing task.

[0088] The machine-readable instructions described herein may be stored in one or more formats, such as a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may also be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.)), or a data structure (e.g., as part of instructions, code, an indication of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be fragmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located at the same or different locations on a network or collection of networks. Machine-readable instructions may require one or more of installing, modifying, adapting, updating, combining, supplementing, configuring, decrypting, decompressing, decompressing, distributing, reallocating, compiling, etc., to become directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions, which may be individually compressed, encrypted, and / or stored on separate computing devices, which, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations, which together may form a program as described herein.

[0089] In another example, machine-readable instructions may be read by processing circuitry, but may require the addition of a library (e.g., a dynamic link library (DLL)), a software deployment kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., to store settings, input data, record network addresses, etc.) before the machine-readable instructions and / or corresponding program can be executed in whole or in part. Thus, machine-readable medium, computer-readable medium, and / or machine-readable medium, as used herein, may include instructions and / or programs, regardless of the particular format or state of the machine-readable instructions and / or programs.

[0090] The machine-readable instructions described herein may be expressed in any past, present, or future command language, script language, programming language, etc. For example, the machine-readable instructions may be expressed using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0091] As mentioned above, the example operations of Figures 6, 7, 8, 9, 10, 11, and / or 12 may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, to exclude propagated signals, and to exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a short-term event, for temporary buffering, and / or for caching information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for holding information for a period of time but excluding propagating signals and excluding transmission media. Examples of non-transitory computer-readable and / or machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term "device" refers to mechanical and / or electrical equipment, hardware, and / or circuit elements that may or may not be configured with and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0092] The terms "including" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, when a claim uses "comprising" (e.g., comprises, includes, comprising, including, having, etc.) in the preamble or any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, the phrase "at least" is open-ended, just as "comprising" is open-ended when used as a transition term, for example, in the preamble of a claim.

[0093] As used herein, singular references (e.g., "a," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" object refers to one or more of that object. "A," "one or more," and "at least one" are used interchangeably herein. Also, although individually listed, multiple means, elements, or actions may be implemented, for example, by the same entity or object. Also, although individual features may be included in different examples or claims, they may also be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0094] 6 is a flowchart representing example machine-readable instructions and / or example operations 600 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of parent device 200 of FIG. 2 to perform channel hopping across multiple frequency bands. The example machine-readable instructions and / or example operations 600 as described may be performed by a parent device (e.g., parent device 200). The example machine-readable instructions and / or example operations 600 of FIG. 6 begin at block 602, where interface circuitry 212 receives a discovery request from a candidate child device. For example, at block 602, receiver circuitry 216 receives the discovery request from the candidate child device. As described above, the discovery request identifies a particular channel to which the interface circuitry of the candidate child device may be tuned for a predetermined period of time.

[0095] 6 , in block 604, processing circuitry 202 causes transmission of a response to the discovery request, the response including synchronization information. For example, in block 604, communications control circuitry 204 causes transmission of a response to the discovery request via interface circuitry 212, the response including synchronization information. In the example of FIG. 6 , communications control circuitry 204 causes transmission of the response to the discovery request on a channel identified by the discovery request. The example synchronization information includes data identifying a base frequency band of parent device 200, an alternative frequency band of parent device 200, a first period (in terms of slots) after which switching from the base frequency band to the alternative frequency band, and a second period (in terms of slots) after switching from the alternative frequency band to the base frequency band.

[0096] In the illustrated example of FIG. 6 , in block 606, processing circuitry 202 performs channel hopping in the base frequency band. For example, FIG. 7 is a flowchart representing example machine-readable instructions and / or example operations 700 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of parent device 200 of FIG. 2 to perform channel hopping in the base frequency band. Example operations in channels and / or frequency bands generally include data exchange and / or other communication between parent device 200 and its child devices. For example, the data exchange and / or other communication is performed in a conventional manner (e.g., devices transmit data packets and / or acknowledgment packets to each other, and parent device 200 transmits timing elements (e.g., timing packets) to child devices to facilitate synchronization). In the example of FIG. 6 , in block 608, processing circuitry 202 determines whether a first time period has expired. For example, in block 608, channel timing circuitry 206 determines whether a first time period has expired after which switching from the base frequency band to the alternate frequency band has occurred based on one or more counters of counter circuitry 208. Based on (e.g., in response to) processing circuitry 202 determining that the first time period has not expired (block 608: no), machine-readable instructions and / or operations 600 return to block 606. Based on (e.g., in response to) processing circuitry 202 determining that the first time period has expired (block 608: yes), machine-readable instructions and / or operations 600 proceed to block 610.

[0097] 6 , in block 610, processing circuitry 202 tunes interface circuitry 212 of parent device 200 to the alternative frequency band. For example, in block 610, communications control circuitry 204 tunes interface circuitry 212 of parent device 200 to the alternative frequency band. In block 612, processing circuitry 202 operates in the alternative frequency band. For example, in block 612, communications control circuitry 204 operates in the alternative frequency band. As described above, example operations include data exchange and / or other communication between parent device 200 and child devices of parent device 200 (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and parent device 200 transmits timing elements (e.g., timing packets) to child devices to facilitate synchronization). In block 614, processing circuitry 202 determines whether a second time period has expired. For example, in block 614, the channel timing circuit element 206 determines whether a second time period for subsequently switching from the alternative frequency band to the base frequency band has expired based on one or more counters of the counter circuit element 208.

[0098] 6 , based on (e.g., in response to) the processing circuitry 202 determining that the second time period has not expired (block 614: NO), the machine-readable instructions and / or operations 600 return to block 612. Based on (e.g., in response to) the processing circuitry 202 determining that the second time period has expired (block 614: YES), the machine-readable instructions and / or operations 600 proceed to block 616. In block 616, the processing circuitry 202 tunes the interface circuitry 212 of the parent device 200 to the base frequency band. For example, in block 616, the communications control circuitry 204 tunes the interface circuitry 212 of the parent device 200 to the base frequency band.

[0099] 6, in block 618, the processing circuitry 202 determines whether to continue operation. For example, in block 618, the communications control circuitry 204 determines whether to continue operation based on whether the parent device 200 is powered. Based on (e.g., in response to) the processing circuitry 202 determining that the parent device 200 will continue operation (block 618: yes), the machine-readable instructions and / or operations 600 return to block 606. Based on (e.g., in response to) the processing circuitry 202 determining that the parent device 200 will not continue operation (block 618: no), the machine-readable instructions and / or operations 600 end.

[0100] 7 is a flowchart representing example machine-readable instructions and / or example operations 700 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of parent device 200 of FIG. 2 to perform channel hopping in the base frequency band. The example machine-readable instructions and / or example operations 700 as described may be performed by a parent device (e.g., parent device 200). As noted above, the example machine-readable instructions and / or example operations 700 of FIG. 7 may be executed, instantiated, and / or performed to implement block 606 of the example machine-readable instructions and / or example operations 600 of FIG. 6. The example machine-readable instructions and / or example operations 700 of FIG. 7 begin at block 702, where processing circuitry 202 tunes interface circuitry 212 of parent device 200 to a first channel in the base frequency band. For example, in block 702, the communications control circuitry 204 tunes the interface circuitry 212 of the parent device 200 to a first channel in the base frequency band.

[0101] 7 , in block 704, processing circuitry 202 operates on a first channel. For example, in block 704, communication control circuitry 204 operates on the first channel. As described above, example operations include data exchange and / or other communication between parent device 200 and its child devices (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and parent device 200 transmits timing elements (e.g., timing packets) to its child devices to facilitate synchronization). In block 706, processing circuitry 202 determines whether a first dwell period has expired. For example, in block 706, channel timing circuitry 206 determines whether a first dwell period for parent device 200 has expired based on one or more counters of counter circuitry 208. Based on (e.g., in response to) the processing circuitry 202 determining that the first dwell time has not expired (block 706: no), the machine-readable instructions and / or operations 700 return to block 704. For example, based on (e.g., in response to) the processing circuitry 202 (e.g., channel timing circuitry 206) determining that the first dwell time has not expired at block 706, the processing circuitry 202 (e.g., communications control circuitry 204) may be configured to continue operating at block 704. Based on (e.g., in response to) the processing circuitry 202 determining that the first dwell time has expired (block 706: yes), the machine-readable instructions and / or operations 700 proceed to block 708.

[0102] 7 , in block 708, processing circuitry 202 determines whether the first data exchange on the first channel is complete. For example, in block 708, communications control circuitry 204 determines whether the first data exchange on the first channel is complete. Based on (e.g., in response to) processing circuitry 202 determining that the first data exchange on the first channel is not complete (block 708: No), the machine-readable instructions and / or operations 700 return to block 704. For example, based on (e.g., in response to) processing circuitry 202 (e.g., communications control circuitry 204) determining that the first data exchange on the first channel is not complete in block 708, processing circuitry 202 (e.g., communications control circuitry 204) may be configured to continue operation on the first channel in block 704. Based on (e.g., in response to) processing circuitry 202 determining that the first data exchange on the first channel is complete (block 708: YES), the machine-readable instructions and / or operations 700 proceed to block 710. In the illustrated example of Figure 7, in block 710, processing circuitry 202 tunes interface circuitry 212 of parent device 200 to a second channel in the base frequency band. For example, in block 710, communications control circuitry 204 tunes interface circuitry 212 of parent device 200 to the second channel in the base frequency band.

[0103] 7, in block 712, processing circuitry 202 determines whether the period during which parent device 200 subsequently rotates dwell times has expired. For example, in block 712, channel timing circuitry 206 determines whether the period during which parent device 200 subsequently rotates dwell times has expired. Based on (e.g., in response to) processing circuitry 202 determining that the period during which subsequent dwell times have rotated has not expired (block 712: no), machine-readable instructions and / or operations 700 proceed to block 714. Based on (e.g., in response to) processing circuitry 202 determining that the period during which subsequent dwell times have rotated has expired (block 712: yes), machine-readable instructions and / or operations 700 proceed to block 720.

[0104] 7 , in block 714, processing circuitry 202 operates on the second channel. For example, in block 714, communication control circuitry 204 operates on the second channel. As described above, example operations include data exchange and / or other communication between parent device 200 and its child devices (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and parent device 200 transmits timing elements (e.g., timing packets) to its child devices to facilitate synchronization). In block 716, processing circuitry 202 determines whether a first dwell period for parent device 200 has expired. For example, in block 716, channel timing circuitry 206 determines whether a first dwell period for parent device 200 has expired based on one or more counters of counter circuitry 208. Based on (e.g., in response to) the processing circuit element 202 determining that the first dwell time has not expired (block 716: no), the machine-readable instructions and / or operations 700 return to block 714. Based on (e.g., in response to) the processing circuit element 202 determining that the first dwell time has expired (block 716: yes), the machine-readable instructions and / or operations 700 proceed to block 718.

[0105] 7 , in block 718, processing circuitry 202 determines whether the second data exchange on the second channel is complete. For example, in block 718, communications control circuitry 204 determines whether the second data exchange on the second channel is complete. Based on (e.g., in response to) processing circuitry 202 determining that the second data exchange on the second channel is not complete (block 718: no), machine-readable instructions and / or operations 700 return to block 714. Based on (e.g., in response to) processing circuitry 202 determining that the second data exchange on the second channel is complete (block 718: yes), machine-readable instructions and / or operations 700 return to machine-readable instructions and / or operations 600 at block 608.

[0106] 7 , in block 720, processing circuitry 202 utilizes a second dwell time for parent device 200 based on expiration of a period after which parent device 200 rotates dwell times. For example, in block 720, channel timing circuitry 206 utilizes a second dwell time for parent device 200 based on expiration of a period after which parent device 200 rotates dwell times. In block 722, processing circuitry 202 operates on a second channel. For example, in block 722, communication control circuitry 204 operates on a second channel. As described above, example operations include data exchange and / or other communications between parent device 200 and child devices of parent device 200 (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and parent device 200 transmits timing elements (e.g., timing packets) to child devices to facilitate synchronization). At block 724, processing circuitry 202 determines whether a second dwell period has expired for parent device 200. For example, at block 724, channel timing circuitry 206 determines whether a second dwell period has expired for parent device 200 based on one or more counters of counter circuitry 208.

[0107] 7 , based on (e.g., in response to) the processing circuitry 202 determining that the second dwell time has not expired (block 724: NO), the machine-readable instructions and / or operations 700 return to block 722. Based on (e.g., in response to) the processing circuitry 202 determining that the second dwell time has expired (block 724: YES), the machine-readable instructions and / or operations 700 proceed to block 726. In block 726, the processing circuitry 202 determines whether the third data exchange on the second channel has completed. For example, in block 726, the communications control circuitry 204 determines whether the third data exchange on the second channel has completed. Based on (e.g., in response to) the processing circuitry 202 determining that the third data exchange on the second channel has not completed (block 726: NO), the machine-readable instructions and / or operations 700 return to block 722. Based on (e.g., in response to) the processing circuit element 202 determining that the third data exchange on the second channel is complete (block 726: yes), the machine-readable instructions and / or operations 700 return to the machine-readable instructions and / or operations 600 at block 608.

[0108] 8 is a flowchart representing example machine-readable instructions and / or example operations 800 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the child device 300 of FIG. 3 to synchronize with an example parent device. The example machine-readable instructions and / or example operations 800 as described may be performed by a child device (e.g., the child device 300). The example machine-readable instructions and / or example operations 800 of FIG. 8 begin at block 802, where the processing circuitry 302 causes one or more discovery requests to be transmitted to one or more candidate parent devices. For example, at block 802, the communications control circuitry 304 causes one or more discovery requests to be transmitted to one or more candidate parent devices. The example discovery requests include information identifying the channels to which the communications control circuitry 304 will tune the interface circuitry 312 for a predetermined period of time.

[0109] In the illustrated example of FIG. 8 , in block 804, the interface circuitry 312 receives one or more responses to the one or more discovery requests from one or more candidate parent devices. For example, the communications control circuitry 304 transmits one or more discovery requests and then tunes the receiver circuitry 316 to the channel identified in the discovery request. Thus, in block 804, the receiver circuitry 316 receives one or more responses to the one or more discovery requests from the one or more candidate parent devices on the channel identified in the discovery request. In block 806, the processing circuitry 302 selects a first parent device to synchronize from the one or more candidate parent devices. For example, in block 806, the communications control circuitry 304 selects a first parent device to synchronize from the one or more candidate parent devices based on one or more connectivity criteria between the child device 3000 and the one or more candidate parent devices. Processing circuit element 302 may be configured to determine one or more connectivity criteria based on, for example, the signal strength of each response received in block 804. Additionally or alternatively, each response may include an indication of the connectivity criteria between child device 300 and its respective parent device.

[0110] 8 , in block 808, the processing circuit element 302 follows the channel hopping sequence of the first parent device in the base frequency band of the first parent device. Example operation in a channel and / or in a frequency band generally includes data exchange and / or other communication between the child device 300 and the parent device with which the child device 300 is synchronized. For example, the data exchange and / or other communication is performed in a conventional manner (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and the parent device with which the child device 300 is synchronized transmits timing elements (e.g., timing packets) to the child device 300 to facilitate synchronization). In block 810, the processing circuit element 302 determines whether a first time period has expired, after which the first parent device switches from the base frequency band to the alternate frequency band. For example, in block 810, the channel timing circuitry 306 determines whether a first time period has expired, after which the first parent device will switch from the base frequency band to the alternate frequency band. Based on (e.g., in response to) the processing circuitry 302 determining that the first time period has not expired (block 810: no), the machine-readable instructions and / or operations 800 return to block 808. Based on (e.g., in response to) the processing circuitry 302 determining that the first time period has expired (block 810: yes), the machine-readable instructions and / or operations 800 proceed to block 812.

[0111] 8 , in block 812, processing circuitry 302 tunes interface circuitry 312 of child device 300 to the alternative frequency band. For example, in block 812, communications control circuitry 304 tunes interface circuitry 312 of child device 300 to the alternative frequency band. In block 814, processing circuitry 302 operates in the alternative frequency band. For example, in block 814, communications control circuitry 304 operates in the alternative frequency band. As described above, example operations include data exchange and / or other communications between child device 300 and a parent device with which child device 300 is synchronized (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and the parent device with which child device 300 is synchronized transmits timing elements (e.g., timing packets) to child device 300 to facilitate synchronization). In block 816, the processing circuitry 302 determines whether a second time period has expired after which the first parent device switches from the alternative frequency band to the base frequency band. For example, in block 816, the channel timing circuitry 306 determines whether a second time period has expired after which the first parent device switches from the alternative frequency band to the base frequency band based on one or more counters of the counter circuitry 308.

[0112] 8 , in response to (e.g., in response to) the processing circuitry 302 determining that the second time period has not expired (block 816: NO), the machine-readable instructions and / or operations 800 return to block 814. In response to (e.g., in response to) the processing circuitry 302 determining that the second time period has expired (block 816: YES), the machine-readable instructions and / or operations 800 proceed to block 818. In block 818, the processing circuitry 302 tunes the interface circuitry 312 of the child device 300 to the base frequency band. For example, in block 818, the communications control circuitry 304 tunes the interface circuitry 312 of the child device 300 to the base frequency band.

[0113] 8 , in block 820, the processing circuitry 302 determines whether to continue operation. For example, in block 820, the communications control circuitry 304 determines whether to continue operation based on whether the child device 300 is powered. Based on (e.g., in response to) the processing circuitry 302 determining to continue operation of the child device 300 (block 820: yes), the machine-readable instructions and / or operations 800 return to block 808. For example, after determining to continue operation of the child device 300 in block 820, the processing circuitry 302 may be configured to follow the channel hopping sequence of the first parent device in block 808. Based on (e.g., in response to) the processing circuitry 302 determining that the child device 300 will not continue operation (block 820: no), the machine-readable instructions and / or operations 800 end.

[0114] 9 is a flowchart representing example machine-readable instructions and / or example operations 900 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of child device 300 of FIG. 3 to perform coordinated sampled listening using channel hopping. The example machine-readable instructions and / or example operations 900 as described may be performed by a child device (e.g., child device 300). The example machine-readable instructions and / or example operations 900 of FIG. 9 begin at block 902, where processing circuitry 302 places the child device in a sleep mode of operation. For example, at block 902, communications control circuitry 304 places child device 300 in a sleep mode of operation by turning off interface circuitry 312.

[0115] 9 , in block 904, the processing circuitry 302 determines a time after which to place the device in a wake mode of operation. For example, in block 904, the channel timing circuitry 306 determines a time after which to place the device in a wake mode of operation. In block 906, the processing circuitry 302 determines whether that time has occurred. For example, in block 906, the channel timing circuitry 306 determines whether that time has occurred based on one or more counters of the counter circuitry 308. Based on (e.g., in response to) the processing circuitry 302 determining that the time has not occurred (block 906: no), the machine-readable instructions and / or operations 900 return to block 906. Based on (e.g., in response to) the processing circuitry 302 determining that the time has occurred (block 906: yes), the machine-readable instructions and / or operations 900 proceed to block 908.

[0116] In the illustrated example of FIG. 9 , in block 908, the processing circuitry 302 tunes the interface circuitry 312 of the child device 300 to the channel on which the parent device is expected to operate, and the child device 300 is synchronized with the parent device. For example, in the illustrated example of FIG. 9 , in block 908, the communications control circuitry 304 tunes the interface circuitry 312 of the child device 300 to the channel on which the parent device is expected to operate during a wake period of the child device 300, and the child device 300 is synchronized with the parent device. In block 910, the processing circuitry 302 operates on that channel. For example, in block 910, the communications control circuitry 204 operates on that channel during a wake period of the child device 300. As described above, example operations include data exchange and / or other communications between the child device 300 and a parent device with which the child device 300 is synchronized (e.g., the devices transmit data packets and / or acknowledgment packets to each other, and the parent device with which the child device 300 is synchronized transmits timing elements (e.g., timing packets) to the child device 300 to facilitate synchronization). Examples of wake periods described in connection with blocks 908 and 910 are described above with respect to FIG. 5. At block 912, the processing circuitry 302 determines whether a dwell period for the parent device has expired. For example, at block 912, the channel timing circuitry 306 determines whether a dwell period for the parent device has expired based on one or more counters of the counter circuitry 308.

[0117] 9 , based on (e.g., in response to) the processing circuitry 302 determining that the dwell time has not expired (block 912: no), the machine-readable instructions and / or operations 900 return to block 910. Based on (e.g., in response to) the processing circuitry 302 determining that the dwell time has expired (block 912: yes), the machine-readable instructions and / or operations 900 proceed to block 914. In block 914, the processing circuitry 302 determines whether the data exchange on the channel is complete. For example, in block 914, the communications control circuitry 304 determines whether the data exchange on the channel is complete. Based on (e.g., in response to) the processing circuitry 302 determining that the third data exchange on the channel is not complete (block 914: no), the machine-readable instructions and / or operations 900 return to block 910. Based on (eg, in response to) processing circuitry 302 determining that data exchange on the channel is complete (block 914: yes), machine-readable instructions and / or operations 900 proceed to block 916.

[0118] 9 , in block 916, the processing circuitry 302 determines whether to continue operation. For example, in block 916, the communications control circuitry 304 determines whether to continue operation based on whether the child device 300 is powered. Based on (e.g., in response to) the processing circuitry 302 determining that the child device 300 will continue operation (block 916: yes), the machine-readable instructions and / or operations 900 return to block 902. For example, after determining that the child device 300 will continue operation in block 916, the processing circuitry 302 may be configured to place the child device 300 in a sleep mode of operation in block 902. Based on (e.g., in response to) the processing circuitry 302 determining that the child device 300 will not continue operation (block 916: no), the machine-readable instructions and / or operations 900 end.

[0119] 10 is a flowchart representing example machine-readable instructions and / or example operations 1000 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of parent device 200 of FIG. 2 to utilize alternative frequency bands to support parent selection for child devices. The example machine-readable instructions and / or example operations 1000 as described may be performed by a first parent device (e.g., parent device 200) that is initially synchronized with a child device. The example machine-readable instructions and / or example operations 1000 of FIG. 10 begin at block 1002, where processing circuitry 202 determines connectivity criteria for child devices that are synchronized with the first parent device. For example, at block 1002, communication control circuitry 204 determines connectivity criteria for child devices that are synchronized with parent device 200. 10, in block 1002, communications control circuitry 204 determines connectivity criteria for a child device based on communications from the child device in a base frequency band (e.g., a sub-1 GHz frequency band) of parent device 200. Example connectivity criteria include a single strength criterion, an RSSI value, a BER value, and / or an LQI value.

[0120] In the illustrated example of Figure 10, in block 1004, processing circuitry 202 causes the connectivity criterion to be transmitted to a second parent device with which the child device is not synchronized. For example, in block 1004, communications control circuitry 204 causes the connectivity criterion to be transmitted to a second parent device with which the child device is not synchronized. In the example of Figure 10, in block 1004, communications control circuitry 204 causes the connectivity criterion to be transmitted to the second parent device in an alternative frequency band (e.g., the 2.4 GHz frequency band) of parent device 200. In some examples, in block 1004, communications control circuitry 204 includes, along with the connectivity criterion, a request to the second parent device to determine a second connectivity criterion that describes connectivity between the second parent device and the child device. At block 1006, processing circuitry 202 determines whether a first communication has been received (e.g., from a second parent device) indicating that the child device has stronger connectivity to the second parent device than to the first parent device. For example, at block 1006, communication control circuitry 204 determines whether a first communication has been received indicating that the child device has stronger connectivity to the second parent device than to the first parent device. For example, receiver circuitry 216 may receive the first communication in an alternative frequency band (e.g., the 2.4 GHz frequency band) of parent device 200.

[0121] 10 , based on (e.g., in response to) the processing circuit element 202 determining that a first communication has not been received indicating that the child device has stronger connectivity to the second parent device than to the first parent device (block 1006: NO), the machine-readable instructions and / or operations 1000 returns to block 1002. Thus, the first parent device may be configured to maintain synchronization with the child device based on (e.g., in response to) not receiving a response from the second parent device (e.g., within a threshold amount of time). Additionally or alternatively, the first parent device may be configured to maintain synchronization with the child device based on (e.g., in response to) receiving a first communication from the second parent device indicating that the second parent device has poorer connectivity with the child device than the first child device. Based on (e.g., in response to) processing circuit element 202 determining that a first communication has been received indicating that the child device has stronger connectivity to the second parent device than to the first parent device (block 1006: yes), machine-readable instructions and / or operations 1000 proceed to block 1008.

[0122] In the illustrated example of FIG. 10 , in block 1008, the processing circuitry 202 causes a second communication to be transmitted to the child device, the second communication indicating that the child device desynchronizes with the first parent device and synchronizes with the second parent device. For example, in block 1008, the communications control circuitry 204 causes a second communication to be transmitted to the child device indicating that the child device desynchronizes with the first parent device and synchronizes with the second parent device. In the example of FIG. 10 , in block 1008, the communications control circuitry 204 transmits the second communication to the child device in the base frequency band (e.g., sub-1 GHz frequency band) of the parent device 200. In block 1010, the processing circuitry 202 determines whether to continue operation. For example, in block 1010, the communications control circuitry 204 determines whether to continue operation based on whether the parent device 200 is powered. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will continue operation (block 1010: yes), machine-readable instructions and / or operations 1000 return to block 1002. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will not continue operation (block 1010: no), machine-readable instructions and / or operations 1000 end.

[0123] 11 is a flowchart representing example machine-readable instructions and / or example operations 1100 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of parent device 200 of FIG. 2 to use alternative frequency bands to support parent selection for a child device. The example machine-readable instructions and / or example operations 1110 as described may be performed by a second parent device (e.g., parent device 200) that is not initially synchronized with the child device. The example machine-readable instructions and / or example operations 1100 of FIG. 11 begin at block 1102, where interface circuitry 212 receives a first connectivity metric representing first connectivity between a first parent device and a child device synchronized with the first parent device. For example, at block 1102, receiver circuitry 216 receives a first connectivity metric representing first connectivity between the first parent device and a child device synchronized with the first parent device. In the example of FIG. 11, at block 1102, receiver circuitry 216 receives a first connectivity criterion in an alternative frequency band (eg, the 2.4 GHz frequency band) of parent device 200.

[0124] 11 , in block 1104, processing circuitry 202 detects a first communication from a child device at a second parent device, where the child device is desynchronized with the second parent device. For example, in block 1104, communications control circuitry 204 detects a first communication from a child device at a second parent device, where the child device is desynchronized with the second parent device. In the example of FIG. 11 , in block 1106, communications control circuitry 204 detects a first communication from the child device in a base frequency band (e.g., a sub-1 GHz frequency band) of parent device 200. In block 1106, processing circuitry 202 determines a second connectivity criterion for the child device, where the second connectivity criterion represents connectivity between the second parent device and the child device. For example, in block 1106, the communications control circuitry 204 determines a second connectivity criterion for the child device, the second connectivity criterion representing connectivity between the second parent device and the child device. In the example of Figure 11, the communications control circuitry 204 can be configured to determine the second connectivity criterion based on signal strength and / or other characteristics of the first communication detected in block 1104.

[0125] 11 , in block 1108, processing circuitry 202 determines whether the second connectivity between the second parent device and the child device is better than the first connectivity between the first parent device and the child device. For example, in block 1108, communication control circuitry 204 determines whether the second connectivity between the second parent device and the child device is better than the first connectivity between the first parent device and the child device. Based on (e.g., in response to) processing circuitry 202 determining that the second connectivity is not better than the first connectivity (block 1108: NO), machine-readable instructions and / or operations 1100 return to block 1102. For example, based on processing circuitry 202 determining that the second connectivity is not better than the first connectivity, parent device 200 may be configured to refrain from attempting to synchronize with the child device (e.g., for a threshold amount of time). Based on (e.g., in response to) processing circuit element 202 determining that the second connectivity is better than the first connectivity (block 1108: yes), machine-readable instructions and / or operations 1100 proceed to block 1110. For example, based on (e.g., in response to) determining that the second connectivity is better than the first connectivity at blocks 1110, 1112, and 1114, parent device 200 attempts to synchronize with the child device.

[0126] In the illustrated example of Figure 11, at block 1110, processing circuitry 202 causes a second communication to be transmitted to the first parent device indicating that the second parent device has better connectivity with the child device than the first parent device. For example, at block 1110, communications control circuitry 204 causes a second communication to be transmitted to the first parent device indicating that the second parent device has better connectivity with the child device than the first parent device. In the example of Figure 11, at block 1110, communications control circuitry 204 causes the second communication to be transmitted to the first parent device in an alternative frequency band (e.g., the 2.4 GHz frequency band) of parent device 200. In some examples, the second communication transmitted by parent device 200 may include an indication of the second connectivity criterion and / or an identification of the child device.

[0127] In the illustrated example of FIG. 11 , the interface circuitry 212 receives a discovery request from a child device at block 1112. For example, the receiver circuitry 216 receives the discovery request from the child device at block 1112. In the example of FIG. 11 , the receiver circuitry 216 receives the discovery request from the child device at block 1112 in the base frequency band (e.g., sub-1 GHz frequency band) of the parent device 200. In some examples, the discovery request received at block 1112 may include an indication of the first parent device. At block 1114, the processing circuitry 202 transmits a response to the discovery request. For example, the communications control circuitry 204 transmits the response to the discovery request. As described above, the example discovery request identifies a particular channel to which the interface circuitry of the child device will be tuned for a predetermined period of time. Thus, at block 1114, the communications control circuitry 204 transmits the response to the discovery request on the channel identified by the discovery request. For example, the identified channel is in the base frequency band of the parent device 200 (eg, the same band in which the discovery request was received in block 1112).

[0128] 11 , in block 1116, the processing circuitry 202 determines whether to continue operation. For example, in block 1116, the communications control circuitry 204 determines whether to continue operation based on whether the parent device 200 is powered. Based on (e.g., in response to) the processing circuitry 202 determining that the parent device 200 will continue operation (block 1116: yes), the machine-readable instructions and / or operations 1100 return to block 1102. Based on (e.g., in response to) the processing circuitry 202 determining that the parent device 200 will not continue operation (block 1116: no), the machine-readable instructions and / or operations 1100 end.

[0129] 12 is a flowchart representing example machine-readable instructions and / or example operations 1200 that may be executed, instantiated, and / or performed using an example processing circuitry implementation of the child device 300 of FIG. 3 to select a parent device. The example machine-readable instructions and / or example operations 1200 as described may be performed by a child device (e.g., the child device 300). The example machine-readable instructions and / or example operations 1200 of FIG. 12 begin at block 1202, where the interface circuitry 312 receives a communication indicating that a first parent device that is not synchronized with the child device has better connectivity with the child device than a second parent device that is synchronized with the child device. For example, in block 1202, the receiver circuitry 316 receives a communication indicating that a first parent device that is not synchronized with the child device 300 has better connectivity with the child device 300 than a second parent device that is synchronized with the child device 300. In some examples, the communication received at block 1202 may include an indication of the first parent device and / or an indication of one or more connectivity criteria. As described with respect to Figure 10, the child device 300 may receive the communication from a second parent device. Alternatively, in some examples, the child device 300 may receive the communication from the first parent device.

[0130] In the illustrated example of FIG. 12 , the processing circuitry 302 causes a discovery request to be transmitted to the first parent device at block 1204. For example, the communications control circuitry 304 causes the discovery request to be transmitted to the first parent device at block 1204. In some examples, the discovery request may include an indication of a second parent device and / or an indication of connectivity criteria. In the example of FIG. 12 , the communications control circuitry 304 causes the discovery request to be transmitted in the base frequency band at block 1204. The example discovery request identifies a particular channel to which the interface circuitry 312 of the child device 300 is tuned for a predetermined period of time. At block 1206, the interface circuitry 312 receives a response to the discovery request from the first parent device. For example, at block 1206, the receiver circuitry 316 receives a response to the discovery request from the first parent device. In the example of FIG. 12, in block 1206, receiver circuitry 316 receives a response to the discovery request in the base frequency band (eg, the same band in which the discovery request was transmitted in block 1204).

[0131] 12 , in block 1208, the processing circuitry 302 determines whether to continue operation. For example, in block 1208, the communications control circuitry 304 determines whether to continue operation based on whether the child device 300 is powered. Based on (e.g., in response to) the processing circuitry 302 determining that the child device 300 will continue operation (block 1208: yes), the machine-readable instructions and / or operations 1200 return to block 1202. Based on (e.g., in response to) the processing circuitry 302 determining that the child device 300 will not continue operation (block 1208: no), the machine-readable instructions and / or operations 1200 end.

[0132] As illustrated in FIGS. 10-12, a parent device can improve network operation because the parent device supports multiple frequency bands. In this manner, using the 2.4 GHz frequency band, the parent device can exchange information about child devices and / or other network details that are useful for operation in a sub-1 GHz network. For example, a first parent device (e.g., a first dual-band router 104) can exchange information about the child devices and / or other network details that are useful for operation in a sub-1 GHz network. A ) reports to other parent devices (e.g., the second dual-band router 104) for any other device's transmissions that the first parent device hears in the sub-1 GHz frequency band, along with the received connectivity metrics for the device's transmissions (e.g., RSSI values, BER values, and / or LQI values). B ) to the second parent device. Thus, if the first parent device identifies a synchronized child device having a first connectivity metric worse than the second connectivity metric between the synchronized child device and the second parent device, the first parent device can inform the synchronized child device of the availability of the second parent device. Additionally or alternatively, if the first parent device identifies that the first connectivity metric corresponding to the child device and reported by the second parent device to the first parent device is better than the second connectivity metric between the child device and the second parent device (the second parent device is synchronized with the child device), the first parent device can inform the second parent device that the child device has stronger connectivity to the first parent device than to the second parent device. Thus, the second parent device can inform the child device of the availability of the first parent device. After the child device is informed of the availability of another parent device that has stronger connectivity with the child device, it can initiate a new discovery request that the child device can target and join if it chooses.

[0133] Figure 13 is a block diagram of an example processing circuitry platform 1300 including processing circuitry configured to execute, instantiate, and / or perform the example machine-readable instructions and / or example operations of Figures 6, 7, 10, and / or 11 for implementing parent device 200 of Figure 2. Processing circuitry platform 1300 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad®), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing and / or electronic device.

[0134] The processing circuitry platform 1300 of the illustrated example includes processing circuitry 1312. The processing circuitry 1312 of the illustrated example is hardware. For example, the processing circuitry 1312 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processing circuitry 1312 can also be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processing circuitry 1312 implements the example communications control circuitry 204, the example channel timing circuitry 206, and the example counter circuitry 208.

[0135] The processing circuitry 1312 of the illustrated example includes local memory 1313 (e.g., cache, registers, etc.). The processing circuitry 1312 of the illustrated example communicates with main memory 1314, 1316, including volatile memory 1314 and non-volatile memory 1316, via bus 1318. The volatile memory 1314 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1316 may be implemented by flash memory and / or any other type of memory device. In this example, one or more of the volatile memory 1314 or non-volatile memory 1316 implements the example memory 218. Access to the main memory 1314, 1316 of the illustrated example is controlled by a memory controller 1317. In some examples, the memory controller 1317 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit elements for managing the flow of data to and from the main memories 1314, 1316.

[0136] The processing circuitry platform 1300 of the depicted example also includes interface circuitry 1320. The interface circuitry 1320 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0137] In the depicted example, one or more input devices 1322 are coupled to the interface circuitry 1320. The input devices 1322 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the processing circuitry 1312. The input devices 1322 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0138] One or more output devices 1324 are also connected to the interface circuitry 1320 of the illustrated example. The output device(s) 1324 may be implemented, for example, by a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1320 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or graphics processor circuitry such as a GPU.

[0139] The interface circuitry 1320 of the depicted example also includes a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface to facilitate the exchange of data with external equipment (e.g., any type of computing device) over a network 1326. Communication may be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a non-line-of-sight wireless system, a line-of-sight wireless system, a cellular system, an optical connection, etc. In this example, the interface circuitry 1320 implements the example antenna 210, the example transmitter circuitry 214, and the example receiver circuitry 216.

[0140] The processing circuitry platform 1300 of the depicted example also includes one or more mass storage disks or devices 1328 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1328 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0141] The machine-readable instructions 1332, which may be implemented by the machine-readable instructions of Figures 6, 7, 10, and / or 11, may be stored in mass storage device 1328, in volatile memory 1314, in non-volatile memory 1316, and / or at least one non-transitory computer-readable storage medium, such as a CD or DVD, which may be removable.

[0142] Figure 14 is a block diagram of an example processing circuitry platform 1400 configured to execute, instantiate, and / or perform the example machine-readable instructions and / or the example operations of Figures 8, 9, and / or 12 to implement child device 300 of Figure 3. Processing circuitry platform 1400 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad®), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing and / or electronic device.

[0143] The processing circuitry platform 1400 of the illustrated example includes processing circuitry 1412. The processing circuitry 1412 of the illustrated example is hardware. For example, the processing circuitry 1412 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processing circuitry 1412 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processing circuitry 1412 implements the example communications control circuitry 304, the example channel timing circuitry 306, and the example counter circuitry 308.

[0144] The processing circuitry 1412 of the illustrated example includes local memory 1413 (e.g., cache, registers, etc.). The processing circuitry 1412 of the illustrated example communicates with main memory 1414, 1416, which includes volatile memory 1414 and non-volatile memory 1416, via bus 1418. The volatile memory 1414 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1416 may be implemented by flash memory and / or any other type of memory device. In this example, one or more of the volatile memory 1414 or non-volatile memory 1416 implements the example memory 318. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit elements for managing the flow of data to and from the main memories 1414, 1416.

[0145] The processing circuitry platform 1400 of the depicted example also includes interface circuitry 1420. The interface circuitry 1420 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0146] In the depicted example, one or more input devices 1422 are coupled to the interface circuitry 1420. The input devices 1422 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the processing circuitry 1412. The input devices 1422 may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0147] One or more output devices 1424 are also connected to the interface circuitry 1420 of the illustrated example. The output device(s) 1424 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1420 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or graphics processor circuitry such as a GPU.

[0148] The interface circuitry 1420 of the depicted example also includes a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, and / or network interface to facilitate the exchange of data with external equipment (e.g., any type of computing device) over a network 1426. Communication may be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a non-line-of-sight wireless system, a line-of-sight wireless system, a cellular system, an optical connection, etc. In this example, the interface circuitry 1420 implements an example antenna 310, an example transmitter circuitry 314, and an example receiver circuitry 316.

[0149] The processing circuitry platform 1400 of the depicted example also includes one or more mass storage disks or devices 1428 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0150] The machine-readable instructions 1432, which may be implemented by the machine-readable instructions of Figures 8, 9, and / or 12, may be stored in and retrievable from the mass storage device 1428, the volatile memory 1414, the non-volatile memory 1416, and / or at least one non-transitory computer-readable storage medium, such as a CD or DVD.

[0151] FIG. 15 is a block diagram of an example implementation of processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14. In this example, processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14 are implemented by a microprocessor 1500. For example, microprocessor 1500 may be a general-purpose microprocessor (e.g., general-purpose microprocessor circuitry). Microprocessor 1500 executes some or all of the machine-readable instructions of the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12 to effectively instantiate the circuit elements of FIGS. 2 and / or 3 as logic circuits to perform operations corresponding to those machine-readable instructions. In some such examples, the circuit elements of FIGS. 2 and / or 3, in combination with machine-readable instructions, are instantiated by hardware circuitry of microprocessor 1500. For example, microprocessor 1500 may be implemented by a multi-core hardware circuit such as a CPU, DSP, GPU, XPU, etc. While it may include any number of exemplary cores 1502 (e.g., one core), the microprocessor 1500 in this example is a multi-core semiconductor device including N cores. The cores 1502 of the microprocessor 1500 may operate independently or cooperate to execute machine-readable instructions. For example, a firmware program, an embedded software program, or machine code corresponding to a software program may be executed by one of the cores 1502 or may be executed at the same or different times by multiple cores 1502. In some examples, the firmware program, the embedded software program, or the machine code corresponding to the software program is divided into threads and executed in parallel by two or more cores 1502. The software program may correspond to some or all of the machine-readable instructions and / or operations represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12.

[0152] The cores 1502 may communicate via a first exemplary bus 1504. In some examples, the first bus 1504 may be implemented by a communication bus to enable communications associated with one (or more) of the cores 1502. For example, the first bus 1504 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1504 may be implemented by any other type of computing or electrical bus. The cores 1502 may obtain data, instructions, and / or signals from one or more external devices via the exemplary interface circuitry 1506. The cores 1502 may output data, instructions, and / or signals to one or more external devices via the exemplary interface circuitry 1506. The cores 1502 in this example include an exemplary local memory 1520 (e.g., a level 1 (L1) cache that may be divided into an L1 data cache and an L1 instruction cache), but the microprocessor 1500 also includes an exemplary shared memory (e.g., a level 2 (L2) cache) that may be shared by the cores for fast access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1510. The local memory 1520 of each of the cores 1502 and the shared memory 1510 may be part of a hierarchy of storage devices that includes multiple levels of cache memory and main memory (e.g., main memories 1314, 1316 of FIG. 13 and / or main memories 1414, 1416 of FIG. 14). Typically, memories at higher levels in the hierarchy exhibit slower access times and have smaller storage capacities than memories at lower levels. Changes at various levels of the cache hierarchy are governed (eg, coordinated) by a cache coherency policy.

[0153] Each core 1502 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1502 includes a control unit circuitry 1514, an arithmetic logic (AL) circuitry 1516 (sometimes referred to as an ALU), multiple registers 1518, a local memory 1520, and a second exemplary bus 1522. Other structures may also exist. For example, each core 1502 may include a vector unit circuitry, a single instruction multiple data (SIMD) unit circuitry, a load / store unit (LSU) circuitry, a branch / jump unit circuitry, a floating point unit (FPU) circuitry, etc. The control unit circuitry 1514 includes semiconductor-based circuitry configured to control (e.g., coordinate) data movement within the corresponding core 1502. The AL circuitry 1516 includes semiconductor-based circuitry configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1502. In some examples, the AL circuit elements 1516 perform integer-based operations. In other examples, the AL circuit elements 1516 also perform floating-point operations. In yet other examples, the AL circuit elements 1516 may include a first AL circuit element that performs integer-based operations and a second AL circuit element that performs floating-point operations. In some examples, the AL circuit elements 1516 may be referred to as an arithmetic logic unit (ALU).

[0154] The registers 1518 are semiconductor-based structures for storing data and / or instructions, such as results of one or more operations performed by the AL circuit elements 1516 of the corresponding core 1502. For example, the registers 1518 may include vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1518 may be organized into banks as shown in FIG. 15 . Alternatively, the registers 1518 may be organized in any other arrangement, format, or structure, such as by being distributed across the cores 1502 to reduce access time. The second bus 1522 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0155] Each core 1502, and / or more generally, microprocessor 1500, may include additional and / or alternative structure to that shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common mesh stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuit elements may be present. Microprocessor 1500 is a semiconductor device fabricated to include many transistors interconnected to implement the above structure in one or more integrated circuits (ICs) contained in one or more packages.

[0156] Microprocessor 1500 may include and / or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented with logic circuitry to perform certain tasks more quickly and / or efficiently than by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. Accelerators may be integrated into microprocessor 1500, may be in the same chip package as microprocessor 1500, and / or may be in one or more packages separate from microprocessor 1500.

[0157] FIG. 16 is a block diagram of another example implementation of processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14. In this example, processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14 are implemented by FPGA circuit element 1600. For example, FPGA circuit element 1600 may be implemented by an FPGA. FPGA circuit element 1600 may be used to perform operations that may otherwise be performed, for example, by example microprocessor 1500 of FIG. 15 executing corresponding machine-readable instructions. However, once configured, FPGA circuit element 1600 instantiates in hardware the operations and / or functions corresponding to the machine-readable instructions and is therefore often able to perform the operations / functions faster than could be performed by a general-purpose microprocessor executing corresponding software.

[0158] More specifically, in contrast to microprocessor 1500 of FIG. 15 above (which is a general-purpose device that is programmed to execute some or all of the machine-readable instructions represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12, but whose interconnections and logic circuitry are fixed once manufactured), example FPGA circuitry 1600 of FIG. 16 includes interconnections and logic circuitry that may be configured, structured, programmed, and / or interconnected in different ways after manufacture, e.g., to instantiate some or all of the operations / functions corresponding to the machine-readable instructions represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12. In particular, FPGA circuitry 1600 may be envisioned as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuitry 1600 is reprogrammed). The configured logic circuits allow the logic gates to cooperate in different ways to perform different operations on data received by the input circuitry. These operations may correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12. In this manner, FPGA circuitry 1600 can be configured and / or structured to effectively instantiate some or all of the operations / functions corresponding to the machine-readable instructions of the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12 as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner similar to an ASIC. Thus, FPGA circuitry 1600 may perform operations / functions corresponding to some or all of the machine-readable instructions of Figures 6, 7, 8, 9, 10, 11, and / or 12 faster than a general-purpose microprocessor can perform the same.

[0159] In the example of FIG. 16 , FPGA circuit element 1600 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in the HDL, the code / program may be translated into a lower-level language as needed, and the code / program (e.g., the code / program in the lower-level language) may be converted into a binary file (e.g., by a compiler, a software application, etc.). In some examples, FPGA circuit element 1600 of FIG. 16 may access and / or load a binary file to configure and / or structure FPGA circuit element 1600 of FIG. 16 to perform one or more operations / functions. For example, a binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to the FPGA circuit element 1600 of FIG. 16 to cause the FPGA circuit element 1600 of FIG. 16, or a portion thereof, to be configured and / or structured.

[0160] In some examples, the binary file is compiled, generated, translated, and / or otherwise output from a uniform software platform utilized to program the FPGA. For example, the uniform software platform may translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, translated, and / or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuit element 1600 of FIG. 16 may be configured and / or structured to access and / or load a binary file such that the FPGA circuit element 1600 of FIG. 16 performs one or more operations / functions. For example, a binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to the FPGA circuit element 1600 of FIG. 16 to configure and / or structure the FPGA circuit element 1600 of FIG. 16 or portions thereof.

[0161] The FPGA circuit element 1600 of FIG. 16 includes example input / output (I / O) circuit element 1602 for obtaining and / or outputting data from example configuration circuit element 1604 and / or external hardware 1606. For example, the configuration circuit element 1604 may be implemented by interface circuit element that may obtain a bitstream, data, and / or a binary file that may be embodied with machine-readable instructions to configure the FPGA circuit element 1600 or a portion thereof. In some such examples, the configuration circuit element 1604 may obtain the binary file from a user, a machine (hardware circuit element (e.g., programmable or dedicated circuit element) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file), etc., and / or any combination thereof. In some examples, the external hardware 1606 may be implemented by external hardware circuit element. For example, the external hardware 1606 may be implemented by the microprocessor 1500 of FIG. 15.

[0162] The FPGA circuit element 1600 also includes an array of example logic gate circuit elements 1608, a plurality of example configurable interconnects 1610, and example storage circuit elements 1612. The logic gate circuit elements 1608 and the configurable interconnects 1610 are configurable to instantiate one or more operations / functions that may correspond to at least some of the machine-readable instructions of FIGS. 6, 7, 8, 9, 10, 11, and / or 12 and / or other desired operations. The logic gate circuit elements 1608 shown in FIG. 16 are fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide the basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuit elements 1608, allowing configuration of the electrical structures and / or logic gates to form circuits to perform desired operations / functions. The logic gate circuitry 1608 may include other electrical structures such as look-up tables (LUTs), registers (eg, flip-flops or latches), multiplexers, and the like.

[0163] The configurable interconnect 1610 in the depicted example is a conductive path, trace, via, etc. that may include electrically controllable switches (e.g., transistors) that can change their state by being programmed to activate or deactivate one or more connections between one or more logic gate circuit elements 1608 to program a desired logic circuit.

[0164] The storage circuit elements 1612 in the illustrated example are structured to store the results of one or more operations performed by the corresponding logic gates. The storage circuit elements 1612 may be implemented by registers, etc. In the illustrated example, the storage circuit elements 1612 are distributed among the logic gate circuit elements 1608 to facilitate access and increase execution speed.

[0165] The example FPGA circuitry 1600 of FIG. 16 also includes example dedicated operation circuitry 1614. In this example, the dedicated operation circuitry 1614 includes dedicated circuitry 1616 that may be provided to implement commonly used functions to avoid the need to program those functions in the art. Examples of such dedicated circuitry 1616 include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiply-accumulator circuitry. Other types of dedicated circuitry may also be present. In some examples, the FPGA circuitry 1600 may also include example general-purpose programmable circuitry 1618, such as an example CPU 1620 and / or an example DSP 1622. Other general-purpose programmable circuitry 1618 may additionally or alternatively be present, such as a GPU, XPU, etc., that may be programmed to perform other operations.

[0166] 15 and 16 illustrate two example implementations of processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14, many other approaches are contemplated. For example, the FPGA circuit element may include an on-board CPU, such as one or more of example CPUs 1620 of FIG. 16. Thus, processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14 may additionally be implemented by combining at least example microprocessor 1500 of FIG. 15 and example FPGA circuit element 1600 of FIG. 16. In some such hybrid examples, one or more cores 1502 of FIG. 15 may execute a first portion of the machine-readable instructions represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12 to perform a first operation / function, the FPGA circuitry 1600 of FIG. 16 may be configured and / or structured to perform a second operation / function corresponding to a second portion of the machine-readable instructions represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12, and / or the ASIC may be configured and / or structured to perform a third operation / function corresponding to a third portion of the machine-readable instructions represented by the flowcharts of FIGS. 6, 7, 8, 9, 10, 11, and / or 12.

[0167] Therefore, it should be understood that some or all of the circuit elements of Figures 2 and / or 3 may be instantiated at the same or different times. For example, the same and / or different portions of microprocessor 1500 of Figure 15 may be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, the same and / or different portions of FPGA circuit elements 1600 of Figure 16 may be configured and / or structured to perform operations / functions corresponding to portions of the machine-readable instructions at the same and / or different times.

[0168] In some examples, some or all of the circuit elements of Figures 2 and / or 3 may be instantiated, for example, in one or more threads that execute simultaneously and / or sequentially. For example, microprocessor 1500 of Figure 15 may execute machine-readable instructions in one or more threads that execute simultaneously and / or sequentially. In some examples, FPGA circuit elements 1600 of Figure 16 may be configured and / or structured to perform operations / functions simultaneously and / or sequentially. Also, in some examples, some or all of the circuit elements of Figures 2 and / or 3 may be implemented within one or more virtual machines and / or containers that execute on microprocessor 1500 of Figure 15.

[0169] In some examples, processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14 may be in one or more packages. For example, processing circuit element 1500 of FIG. 15 and / or processing circuit element 1600 of FIG. 16 may be in one or more packages. In some examples, processing circuit element 1312 of FIG. 13 and / or processing circuit element 1412 of FIG. 14 may implement an XPU, which may be in one or more packages. For example, an XPU may include a CPU (e.g., microprocessor 1500 of FIG. 15, CPU 1620 of FIG. 16, etc.) in one package, a DSP (e.g., DSP 1622 of FIG. 16) in another package, a GPU in yet another package, and an FPGA (e.g., FPGA circuit element 1600 of FIG. 16) in yet yet another package.

[0170] FIG. 17 illustrates a block diagram of an example software distribution platform 1705 for distributing software, such as the example machine-readable instructions 1332 of FIG. 13 and / or the example machine-readable instructions 1432 of FIG. 14 , to other hardware devices (e.g., hardware devices owned and / or operated by a third party from the owner and / or operator of the software distribution platform). The example software distribution platform 1705 may be implemented by any computer server, data facility, cloud service, etc. that may store and transmit software to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 1705. For example, the entity that owns and / or operates the software distribution platform 1705 may be the developer, distributor, and / or licensor of software, such as the example machine-readable instructions 1332 of FIG. 13 and / or the example machine-readable instructions 1432 of FIG. 14 . The third party may be a consumer, user, wholesaler, OEM, etc. that has purchased the software and / or licenses the software for use and / or resale and / or sublicensing. In the illustrated example, the software distribution platform 1705 includes one or more servers and one or more storage devices. The storage devices store machine-readable instructions 1332 and / or machine-readable instructions 1432, which may correspond to the machine-readable instructions of FIGS. 6, 7, 8, 9, 10, 11, and / or 12, as described above. The one or more servers of the example software distribution platform 1705 are in communication with an example network 1710, which may correspond to the Internet and / or any one or more of the example networks described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for delivery, sale, and / or licensing of the software may be handled by the one or more servers of the software distribution platform and / or by a third-party payment entity.The server enables purchasers and / or licensees to download machine-readable instructions 1332 and / or machine-readable instructions 1432 from software distribution platform 1705. For example, software that may correspond to the example machine-readable instructions of Figures 6, 7, 10, and / or 11 may be downloaded to example processing circuitry platform 1300, which is for executing machine-readable instructions 1332 to implement parent device 200. Also, software that may correspond to the example machine-readable instructions of Figures 8, 9, and / or 12 may be downloaded to example processing circuitry platform 1400, which is for executing machine-readable instructions 1432 to implement child device 300. In some examples, one or more servers of software distribution platform 1705 periodically provide, transmit, and / or force updates to the software (e.g., example machine-readable instructions 1332 of FIG. 13 and / or example machine-readable instructions 1432 of FIG. 14) to ensure that improvements, patches, updates, etc. are distributed and applied to the software on end-user devices. Although referred to above as software, the "software" distributed may alternatively be firmware.

[0171] In this description, the term "and / or" (when used in the form of A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as (a) A alone, (b) B alone, (c) C alone, (d) A and B, (e) A and C, (f) B and C, and (g) A, B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to implementations that include any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0172] The term "couple" is used throughout the specification. This term may encompass connection, communication, or signal path that allows for a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal provided by device A, where intervening component C does not substantially change the functional relationship between device A and device B.

[0173] Numerical identifiers such as "first," "second," "third," etc. are merely used to distinguish between elements of substantially the same type in terms of structure and / or function. As used in the detailed description, these identifiers do not necessarily parallel those used in the claims.

[0174] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0175] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably and, unless specifically stated to the contrary, are used generally to refer to an interconnection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0176] A circuit or device described herein as including certain components may instead be adapted to be combined with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements (e.g., a semiconductor die and / or integrated circuit (IC) package) within a single physical device and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0177] Circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. A component depicted as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor, unless otherwise noted. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor. While some elements in the described examples are included in an integrated circuit and others are external to the integrated circuit, in other illustrative embodiments, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features depicted as being external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) integrated in / on a semiconductor substrate, (2) integrated in a single semiconductor package, (3) integrated in the same module, and / or (4) integrated in / on the same printed circuit board.

[0178] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value, or, if the value is zero, a reasonable range around zero.

[0179] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0180] From the foregoing, it should be appreciated that exemplary systems, apparatus, articles of manufacture, and methods are described that enable channel hopping across different frequency bands. Additionally, the exemplary systems, apparatus, articles of manufacture, and methods described herein reduce the computational overhead utilized to synchronize devices within a network. For example, the exemplary child device described herein tracks synchronization information of a parent device, and the exemplary parent device does not track synchronization information of other devices. The examples described herein also enable channel hopping on CSL-compatible devices. The described systems, apparatus, articles of manufacture, and methods improve the efficiency of using computing devices by improving the strength of connectivity between parent and child devices. For example, the described systems, apparatus, articles of manufacture, and methods improve the efficiency of using computing devices by supporting better parent selection and lower synchronization overhead. Accordingly, the described systems, apparatus, articles of manufacture, and methods are directed to one or more improvements in the operation of machines, such as computers or other electronic and / or mechanical devices.

[0181] The following claims are incorporated into this detailed description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been described herein, the scope of coverage of this application is not limited thereto. Rather, this application covers all systems, apparatus, articles of manufacture, and methods that fairly fall within the scope of the claims of this application.

Claims

1. A device for improving the performance of a network operating in multiple frequency bands, Interface circuit elements and, A memory configured to store machine-readable instructions, A processing circuit element configured to perform at least one of the instantiation or execution of the machine-readable instruction, Determine the first connectivity criterion for the first device that synchronizes with the second device. The interface circuit element causes the first device to transmit the first connectivity standard in the first radio frequency (RF) band to a third device that is not synchronized. Based on the first communication from the third device, a second communication is transmitted to the first device in a second RF band having a lower frequency than the first RF band in order to synchronize the first device with the third device. The processing circuit element is configured as follows: A device including a device.

2. The apparatus according to claim 1, The apparatus further comprises a processing circuit element configured to determine whether the first communication indicates that the first device has stronger connectivity with the third device than the second device.

3. The apparatus according to claim 1, The processing circuit element is further configured to determine a second connectivity criterion for a fourth device, The fourth device is not synchronized with the second device. An apparatus in which the second connectivity criterion represents the connectivity strength between the second device and the fourth device.

4. The apparatus according to claim 3, The processing circuit element is further configured to determine, based on the second connectivity criterion and the third connectivity criterion, whether the fourth device has stronger connectivity to the second device than the fifth device. The fourth device is synchronized with the fifth device, An apparatus in which the third connectivity criterion represents the connectivity strength between the fifth device and the fourth device.

5. The apparatus according to claim 3, The processing circuit element is further configured to transmit the third communication to the fifth device based on the fact that the fourth device has stronger connectivity with the second device than the fifth device. The fourth device is synchronized with the fifth device, An apparatus configured to determine whether the third communication indicates that the fourth device has stronger connectivity with the second device than the fifth device.

6. The apparatus according to claim 1, An apparatus in which the first connectivity criterion includes at least one of a received signal strength index, a bit error rate, or a link quality index.

7. The apparatus according to claim 1, An apparatus in which the first RF band includes a frequency band of 2.4 GHz, and the second RF band includes a frequency band of sub-1 GHz.

8. The apparatus according to claim 1, An apparatus in which the separation between the first RF band and the second RF band is greater than 1 GHz.

9. A non-temporary machine-readable storage medium containing instructions, wherein the instructions are provided to a processing circuit element, at least Determine the first connectivity criterion for the first device that is synchronized with the second device. The first device transmits the first connectivity standard in the first radio frequency (RF) band to a third device that is not synchronized. A non-temporary machine-readable storage medium that transmits a second communication to the first device in a second RF band having a lower frequency than the first RF band, in order to synchronize the first device with the third device based on a first communication from the third device.

10. A non-temporary machine-readable storage medium according to claim 9, A non-temporary machine-readable storage medium, wherein the instruction further causes the processing circuit element to determine whether the first communication indicates that the first device has stronger connectivity with the third device than the second device.

11. A non-temporary machine-readable storage medium according to claim 9, The instruction further causes the processing circuit element to determine a second connectivity criterion for the fourth device. The fourth device is not synchronized with the second device. A non-transient machine-readable storage medium in which the second connectivity criterion represents the strength of connectivity between the second device and the fourth device.

12. A non-temporary machine-readable storage medium according to claim 11, The instruction further causes the processing circuit element to determine, based on the second connectivity criterion and the third connectivity criterion, whether the fourth device has stronger connectivity to the second device than the fifth device. The fourth device is synchronized with the fifth device, A non-transient machine-readable storage medium in which the third connectivity criterion represents the strength of connectivity between the fifth device and the fourth device.

13. A non-temporary machine-readable storage medium according to claim 11, The instruction further causes the processing circuit element to transmit a third communication to the fifth device based on the fact that the fourth device has stronger connectivity with the second device than the fifth device. The fourth device is synchronized with the fifth device, A non-temporary machine-readable storage medium in which the third communication indicates that the fourth device has stronger connectivity with the second device than the fifth device.

14. A non-temporary machine-readable storage medium according to claim 9, A non-transient machine-readable storage medium in which the first connectivity criterion includes at least one of received signal strength, bit error rate, or link quality index.

15. A method for improving the performance of a network operating in multiple frequency bands, The process involves executing instructions using processing circuit elements to determine a first connectivity criterion for a first device that is synchronized with a second device, The first device transmits the first connectivity standard in the first radio frequency (RF) band to a third device that is not synchronized with it. Based on the first communication from the third device, a second communication is transmitted to the first device in a second RF band having a lower frequency than the first RF band in order to synchronize the first device with the third device. Methods that include...

16. The method according to claim 15, A method further comprising determining whether the first communication indicates that the first device has stronger connectivity with the third device than the second device.

17. The method according to claim 15, Further including determining a second connectivity criterion for a fourth device that is not synchronized with the second device, A method wherein the second connectivity criterion represents the strength of connectivity between the second device and the fourth device.

18. The method according to claim 17, The method further includes determining, based on the second connectivity criterion and the third connectivity criterion, whether the fourth device has stronger connectivity to the second device than the fifth device. The fourth device is synchronized with the fifth device, A method wherein the third connectivity criterion represents the strength of connectivity between the fifth device and the fourth device.

19. The method according to claim 17, The third communication is further transmitted to the fifth device based on the fact that the fourth device has stronger connectivity with the second device than the fifth device. The fourth device is synchronized with the fifth device, A method for demonstrating that the third communication has stronger connectivity with the second device than the fifth device.

20. The method according to claim 15, A method wherein the first RF band includes a frequency band of 2.4 GHz, and the second RF band includes a frequency band of sub-1 GHz.

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