Power converter

Abstract

To provide a power converter which suppresses power loss due to a rectifying element.SOLUTION: The power converter 10 includes the conversion circuit 30 that converts a DC voltage from the DC power source 12 into a volts alternating current, the transformer 34 that steps up and down the volts alternating current, the rectifier elements 41 and 42 that are transistors and rectify the volts alternating current stepped up and down by the transformer 34, the detection circuit 72 that detects a transformer voltage that is a voltage between the transformer 34 and the rectifier elements 41 and 42, and the control unit 74 that turns off the rectifier elements 41 and 42 in an ON state based on the transformer voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to power converters. [Background technology]

[0002] As described in Patent Document 1, a DC-DC converter is known that generates a drive signal for a rectifying switching element in a synchronous rectifier circuit by predicting the secondary current from the primary current and controlling the off timing according to the predicted current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-116016 Summary of the Invention [Problem to be solved by the invention]

[0004] In a DC-DC converter such as that described in Patent Document 1, current flows through the primary-side transformer, as well as through the coil connected to the transformer and the transformer's parasitic inductance. Furthermore, due to manufacturing variations in coils and transformers, there are variations in characteristics such as reactance. This causes variations in the primary-side current between DC-DC converters. This reduces the accuracy of predicting the secondary-side current. This also causes variations in the off-timing corresponding to the predicted current. Therefore, in a DC-DC converter such as that described in Patent Document 1, there is a large variation in the power loss due to the rectifying switching elements. Therefore, in a DC-DC converter such as that described in Patent Document 1, there is a large variation in the power loss due to the rectifying switching elements.

[0005] An object of the present disclosure is to provide a power converter that suppresses power loss due to rectifying elements. [Means for solving the problem]

[0006] The invention described in claim 1 is a power converter including a conversion unit (30) that converts a DC voltage from a DC power supply (12) into an AC voltage, a transformer (34) that steps up or down the AC voltage, rectifying elements (41, 42) that are transistors that rectify the current of the AC voltage stepped up or down by the transformer, a detection unit (72) that detects transformer voltages (Vt1, Vt2) that are voltages between the transformer and the rectifying elements, and a control unit (74) that turns off the rectifying elements that are in an on state based on the transformer voltage.

[0007] As a result, the rectifying elements in the ON state are turned off without using the current flowing through the primary side corresponding to the portion between the conversion unit and the transformer. Therefore, the influence of variations in the current flowing through the primary side is suppressed, and the rectifying elements in the ON state are turned off. Therefore, variations in the turn-off timing of the rectifying elements in the ON state are suppressed. Furthermore, by using the voltage between the transformer and the rectifying elements, the power loss period for the rectifying elements can be shortened and the rectifying elements can be turned off. Therefore, the power loss period can be shortened while suppressing variations in the turn-off timing of the rectifying elements in the ON state. Therefore, power loss by the rectifying elements is suppressed.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a power converter according to a first embodiment. [Figure 2] FIG. 1 is a configuration diagram of a detection circuit in a power converter. [Figure 3] 4 is a time chart showing the operation of the power converter. [Figure 4] Circuit showing current flow when the power converter is operating. [Figure 5] Circuit showing current flow when the power converter is operating. [Figure 6]Circuit showing current flow when the power converter is operating. [Figure 7] Circuit showing current flow when the power converter is operating. [Figure 8] Circuit showing current flow when the power converter is operating. [Figure 9] Circuit showing current flow when the power converter is operating. [Figure 10] 4 is a flowchart showing the processing of a control circuit in the power converter. [Figure 11] 4 is a time chart for explaining the processing of a control circuit. [Figure 12] 10 is a flowchart showing the processing of a control circuit in a power converter according to a second embodiment. [Figure 13] 4 is a time chart for explaining the processing of a control circuit. [Figure 14] 10 is a time chart for explaining the processing of a control circuit in a power converter according to a third embodiment. [Figure 15] 4 is a time chart for explaining the processing of a control circuit. [Figure 16] 10 is a time chart for explaining the processing of a control circuit in a power converter according to a fourth embodiment. [Figure 17] 4 is a time chart for explaining the processing of a control circuit. [Figure 18] 10 is a flowchart showing the processing of a control circuit in a power converter according to a fifth embodiment. [Figure 19] 10 is a flowchart showing the processing of a control circuit in a power converter according to a sixth embodiment. [Figure 20] 13 is a time chart for explaining the processing of a control circuit in a power converter according to a seventh embodiment. [Figure 21] FIG. 13 is a circuit diagram of a power converter according to an eighth embodiment. [Figure 22] FIG. 13 is a circuit diagram of a power converter according to a ninth embodiment. [Figure 23] FIG. 23 is a circuit diagram of a power converter according to a tenth embodiment. [Figure 24] FIG. 23 is a circuit diagram of a power converter according to an eleventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals, and description thereof will be omitted.

[0011] (First embodiment) The power converter of this embodiment is, for example, a DC-DC converter for a vehicle, and suppresses power loss due to rectifying elements. Specifically, as shown in Fig. 1, the power converter 10 includes a DC power supply 12, a main circuit 20, and a sub-circuit 70.

[0012] The DC power supply 12 is connected to a main circuit 20 (described later) and applies a relatively high DC voltage to the main circuit 20.

[0013] The main circuit 20 has a positive input terminal 24, a negative input terminal 26, an input capacitor 28, a conversion circuit 30, a magnetic component 32, a transformer 34, a first rectifying element 41, a first element adjusting resistor 51, a second rectifying element 42, and a second element adjusting resistor 52. The main circuit 20 also has an output capacitor 54, a choke coil 56, a filter 58, an output terminal 60, a main circuit ground terminal 62, and a main circuit ground 64.

[0014] The positive input terminal 24 is connected to the positive electrode of the DC power supply 12. The negative input terminal 26 is connected to the negative electrode of the DC power supply 12.

[0015] One end of the input capacitor 28 is connected to the positive input terminal 24. The other end of the input capacitor 28 is connected to the negative input terminal 26. Furthermore, the input capacitor 28 smoothes the DC voltage applied from the DC power supply 12 to the main circuit 20.

[0016] The conversion circuit 30 corresponds to a conversion unit, and is connected to one end and the other end of the input capacitor 28, and is also connected in parallel to the DC power supply 12. The conversion circuit 30 is, for example, a full-bridge inverter circuit. Therefore, the conversion circuit 30 includes a first transistor 301, a second transistor 302, a third transistor 303, and a fourth transistor 304. The conversion circuit 30 also includes a first adjustment resistor 311, a second adjustment resistor 312, a third adjustment resistor 313, and a fourth adjustment resistor 314.

[0017] The first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304 are transistors such as FETs. The first transistor 301 and the third transistor 303 are connected in series and in parallel to the DC power supply 12. The second transistor 302 and the fourth transistor 304 are connected in series and in parallel to the DC power supply 12. The first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304 are turned on and off based on a signal from a drive circuit 76, which will be described later. This converts the DC voltage from the DC power supply 12 into an AC voltage.

[0018] One end of the first adjusting resistor 311 is connected to the gate electrode of the first transistor 301. The first adjusting resistor 311 adjusts the voltage applied to the gate electrode of the first transistor 301.

[0019] One end of the second adjusting resistor 312 is connected to the gate electrode of the second transistor 302. Furthermore, the second adjusting resistor 312 adjusts the voltage applied to the gate electrode of the second transistor 302.

[0020] One end of the third adjusting resistor 313 is connected to the gate electrode of the third transistor 303. The third adjusting resistor 313 adjusts the voltage applied to the gate electrode of the third transistor 303.

[0021] One end of the fourth adjustment resistor 314 is connected to the gate electrode of the fourth transistor 304. Furthermore, the fourth adjustment resistor 314 adjusts the voltage applied to the gate electrode of the fourth transistor 304.

[0022] The magnetic component 32 is, for example, a coil. One end of the magnetic component 32 is connected to the conversion circuit 30. The other end of the magnetic component 32 is connected to a transformer 34, which will be described later. Therefore, an AC voltage converted by the conversion circuit 30 is applied to the magnetic component 32. The AC voltage converted by the conversion circuit 30 is also applied to the transformer 34 via the magnetic component 32.

[0023] The transformer 34 has a primary winding 341 and a secondary winding 342. The primary winding 341 is connected to the conversion circuit 30. The secondary winding 342 is connected to a first rectifying element 41 and a second rectifying element 42, which will be described later. The secondary winding 342 further includes a center tap 343. The center tap 343 is connected to ground. The transformer 34 then steps down the AC voltage applied from the conversion circuit 30 via the magnetic component 32, using the primary winding 341 and the secondary winding 342. The transformer 34 then applies the stepped-down AC voltage to the first rectifying element 41 and the second rectifying element 42.

[0024] The first rectifier element 41 is, for example, an FET, and rectifies the current of the AC voltage stepped down by the transformer 34. Furthermore, the first rectifier element 41 performs synchronous rectification by being turned on while a current is flowing through the first rectifier element 41. This allows the first rectifier element 41 to suppress power loss occurring in the first rectifier element 41.

[0025] One end of the first element adjusting resistor 51 is connected to the gate electrode of the first rectifying element 41. Furthermore, the first element adjusting resistor 51 adjusts the voltage applied to the gate electrode of the first rectifying element 41.

[0026] The second rectifier element 42 is, for example, an FET, and rectifies the current of the AC voltage stepped down by the transformer 34. The second rectifier element 42 is connected to the side of the secondary winding 342 opposite to the first rectifier element 41. Therefore, the second rectifier element 42 rectifies a current flowing in the opposite direction to the current flowing from the transformer 34 to the first rectifier element 41. Furthermore, the second rectifier element 42 performs synchronous rectification by being turned on during a period in which a current flows through the second rectifier element 42. This allows the second rectifier element 42 to suppress power loss that occurs in the second rectifier element 42.

[0027] One end of the second element adjusting resistor 52 is connected to the gate electrode of the second rectifying element 42. Furthermore, the second element adjusting resistor 52 adjusts the voltage applied to the gate electrode of the second rectifying element 42.

[0028] One end of the output capacitor 54 is connected to a choke coil 56, which will be described later, and the other end of the output capacitor 54 is connected to ground.

[0029] One end of the choke coil 56 is connected to the drain electrode of the first rectifier element 41 and the drain electrode of the second rectifier element 42. In addition, the choke coil 56, together with the output capacitor 54, smoothes the current rectified by the first rectifier element 41 and the second rectifier element 42.

[0030] One end of the filter 58 is connected to one end of the output capacitor 54 and the other end of the choke coil 56. Furthermore, the filter 58 is, for example, a low-pass filter, and removes noise contained in the current smoothed by the choke coil 56.

[0031] The output terminal 60 is connected to the other end of the filter 58. The main circuit ground terminal 62 is connected to a main circuit ground 64.

[0032] Furthermore, output terminal 60 outputs the voltage of the current that has passed through filter 58 to the outside of power converter 10. The outside of power converter 10 may be, for example, an auxiliary battery used for audio equipment in a vehicle. The auxiliary battery is charged by the voltage from output terminal 60.

[0033] The main circuit 20 is configured as described above. Therefore, the positive input terminal 24, the negative input terminal 26, the input capacitor 28, the conversion circuit 30, the magnetic component 32, and the primary winding 341 correspond to the primary side of the main circuit 20. Furthermore, the secondary winding 342, the first rectifying element 41, the second rectifying element 42, the output capacitor 54, the choke coil 56, the filter 58, and the output terminal 60 correspond to the secondary side of the main circuit 20.

[0034] The sub-circuit 70 includes a detection circuit 72, a control circuit 74, and a drive circuit 76. Here, the voltage between the transformer 34 and the first rectifier element 41 is defined as a first transformer voltage Vt1. The voltage between the transformer 34 and the second rectifier element 42 is defined as a second transformer voltage Vt2. The voltage between the gate electrode and source electrode of the first rectifier element 41 is defined as a first gate voltage Vgs1. The voltage between the gate electrode and source electrode of the second rectifier element 42 is defined as a second gate voltage Vgs2.

[0035] 2, the detection circuit 72 corresponds to the detection unit, and includes a first transformer voltage detection unit 721, a first transformer voltage comparator 731, a second transformer voltage detection unit 722, and a second transformer voltage comparator 732. The detection circuit 72 also includes a first gate voltage detection unit 741, a first gate voltage comparator 751, a second gate voltage detection unit 742, and a second gate voltage comparator 752.

[0036] The first transformer voltage detection unit 721 detects the first transformer voltage Vt1. Furthermore, the first transformer voltage detection unit 721 outputs the detected first transformer voltage Vt1 to a first transformer voltage comparator 731, which will be described later.

[0037] The first transformer voltage Vt1 detected by the first transformer voltage detection unit 721 is input to a non-inverting input terminal of the first transformer voltage comparator 731. Furthermore, the first transformer voltage threshold Vt1_th is input to an inverting input terminal of the first transformer voltage comparator 731. Therefore, the first transformer voltage comparator 731 outputs a signal according to the result of comparison between the first transformer voltage Vt1 and the first transformer voltage threshold Vt1_th to the control circuit 74 described below as a first transformer detection signal St1.

[0038] The second transformer voltage detection unit 722 detects the second transformer voltage Vt2. Furthermore, the second transformer voltage detection unit 722 outputs the detected second transformer voltage Vt2 to a second transformer voltage comparator 732, which will be described later.

[0039] The second transformer voltage Vt2 detected by the second transformer voltage detection unit 722 is input to a non-inverting input terminal of the second transformer voltage comparator 732. Furthermore, the second transformer voltage threshold Vt2_th is input to an inverting input terminal of the second transformer voltage comparator 732. Therefore, the second transformer voltage comparator 732 outputs a signal according to the result of comparison between the second transformer voltage Vt2 and the second transformer voltage threshold Vt2_th to the control circuit 74 described below as a second transformer detection signal St2.

[0040] The first gate voltage detection unit 741 detects the first gate voltage Vgs1, and further outputs the detected first gate voltage Vgs1 to a first gate voltage comparator 751, which will be described later.

[0041] The first gate voltage Vgs1 detected by the first gate voltage detection unit 741 is input to a non-inverting input terminal of the first gate voltage comparator 751. Furthermore, a first gate voltage threshold Vgs1_th is input to an inverting input terminal of the first gate voltage comparator 751. Therefore, the first gate voltage comparator 751 outputs a signal according to the result of comparison between the first gate voltage Vgs1 and the first gate voltage threshold Vgs1_th as a first gate detection signal Sg1 to the control circuit 74, which will be described later.

[0042] The second gate voltage detection section 742 detects the second gate voltage Vgs2 and outputs the detected second gate voltage Vgs2 to a second gate voltage comparator 752, which will be described later.

[0043] The second gate voltage Vgs2 detected by the second gate voltage detection unit 742 is input to a non-inverting input terminal of the second gate voltage comparator 752. Furthermore, the second gate voltage threshold Vgs2_th is input to an inverting input terminal of the second gate voltage comparator 752. Therefore, the second gate voltage comparator 752 outputs a signal according to the result of comparison between the second gate voltage Vgs2 and the second gate voltage threshold Vgs2_th as a second gate detection signal Sg2 to the control circuit 74, which will be described later.

[0044] Returning to FIG. 1 , the control circuit 74 corresponds to a control unit and is mainly composed of a microcomputer or the like, and includes a CPU, ROM, flash memory, RAM, I / O, a communication interface, and bus lines connecting these components. Furthermore, the control circuit 74 executes a program stored in its ROM. This causes the control circuit 74 to generate signals that drive the conversion circuit 30. Specifically, the control circuit 74 generates signals that turn on and off the first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304. The control circuit 74 also generates signals that turn on and off the first rectifier element 41 and the second rectifier element 42. Furthermore, the control circuit 74 acquires a first transformer detection signal St1, a second transformer detection signal St2, a first gate detection signal Sg1, and a second gate detection signal Sg2. Furthermore, the control circuit 74 generates signals for turning off the first rectifier element 41 and the second rectifier element 42 that are in the ON state, based on the acquired first transformer detection signal St1, second transformer detection signal St2, first gate detection signal Sg1, and second gate detection signal Sg2. Furthermore, the control circuit 74 outputs these generated signals to a drive circuit 76, which will be described later.

[0045] The drive circuit 76 is connected to the other end of the first adjustment resistor 311, the other end of the second adjustment resistor 312, the other end of the third adjustment resistor 313, the other end of the fourth adjustment resistor 314, the other end of the first element adjustment resistor 51, and the other end of the second element adjustment resistor 52. The drive circuit 76 also receives a signal from the control circuit 74.

[0046] Furthermore, the drive circuit 76 applies and stops applying a voltage to the gate electrode of the first transistor 301 via the first adjustment resistor 311 based on a signal from the control circuit 74. This turns the first transistor 301 on and off. The drive circuit 76 also applies and stops applying a voltage to the gate electrode of the second transistor 302 via the second adjustment resistor 312 based on a signal from the control circuit 74. This turns the second transistor 302 on and off. The drive circuit 76 also applies and stops applying a voltage to the gate electrode of the third transistor 303 via the third adjustment resistor 313 based on a signal from the control circuit 74. This turns the third transistor 303 on and off. The drive circuit 76 also applies and stops applying a voltage to the gate electrode of the fourth transistor 304 via the fourth adjustment resistor 314 based on a signal from the control circuit 74. This turns the fourth transistor 304 on and off. Furthermore, the drive circuit 76 applies and stops the application of voltage to the gate electrode of the first rectifier element 41 via the first element adjusting resistor 51 based on a signal from the control circuit 74. This turns the first rectifier element 41 on and off. The drive circuit 76 also applies and stops the application of voltage to the gate electrode of the second rectifier element 42 via the second element adjusting resistor 52 based on a signal from the control circuit 74. This turns the second rectifier element 42 on and off.

[0047] The power converter 10 of the first embodiment is configured as described above. Next, the operation of the power converter 10 will be described.

[0048] The first transistor 301 and the third transistor 303 are turned on and off complementarily with a phase difference of 180°. Furthermore, the second transistor 302 and the fourth transistor 304 are turned on and off complementarily with a phase difference of 180°. Furthermore, the first transistor 301 and the fourth transistor 304 are turned on and off with a phase difference. Furthermore, the second transistor 302 and the third transistor 303 are turned on and off with a phase difference.

[0049] For example, at time x1 in the time chart of FIG. 3, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the first transistor 301. The drive circuit 76 applies a voltage to the gate electrode of the first transistor 301 via the first adjustment resistor 311. This turns on the first transistor 301. At this time, the third transistor 303 is turned off. Note that in the time chart of FIG. 3, the on / off states of the first transistor 301 are indicated by Q1_1 and a solid line. The on / off states of the third transistor 303 are indicated by Q1_3 and a dashed line.

[0050] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the fourth transistor 304. The drive circuit 76 applies a voltage to the gate electrode of the fourth transistor 304 via the fourth adjustment resistor 314. This turns on the fourth transistor 304. At this time, the second transistor 302 is turned off. In the time chart of FIG. 3, the on / off of the second transistor 302 is indicated by Q1_2 and a dashed line. The on / off of the fourth transistor 304 is indicated by Q1_4 and a solid line.

[0051] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the first rectifying element 41. The drive circuit 76 applies a voltage to the gate electrode of the first rectifying element 41 via the first element adjusting resistor 51. This turns on the first rectifying element 41. At this time, the second rectifying element 42 is turned off. In the time chart of FIG. 3, the on / off state of the first rectifying element 41 is indicated by Q2_1 and a solid line. The on / off state of the second rectifying element 42 is indicated by Q2_2 and a dashed line.

[0052] During the period from time x1 to time x2, the first transistor 301 and the fourth transistor 304 are on. Therefore, as shown in Fig. 4, a current flows from the positive electrode of the DC power supply 12 to the negative electrode of the DC power supply 12 via the first transistor 301, the magnetic component 32, the primary winding 341, and the fourth transistor 304. In Fig. 4, the current flow is schematically indicated by a two-dot chain line.

[0053] Therefore, the current flowing through the primary winding 341 increases during the period from time x1 to time x2 in the time chart of Fig. 3. In the time chart of Fig. 3, the current flowing through the primary winding 341 is indicated by It1 and a solid line. Furthermore, here, the direction of the current flowing from the positive electrode of the DC power supply 12 via the first transistor 301, the magnetic component 32, the primary winding 341, and the fourth transistor 304 to the negative electrode of the DC power supply 12 is set to the positive direction of the current flowing through the primary winding 341.

[0054] Furthermore, because a current flows through the primary winding 341, a current whose voltage is lowered than the voltage of the current flowing through the primary winding 341 flows through the secondary winding 342 due to the turn ratio between the primary winding 341 and the secondary winding 342 and electromagnetic induction. At this time, rectification is performed by the first rectifying element 41 and the second rectifying element 42.

[0055] Therefore, in the period from time x1 to time x2 in the time chart of Fig. 3, the current flowing through the first rectifying element 41 increases. Furthermore, no current flows through the second rectifying element 42. In the time chart of Fig. 3, the current flowing through the first rectifying element 41 is indicated by I2_1 and a solid line. The current flowing through the second rectifying element 42 is indicated by I2_2 and a dashed line.

[0056] Furthermore, the current rectified by first rectifying element 41 and second rectifying element 42 is smoothed by output capacitor 54 and choke coil 56. Noise contained in the current smoothed by output capacitor 54 and choke coil 56 is removed by filter 58. The voltage of the current that has passed through filter 58 is output to the outside of power converter 10 via output terminal 60.

[0057] Furthermore, in the period from time x1 to time x2, the first transformer voltage Vt1 is a positive value, and the second transformer voltage Vt2 is a negative value.

[0058] At time x2, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the fourth transistor 304. The drive circuit 76 stops applying voltage to the gate electrode of the fourth transistor 304. This turns off the fourth transistor 304. The control circuit 74 also outputs a signal to the drive circuit 76 to turn on the second transistor 302. The drive circuit 76 applies a voltage to the gate electrode of the second transistor 302 via the second adjustment resistor 312. This turns on the second transistor 302. At this time, the first transistor 301 is on. The third transistor 303 is off. The first rectifying element 41 is on. The second rectifying element 42 is off.

[0059] Since the fourth transistor 304 is turned off and the second transistor 302 is turned on, a current flows back from the magnetic component 32 to the magnetic component 32 via the primary winding 341, the second transistor 302, and the first transistor 301, as shown in Fig. 5. In Fig. 5, the current flow is schematically indicated by a two-dot chain line.

[0060] As a result, the current flowing through the primary winding 341 decreases during the period from time x2 to time x3 in the timing chart of Fig. 3. Therefore, the current flowing through the secondary winding 342 and the first rectifier element 41 decreases during the period from time x2 to time x3. Furthermore, the first transformer voltage Vt1 and the second transformer voltage Vt2 become zero.

[0061] At time x3, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the first transistor 301. The drive circuit 76 stops applying voltage to the gate electrode of the first transistor 301. This turns off the first transistor 301. Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the third transistor 303. The drive circuit 76 applies voltage to the gate electrode of the third transistor 303 via the third adjustment resistor 313. This turns on the third transistor 303. At this time, the second transistor 302 is on. The fourth transistor 304 is off.

[0062] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the first rectifying element 41. The drive circuit 76 stops applying a voltage to the gate electrode of the first rectifying element 41. This turns off the first rectifying element 41.

[0063] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the second rectifier element 42. The drive circuit 76 applies a voltage to the gate electrode of the second rectifier element 42 via the second element adjusting resistor 52. This turns on the second rectifier element 42.

[0064] Also, immediately after time x3, the second transistor 302 and the third transistor 303 are turned on, and therefore a voltage in the opposite direction to the current flow is applied to the magnetic component 32 and the primary winding 341, as shown in Fig. 6. In Fig. 6, the current flow is schematically indicated by a two-dot chain line.

[0065] This causes a sudden decrease in the current in the primary winding 341. As a result, the current in the primary winding 341 becomes a negative value between time x3 and time x4 in the timing chart of FIG.

[0066] Furthermore, at this time, a continuous current flows through the choke coil 56, so the current flowing through the first rectifier element 41 decreases. The current flowing through the second rectifier element 42 increases. Furthermore, because current flows through both the first rectifier element 41 and the second rectifier element 42, the first transformer voltage Vt1 and the second transformer voltage Vt2 become zero.

[0067] At time x4, when the current flowing through the first rectifier element 41 becomes zero, the first transformer voltage Vt1 becomes negative. The second transformer voltage Vt2 becomes positive. At this time, as shown in Fig. 7, current flows from the positive electrode of the DC power supply 12 to the negative electrode of the DC power supply 12 via the second transistor 302, the primary winding 341, the magnetic component 32, and the third transistor 303. In Fig. 7, the current flow is schematically indicated by a two-dot chain line.

[0068] Furthermore, because a current flows through the primary winding 341, a current whose voltage is lower than the voltage of the current flowing through the primary winding 341 flows through the secondary winding 342 due to the turns ratio between the primary winding 341 and the secondary winding 342 and electromagnetic induction. Furthermore, the direction of the current flowing through the primary winding 341 at this time is opposite to the direction of the current flowing through the primary winding 341 when the first transistor 301 and the fourth transistor 304 are on. Therefore, the DC voltage from the DC power supply 12 is converted into an AC voltage by the conversion circuit 30 including the first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304. Furthermore, the direction of the current flowing through the secondary winding 342 at this time is opposite to the direction of the current flowing through the secondary winding 342 when the first transistor 301 and the fourth transistor 304 are on. Therefore, the current of the secondary winding 342 flows through the second rectifying element 42.

[0069] Therefore, the current flowing through the second rectifying element 42 increases during the period from time x4 to time x5 in the time chart of Fig. 3. Furthermore, no current flows through the first rectifying element 41.

[0070] Furthermore, the current rectified by first rectifying element 41 and second rectifying element 42 is smoothed by output capacitor 54 and choke coil 56. Noise contained in the current smoothed by output capacitor 54 and choke coil 56 is removed by filter 58. The voltage of the current that has passed through filter 58 is output to the outside of power converter 10 via output terminal 60.

[0071] At time x5, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the second transistor 302. The drive circuit 76 stops applying voltage to the gate electrode of the second transistor 302. This turns off the second transistor 302. The control circuit 74 also outputs a signal to the drive circuit 76 to turn on the fourth transistor 304. The drive circuit 76 applies voltage to the gate electrode of the fourth transistor 304 via the fourth adjustment resistor 314. This turns on the fourth transistor 304. At this time, the first transistor 301 is off. The third transistor 303 is on. The first rectifying element 41 is off. The second rectifying element 42 is on.

[0072] Because the second transistor 302 is turned off and the fourth transistor 304 is turned on, current flows back from the primary winding 341 via the magnetic component 32, the third transistor 303, and the fourth transistor 304 to the primary winding 341, as shown in FIG. 8. As a result, the current flowing through the primary winding 341 increases during the period from time x5 to x6 in the timing chart of FIG. 3. Therefore, the absolute value of the current flowing through the primary winding 341 decreases. Therefore, the current flowing through the secondary winding 342 and the second rectifier element 42 decreases. Furthermore, the first transformer voltage Vt1 and the second transformer voltage Vt2 become zero.

[0073] At time x6, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the third transistor 303. The drive circuit 76 stops applying voltage to the gate electrode of the third transistor 303. This turns off the third transistor 303. The control circuit 74 also outputs a signal to the drive circuit 76 to turn on the first transistor 301. The drive circuit 76 applies voltage to the gate electrode of the first transistor 301 via the first adjustment resistor 311. This turns on the first transistor 301. At this time, the second transistor 302 is off. The fourth transistor 304 is on.

[0074] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn off the second rectifying element 42. The drive circuit 76 stops applying a voltage to the gate electrode of the second rectifying element 42. This turns off the second rectifying element 42.

[0075] Furthermore, the control circuit 74 outputs a signal to the drive circuit 76 to turn on the first rectifying element 41. The drive circuit 76 applies a voltage to the gate electrode of the first rectifying element 41 via the first element adjusting resistor 51. This turns on the first rectifying element 41.

[0076] Also, immediately after time x6, the first transistor 301 and the fourth transistor 304 are turned on, and therefore a voltage in the opposite direction to the current flow is applied to the magnetic component 32 and the primary winding 341, as shown in Fig. 9. In Fig. 9, the current flow is schematically indicated by a two-dot chain line.

[0077] This causes a sudden increase in the current in the primary winding 341. As a result, the current in the primary winding 341 becomes a positive value between time x6 and time x7 in the timing chart of FIG.

[0078] Furthermore, at this time, because a continuous current flows through the choke coil 56, the current flowing through the second rectifier element 42 decreases. The current flowing through the first rectifier element 41 increases. Furthermore, because current flows through both the first rectifier element 41 and the second rectifier element 42, the first transformer voltage Vt1 and the second transformer voltage Vt2 become zero.

[0079] At time x7, when the current flowing through the second rectifier element 42 becomes zero, the first transformer voltage Vt1 becomes a positive value. The second transformer voltage Vt2 becomes a negative value. At this time, as shown in FIG. 4, current flows from the positive electrode of the DC power supply 12 to the negative electrode of the DC power supply 12 via the first transistor 301, the magnetic component 32, the primary winding 341, and the fourth transistor 304. Therefore, from time x7 onwards, the processes and states from time x1 to time x6 are repeated.

[0080] As described above, the power converter 10 operates as a DC-DC converter for a vehicle. Assume that the first rectifier element 41 is turned on during the period from time x4, when the second transformer voltage Vt2 increases from zero, to time x5, when the current flowing through the second rectifier element 42 begins to decrease as the second transistor 302 turns off. In this case, a short circuit occurs between the secondary winding 342, the first rectifier element 41, and the second rectifier element 42. Therefore, as shown in the time chart of FIG. 3 , the period from time x4 to time x5 is the on-inhibit period T_on_ban for the first rectifier element 41. Therefore, the first rectifier element 41 must be turned off during the period from time x4 to time x5. Therefore, the first rectifier element 41 is turned off, for example, at time x3, which is before time x4, so that the first rectifier element 41 is not turned on during the period from time x4 to time x5.

[0081] Furthermore, here, during the period from time x3 to time x4, a current flows through the first rectifying element 41. However, because the first rectifying element 41 is off during this period, synchronous rectification by the first rectifying element 41 is not performed. Because synchronous rectification by the first rectifying element 41 is not performed, the voltage corresponding to the current flowing through the first rectifying element 41 during this period from time x3 to time x4 is higher than when the first rectifying element 41 is on. Therefore, the period from time x3 to time x4 is a power loss period Ts for the first rectifying element 41. By shortening this power loss period Ts, power loss by the first rectifying element 41 and the second rectifying element 42 is suppressed.

[0082] Furthermore, the DC-DC converter described in Patent Document 1 predicts the secondary-side current from the primary-side current and controls the off-timing corresponding to the predicted current. However, the primary side includes a magnetic component 32 such as a coil and a transformer 34. Furthermore, the magnetic component 32 and the transformer 34 have manufacturing variations, resulting in variations in characteristics such as reactance. This causes variations in the primary-side current between DC-DC converters. This reduces the prediction accuracy of the secondary-side current. This results in variations in the off-timing corresponding to the predicted current. Therefore, in the DC-DC converter described in Patent Document 1, the power loss due to the rectifying switching elements varies greatly. Therefore, in the DC-DC converter described in Patent Document 1, the power loss due to the rectifying switching elements increases.

[0083] In contrast, the power converter 10 of this embodiment suppresses power loss due to the first rectifier element 41 and the second rectifier element 42. To this end, the control circuit 74 executes its own program to turn off the first rectifier element 41 that is in the ON state based on the second transformer voltage Vt2 and the first gate voltage Vgs1. The control circuit 74 also executes its own program to turn off the second rectifier element 42 that is in the ON state based on the first transformer voltage Vt1 and the second gate voltage Vgs2.

[0084] Next, the turning off of the first rectifier element 41 based on the second transformer voltage Vt2 and the first gate voltage Vgs1 by executing the program of the control circuit 74 will be described with reference to the flowchart of Fig. 10 and the time chart of Fig. 11. The program of the control circuit 74 is executed, for example, when the power supply to the power converter 10 is turned on. Furthermore, in the program of the control circuit 74, the period of a series of operations from when the control circuit 74 starts processing in step S100 until when the control circuit 74 returns from processing in step S100 is defined as the control cycle of the control circuit 74.

[0085] 10, the control circuit 74 acquires various information. Specifically, the control circuit 74 acquires the second transformer detection signal St2 for a predetermined period as signal data from the second transformer voltage comparator 732 of the detection circuit 72. The control circuit 74 also acquires the first gate detection signal Sg1 for a predetermined period as signal data from the first gate voltage comparator 751 of the detection circuit 72.

[0086] As described above, the second transformer detection signal St2 is a signal corresponding to the comparison result between the second transformer voltage Vt2 and the second transformer voltage threshold Vt2_th. The second transformer voltage Vt2 is the voltage between the transformer 34 and the second rectifier element 42. The first gate detection signal Sg1 is a signal corresponding to the comparison result between the first gate voltage Vgs1 and the first gate voltage threshold Vgs1_th. The first gate voltage Vgs1 is the voltage of the gate electrode of the first rectifier element 41. Furthermore, the power loss period Ts for the first rectifier element 41 is the period from when the first rectifier element 41 is turned off to when the second transformer voltage Vt2 increases from zero. The on / off of the first rectifier element 41 corresponds to a change in the first gate voltage Vgs1, and therefore to a change in the voltage level of the first gate detection signal Sg1. A change in the second transformer voltage Vt2 corresponds to a change in the voltage level of the second transformer detection signal St2.

[0087] Therefore, the power loss period Ts for the first rectifier element 41 can be calculated from the change in the voltage level of the first gate detection signal Sg1 and the change in the voltage level of the second transformer detection signal St2.

[0088] Therefore, in step S102 following step S100, the control circuit 74 calculates the power loss period Ts(n) for the first rectifying element 41 in the current control cycle based on the change in the voltage level of the signal acquired in step S100.

[0089] 11, the control circuit 74 calculates the time xs(n) when the voltage level of the first gate detection signal Sg1 changes from high to low. The control circuit 74 also calculates the time xe(n) when the voltage level of the second transformer detection signal St2 changes from low to high. In the time chart, the high voltage level is indicated as High, and the low voltage level is indicated as Low.

[0090] Here, time xs(n) is the time when the first gate voltage Vgs1 changes from equal to or greater than the first gate voltage threshold Vgs1_th to less than the first gate voltage threshold Vgs1_th. Therefore, time xs(n) corresponds to the timing when the first rectifying element 41, which is in the on state, turns off. Therefore, the first gate voltage threshold Vgs1_th is set by experiment, simulation, or the like so that the on / off state of the first rectifying element 41 can be determined.

[0091] Furthermore, time xe(n) is the time when the second transformer voltage Vt2 changes from less than the second transformer voltage threshold Vt2_th to equal to or greater than the second transformer voltage threshold Vt2_th. Therefore, time xe(n) corresponds to the time when the second transformer voltage Vt2 increases from zero. Therefore, the time when the second transformer voltage Vt2 is less than the second transformer voltage threshold Vt2_th is set by experiment, simulation, or the like so that it can be determined whether the second transformer voltage Vt2 is increasing from zero.

[0092] Therefore, the control circuit 74 calculates the period from the calculated time xs(n) to the time xe(n), thereby calculating the power loss period Ts(n) for the first rectifying element 41 in the current control cycle.

[0093] In step S104 following step S102, the control circuit 74 calculates a quantity Td(n+1) related to the off timing for the first rectifying element 41 in the next control cycle from the power loss period Ts(n) calculated in step S102 and the following relational expression (1).

[0094] Td(n+1)=Td(n)+Ts(n)-Tm ···(1)

[0095] Here, Td(n) in the above relational expression (1) is the amount Td related to the timing of turning off the first rectifying element 41 in the ON state in the current control cycle, and is calculated in the previous control cycle. Therefore, Td(1) is the amount Td related to the timing of turning off the first rectifying element 41 in the ON state in the initial control cycle. To calculate Td(2), Td(1) is set to, for example, the time from when the control circuit 74 outputs a signal to turn on the first transistor 301 from OFF to when the control circuit 74 outputs a signal to turn off the first transistor 301 from ON. Here, the start time of the amount Td related to the timing of turning off the first rectifying element 41 is set to when the control circuit 74 outputs a signal to turn on the first transistor 301 from OFF. Alternatively, the start time of the amount Td related to the timing of turning off the first rectifying element 41 may be set to when the control circuit 74 outputs a signal to turn on the fourth transistor 304 from OFF. Alternatively, the start time of the amount Td related to the off-timing of the first rectifying element 41 may be the time when the control circuit 74 outputs a signal to change the first rectifying element 41 from off to on. Alternatively, the start time of the amount Td related to the off-timing of the first rectifying element 41 may be a predetermined time when the first transistor 301, the fourth transistor 304, and the first rectifying element 41 are all on.

[0096] Furthermore, Tm in the above relational expression (1) is an adjustment amount for the amount Td related to the off-timing of the first rectifying element 41. Tm is set by experiment, simulation, or the like so that the off-timing of the first rectifying element 41 does not fall within the on-inhibit period T_on_ban.

[0097] In step S106 following step S104, the control circuit 74 outputs signals to the drive circuit 76 that turn on and off the second transistor 302, the third transistor 303, and the second rectifier element 42. As a result, a rectified current flows through the second rectifier element 42. Thereafter, the control circuit 74 turns off the second transistor 302, the third transistor 303, and the second rectifier element 42. Then, the control circuit 74 outputs signals to the drive circuit 76 that turn on the first transistor 301, the fourth transistor 304, and the first rectifier element 41. As a result, a rectified current flows through the first rectifier element 41, as described above. Thereafter, the control circuit 74 turns off the first transistor 301 and the fourth transistor 304.

[0098] Then, the control circuit 74 outputs a signal to turn off the first rectifying element 41 based on the amount Td(n+1) related to the off-timing of the first rectifying element 41 calculated in step S104. Because the amount Td related to the off-timing of the first rectifying element 41 includes the power loss period Ts, the power loss period Ts is shortened and the first rectifying element 41 is turned off. This suppresses power loss by the first rectifying element 41. Thereafter, the processing of the control circuit 74 returns to step S100.

[0099] As described above, the control circuit 74 turns off the first rectifier element 41 that is in the on state based on the second transformer voltage Vt2 and the first gate voltage Vgs1. Next, the turning off of the second rectifier element 42 based on the first transformer voltage Vt1 and the second gate voltage Vgs2 by executing a program in the control circuit 74 will be described.

[0100] The second rectifier element 42 is turned off based on the first transformer voltage Vt1 and the second gate voltage Vgs2 in the same manner as the first rectifier element 41 is turned off based on the second transformer voltage Vt2 and the first gate voltage Vgs1. Specifically, in the process from step S100 to returning to step S100, the first transistor 301 is replaced with the third transistor 303. The fourth transistor 304 is replaced with the second transistor 302. The first rectifier element 41 is replaced with the second rectifier element 42. The second rectifier element 42 is replaced with the first rectifier element 41. The second transformer voltage Vt2 is replaced with the first transformer voltage Vt1. The second transformer voltage threshold Vt2_th is replaced with the first transformer voltage threshold Vt1_th. The first gate voltage Vgs1 is replaced with the second gate voltage Vgs2. The first gate voltage threshold Vgs1_th is replaced with the second gate voltage threshold Vgs2_th. The second transformer detection signal St2 is replaced with the first transformer detection signal St1. The second transformer voltage comparator 732 is replaced with the first transformer voltage comparator 731. The first gate detection signal Sg1 is replaced with the second gate detection signal Sg2. The first gate voltage comparator 751 is replaced with the second gate voltage comparator 752.

[0101] Next, it will be described how power loss caused by the first rectifying element 41 and the second rectifying element 42 is suppressed in the power converter 10 of this embodiment.

[0102] The power converter 10 includes a conversion circuit 30, a magnetic component 32, a transformer 34, a first rectifier element 41, a second rectifier element 42, a detection circuit 72, and a control circuit 74. The conversion circuit 30 converts a DC voltage from a DC power supply 12 into an AC voltage. The AC voltage converted by the conversion circuit 30 is applied to the magnetic component 32. The transformer 34 steps down the AC voltage applied via the magnetic component 32. The first rectifier element 41 and the second rectifier element 42 are transistors that rectify the current of the AC voltage stepped down by the transformer 34. The first rectifier element 41 performs synchronous rectification by being turned on during a period when a current flows through the first rectifier element 41. This allows the first rectifier element 41 to suppress power loss that occurs in the first rectifier element 41. The second rectifier element 42 performs synchronous rectification by being turned on during a period when a current flows through the second rectifier element 42. This allows the second rectifier element 42 to suppress power loss that occurs in the second rectifier element 42. The detection circuit 72 detects the first transformer voltage Vt1 and the second transformer voltage Vt2. The control circuit 74 turns off the first rectifier element 41 that is in the ON state based on the second transformer voltage Vt2. Furthermore, the control circuit 74 turns off the second rectifier element 42 that is in the ON state based on the first transformer voltage Vt1.

[0103] As a result, the first rectifier element 41 and the second rectifier element 42 in the ON state are turned off without using a current flowing through the primary side corresponding to the portion between the conversion circuit 30 and the transformer 34. This suppresses the influence of variations in the current flowing through the primary side, turning off the first rectifier element 41 and the second rectifier element 42 in the ON state. This suppresses variations in the turn-off timing of the first rectifier element 41 and the second rectifier element 42 in the ON state. Furthermore, by using the second transformer voltage Vt2, the first rectifier element 41 is not turned on during the on-inhibit period T_on_ban for the first rectifier element 41, and the power loss period Ts for the first rectifier element 41 can be shortened, allowing the first rectifier element 41 to be turned off. Furthermore, by using the first transformer voltage Vt1, the second rectifier element 42 is not turned on during the on-inhibit period T_on_ban for the second rectifier element 42, and the power loss period Ts for the second rectifier element 42 can be shortened, allowing the second rectifier element 42 to be turned off. This reduces the variation in the off timing of the first rectifying element 41 and the second rectifying element 42 that are in the on state, and shortens the power loss period Ts. This reduces the power loss caused by the first rectifying element 41 and the second rectifying element 42.

[0104] Furthermore, the power converter 10 of the first embodiment also provides the following effects.

[0105] [1] The first rectifier element 41 and the second rectifier element 42 include transistors. The detection circuit 72 detects the first gate voltage Vgs1 and the second gate voltage Vgs2 in addition to the first transformer voltage Vt1 and the second transformer voltage Vt2.

[0106] The control circuit 74 calculates a quantity Td related to the off-timing of the first rectifier element 41 based on the first gate voltage Vgs1 and the second transformer voltage Vt2. Specifically, the control circuit 74 calculates a power loss period Ts(n) for the current first rectifier element 41 using the first gate voltage Vgs1 and the second transformer voltage Vt2. Furthermore, the control circuit 74 uses the power loss period Ts(n) for the current first rectifier element 41 and a quantity Td(n) related to the off-timing of the current first rectifier element 41. As a result, the control circuit 74 calculates a quantity Td(n+1) related to the next off-timing of the first rectifier element 41. Furthermore, the control circuit 74 turns off the first rectifier element 41 that is in the on state next time based on the calculated quantity Td(n+1) related to the next off-timing of the first rectifier element 41. Note that although the quantity Td(n) related to the current off-timing is used here, a quantity Td related to an off-timing earlier than the current time may also be used.

[0107] By using the first gate voltage Vgs1 and the second transformer voltage Vt2, it becomes easier to calculate the amount Td related to the off-timing of the first rectifier element 41. This prevents a decrease in the accuracy of calculating the amount Td related to the off-timing of the first rectifier element 41. This reduces variations in the off-timing of the first rectifier element 41 in the on state. This reduces power loss due to the first rectifier element 41.

[0108] The control circuit 74 also calculates a quantity Td related to the off-timing for the second rectifier element 42 based on the second gate voltage Vgs2 and the first transformer voltage Vt1. Specifically, the control circuit 74 calculates a power loss period Ts(n) for the current second rectifier element 42 using the second gate voltage Vgs2 and the first transformer voltage Vt1. The control circuit 74 then uses the power loss period Ts(n) for the current second rectifier element 42 and the quantity Td(n) related to the off-timing for the current second rectifier element 42. The control circuit 74 then calculates a quantity Td(n+1) related to the next off-timing for the second rectifier element 42. The control circuit 74 then turns off the second rectifier element 42 that is in the on state at the next time based on the calculated quantity Td(n+1) related to the next off-timing for the second rectifier element 42.

[0109] Using the second gate voltage Vgs2 and the first transformer voltage Vt1 makes it easier to calculate the amount Td related to the off timing of the second rectifier element 42. Therefore, similarly to the above, power loss due to the second rectifier element 42 is suppressed.

[0110] (Second embodiment) In the second embodiment, the processing by the control circuit 74 when the first rectifier element 41 is turned off based on the second transformer voltage Vt2 and the first gate voltage Vgs1 differs from that in the first embodiment. Also, the processing by the control circuit 74 when the second rectifier element 42 is turned off based on the first transformer voltage Vt1 and the second gate voltage Vgs2 differs from that in the first embodiment. Other than these, the second embodiment is the same as the first embodiment. Below, the processing by the control circuit 74 when the first rectifier element 41 is turned off based on the second transformer voltage Vt2 and the first gate voltage Vgs1 will be described.

[0111] 12, in step S100, similarly to the first embodiment, the control circuit 74 acquires the second transformer detection signal St2 for a predetermined period as signal data from the second transformer voltage comparator 732 of the detection circuit 72. Furthermore, the control circuit 74 acquires the first gate detection signal Sg1 for a predetermined period as signal data from the first gate voltage comparator 751 of the detection circuit 72.

[0112] As described above, the power loss period Ts for the first rectifier element 41 is calculated based on changes in the voltage levels of the second transformer detection signal St2 and the first gate detection signal Sg1. However, noise or other factors may cause the voltage levels of the second transformer detection signal St2 and the first gate detection signal Sg1 to change during a period that does not correspond to the power loss period Ts. In this case, the changes in the voltage levels of the second transformer detection signal St2 and the first gate detection signal Sg1 are erroneously detected, resulting in an incorrect power loss period Ts calculated by the control circuit 74. If the power loss period Ts calculated by the control circuit 74 is incorrect, the off timing for the first rectifier element 41 will be incorrect.

[0113] Therefore, in step S200 following step S100, the control circuit 74 extracts a second transformer detection signal St2 suitable for calculating the power loss period Ts from the signal data acquired in step S100. Specifically, as shown in the time chart of Fig. 13, the control circuit 74 extracts the second transformer detection signal St2 for the period from when a signal that changes the first transistor 301 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output. Note that in the time chart of Fig. 13, the period from when a signal that changes the first transistor 301 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output is indicated as Te_t.

[0114] Furthermore, the control circuit 74 extracts a first gate detection signal Sg1 suitable for calculating the power loss period Ts from the signal data acquired in step S100. Specifically, the control circuit 74 extracts the first gate detection signal Sg1 for the period from when a signal that changes the first rectifier element 41 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output. Note that in the time chart of FIG. 13, the period from when a signal that changes the first rectifier element 41 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output is indicated as Te_g.

[0115] 12, in step S202 following step S200, the control circuit 74 determines whether or not there is a change in the voltage levels of the second transformer detection signal St2 and the first gate detection signal Sg1 extracted in step S200. In this way, the control circuit 74 determines whether or not the power converter 10 is normal.

[0116] Specifically, the control circuit 74 determines whether the voltage level of the second transformer detection signal St2 extracted in step S200 has changed from a low level to a high level, and further determines whether the voltage level of the first gate detection signal Sg1 extracted in step S200 has changed from a high level to a low level.

[0117] If the voltage level of the second transformer detection signal St2 does not change from low to high, the power converter 10 is not operating normally, and the control circuit 74 proceeds to step S204. If the voltage level of the first gate detection signal Sg1 does not change from high to low, the power converter 10 is not operating normally, and the control circuit 74 proceeds to step S204. If the voltage level of the second transformer detection signal St2 changes from low to high and the voltage level of the first gate detection signal Sg1 changes from high to low, the power converter 10 is operating normally. Therefore, the control circuit 74 proceeds to step S102. In step S102, the control circuit 74 calculates the power loss period Ts(n) for the first rectifying element 41 in the current control cycle based on the changes in the voltage levels of the first transformer detection signal St1 and the first gate detection signal Sg1 extracted in step S200. After the process of step S102, the control circuit 74 performs the processes of steps S104 and S106 in the same manner as in the first embodiment.

[0118] In step S204 following step S202, although the voltage levels of the second transformer detection signal St2 and the first gate detection signal Sg1 should change, there is no change in the voltage levels of the second transformer detection signal St2 or the first gate detection signal Sg1. Therefore, at this time, the control circuit 74 determines that the power converter 10 is abnormal. Furthermore, the control circuit 74 stops outputting signals that turn on and off the first transistor 301, the second transistor 302, the third transistor 303, the fourth transistor 304, the first rectifier element 41, and the second rectifier element 42. The control circuit 74 also outputs an alarm using, for example, text, sound, and light. The control circuit 74 then returns to step S100.

[0119] As described above, the control circuit 74 of the power converter 10 of the second embodiment turns off the first rectifier element 41, which is in the on state, based on the first transformer voltage Vt1 and the first gate voltage Vgs1. The processing by the control circuit 74 when the second rectifier element 42 is turned off is the same as the processing by the control circuit 74 when the first rectifier element 41 is turned off. Specifically, in the processing from step S100 to returning to step S100, the first transistor 301 is replaced with the third transistor 303. The fourth transistor 304 is replaced with the second transistor 302. The first rectifier element 41 is replaced with the second rectifier element 42. The second rectifier element 42 is replaced with the first rectifier element 41. The second transformer voltage Vt2 is replaced with the first transformer voltage Vt1. The first gate voltage Vgs1 is replaced with the second gate voltage Vgs2. The second transformer detection signal St2 is replaced with the first transformer detection signal St1. The second transformer voltage comparator 732 is replaced with the first transformer voltage comparator 731. The first gate detection signal Sg1 is replaced with the second gate detection signal Sg2. The first gate voltage comparator 751 is replaced with the second gate voltage comparator 752.

[0120] The second embodiment also provides the same effects as the first embodiment. The second embodiment also provides the following effects.

[0121] [2-1] The control circuit 74 calculates the power loss period Ts for the first rectifier element 41 by using the first gate voltage Vgs1 for a period based on a change in the voltage level of the signal that drives the conversion circuit 30 and a change in the voltage level of the signal that turns the first rectifier element 41 on and off. Note that this period corresponds to the period from when the control circuit 74 outputs a signal that turns the first rectifier element 41 from on to off until when the control circuit 74 outputs a signal that turns the fourth transistor 304 from off to on.

[0122] This suppresses erroneous detection of a change in the voltage level of the first gate detection signal Sg1, thereby suppressing miscalculation of the power loss period Ts for the first rectifier element 41. This suppresses erroneous timing for turning off the first rectifier element 41.

[0123] Furthermore, the control circuit 74 calculates the power loss period Ts for the second rectifier element 42 using the second gate voltage Vgs2 for a period based on changes in the voltage level of the signal that drives the conversion circuit 30 and changes in the signal that turns the second rectifier element 42 on and off. Note that this period corresponds to the period from when the control circuit 74 outputs a signal that turns the second rectifier element 42 from on to off until when the control circuit 74 outputs a signal that turns the second transistor 302 from off to on.

[0124] This prevents erroneous detection of a change in the voltage level of the second gate detection signal Sg2, thereby preventing miscalculation of the power loss period Ts for the second rectifier element 42. This prevents erroneous timing for turning off the second rectifier element 42.

[0125] [2-2] Assume that the voltage level of the first gate detection signal Sg1 does not change from high to low during a period based on changes in the signal that drives the conversion circuit 30 and changes in the signal that turns the first rectifier element 41 on and off. At this time, the control circuit 74 determines that the power converter 10 is abnormal. This makes it possible to determine whether the power converter 10 is abnormal. Note that when the voltage level of the first gate detection signal Sg1 does not change from high to low, this corresponds to when the first gate voltage Vgs1 does not change from equal to or greater than the first gate voltage threshold Vgs1_th to less than the first gate voltage threshold Vgs1_th.

[0126] Furthermore, suppose that the voltage level of the second gate detection signal Sg2 does not change from high to low during a period based on changes in the signal that drives the conversion circuit 30 and changes in the signal that turns the second rectifier element 42 on and off. At this time, the control circuit 74 determines that there is an abnormality in the power converter 10. This makes it possible to determine whether there is an abnormality in the power converter 10. Note that when the voltage level of the second gate detection signal Sg2 does not change from high to low, this corresponds to when the second gate voltage Vgs2 does not change from equal to or greater than the second gate voltage threshold Vgs2_th to less than the second gate voltage threshold Vgs2_th.

[0127] [2-3] The control circuit 74 calculates the power loss period Ts for the first rectifier element 41 using the second transformer voltage Vt2 for a period based on a change in the voltage level of the signal that drives the conversion circuit 30. Note that the period based on a change in the voltage level of the signal that drives the conversion circuit 30 corresponds to the period from when a signal that changes the first transistor 301 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output.

[0128] This suppresses erroneous detection of a change in the voltage level of the second transformer detection signal St2, thereby suppressing miscalculation of the power loss period Ts for the first rectifier element 41. This suppresses erroneous timing for turning off the first rectifier element 41.

[0129] The control circuit 74 also calculates the power loss period Ts for the second rectifier element 42 using the first transformer voltage Vt1 during a period based on a change in the voltage level of the signal that drives the conversion circuit 30. The period based on a change in the voltage level of the signal that drives the conversion circuit 30 corresponds to the period from when a signal that changes the third transistor 303 from on to off is output to when a signal that changes the second transistor 302 from off to on is output.

[0130] This suppresses erroneous detection of a change in the voltage level of the first transformer detection signal St1, thereby suppressing miscalculation of the power loss period Ts for the second rectifier element 42. This suppresses erroneous timing for turning off the second rectifier element 42.

[0131] [2-4] Assume that the voltage level of the first transformer detection signal St1 does not change from low to high during a period based on a change in the voltage level of the signal that drives the conversion circuit 30. At this time, the control circuit 74 determines that the power converter 10 is abnormal. This makes it possible to determine whether the power converter 10 is abnormal. Note that when the voltage level of the first transformer detection signal St1 does not change from low to high, this corresponds to when the first transformer voltage Vt1 does not change from less than the first transformer voltage threshold Vt1_th to greater than or equal to the first transformer voltage threshold Vt1_th.

[0132] Also, assume that the voltage level of the second transformer detection signal St2 does not change from low to high during a period based on a change in the voltage level of the signal that drives the conversion circuit 30. At this time, the control circuit 74 determines that the power converter 10 is abnormal. This makes it possible to determine whether the power converter 10 is abnormal. Note that when the voltage level of the second transformer detection signal St2 does not change from low to high, this corresponds to when the second transformer voltage Vt2 does not change from less than the second transformer voltage threshold Vt2_th to greater than or equal to the second transformer voltage threshold Vt2_th.

[0133] (Third embodiment) The third embodiment differs from the second embodiment in the calculation of the power loss period Ts in step S102, but is otherwise similar to the second embodiment.

[0134] 14, this period is assumed to be from when a signal that changes the first transistor 301 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output. At this time, noise may cause the second transformer voltage Vt2 to fluctuate from below the second transformer voltage threshold Vt2_th to above the second transformer voltage threshold Vt2_th. As a result, during this period, the voltage level of the second transformer detection signal St2 may change from low to high multiple times.

[0135] 15, the period is assumed to be from when a signal that changes the first transistor 301 from on to off is output to when a signal that changes the fourth transistor 304 from off to on is output. At this time, due to resonance, the second transformer voltage Vt2 may fluctuate from below the second transformer voltage threshold Vt2_th to above the second transformer voltage threshold Vt2_th. As a result, during this period, the voltage level of the second transformer detection signal St2 may change from low to high multiple times.

[0136] If the voltage level of the second transformer detection signal St2 changes from low to high multiple times, the change in the voltage level of the second transformer detection signal St2 is erroneously detected, and the power loss period Ts calculated by the control circuit 74 becomes an incorrect period. If the power loss period Ts calculated by the control circuit 74 becomes an incorrect period, the off timing for the first rectifying element 41 becomes an incorrect timing.

[0137] In contrast to these, in the third embodiment, in step S102, the control circuit 74 determines the time when the voltage level of the second transformer detection signal St2 changes from low level to high level, which is the longest of the following times, as the time xe(n) for the first rectifier element 41. Furthermore, as shown in the time chart of FIG. 14, the control circuit 74 uses this time xe(n) for the first rectifier element 41 to calculate the power loss period Ts for the first rectifier element 41. Note that the above time is the time from when the voltage level of the second transformer detection signal St2 changes from low level to high level until when the voltage level of the second transformer detection signal St2 changes from high level to low level.

[0138] Alternatively, in step S102, the control circuit 74 selects a time when the above-mentioned time is longer than the resonance period Tr, as shown in the time chart of FIG. 15. Furthermore, the control circuit 74 sets the earliest time among the selected times as the time xe(n) for the first rectifying element 41. The control circuit 74 also uses this time xe(n) for the first rectifying element 41 to calculate the power loss period Ts for the first rectifying element 41. The resonance period Tr is set based on a resonance frequency determined from the inductances of the magnetic component 32 and the transformer 34 and the capacitances of the first rectifying element 41 and the second rectifying element 42.

[0139] Furthermore, the control circuit 74 determines the time when the voltage level of the first transformer detection signal St1 changes from low level to high level, which is the longest of the following times, as the time xe(n) for the second rectifier element 42. The control circuit 74 also uses this time xe(n) for the second rectifier element 42 to calculate the power loss period Ts for the second rectifier element 42. Note that the above time is the time from when the voltage level of the first transformer detection signal St1 changes from low level to high level until when the voltage level of the first transformer detection signal St1 changes from high level to low level.

[0140] Alternatively, the control circuit 74 selects a time when the above-mentioned time is longer than the resonance period Tr. The control circuit 74 sets the earliest time among the selected times as the time xe(n) for the second rectifying element 42. The control circuit 74 then uses the time xe(n) for the second rectifying element 42 to calculate the power loss period Ts for the second rectifying element 42.

[0141] As described above, the control circuit 74 of the power converter 10 of the third embodiment calculates the power loss period Ts in step S102. The third embodiment also provides the same effects as the second embodiment. The third embodiment also provides the following effects.

[0142] [3] The control circuit 74 determines the time when the voltage level of the second transformer detection signal St2 changes from low to high, during which the above-mentioned time period for the second transformer detection signal St2 is longest, as the time xe(n) for the first rectifying element 41. Alternatively, the control circuit 74 determines the earliest time among the times during which the above-mentioned time period for the second transformer detection signal St2 is longer than the resonance period Tr as the time xe(n). Furthermore, the control circuit 74 calculates the power loss period Ts for the first rectifying element 41 using the time xe(n) for the selected first rectifying element 41.

[0143] This suppresses a decrease in the accuracy of calculating the power loss period Ts for the first rectifying element 41. This suppresses a decrease in the accuracy of calculating the amount Td related to the off-timing for the first rectifying element 41. This suppresses variations in the off-timing for the first rectifying element 41 in the on state. This suppresses power loss due to the first rectifying element 41.

[0144] The control circuit 74 also determines the time when the voltage level of the first transformer detection signal St1 changes from low to high, which is the longest time for the first transformer detection signal St1, as the time xe(n) for the second rectifier element 42. Alternatively, the control circuit 74 determines the earliest time among times for which the time for the first transformer detection signal St1 is longer than the resonance period Tr as the time xe(n). Furthermore, the control circuit 74 calculates the power loss period Ts for the second rectifier element 42 using the time xe(n) for the selected second rectifier element 42.

[0145] This suppresses a decrease in the accuracy of calculating the power loss period Ts for the second rectifying element 42. This suppresses a decrease in the accuracy of calculating the amount Td related to the off-timing for the second rectifying element 42. This suppresses variations in the off-timing for the second rectifying element 42 in the on state. This suppresses power loss due to the second rectifying element 42.

[0146] (Fourth embodiment) In the fourth embodiment, the control circuit 74 corrects the power loss period Ts calculated in step S102. Other than this, the fourth embodiment is the same as the first embodiment.

[0147] Here, the time when the first gate voltage Vgs1 is detected by the first gate voltage detection unit 741 is defined as time xgi. The time when the first gate detection signal Sg1 corresponding to the first gate voltage Vgs1 detected by the first gate voltage detection unit 741 is output from the first gate voltage comparator 751 is defined as time xgo. As shown in the time chart of FIG. 16, time xgo occurs after time xgi. Therefore, there is a time difference between time xgi and time xgo.

[0148] Furthermore, the time when the second transformer voltage Vt2 is detected by the second transformer voltage detection unit 722 is defined as time xti. The time when the second transformer detection signal St2 corresponding to the second transformer voltage Vt2 detected by the second transformer voltage detection unit 722 is output from the second transformer voltage comparator 732 is defined as time xto. As shown in the time chart of FIG. 17, time xto occurs after time xti. Therefore, there is a time difference between time xti and time xto.

[0149] Due to these time differences, the accuracy of calculating the power loss period Ts for the first rectifying element 41 may decrease.

[0150] In contrast to this, in the fourth embodiment, in step S102, the control circuit 74 corrects the power loss period Ts(n) for the first rectifying element 41 based on the times xgi, xgo, xti, and xto.

[0151] Here, the time from time xgi to time xgo in the current control cycle is defined as Tg_delay(n), and the time from time xti to time xto in the current control cycle is defined as Tt_delay(n).

[0152] Then, for example, the control circuit 74 substitutes Tg_delay(n) and Tt_delay(n) into the following relational expression (2). As a result, the control circuit 74 corrects the power loss period Ts(n) in the current control cycle. In the following relational expression (2), Ts_C(n) is the corrected power loss period Ts in the current control cycle.

[0153] Ts_C(n)=Ts(n)+Tg_delay(n)-Tt_delay(n) ···(2)

[0154] Furthermore, the control circuit 74 uses Ts_C(n) to calculate a quantity Td(n+1) related to the off timing of the first rectifying element 41 in the next control cycle.

[0155] Furthermore, the control circuit 74 corrects the power loss period Ts(n) for the second rectifier element 42 in the same manner as described above. Specifically, in the description of the correction of the power loss period Ts(n) for the first rectifier element 41, the first gate voltage detection unit 741 is replaced with the second gate voltage detection unit 742. The first gate voltage Vgs1 is replaced with the second gate voltage Vgs2. The first gate detection signal Sg1 is replaced with the second gate detection signal Sg2. The first gate voltage comparator 751 is replaced with the second gate voltage comparator 752. The second transformer voltage detection unit 722 is replaced with the first transformer voltage detection unit 721. The second transformer voltage Vt2 is replaced with the first transformer voltage Vt1. The second transformer detection signal St2 is replaced with the first transformer detection signal St1. The second transformer voltage comparator 732 is replaced with the first transformer voltage comparator 731. The first rectifying element 41 is replaced with the second rectifying element 42 .

[0156] As described above, the control circuit 74 of the power converter 10 of the fourth embodiment corrects the power loss period Ts. The fourth embodiment also provides the same effects as the first embodiment. The first embodiment also provides the following effects.

[0157] [4] The control circuit 74 corrects the power loss period Ts for the first rectifier element 41 based on the times xgi and xgo. Note that the time xgi at this time corresponds to the time when the first gate voltage Vgs1 is detected by the detection circuit 72. The time xgo at this time corresponds to the time when the first gate detection signal Sg1 corresponding to the first gate voltage Vgs1 detected by the detection circuit 72 is output from the detection circuit 72.

[0158] Furthermore, the control circuit 74 corrects the power loss period Ts for the first rectifying element 41 based on the times xti and xto. Note that the time xti at this time corresponds to the time when the second transformer voltage Vt2 is detected by the detection circuit 72. The time xto at this time corresponds to the time when the second transformer detection signal St2 corresponding to the second transformer voltage Vt2 detected by the detection circuit 72 is output from the detection circuit 72.

[0159] This suppresses a decrease in the accuracy of calculating the power loss period Ts for the first rectifying element 41. This suppresses a decrease in the accuracy of calculating the amount Td related to the off-timing for the first rectifying element 41. This suppresses variations in the off-timing for the first rectifying element 41 in the on state. This suppresses power loss due to the first rectifying element 41.

[0160] The control circuit 74 also corrects the power loss period Ts for the second rectifier element 42 based on the times xgi and xgo. Note that the time xgi at this time corresponds to the time when the second gate voltage Vgs2 is detected by the detection circuit 72. The time xgo at this time corresponds to the time when the second gate detection signal Sg2 corresponding to the second gate voltage Vgs2 detected by the detection circuit 72 is output from the detection circuit 72.

[0161] Furthermore, the control circuit 74 corrects the power loss period Ts for the second rectifier element 42 based on the times xti and xto. Note that the time xti at this time corresponds to the time when the first transformer voltage Vt1 is detected by the detection circuit 72. The time xto at this time corresponds to the time when the first transformer detection signal St1 corresponding to the first transformer voltage Vt1 detected by the detection circuit 72 is output from the detection circuit 72.

[0162] This suppresses a decrease in the accuracy of calculating the power loss period Ts for the second rectifying element 42. This suppresses a decrease in the accuracy of calculating the amount Td related to the off-timing for the second rectifying element 42. This suppresses variations in the off-timing for the second rectifying element 42 in the on state. This suppresses power loss due to the second rectifying element 42.

[0163] (Fifth embodiment) The fifth embodiment differs from the first embodiment in the processing of the control circuit 74. Other than this, the fifth embodiment is similar to the first embodiment.

[0164] Specifically, as shown in the flowchart of FIG. 18, the control circuit 74 performs the processes from step S100 to step S104 in the same manner as in the first embodiment.

[0165] Here, if the amount Td relating to the off timing changes suddenly during a control period, the first rectifying element 41 and the second rectifying element 42 may be turned on during the on-inhibit period T_on_ban.

[0166] Therefore, in step S300 following step S104, the control circuit 74 calculates the change in the amount Td related to the off-timing. Specifically, the control circuit 74 calculates the absolute value of the difference between the amount Td(n+1) related to the next off-timing calculated in step S104 and the amount Td(n) related to the off-timing calculated in the previous control cycle. As a result, the control circuit 74 calculates the amount of change over time |ΔTd_ti(n)|.

[0167] In step S302 following step S300, the control circuit 74 determines whether the time change |ΔTd_ti(n)| calculated in step S300 is equal to or greater than a change threshold ΔTd_ti_th. This allows the control circuit 74 to determine whether the change in the amount Td related to the off-timing is abrupt. The change threshold ΔTd_ti_th is set by experiment, simulation, or the like so that it can be determined whether the change in the amount Td related to the off-timing is abrupt.

[0168] When the amount of change over time |ΔTd_ti(n)| is equal to or greater than the change threshold ΔTd_ti_th, the change in the amount Td related to the off-timing is abrupt. Therefore, at this time, the processing of the control circuit 74 proceeds to step S306. On the other hand, when the amount of change over time |ΔTd_ti(n)| is less than the change threshold ΔTd_ti_th, the change in the amount Td related to the off-timing is not abrupt. Therefore, at this time, the processing of the control circuit 74 proceeds to step S304.

[0169] In step S304 following step S302, the change in the amount Td related to the off timing is not a sudden change. Therefore, the control circuit 74 leaves the amount Td(n+1) related to the next off timing as the amount Td(n+1) related to the next off timing calculated in step S104. Thereafter, the processing of the control circuit 74 proceeds to step S106.

[0170] In step S306 following step S302, since the change in the amount Td related to the off timing is abrupt, the control circuit 74 corrects the amount Td(n+1) related to the next off timing.

[0171] Specifically, the control circuit 74 substitutes the amount Td(n) related to the off-timing calculated in the previous control cycle and the change threshold value ΔTd_ti_th into the following relational expression (3). As a result, the control circuit 74 corrects the amount Td(n+1) related to the next off-timing. At this time, two amounts Td(n+1) related to the next off-timing are calculated, and the control circuit 74 selects the amount Td(n+1) related to the next off-timing at which the first rectifying element 41 and the second rectifying element 42 are not turned on during the on-inhibit period T_on_ban. Thereafter, the process of the control circuit 74 proceeds to step S106.

[0172] Td(n+1)=Td(n)±ΔTd_ti_th ···(3)

[0173] In step S106, when turning off the first rectifying element 41 and the second rectifying element 42, the control circuit 74 outputs a signal to turn off each rectifying element based on the amount Td(n+1) related to the off timing calculated in step S304 or step S306. This prevents the first rectifying element 41 and the second rectifying element 42 from being turned on during the on-inhibit period T_on_ban.

[0174] As described above, the control circuit 74 of the power converter 10 of the fifth embodiment performs the processing. The fifth embodiment also provides the same effects as the first embodiment. The fifth embodiment also provides the following effects.

[0175] [5] The control circuit 74 corrects the amount Td related to the off timing of the first rectifying element 41 and the second rectifying element 42 when the time change amount |ΔTd_ti(n)| is equal to or greater than the change threshold value ΔTd_ti_th.

[0176] This prevents the first rectifying element 41 and the second rectifying element 42 from being turned on during the on-inhibit period T_on_ban.

[0177] (Sixth embodiment) The sixth embodiment differs from the first embodiment in the processing of the control circuit 74. Other than this, the sixth embodiment is similar to the first embodiment.

[0178] 19, the control circuit 74 performs the processes from step S100 to step S102 in the same manner as in the first embodiment. Furthermore, in step S104 following step S102, the control circuit 74 calculates a quantity Td(n+1) related to the next turn-off timing for the first rectifying element 41 in the same manner as in the first embodiment. Furthermore, the control circuit 74 calculates a quantity Td(n+1) related to the next turn-off timing for the second rectifying element 42 in the same manner as in the first embodiment.

[0179] Here, the amount Td relating to the off-timing of the first rectifying element 41 is defined as an amount Td1 relating to the first timing, and the amount Td relating to the off-timing of the second rectifying element 42 is defined as an amount Td2 relating to the second timing.

[0180] Furthermore, when the power converter 10 is normal, the first rectifying element 41 and the second rectifying element 42 are driven in the same manner, and therefore the difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing is small. However, if the difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing is large, there is a high possibility that the power converter 10 is abnormal.

[0181] Therefore, in step S400 following step S104, the control circuit 74 calculates the absolute value of the difference between the amount Td1(n+1) related to the first timing calculated in step S104 and the amount Td2(n+1) related to the second timing calculated in step S104. As a result, the control circuit 74 calculates the timing difference |ΔTd_e(n)|.

[0182] In step S402 following step S400, the control circuit 74 determines whether the timing difference |ΔTd_e(n)| calculated in step S400 is equal to or greater than a timing threshold ΔTd_e_th. This allows the control circuit 74 to determine whether the difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing is large. The timing threshold ΔTd_e_th is set by experiment, simulation, or the like so that it can be determined whether the difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing is large.

[0183] When the timing difference |ΔTd_e(n)| is less than the timing threshold value ΔTd_e_th, the difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing is small. Therefore, at this time, the processing of the control circuit 74 proceeds to step S106. In step S106, when turning off the first rectifying element 41, the control circuit 74 outputs a signal to turn off the first rectifying element 41 based on the quantity Td1(n+1) related to the first timing calculated in step S104. Furthermore, when turning off the second rectifying element 42, the control circuit 74 outputs a signal to turn off the second rectifying element 42 based on the quantity Td2(n+1) related to the second timing calculated in step S104.

[0184] Furthermore, when the timing difference |ΔTd_e(n)| is equal to or greater than the timing threshold ΔTd_e_th, the difference between the amount Td1 related to the first timing and the amount Td2 related to the second timing is large, and therefore, at this time, the process of the control circuit 74 proceeds to step S404.

[0185] In step S404 following step S402, the timing difference |ΔTd_e(n)| is equal to or greater than the timing threshold value ΔTd_e_th, indicating a large difference between the quantity Td1 related to the first timing and the quantity Td2 related to the second timing. Therefore, the control circuit 74 determines that the power converter 10 is abnormal. Furthermore, the control circuit 74 stops outputting signals that turn on and off the first transistor 301, the second transistor 302, the third transistor 303, the fourth transistor 304, the first rectifier element 41, and the second rectifier element 42. The control circuit 74 also outputs an alarm using, for example, text, sound, and light. The control circuit 74 then returns to step S100.

[0186] As described above, the control circuit 74 of the power converter 10 of the sixth embodiment performs the processing. The sixth embodiment also provides the same effects as the first embodiment. The sixth embodiment also provides the following effects.

[0187] [6] When the timing difference |ΔTd_e(n)| is equal to or greater than the timing threshold value ΔTd_e_th, the control circuit 74 determines that the power converter 10 is abnormal. This makes it possible to determine whether the power converter 10 is abnormal.

[0188] Seventh embodiment The seventh embodiment differs from the first embodiment in the processing of the control circuit 74. Other than this, the seventh embodiment is similar to the first embodiment.

[0189] Specifically, the control circuit 74 generates a plurality of clock signals with different phases. For example, as shown in FIG. 20, the control circuit 74 generates a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4.

[0190] Here, the period of the first clock signal CLK1 is Tclk. The phase difference between the first clock signal CLK1 and the second clock signal CLK2 is 1 / 4×Tclk, or 90°. The phase difference between the first clock signal CLK1 and the third clock signal CLK3 is 2 / 4×Tclk, or 180°. The phase difference between the first clock signal CLK1 and the fourth clock signal CLK4 is 3 / 4×Tclk, or 270°.

[0191] In step S100, the control circuit 74 acquires a first gate detection signal Sg1, for example, each time the voltage levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 change. In step S100, the control circuit 74 acquires a second gate detection signal Sg2 each time the voltage levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 change. In step S100, the control circuit 74 acquires a first transformer detection signal St1 each time the voltage levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 change. In step S100, the control circuit 74 acquires a second transformer detection signal St2 each time the voltage levels of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 change.

[0192] Therefore, in step S100, the control circuit 74 acquires the first gate detection signal Sg1 multiple times with shifted timing using these generated clock signals. The control circuit 74 also acquires the second gate detection signal Sg2 multiple times with shifted timing using these generated clock signals. The control circuit 74 also acquires the first transformer detection signal St1 multiple times with shifted timing using these generated clock signals. The control circuit 74 also acquires the second transformer detection signal St2 multiple times with shifted timing using these generated clock signals. The processes of steps S102 to S106 following step S100 are performed in the same manner as in the first embodiment.

[0193] As described above, the control circuit 74 of the power converter 10 of the seventh embodiment performs the processing. The seventh embodiment also provides the same effects as the first embodiment. The seventh embodiment also provides the following effects.

[0194] [7] The control circuit 74 acquires the first gate detection signal Sg1 multiple times at different timings. The control circuit 74 also acquires the second gate detection signal Sg2 multiple times at different timings. The control circuit 74 also acquires the first transformer detection signal St1 multiple times at different timings. The control circuit 74 also acquires the second transformer detection signal St2 multiple times at different timings.

[0195] This improves the time resolution of the control circuit 74 when acquiring the first gate detection signal Sg1, the second gate detection signal Sg2, the first transformer detection signal St1, and the second transformer detection signal St2. This reduces the accuracy degradation of the first gate detection signal Sg1, the second gate detection signal Sg2, the first transformer detection signal St1, and the second transformer detection signal St2. This reduces the accuracy degradation of the calculation of the power loss period Ts calculated using the first gate detection signal Sg1, the second gate detection signal Sg2, the first transformer detection signal St1, and the second transformer detection signal St2. This reduces the accuracy degradation of the calculation of the amount Td related to the off-timing.

[0196] (Eighth embodiment) The eighth embodiment differs from the first embodiment in the form of the detection circuit 72. Also, the processing of the control circuit 74 differs from the first embodiment. Other than these, the eighth embodiment is similar to the first embodiment.

[0197] 21, the detection circuit 72 detects the second transformer voltage Vt2 and the first gate voltage Vgs1, but does not detect the first transformer voltage Vt1 and the second gate voltage Vgs2. Therefore, the detection circuit 72 does not include a first transformer voltage detection unit 721, a first transformer voltage comparator 731, a second gate voltage detection unit 742, or a second gate voltage comparator 752.

[0198] Here, because the detection circuit 72 does not detect the first transformer voltage Vt1 and the second gate voltage Vgs2, it is not possible to calculate the amount Td related to the off-timing of the second rectifier element 42 using the first transformer voltage Vt1 and the second gate voltage Vgs2. However, as described above, the difference between the amount Td related to the off-timing of the first rectifier element 41 and the amount Td related to the off-timing of the second rectifier element 42 is small. Therefore, the amount Td related to the off-timing of the first rectifier element 41 and the amount Td related to the off-timing of the second rectifier element 42 are approximately the same.

[0199] Therefore, when turning off the second rectifying element 42 in step S106, the control circuit 74 outputs a signal to turn off the second rectifying element 42 based on the amount Td related to the timing at which the first rectifying element 41 is turned off.

[0200] As described above, the power converter 10 of the eighth embodiment is configured, and the control circuit 74 performs processing. The eighth embodiment also provides the same effects as the first embodiment.

[0201] (Ninth embodiment) The ninth embodiment differs from the first embodiment in the form of the detection circuit 72. Also, the processing of the control circuit 74 differs from the first embodiment. Other than these, the ninth embodiment is similar to the first embodiment.

[0202] 22, the detection circuit 72 detects the first transformer voltage Vt1 and the second gate voltage Vgs2, but does not detect the second transformer voltage Vt2 and the first gate voltage Vgs1. Therefore, the detection circuit 72 does not include a second transformer voltage detection unit 722, a second transformer voltage comparator 732, a first gate voltage detection unit 741, or a first gate voltage comparator 751.

[0203] Here, because the detection circuit 72 does not detect the second transformer voltage Vt2 and the first gate voltage Vgs1, it is not possible to use the second transformer voltage Vt2 and the first gate voltage Vgs1 to calculate the amount Td related to the off-timing of the first rectifier element 41. However, as described above, the amount Td related to the off-timing of the first rectifier element 41 and the amount Td related to the off-timing of the second rectifier element 42 are substantially the same.

[0204] Therefore, when turning off the first rectifying element 41 in step S106, the control circuit 74 outputs a signal to turn off the first rectifying element 41 based on the amount Td related to the turn-off timing of the second rectifying element .

[0205] As described above, the power converter 10 of the ninth embodiment is configured, and the control circuit 74 performs processing. The ninth embodiment also provides the same effects as the first embodiment.

[0206] (Tenth embodiment) The tenth embodiment differs from the first embodiment in the configuration of the detection circuit 72. Also, the processing of the control circuit 74 differs from the first embodiment. Other than these, the tenth embodiment is similar to the first embodiment.

[0207] 23, the detection circuit 72 detects the first transformer voltage Vt1 and the first gate voltage Vgs1, but does not detect the second transformer voltage Vt2 and the second gate voltage Vgs2. Therefore, the detection circuit 72 does not include a second transformer voltage detection unit 722, a second transformer voltage comparator 732, a second gate voltage detection unit 742, or a second gate voltage comparator 752.

[0208] Here, because the detection circuit 72 does not detect the second transformer voltage Vt2, it is not possible to calculate the amount Td related to the off-timing of the first rectifier element 41 using the second transformer voltage Vt2 and the first gate voltage Vgs1. However, the second transformer voltage Vt2 is a voltage whose positive and negative polarities are different from those of the first transformer voltage Vt1. Furthermore, the absolute value of the second transformer voltage Vt2 is the same as the absolute value of the first transformer voltage Vt1.

[0209] For this reason, the detection circuit 72 has a NOT circuit or the like (not shown) to invert the polarity of the first transformer voltage Vt1, so that the first transformer detection signal St1 output from the detection circuit 72 becomes the same as the second transformer detection signal St2.

[0210] Therefore, in step S102, the control circuit 74 calculates the power loss period Ts for the first rectifying element 41 based on the first transformer detection signal St1 and the first gate detection signal Sg1. Furthermore, in step S104, the control circuit 74 calculates a quantity Td related to the off-timing for the first rectifying element 41 based on the calculated power loss period Ts for the first rectifying element 41. Therefore, in step S106, when turning off the first rectifying element 41, the control circuit 74 outputs a signal to turn off the first rectifying element 41 based on the calculated quantity Td related to the off-timing for the first rectifying element 41.

[0211] Furthermore, as described above, the amount Td relating to the off timing of the first rectifying element 41 and the amount Td relating to the off timing of the second rectifying element 42 are substantially the same.

[0212] Therefore, in step S106, when turning off the second rectifying element 42, the control circuit 74 outputs a signal to turn off the second rectifying element 42 based on the amount Td related to the off timing for the first rectifying element 41 calculated as above.

[0213] As described above, the power converter 10 of the tenth embodiment is configured, and the control circuit 74 performs processing. The tenth embodiment also provides the same effects as the first embodiment.

[0214] (Eleventh embodiment) The eleventh embodiment differs from the first embodiment in the form of the detection circuit 72. Also, the processing of the control circuit 74 differs from the first embodiment. Other than these, the eleventh embodiment is similar to the first embodiment.

[0215] 24, the detection circuit 72 detects the second transformer voltage Vt2 and the second gate voltage Vgs2, but does not detect the first transformer voltage Vt1 and the first gate voltage Vgs1. Therefore, the detection circuit 72 does not include a first transformer voltage detection unit 721, a first transformer voltage comparator 731, a first gate voltage detection unit 741, or a first gate voltage comparator 751.

[0216] As described above, the first transformer voltage Vt1 is a voltage whose positive and negative polarities are different from those of the second transformer voltage Vt2. Furthermore, the absolute value of the first transformer voltage Vt1 is the same as the absolute value of the second transformer voltage Vt2.

[0217] For this reason, the detection circuit 72 has a NOT circuit or the like (not shown) to invert the polarity of the second transformer voltage Vt2, so that the second transformer detection signal St2 output from the detection circuit 72 becomes the same as the first transformer detection signal St1.

[0218] Therefore, in step S102, the control circuit 74 calculates the power loss period Ts for the second rectifying element 42 based on the second transformer detection signal St2 and the second gate detection signal Sg2. Furthermore, in step S104, the control circuit 74 calculates a quantity Td related to the off-timing for the second rectifying element 42 based on the calculated power loss period Ts for the second rectifying element 42. Therefore, in step S106, when turning off the second rectifying element 42, the control circuit 74 outputs a signal to turn off the second rectifying element 42 based on the calculated quantity Td related to the off-timing for the second rectifying element 42.

[0219] Furthermore, as described above, the amount Td relating to the off timing of the first rectifying element 41 and the amount Td relating to the off timing of the second rectifying element 42 are substantially the same.

[0220] Therefore, when the control circuit 74 turns off the first rectifying element 41 in step S106, the control circuit 74 outputs a signal to turn off the first rectifying element 41 based on the amount Td related to the off timing for the second rectifying element 42 calculated above.

[0221] As described above, the power converter 10 of the eleventh embodiment is configured, and the control circuit 74 performs processing. In the eleventh embodiment, the same effects as in the first embodiment are achieved.

[0222] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, it goes without saying that the elements constituting the embodiments in the above-described embodiments are not necessarily essential unless they are specifically stated as essential or are considered to be clearly essential in principle.

[0223] The detection unit, control unit, and methods described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the detection unit, control unit, and methods described herein may be implemented by a special-purpose computer configured with a processor configured with one or more dedicated hardware logic circuits. Alternatively, the detection unit, control unit, and methods described herein may be implemented by one or more special-purpose computers configured with a processor and memory programmed to perform one or more functions in combination with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium.

[0224] In each of the above embodiments, the power converter 10 is a DC-DC converter for a vehicle. However, the power converter 10 is not limited to being used in a vehicle, and may be used in, for example, equipment or the like.

[0225] In each of the above embodiments, the conversion circuit 30 is a full-bridge inverter circuit. However, the conversion circuit 30 is not limited to being a full-bridge inverter circuit, and may be a push-pull inverter circuit, a half-bridge inverter circuit, or the like.

[0226] In each of the above embodiments, the first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304 are FETs. However, the first transistor 301, the second transistor 302, the third transistor 303, and the fourth transistor 304 are not limited to FETs and may be IGBTs or the like. IGBT stands for Insulated Gate Bipolar Transistor.

[0227] In each of the above embodiments, the transformer 34 steps down the AC voltage from the conversion circuit 30. However, the transformer 34 may step up the AC voltage from the conversion circuit 30.

[0228] In each of the above embodiments, the first rectifying element 41 and the second rectifying element 42 are transistors, i.e., FETs. However, the first rectifying element 41 and the second rectifying element 42 are not limited to FETs and may be transistors such as IGBTs.

[0229] In each of the above embodiments, the control circuit 74 calculates the amount Td related to the off-timing of each rectifying element based on the voltage between the transformer 34 and each rectifying element and the gate voltage of each rectifying element. Alternatively, the control circuit 74 may calculate the amount Td related to the off-timing of each rectifying element based only on the voltage between the transformer 34 and each rectifying element. For example, the control circuit 74 calculates the amount Td related to the off-timing of each rectifying element as the period from when a signal is output to switch each rectifying element from off to on to when the voltage between the transformer 34 and each rectifying element becomes equal to or greater than the transformer voltage threshold Vt_th. This allows the control circuit 74 to calculate the amount Td related to the off-timing of each rectifying element without using the gate voltage of each rectifying element.

[0230] In each of the above embodiments, the number of rectifying elements is 2. However, the number of rectifying elements may be 1, or 3 or more.

[0231] In each of the above embodiments, the main circuit 20 includes the magnetic component 32. However, the main circuit 20 does not necessarily need to include the magnetic component 32.

[0232] The above embodiments may be combined as appropriate.

[0233] (Aspects of the present disclosure) [Point 1] a converter (30) that converts a DC voltage from a DC power supply (12) into an AC voltage; a transformer (34) that steps up and down the AC voltage; rectifying elements (41, 42) which are transistors and rectify the current of the AC voltage stepped up or down by the transformer; a detection unit (72) for detecting a transformer voltage (Vt1, Vt2) between the transformer and the rectifying element; a control unit (74) that turns off the rectifying elements that are in an on state based on the transformer voltage; A power converter comprising: [Point 2] the detection unit detects gate voltages (Vgs1, Vgs2) of the rectifying elements, The power converter according to aspect 1, wherein the control unit calculates quantities (Td, Td1, Td2) related to off timing, which is the timing to turn off the rectifying elements in an on state, based on the gate voltage and the transformer voltage, and turns off the rectifying elements in an on state based on the calculated quantities related to the off timing. [Point 3] The power converter according to aspect 2, wherein the control unit calculates the quantity related to the off timing based on a power loss period (Ts), which is the period from when the gate voltage changes from equal to or greater than a gate voltage threshold (Vgs1_th, Vgs2_th) to less than the gate voltage threshold, to when the absolute value of the transformer voltage changes from less than a transformer voltage threshold (Vt1_th, Vt2_th) to equal to or greater than the transformer voltage threshold. [Point 4] The control unit calculating an amount related to the next off-timing based on the power loss period at the current time and the previous period and the amount related to the off-timing at the current time and the previous period; The power converter according to Aspect 3, wherein the rectifying elements that are in an on state at the next time are turned off based on the calculated amount related to the next off timing. [Point 5] The power converter according to aspect 4, wherein the control unit corrects the amount related to the next off timing when the absolute value (|ΔTd_ti(n)|) of the difference between the amount related to the next off timing and the amount related to the off timing before the current time is greater than or equal to a change threshold (ΔTd_ti_th). [Point 6] The control unit outputting a signal for driving the conversion unit and a signal for turning on and off the rectifying element; A power converter according to any one of aspects 3 to 5, wherein the power loss period is calculated using the gate voltage during a period (Te_g) based on a change in the level of a signal that drives the conversion unit and a change in the level of a signal that turns the rectifying element on and off. [Point 7] The power converter according to aspect 6, wherein the control unit determines that the power converter is abnormal when the gate voltage does not change from above the gate voltage threshold to below the gate voltage threshold during a period based on changes in the signal that drives the conversion unit and changes in the signal that turns the rectifying element on and off. [Point 8] The conversion unit includes a transistor (304), the transistor of the conversion unit converts the DC voltage from the DC power supply into an AC voltage by being turned on and off; the control unit outputs a signal that turns on and off a transistor of the conversion unit; The power converter according to aspect 6 or 7, wherein the period based on the change in the level of the signal that drives the conversion unit and the change in the level of the signal that turns the rectifying element on and off is the period from when the control unit outputs a signal that turns the rectifying element from on to off to when the control unit outputs a signal that turns the transistor of the conversion unit from off to on. [Point 9] The control unit outputting a signal to drive the conversion unit; The power converter according to any one of Aspects 3 to 5, wherein the power loss period is calculated using the transformer voltage in a period (Te_t) based on a change in the level of a signal that drives the conversion unit. [Point 10] The power converter according to aspect 9, wherein the control unit determines that the power converter is abnormal when the transformer voltage does not change from below the transformer voltage threshold to above the transformer voltage threshold during a period based on a change in the level of the signal that drives the conversion unit. [Point 11] The conversion unit includes a first transistor (301) and a second transistor (304), the first transistor and the second transistor are turned on and off to convert a DC voltage from the DC power supply into an AC voltage; the control unit outputs signals that turn on and off the first transistor and the second transistor; The power converter according to aspect 9 or 10, wherein the period based on the change in the level of the signal that drives the conversion unit is the period from when the control unit outputs a signal that changes the first transistor from on to off to when the control unit outputs a signal that changes the second transistor from off to on. [Point 12] The control unit In a period based on a change in the level of the signal that drives the conversion unit, there are a plurality of times when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold. The power converter according to any one of aspects 9 to 11, wherein the power loss period is calculated using the time (xe) when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold, which is the longest time, among a plurality of times, when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold, and then changes from equal to or greater than the transformer voltage threshold to less than the transformer voltage threshold. [Point 13] The control unit In a period based on a change in the level of the signal that drives the conversion unit, there are a plurality of times when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold. selecting, from among the plurality of times, a time when the time from when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold to when the absolute value of the transformer voltage changes from equal to or greater than the transformer voltage threshold to less than the transformer voltage threshold is longer than a resonance period (Tr) set by the inductance of the transformer and the capacitance of the rectifying element; 12. The power converter according to any one of Aspects 9 to 11, wherein the power loss period is calculated using the earliest time (xe) among the selected times. [Point 14] The detection unit outputting gate detection signals (Sg1, Sg2) corresponding to the gate voltage to the control unit; When the gate voltage changes from equal to or greater than the gate voltage threshold to less than the gate voltage threshold, a level of the gate detection signal is changed; A power converter according to any one of aspects 3 to 13, wherein the control unit corrects the power loss period based on the time (xgi) at which the gate voltage is detected by the detection unit and the time (xgo) at which the gate detection signal corresponding to the gate voltage detected by the detection unit is output from the detection unit. [Point 15] The detection unit outputting a transformer detection signal (St1, St2) corresponding to the transformer voltage to the control unit; When the transformer voltage changes from less than the transformer voltage threshold to greater than or equal to the transformer voltage threshold, a level of the transformer detection signal is changed; The power converter according to any one of Aspects 3 to 14, wherein the control unit corrects the power loss period based on the time (xti) at which the transformer voltage is detected by the detection unit and the time (xto) at which the transformer detection signal corresponding to the transformer voltage detected by the detection unit is output from the detection unit. [Point 16] The detection unit outputting gate detection signals (Sg1, Sg2) corresponding to the gate voltage to the control unit; When the gate voltage changes from equal to or greater than the gate voltage threshold to less than the gate voltage threshold, a level of the gate detection signal is changed; 14. The power converter according to any one of Aspects 3 to 13, wherein the control unit acquires the gate detection signal a plurality of times at different timings. [Point 17] The detection unit outputting a transformer detection signal (St1, St2) corresponding to the transformer voltage to the control unit; When the transformer voltage changes from less than the transformer voltage threshold to greater than or equal to the transformer voltage threshold, a level of the transformer detection signal is changed; 14. The power converter according to any one of Aspects 3 to 13, wherein the control unit acquires the transformer detection signal a plurality of times at different timings. [Point 18] The rectifying element is a first rectifying element (41), The gate voltage is a first gate voltage (Vgs1), the amount related to the off-timing is an amount related to a first timing (Td1), the power converter includes a second rectifying element (42); the second rectifying element is a transistor that rectifies the current of the AC voltage stepped up or down by the transformer; the detection unit detects a second gate voltage (Vgs2) of the second rectifier element, The power converter according to any one of Aspects 2 to 17, wherein the control unit calculates a quantity (Td2) related to a second timing, which is the timing to turn off the second rectifier element in an on state, based on the second gate voltage and the transformer voltage, and turns off the second rectifier element in an on state based on the calculated quantity related to the second timing. [Point 19] The power converter according to aspect 18, wherein the control unit determines that the power converter is abnormal when the absolute value (|ΔTd_e(n)|) of the difference between the quantity related to the first timing and the quantity related to the second timing is greater than or equal to a timing threshold (ΔTd_e_th). [Explanation of symbols]

[0234] 10 Power Converter 30 Conversion circuit 32 Magnetic Components 34 Transformer 41 First rectifying element 42 Second rectifying element 72 Detection circuit 74 Control Circuit

Claims

1. A converter (30) that converts a DC voltage from a DC power source (12) into an AC voltage; a transformer (34) for stepping up and down the AC voltage; a rectifying element (41, 42) which is a transistor and rectifies the current of the AC voltage stepped up or down by the transformer; a detection unit (72) for detecting a transformer voltage (Vt1, Vt2) between the transformer and the rectifying element; a control unit (74) that turns off the rectifying element that is in an on state based on the transformer voltage; A power converter comprising:

2. the detection unit detects gate voltages (Vgs1, Vgs2) of the rectifying elements, 2. The power converter according to claim 1, wherein the control unit calculates amounts (Td, Td1, Td2) related to off timing, which is a timing for turning off the rectifying elements in an on state, based on the gate voltage and the transformer voltage, and turns off the rectifying elements in an on state based on the calculated amounts related to the off timing.

3. 3. The power converter according to claim 2, wherein the control unit calculates the amount related to the off-timing based on a power loss period (Ts), which is a period from when the gate voltage changes from equal to or greater than a gate voltage threshold (Vgs1_th, Vgs2_th) to less than the gate voltage threshold, to when the absolute value of the transformer voltage changes from less than a transformer voltage threshold (Vt1_th, Vt2_th) to equal to or greater than the transformer voltage threshold.

4. The control unit calculating an amount related to the next off-timing based on the power loss period at the current time and the previous period and the amount related to the off-timing at the current time and the previous period; The power converter according to claim 3 , wherein the rectifying elements that are in an on state at the next time are turned off based on the calculated amount related to the next off timing.

5. The power converter according to claim 4, wherein the control unit corrects the amount related to the next off timing when the absolute value (|ΔTd_ti(n)|) of the difference between the amount related to the next off timing and the amount related to the off timing at the current time and the time before the current time is greater than or equal to a change threshold (ΔTd_ti_th).

6. The control unit outputting a signal for driving the conversion unit and a signal for turning on and off the rectifying element; 6. The power converter according to claim 3, wherein the power loss period is calculated using the gate voltage during a period (Te_g) based on a change in the level of a signal that drives the conversion unit and a change in the level of a signal that turns the rectifying element on and off.

7. 7. The power converter according to claim 6, wherein the control unit determines that the power converter is abnormal when the gate voltage does not change from equal to or greater than the gate voltage threshold to less than the gate voltage threshold during a period based on a change in a signal that drives the conversion unit and a change in a signal that turns the rectifying element on and off.

8. The conversion unit includes a transistor (304), the transistor of the conversion unit converts the DC voltage from the DC power supply into an AC voltage by being turned on and off; the control unit outputs a signal that turns on and off a transistor of the conversion unit; 7. The power converter according to claim 6, wherein the period based on the change in the level of the signal that drives the conversion unit and the change in the level of the signal that turns the rectifying element on and off is the period from when the control unit outputs a signal that turns the rectifying element from on to off to when the control unit outputs a signal that turns a transistor of the conversion unit from off to on.

9. The control unit outputting a signal to drive the conversion unit; 6. The power converter according to claim 3, wherein the power loss period is calculated using the transformer voltage during a period (Te_t) based on a change in the level of a signal that drives the conversion unit.

10. The power converter according to claim 9, wherein the control unit determines that the power converter is abnormal when the transformer voltage does not change from less than the transformer voltage threshold to greater than or equal to the transformer voltage threshold during a period based on a change in the level of the signal that drives the conversion unit.

11. The conversion unit includes a first transistor (301) and a second transistor (304), the first transistor and the second transistor are turned on and off to convert a DC voltage from the DC power supply into an AC voltage; the control unit outputs signals that turn on and off the first transistor and the second transistor; 10. The power converter according to claim 9, wherein the period based on a change in the level of the signal that drives the conversion unit is a period from when the control unit outputs a signal that causes the first transistor to change from on to off to when the control unit outputs a signal that causes the second transistor to change from off to on.

12. The control unit In a period based on a change in the level of the signal that drives the conversion unit, there are a plurality of times when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold.

10. The power converter according to claim 9, wherein the power loss period is calculated using a time (xe) when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold, when the time when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold is the longest among a plurality of times.

13. The control unit In a period based on a change in the level of the signal that drives the conversion unit, there are a plurality of times when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold. selecting, from among the plurality of times, a time when the time from when the absolute value of the transformer voltage changes from less than the transformer voltage threshold to equal to or greater than the transformer voltage threshold to when the absolute value of the transformer voltage changes from equal to or greater than the transformer voltage threshold to less than the transformer voltage threshold is longer than a resonance period (Tr) set by the inductance of the transformer and the capacitance of the rectifying element; The power converter according to claim 9 , wherein the power loss period is calculated using the earliest time (xe) among the selected times.

14. The detection unit outputting gate detection signals (Sg1, Sg2) corresponding to the gate voltage to the control unit; When the gate voltage changes from equal to or greater than the gate voltage threshold to less than the gate voltage threshold, a level of the gate detection signal is changed; 4. The power converter according to claim 3, wherein the control unit corrects the power loss period based on the time (xgi) at which the gate voltage is detected by the detection unit and the time (xgo) at which the gate detection signal corresponding to the gate voltage detected by the detection unit is output from the detection unit.

15. The detection unit outputting transformer detection signals (St1, St2) corresponding to the transformer voltage to the control unit; When the transformer voltage changes from less than the transformer voltage threshold to greater than or equal to the transformer voltage threshold, a level of the transformer detection signal is changed; 4. The power converter according to claim 3, wherein the control unit corrects the power loss period based on a time (xti) at which the transformer voltage is detected by the detection unit and a time (xto) at which the transformer detection signal corresponding to the transformer voltage detected by the detection unit is output from the detection unit.

16. The detection unit outputting gate detection signals (Sg1, Sg2) corresponding to the gate voltage to the control unit; When the gate voltage changes from equal to or greater than the gate voltage threshold to less than the gate voltage threshold, a level of the gate detection signal is changed; The power converter according to claim 3 , wherein the control unit acquires the gate detection signal a plurality of times at different timings.

17. The detection unit outputting transformer detection signals (St1, St2) corresponding to the transformer voltage to the control unit; When the transformer voltage changes from less than the transformer voltage threshold to greater than or equal to the transformer voltage threshold, a level of the transformer detection signal is changed; The power converter according to claim 3 , wherein the control unit acquires the transformer detection signal a plurality of times at different timings.

18. The rectifying element is a first rectifying element (41), The gate voltage is a first gate voltage (Vgs1), The amount related to the off timing is an amount related to a first timing (Td1), The power converter includes a second rectifying element (42); the second rectifying element is a transistor that rectifies the current of the AC voltage stepped up or down by the transformer; the detection unit detects a second gate voltage (Vgs2) of the second rectifying element, 3. The power converter according to claim 2, wherein the control unit calculates a quantity (Td2) related to a second timing, which is a timing for turning off the second rectifier element in an on state, based on the second gate voltage and the transformer voltage, and turns off the second rectifier element in an on state based on the calculated quantity related to the second timing.

19. 19. The power converter according to claim 18, wherein the control unit determines that the power converter is abnormal when an absolute value (|ΔTd_e(n)|) of a difference between a quantity related to the first timing and a quantity related to the second timing is equal to or greater than a timing threshold (ΔTd_e_th).

Images