Image forming apparatus

Abstract

To reduce the influence of coupling noise without requiring complicated control while achieving miniaturization.SOLUTION: A period in which the charge voltage generation circuit 132b is controlled to output - 1000V and the developing voltage generation circuit 133b is controlled to output - 450V is defined as a period I, a period after the period I is defined as a period II, a period after the period II in which the charge voltage generation circuit 132b is controlled to output - 1000V and the developing voltage generation circuit 133b is controlled to output - 450V is defined as a period III, and a difference between the cycle of PRI _ VOL _ CONT and the cycle of DEV _ VOL _ CONT in the period I is defined as Δ 3, the difference between the cycle of PRI _ VOL _ CONT and the cycle of DEV _ VOL _ CONT in the period III is represented by Δ 4, and the controller 200 controls the charging-voltage generation circuit 132b and the developing-voltage generation circuit 133b so that the absolute difference between Δ 3 and Δ 4 is smaller than a predetermined value in the period III.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an image forming apparatus. [Background technology]

[0002] In Patent Document 1, as a countermeasure against coupling noise generated from a control signal line, a clock signal having an opposite phase to the clock signal that causes noise is supplied. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-267024 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional examples, supplying an opposite-phase clock signal to counter coupling noise requires an increase in the number of signal lines, electrodes, and circuits, which hinders miniaturization. Also, control is required to match the frequency and duty of the clock signal and the opposite-phase clock signal, which complicates control when applied to a circuit that requires changing the duty of the control signal according to the output.

[0005] The present invention has been made under these circumstances, and has as its object to reduce the influence of coupling noise without requiring complex control while realizing miniaturization. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention has the following configuration.

[0007] (1) A power supply includes a first voltage generating circuit that outputs a first voltage, a first member to which the first voltage is applied, a second voltage generating circuit that outputs a second voltage, a second member to which the second voltage is applied, and a control unit that outputs a first signal to control the first voltage generating circuit so that the first voltage generating circuit outputs a first target voltage, and outputs a second signal to control the second voltage generating circuit so that the second voltage generating circuit outputs a second target voltage, wherein a period during which the first voltage generating circuit is controlled to output the first target voltage and the second voltage generating circuit is controlled to output the second target voltage is defined as a first period, and a period after the first period is defined as a second period. a second period is a period after the second period during which the first voltage generation circuit is controlled to output the first target voltage and the second voltage generation circuit is controlled to output the second target voltage, a first value is a difference between the period of the first signal and the period of the second signal during the first period, and a second value is a difference between the period of the first signal and the period of the second signal during the third period, and the control unit controls the first voltage generation circuit and the second voltage generation circuit during the third period so that the absolute value of the difference between the first value and the second value is smaller than a predetermined threshold.

[0008] (2) An image forming apparatus comprising: a voltage generating circuit that outputs an output voltage; a member to which the output voltage is applied; a control unit that outputs a control signal to control the voltage generating circuit so that the voltage generating circuit outputs a target voltage; and a detection circuit that inputs an input signal to the control unit according to a current flowing through the member; wherein a period during which the voltage generating circuit is controlled to output the target voltage is defined as a first period, a period following the first period is defined as a second period, and a period following the second period during which the voltage generating circuit is controlled to output the target voltage is defined as a third period; the control unit detects the current by sampling the input signal input from the detection circuit at a sampling period; a first value is a difference between the period of the control signal and the sampling period during the first period; a second value is a difference between the period of the control signal and the sampling period during the third period; and the control unit controls the voltage generating circuit so that the absolute value of the difference between the first value and the second value during the third period is smaller than a predetermined threshold value. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce the influence of coupling noise without requiring complex control while realizing miniaturization. [Brief explanation of the drawings]

[0010] [Figure 1] Schematic cross-sectional view of the image forming apparatus according to the first and second embodiments. [Figure 2] Circuit diagram of the imaging unit in Examples 1 and 2 [Figure 3] Circuit diagram of the imaging unit in Examples 1 and 2 [Figure 4] FIG. 1 is a block diagram showing the configuration of a control device according to a first embodiment. [Figure 5] 1 is a waveform diagram showing the operational relationship when the control of the first embodiment is not performed. [Figure 6] Waveform diagram showing the effect when the control of the first embodiment is performed [Figure 7] A block diagram showing the configuration of a control device according to a second embodiment. [Figure 8]10 is a waveform diagram showing the operational relationship when the control of the second embodiment is not performed. [Figure 9] Waveform diagram showing the effect when the control of the second embodiment is performed DETAILED DESCRIPTION OF THE INVENTION [Example]

[0011] A first embodiment of the present invention will be described.

[0012] (Configuration of image forming device) FIG. 1 shows a cross-sectional view of an image forming apparatus 101. A paper feed unit 102 has a paper feed tray 121 and a paper feed roller 122. Paper P, which is a recording material to be printed, is stored in the paper feed tray 121. The image forming unit 103 is composed of a photosensitive drum 131 as a photosensitive member, a charging roller 132a, a developing roller 133a, a toner supply roller 134a, a developing blade 135a, a toner container 136, a laser scanner 137, and the like. A high voltage generated by a charging voltage generating circuit 132b as a first voltage generating circuit can be applied to the charging roller 132a as a first member. Similarly, a high voltage generated by a developing voltage generating circuit 133b as a second voltage generating circuit can be applied to the developing roller 133a as a second member. A high voltage generated by a toner supply roller circuit 134b (a third voltage generating circuit) can be applied to the toner supply roller 134a, and a high voltage generated by a blade circuit 135b (a fourth voltage generating circuit) can be applied to the developing blade 135a. A charging current detection circuit 132c is connected in series to the charging voltage generation circuit 132b, allowing the current flowing through the charging roller 132a to be detected. The transfer unit 104 has a transfer roller 141a, and can apply a high voltage generated by a positive transfer circuit 141b and a negative transfer circuit 141c connected in series with the positive transfer circuit 141b. Here, the negative transfer circuit 141c may be connected in parallel with the positive transfer circuit 141b, and its connection to the transfer roller 141a may be switched by a switch, or the negative transfer circuit 141c may not even be necessary. The transfer roller 141a is in opposing contact with the photosensitive drum 131. The fixing unit 105 has a fixing roller 151 and a pressure roller 152. The discharge unit 106 includes discharge rollers 161 a and 161 b and a discharge tray 162 .

[0013] (Operation of image forming device) First, the operation of forming a toner image on the surface of the photosensitive drum 131 by the image forming unit 103 will be described. The charging roller 132a, to which a negative high voltage is applied from the charging voltage generation circuit 132b, uniformly charges the surface of the photosensitive drum 131. The charging process in the first embodiment employs a roller charging method. The charging roller 132a and the photosensitive drum 131 face each other with a small gap between them, and the surface of the photosensitive drum 131 is charged by utilizing discharge across the gap. The laser scanner 137 irradiates the photosensitive drum 131 with a laser according to image data, forming a latent image on the surface of the photosensitive drum 131. The toner stored in the toner container 136 is negatively charged by stirring. The toner is moved to the surface of the developing roller 133a by the toner supply roller 134a, to which a negative high voltage is applied from the toner supply roller circuit 134b, and adheres to the surface. Because the toner adhering to the surface of the developing roller 133a varies in height from place to place, the developing blade 135a, to which a negative high voltage is applied by the blade circuit 135b, smooths it out evenly, i.e., regulates the amount of toner. The developing roller 133a, with toner adhering to its surface, uses the negative high voltage applied from the developing voltage generation circuit 133b to move the toner to the surface of the photosensitive drum 131, thereby developing the latent image carried by the developing roller 133a. By setting the output voltage of the toner supply roller circuit 134b to have a larger absolute value than the output voltage of the developing voltage generation circuit 133b, the negatively charged toner is more likely to move to the developing roller 133a. Furthermore, by setting the output voltage of the blade circuit 135b to have a larger absolute value than the output voltage of the developing voltage generation circuit 133b, the negatively charged toner is less likely to adhere to the developing blade 135a. For example, the output voltage of the developing voltage generating circuit 133b is set to −300V, and the output voltages of the toner supply roller circuit 134b and the blade circuit 135b are set to −400V.

[0014] Next, the operation of forming an image on paper P will be described. When image forming apparatus 101 receives a print job, each roller and laser scanner 137 start operating. Paper P stored in paper feed tray 121 is fed by paper feed roller 122, passes through conveyance path 111, and eventually reaches a position (transfer position) where photosensitive drum 131 and transfer roller 141a face each other. Paper P is nipped by photosensitive drum 131 and transfer roller 141a, to which a positive high voltage is applied from positive transfer circuit 141b, and at this time, the toner image formed on the surface of photosensitive drum 131 is transferred to paper P. As paper P continues to be conveyed, it next reaches fixing unit 105, where it is pressure-nipped by fixing roller 151 and pressure roller 152, and the toner image is fixed to paper P. Thereafter, paper P is discharged to discharge tray 162 via discharge rollers 161a and 161b. Note that the image forming apparatus to which the present invention can be applied is not limited to the configuration shown in FIG. 1.

[0015] (Configuration and operation of charging voltage generation circuit and developing voltage generation circuit) The configurations and operations of the charging voltage generation circuit 132b and the developing voltage generation circuit 133b in the image forming unit 103 will be described with reference to Figures 2, 3, and 4. The transformer T11 has a primary winding T11-1 and a secondary winding T11-2. One terminal of the primary winding T11-1 is connected to a power supply voltage V1, and the other terminal is connected to the drain terminal of a field effect transistor (hereinafter referred to as FET) 11. A resistor R12 is connected between the gate terminal and the source terminal of the FET 11, and the gate terminal is connected to the CLK terminal of the control unit 200 via a resistor R17. A parallel circuit of a capacitor C11 and a resistor R11 and a diode D11 are connected in series between both terminals of the primary winding T11-1.

[0016] Meanwhile, a diode D12 and a capacitor C12 are connected between both terminals of the secondary winding T11-2. The cathode of the diode D12 is connected to one terminal of the secondary winding T11-2 of the transformer T11, the anode of the diode D12 is connected to one terminal of the capacitor C12, and the other terminal of the capacitor C12 is connected to the charging current detection circuit 132c. The power supply voltage V1 in the first embodiment is 24 V.

[0017] The control unit 200 has a CLK terminal, a PRI_VOL_CONT terminal, a PRI_CUR_AD terminal, and a PRI_CUR_CONT terminal. The analog voltage value input to the PRI_CUR_AD terminal is converted to a digital value. When a high-level signal is output from the CLK terminal of the control unit 200, the FET 11 turns on, and the drain voltage of the FET 11 drops to approximately the same potential as GND (ground). This applies a voltage across the primary winding T11-1 of the transformer T11, causing an excitation current to flow. In this state, when the voltage output from the CLK terminal changes to a low level, the FET 11 turns off, and a flyback voltage is generated across the primary winding T11-1. At the same time, a flyback voltage proportional to the turns ratio between the primary winding T11-1 and the secondary winding T11-2 is generated in the secondary winding T11-2. This voltage is rectified and smoothed by the diode D12 and the capacitor C12, generating the charging voltage Vpri. The charging voltage Vpri is applied to the charging roller 132a via a resistor R132.

[0018] The voltage output from the CLK terminal of the control unit 200 is a square wave in which high and low levels alternate. In the first embodiment, a fixed square wave with a frequency of 50 kHz and a duty (proportion of high level time per cycle) of 10% is output from the CLK terminal. Note that the frequency and duty of the square wave should be designed to optimal values ​​for each circuit, and the values ​​in the first embodiment are merely an example. Furthermore, they do not have to be fixed values ​​and may be variable depending on the configuration of the controlled object.

[0019] The charge voltage generating circuit 132b feeds back the charge voltage Vpri to a comparator, IC11, to stabilize and control the output charge voltage Vpri to a desired voltage. The charge voltage Vpri is connected to a power supply voltage V2 via resistors R14 and R13. The connection point between resistors R14 and R13 is connected to the positive input terminal (+ terminal, non-inverting input terminal) of the comparator IC11. The negative input terminal (- terminal, inverting input terminal) of the comparator IC11 is connected to the power supply voltage V2 via resistors R16 and R15, and is further connected to GND via a capacitor C16. The connection point between resistors R15 and R16 is connected to the PRI_VOL_CONT terminal of the control unit 200.

[0020] The output terminal of comparator IC11 is connected to the gate terminal of FET11. The PRI_VOL_CONT terminal outputs a pulse signal as a first signal that alternates between a high-impedance (hereinafter referred to as Hi-Z) state and a low level. When the PRI_VOL_CONT terminal is in the Hi-Z state, a current flows from the power supply voltage V2 through resistors R15 and R16 to charge capacitor C16. On the other hand, when the PRI_VOL_CONT terminal is at a low level, a current flows to the PRI_VOL_CONT terminal through resistor R16 to discharge capacitor C16. When the PRI_VOL_CONT terminal alternates between the Hi-Z state and a low level, the balance between charging and discharging capacitor C16 stabilizes at a predetermined voltage. In other words, the PRI_VOL_CONT signal is smoothed and input to the negative input terminal of comparator IC11. Therefore, the voltage at the negative input terminal of comparator IC11 is determined according to the duty cycle of the pulse signal output from the PRI_VOL_CONT terminal.

[0021] When the voltage at the negative input terminal of comparator IC11 is lower than that at the positive input terminal, the output terminal of comparator IC11 becomes Hi-Z. At this time, the signal output from the CLK terminal of control unit 200 drives FET11 on and off as is. On the other hand, when the voltage at the negative input terminal of comparator IC11 is higher than that at the positive input terminal, the output terminal of comparator IC11 becomes low level. The current output from the CLK terminal is pulled to GND by the output terminal of comparator IC11, forcing the gate voltage of FET11 to become low level. This prevents FET11 from turning on at the timing it should, thereby promoting a decrease in the absolute value of charge voltage Vpri. This operation makes it possible to control charge voltage Vpri to the desired voltage (first target voltage). Here, the power supply voltage V2 in Example 1 is 5V. Through the above operation, a stable charging voltage Vpri is generated and applied to the charging roller 132a. The resistor R132 may be inserted as needed to limit the output current. The value of the charging voltage Vpri (first target voltage) in the first embodiment is −1000V.

[0022] The developing voltage generation circuit 133b has the same circuit configuration as the charging voltage generation circuit 132b. Therefore, when the comparator IC11 of the charging voltage generation circuit 132b is defined as the first comparator, the comparator included in the developing voltage generation circuit 133b (not shown in FIG. 2) is defined as the second comparator. The control unit 200 has a DEV_VOL_CON terminal (not shown in FIG. 2). The control unit 200 controls the developing voltage Vdev according to the duty of a pulse signal serving as a second signal output from the DEV_VOL_CONT terminal. That is, the control unit 200 controls the developing voltage Vdev to a desired voltage (second target voltage). In addition, the value of the developing voltage Vdev (second target voltage) in the second embodiment is −450 V. The charging current detection circuit 132c and the terminal protection control circuit 132d will be described later.

[0023] The configurations of the developing voltage generation circuit 133b, the developing current detection circuit 133c, and the terminal protection control circuit 133d shown in FIG. 3 are the same as those shown in FIG. 4, and therefore will not be described here. The elements in the developing voltage generation circuit 133b, the developing current detection circuit 133c, and the terminal protection control circuit 133d are assigned reference numerals in the hundreds, obtained by adding 100 to the value of "FET11" in FIG. 2, such as "FET111" for the FET in the developing voltage generation circuit 133b. The DEV_CUR_AD terminal and the DEV_CUR_CONT terminal of the control unit 200 will also not be described here. In addition, while the circuits related to the charging voltage (132b, 132c, 132d) and the circuits related to the developing voltage (133b, 133c, 133d) are provided as independent circuits in the first embodiment, this is not limiting. For example, the present invention can also be applied to a power supply configured to generate a developing voltage from the charging voltage generated by the charging voltage generation circuit 132b.

[0024] (Cable connection status) 4 is a block diagram of a control device 301 showing the configuration of Example 1. The control device 301 includes a control unit 200, a storage device 210, a flexible flat cable 303, a connector 321, a charging voltage generation circuit 132b, and a developing voltage generation circuit 133b. Here, the AC control signal output from the PRI_VOL_CONT terminal of the control unit 200 is referred to as a first control signal PRI_VOL_CONT, and the AC control signal output from the DEV_VOL_CONT terminal is referred to as a second control signal DEV_VOL_CONT.

[0025] In the first embodiment, the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT are connected to the charging voltage generation circuit 132b and the developing voltage generation circuit 133b, respectively, via a flexible flat cable 303 and a connector 321. The flexible flat cable 303 is hereinafter referred to as an FFC cable 303. The first control signal PRI_VOL_CONT is output to the charging voltage generation circuit 132b, which outputs a charging voltage Vpri based on the first control signal PRI_VOL_CONT. The second control signal DEV_VOL_CONT is output to the developing voltage generation circuit 133b, which outputs a developing voltage Vdev based on the second control signal DEV_VOL_CONT.

[0026] A first signal line 303a is a signal line through which the first control signal PRI_VOL_CONT, which is a first signal output from the PRI_VOL_CONT terminal of the control unit 200, is transmitted in the FFC cable 303. A second signal line 303b is a signal line through which the second control signal DEV_VOL_CONT, which is a second signal output from the DEV_VOL_CONT terminal of the control unit 200, is transmitted in the FFC cable 303. The charging voltage Vpri controlled by the first control signal PRI_VOL_CONT corresponds to the first voltage, and the developing voltage Vdev controlled by the second control signal DEV_VOL_CONT corresponds to the second voltage.

[0027] The storage device 210 stores information associating the frequencies and duties of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT with phase differences (first and second values) described below. Once the frequencies and duties of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT have been determined, the control unit 200 determines a phase difference corresponding to the frequencies and duties based on the information stored in the storage device 210. For example, the storage device 210 stores a plurality of frequencies and duties of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT, and stores a phase difference associated with each of the plurality of frequencies and duties. Once a predetermined frequency and duty have been determined, the control unit 200 extracts a phase difference corresponding to the predetermined frequency and duty stored in the storage device 210. When switching the output of the charging voltage Vpri and the developing voltage Vdev from OFF to ON, the control unit 200 outputs the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT so that the phase difference between them becomes the determined (extracted) phase difference.

[0028] (Control of Example 1) The first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT are PWM signals of the same frequency controlled by the control unit 200, which starts outputting these signals simultaneously or individually. The control unit 200 also controls the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT so that the phase difference between them is fixed. The first signal line 303a of the first control signal PRI_VOL_CONT and the second signal line 303b of the second control signal DEV_VOL_CONT run adjacent to each other in the FFC cable 303, and the signal lines of the FFC cable 303 are closely spaced apart. Specifically, the signal lines run parallel to each other at a distance such that noise generated in each signal is transferred to the other signal. The proximity of the signal lines is also due to factors such as circuit board patterns and wire bundles, and is not limited to the FFC cable 303. In the first embodiment, the signal line width of the FFC cable 303 is 1 mm, and the frequencies and duties of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT are 30 kHz and 50%, respectively (these values ​​are merely examples). The control and operation of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT by the control unit 200 in this configuration will be described below with reference to FIGS. 5 and 6.

[0029] (Phase difference between PRI_VOL_CONT and DEV_VOL_CONT) Figures 5 and 6 show the output relationship between the PWM signals of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT and the charging voltage Vpri and the developing voltage Vdev in time series. (i) in Figures 5 and 6 shows the first control signal PRI_VOL_CONT (Hi-Z, Lo output), and (ii) shows the second control signal DEV_VOL_CONT (Hi-Z, Lo output). The vertical axis represents voltage. (iii) in Figures 5 and 6 shows the charging voltage Vpri (ON (-1000V), OFF (0V)). (iv) in Figures 5 and 6 shows the developing voltage Vdev (ON (-450V), OFF (0V)). The horizontal axis represents time. t10, t11, t12, etc., t20, t21, t22, etc., all represent time (timing). In the following description, the first control signal PRI_VOL_CONT will be simply referred to as PRI_VOL_CONT, and the second control signal DEV_VOL_CONT will be simply referred to as DEV_VOL_CON.

[0030] Here, the period during which the charging voltage generation circuit 132b is controlled to output the first target voltage and the developing voltage generation circuit 133b is controlled to output the second target voltage is referred to as a first period (hereinafter referred to as period I). The period following period I is referred to as a second period (hereinafter referred to as period II). The period following period II during which the charging voltage generation circuit 132b is controlled to output the first target voltage and the developing voltage generation circuit 133b is controlled to output the second target voltage is referred to as a third period (hereinafter referred to as period III).

[0031] 5 and 6, the state transitions from turning on the charging voltage output and the developing voltage output for a certain period of time, turning the output off, and then turning the output on again are represented by an output-on state (output) period I, an output-off state (non-output) period II, and an output-on state period III. Specifically, the output-on state period I is from time t10 (t20) to time t11 (t21). The output-off state period II is from time t11 (t21) to time t12 (t22). The output-on state period III is from time t12 (t22) onward. Note that after the image forming apparatus 101 is powered on, these voltage outputs are repeatedly turned on and off in accordance with the printing operation on the paper P. For example, the period I may be the period during which image formation operation for one job that prints on multiple sheets of paper is performed, the period III may be the period during which image formation operation for the next job is performed, and the period II may be the standby state. Furthermore, even during one job, if the charging voltage output is turned off between sheets of paper, that period corresponds to period II. In other words, periods I and III may be for different jobs or the same job.

[0032] The output (-1000 V) (target voltage) of the charging voltage Vpri is the same in periods I and III, i.e., before and after the charging voltage output is set to 0 V. Also, the developing voltage Vdev (-450 V) (target voltage) is the same in periods I and III, i.e., before and after the developing voltage output is set to 0 V.

[0033] Here, one cycle of the waveforms of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT is defined as the time from the rising edge of the waveform from low output to Hi-Z to the next rising edge. Note that one cycle may also be the time from the falling edge of the waveform to the next falling edge. The phase represents the position within one cycle of the waveform, for example, the time (timing) within one cycle in FIG. 5 etc. The phase may be expressed in degrees (°) or radians (rad). For example, if the rising edge of the first control signal PRI_VOL_CONT and the second control signal DEV_VOL_CONT is defined as 0° (0 rad), the next falling edge can be expressed as 180° (π rad), and the next rising edge can be expressed as 360° (2π) or 0° (0 rad).

[0034] In the following description, the phase difference is defined as the difference between the rise of the second control signal DEV_VOL_CONT from low output to Hi-Z and the rise of the first subsequent first control signal PRI_VOL_CONT from low output to Hi-Z. In other words, the phase difference is defined as the difference between the phase of the second control signal DEV_VOL_CONT at 0° (0 rad) (predetermined phase) and the phase of the first subsequent first control signal PRI_VOL_CONT at 0° (0 rad) (predetermined phase). Note that the phase difference may also be defined as the difference between the rise of the first control signal PRI_VOL_CONT from low output to Hi-Z and the rise of the first subsequent second control signal DEV_VOL_CONT from low output to Hi-Z. Furthermore, the phase difference may be defined as the difference between the fall times from Hi-Z to low output, rather than the difference between the rise times of the waveform. Furthermore, the phase when defining the phase difference is not limited to 0° (0 rad), 180° (π rad), or 360° (2π rad), but may be other phases (90° (π / 2 rad), 45° (π / 4 rad), etc.).

[0035] FIG. 5 shows that the phase difference between PRI_VOL_CONT and DEV_VOL_CONT changes each time PRI_VOL_CONT and DEV_VOL_CONT transition from output OFF to output ON. That is, in FIG. 5, the phase difference between PRI_VOL_CONT and DEV_VOL_CONT changes each time a state transition occurs from period II to period III. Here, in period I, the difference (phase difference) between the rise of DEV_VOL_CONT from low output to Hi-Z and the rise of PRI_VOL_CONT from low output to Hi-Z is defined as Δ1. Also, in period III, the difference (phase difference) between the rise of DEV_VOL_CONT from low output to Hi-Z and the rise of PRI_VOL_CONT from low output to Hi-Z is defined as Δ2. In FIG. 5, Δ2 changes from Δ1.

[0036] Figure 6 shows that the phase difference between PRI_VOL_CONT and DEV_VOL_CONT is always constant (fixed) even when PRI_VOL_CONT and DEV_VOL_CONT transition from output OFF to output ON. That is, in Figure 6, the phase difference between PRI_VOL_CONT and DEV_VOL_CONT does not change every time the state transitions from period II to period III. Specifically, the phase difference does not change between period I and period III. Note that the phases (0, π, 2π) are shown in radians in part of the two signals in period I and period III in Figure 6.

[0037] Here, the difference between the rise of DEV_VOL_CONT from low output to Hi-Z and the rise of PRI_VOL_CONT from low output to Hi-Z during period I is defined as Δ3. Δ3, which is a first value, is the difference between the period of the first control signal PRI_VOL_CONT as the first signal and the period of the second control signal DEV_VOL_CONT as the second signal during period I. Also, the difference between the rise of DEV_VOL_CONT from low output to Hi-Z and the rise of PRI_VOL_CONT from low output to Hi-Z during period III is defined as Δ4. Δ4, which is a second value, is the difference between the period of the first control signal PRI_VOL_CONT and the period of the second control signal DEV_VOL_CONT during period III. In FIG. 6, Δ4 remains unchanged from Δ3 (Δ4=Δ3). In the first embodiment, Δ3 and Δ4 are set to the same value, but this is not limiting. The control unit 200 may control the charging voltage generation circuit 132b and the developing voltage generation circuit 133b so that the absolute value of the difference between Δ3 and Δ4 becomes smaller than a predetermined threshold value during period III.

[0038] 5 and 6, when the charging voltage output and developing voltage output are ON, PRI_VOL_CONT and DEV_VOL_CONT alternate between the Hi-Z state and the low level state. When the charging voltage output and developing voltage output are OFF, PRI_VOL_CONT and DEV_VOL_CONT maintain the Hi-Z state (period II).

[0039] Coupling noise occurs at triangular convex or concave portions that appear in the rectangular waveforms of PRI_VOL_CONT and DEV_VOL_CONT in Figures 5 and 6. Coupling noise is crosstalk noise that occurs in adjacent signals when the voltage of an AC control signal changes suddenly. That is, coupling noise occurs in PRI_VOL_CONT when DEV_VOL_CONT switches from low level to Hi-Z state (e.g., time t14) and when it switches from Hi-Z state to low level (e.g., time t13). Coupling noise also occurs in DEV_VOL_CONT when PRI_VOL_CONT switches from low level to Hi-Z state (e.g., time t15) and when it switches from Hi-Z state to low level (e.g., time t16). Furthermore, PRI_VOL_CONT and DEV_VOL_CONT have different impedances in the Hi-Z state and at low level, and the voltage that fluctuates due to coupling noise differs between the Hi-Z state and at low level.

[0040] If the phase difference between PRI_VOL_CONT and DEV_VOL_CONT is not constant each time PRI_VOL_CONT and DEV_VOL_CONT transition from output OFF to output ON as shown in Figure 5, the following occurs. That is, the timing at which coupling noise occurs in PRI_VOL_CONT and DEV_VOL_CONT differs between Period I and Period III. For example, in Period I, the coupling noise that occurs when PRI_VOL_CONT is in the Hi-Z state is at the falling edge of DEV_VOL_CONT. However, in Period III, the coupling noise that occurs when PRI_VOL_CONT is in the Hi-Z state changes from the falling edge of DEV_VOL_CONT to the rising edge. Furthermore, the value of the PRI_VOL_CONT voltage that fluctuates due to coupling noise differs between Period I and Period III.

[0041] An example of different coupling noise occurrence timings is described with reference to FIG. 5. During Period I, when PRI_VOL_CONT is in the Hi-Z state, coupling noise occurs when DEV_VOL_CONT switches from the Hi-Z state to a low level. During Period III, coupling noise occurs when DEV_VOL_CONT switches from a low level to the Hi-Z state. Therefore, each time the charging voltage and development voltage outputs are switched from OFF to ON, the timing of coupling noise occurrence changes, causing variations in the voltage fluctuations of PRI_VOL_CONT and DEV_VOL_CONT. In a configuration in which the output value is determined by a PWM signal, variations in the voltage fluctuations due to coupling noise lead to reduced stability of the output value. To reduce this reduction in stability of the output value, control is performed in Example 1 as shown in FIG. 6, even when PRI_VOL_CONT and DEV_VOL_CONT transition from output OFF to output ON. That is, when the output is ON, the control unit 200 controls the phase difference between PRI_VOL_CONT and DEV_VOL_CONT to be constant.

[0042] If the phase difference between PRI_VOL_CONT and DEV_VOL_CONT when their outputs are ON is constant as shown in Figure 6, the timing at which coupling noise occurs in PRI_VOL_CONT and DEV_VOL_CONT is the same in Period I and Period III. For example, in Period I, coupling noise that occurs when PRI_VOL_CONT is in the Hi-Z state is the timing of the falling edge of DEV_VOL_CONT (for example, time t23). Also, in Period III, coupling noise that occurs when PRI_VOL_CONT is in the Hi-Z state is the timing of the falling edge of DEV_VOL_CONT (for example, time t24). Also, the voltage of PRI_VOL_CONT, which fluctuates due to coupling noise, remains almost unchanged between Period I and Period III, and the same is true for DEV_VOL_CONT. Therefore, in the control of the first embodiment, even if the output of the charging voltage and the developing voltage is repeatedly switched from the OFF state to the ON state, the timing at which coupling noise occurs is constant, and the variation in the voltages of PRI_VOL_CONT and DEV_VOL_CONT is reduced.

[0043] As described above, according to the first embodiment, two adjacent AC control signals can reduce the voltage variation while each being affected by coupling noise, and there is no need to add circuits or components for countermeasures. The frequencies of the first control signal and the second control signal may be in a multiplication relationship. For example, the first control signal may have a frequency that is n times (n is an integer (n=1, 2, 3, ...)) (integer multiple) the frequency of the second control signal, or the second control signal may have a frequency that is n times (n is an integer (n=1, 2, 3, ...)) the frequency of the first control signal. Furthermore, by setting multiple fixed conditions for the phase difference between the first control signal and the second control signal, it is possible to generate coupling noise by avoiding the timing of logic switching, such as from a Hi-Z state to a low level or from a low level to a Hi-Z state.

[0044] Furthermore, in the first embodiment, an example was shown in which the control signal PRI_VOL_CONT of the charging voltage generation circuit 132b and the control signal DEV_VOL_CONT of the developing voltage generation circuit 133b are mutually affected by coupling noise, but this is not limiting. The present invention is applicable to any AC control signals transmitted through two adjacent signal lines in an FFC cable, such as the AC control signal of the charging voltage generation circuit 132b and the AC control signal of the toner supply roller circuit 134b, or the AC control signal of the charging voltage generation circuit 132b and the blade circuit 135b.

[0045] As described above, according to the first embodiment, it is possible to reduce the influence of coupling noise without requiring complex control while realizing miniaturization. [Example]

[0046] (Charging current detection circuit) The configurations and operations of the charging current detection circuit 132c and terminal protection control circuit 132d in the image forming unit 103 will be described with reference to Fig. 2. The charging current detection circuit 132c is a circuit that detects the current (hereinafter referred to as charging current) supplied to the charging roller 132a. The terminal protection control circuit 132d is a circuit that controls the PRI_CUR_AD terminal of the control unit 200 so that an overvoltage is not applied.

[0047] The junction of the secondary winding T11-2 and capacitor C12 is connected to the negative input terminal of operational amplifier IC12 via resistors R18 and R19. The positive input terminal of operational amplifier IC12 is connected to power supply voltage V2 via resistors R20 and R21, and the junction of resistors R20 and R21 is connected to GND via resistor R22. The output terminal of operational amplifier IC12 is connected to GND via resistors R23 and R24, and the junction of resistors R23 and R24 is connected to the PRI_CUR_AD terminal of control unit 200 via resistor R25. The PRI_CUR_AD terminal is connected to the PRI_CUR_CONT terminal of control unit 200 via resistor R26, and to GND via capacitor C17. The junction of resistors R18 and R19 is connected to the junction of resistors R23, R24, and R25, with resistor R27 and capacitor C18 connected in parallel. Furthermore, the voltage at the connection point of the resistors R23, R24, R25 and R27 is defined as Visns.

[0048] The charging current generated in the secondary winding T11-2 flows to ground via resistors R18, R27, and R24, then passes through the metal housing and other components, and returns to the secondary winding T11-2 via ground via the photosensitive drum 131, charging roller 132a, resistor R132, and diode D12. The voltage obtained by dividing the power supply voltage V2 by resistors R21 and R22 is applied to the positive input terminal of the operational amplifier IC12 as the operating reference voltage. The voltages at the positive and negative input terminals of the operational amplifier IC12 are at the same potential due to the virtual ground. Therefore, while the operational amplifier IC12 maintains virtual ground, Visns is controlled by resistor R27, which steps down the operating reference voltage of the operational amplifier IC12 in response to the magnitude of the charging current. In other words, the resistance of resistor R27 determines the amount of voltage step-down that varies with the magnitude of the charging current. Specifically, the larger the resistance value of resistor R27, the smaller the changes in charging current that can be detected. Also, when no charging current is flowing, Visns is at the same potential as the operating reference voltage of operational amplifier IC12. When the PRI_CUR_CONT terminal is controlled to Hi-Z, Visns is applied to the PRI_CUR_AD terminal. On the other hand, when the PRI_CUR_CONT terminal is controlled to low level, the voltage obtained by dividing Visns by resistors R25 and R26 is applied to the PRI_CUR_AD terminal.

[0049] As described above, when detecting a charging current, the PRI_CUR_CONT terminal is controlled to Hi-Z and the voltage of the PRI_CUR_AD terminal is detected, and when no charging current is detected, the PRI_CUR_CONT terminal is controlled to low level. This prevents the operating reference voltage of the operational amplifier IC12 from being applied to the PRI_CUR_AD terminal. Note that the operating reference voltage of the operational amplifier IC12 in the second embodiment is 5V.

[0050] In the second embodiment, as shown in Fig. 7, PRI_VOL_CONT is connected to a charging voltage generation circuit 132b as an output voltage generation circuit via an FFC cable 303 and a connector 321. Also, as shown in Fig. 7, PRI_CUR_AD is connected to a charging current detection circuit 132c as a current detection circuit via an FFC cable 303 and a connector 321. Note that PRI_VOL_CONT is a control signal for controlling the charging voltage. PRI_CUR_AD is an AD input signal input from the charging current detection circuit 132c to the control unit 200.

[0051] A first signal line 303a is a signal line through which the control signal PRI_VOL_CONT output from the PRI_VOL_CONT terminal of the control unit 200 is transmitted in the FFC cable 303. A second signal line 303c is a signal line through which the input signal PRI_CUR_AD input to the PRI_CUR_AD terminal of the control unit 200 is transmitted in the FFC cable 303. The charging voltage Vpri controlled by the control signal PRI_VOL_CONT corresponds to the output voltage, and Visns corresponds to the input voltage.

[0052] The storage device 210 stores information associating the frequency, duty, and phase of PRI_VOL_CONT, the sampling frequency and sampling timing of PRI_CUR_AD, and the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD. Note that this information may also associate the frequency and duty of PRI_VOL_CONT, the sampling frequency of PRI_CUR_AD, and the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD (first and second values, described later). The control unit 200 determines the frequency, duty, and phase of PRI_VOL_CONT, as well as the sampling frequency and sampling timing of PRI_CUR_AD. Based on the information stored in the storage device 210, the control unit 200 determines the frequency, duty, and phase of PRI_VOL_CONT, as well as the phase difference according to the determined sampling frequency and sampling timing of PRI_CUR_AD. For example, the storage device 210 stores a plurality of combinations of the frequency, duty, and phase of PRI_VOL_CONT and the sampling frequency and sampling timing of PRI_CUR_AD. The phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD is stored in association with each of these combinations. After determining the predetermined frequency, duty, and phase of PRI_VOL_CONT and the predetermined sampling frequency and sampling timing of PRI_CUR_AD, the control unit 200 extracts the corresponding phase difference stored in the storage device 210. When switching the output of the charging voltage Vpri from OFF to ON, the control unit 200 outputs PRI_VOL_CONT so that the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD becomes the determined (extracted) phase difference.

[0053] (Control of Example 2) The control signal PRI_VOL_CONT is a PWM signal, and its frequency, duty, and phase are changed by the control unit 200. On the other hand, PRI_CUR_AD is an AD input signal, and its sampling frequency and sampling timing are changed by the control unit 200. The frequency of PRI_VOL_CONT and the sampling frequency of PRI_CUR_AD are the same, and the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD is fixed by the control unit 200.

[0054] The first signal line 303a of PRI_VOL_CONT and the second signal line 303c of PRI_CUR_AD run adjacent to each other in the FFC cable 303, and the signal lines of the FFC cable 303 are closely spaced apart. The proximity of signals can also be affected by factors such as board patterns and wire bundles, and is not limited to FFC cables. In the second embodiment, the signal line width of the FFC cable 303 is 1 mm, the frequency and duty of PRI_VOL_CONT are 30 kHz and 50%, respectively, and the sampling frequency of PRI_CUR_AD is 30 kHz; these values ​​are merely examples. The control and operation of PRI_VOL_CONT and PRI_CUR_AD in this configuration will be described below with reference to Figures 8 and 9.

[0055] Here, for PRI_CUR_AD, one period (sampling period) is defined as the time from one sample point to the next, and the time (or degree, radian) within one period (within the sampling period) is defined as the phase. That is, the sample point can be expressed as a phase of 0° (0 rad), and the next sample point as a phase of 360° (2π rad), which is expressed as the phase of the input signal PRI_CUR_AD. In the following explanation, the phase difference is defined as the time from the first control signal PRI_VOL_CONT rising from a low output to Hi-Z, using the phase (sample point) of the input signal PRI_CUR_AD as the reference. In other words, the phase difference is defined as the difference between the phase of the input signal PRI_CUR_AD at 0° (0 rad) and the phase of the control signal PRI_VOL_CONT immediately thereafter at 0° (0 rad). Note that the phase difference may be defined as the period from the rising edge of the control signal PRI_VOL_CONT from low output to Hi-Z to the sample point thereafter. The phase difference may also be defined as the period from the sample point to the falling edge of the control signal waveform, or from the falling edge of the control signal waveform to the sample point.

[0056] Here, the period during which the charge voltage generation circuit 132b is controlled to output the target voltage (-1000V) is referred to as period I (first period). The period following period I is referred to as period II (second period). The period following period II during which the charge voltage generation circuit 132b is controlled to output the target voltage is referred to as period III (third period).

[0057] Figures 8 and 9 show the relationship between the sampling timing of PRI_VOL_CONT, PRI_CUR_AD, charging voltage, and PRI_CUR_AD in chronological order. (i) in Figures 8 and 9 shows PRI_VOL_CONT (Hi-Z, Lo output), and (ii) shows PRI_CUR_AD. The vertical axis represents voltage. (iii) in Figures 8 and 9 shows the sampling timing of PRI_CUR_AD. Note that the sample points in (ii) are indicated by white circles. (iv) in Figures 8 and 9 shows the charging voltage Vpri (ON (-1000V), OFF (0V)). The horizontal axis represents time. Note that the phase (0, π, 2π) is shown in radians for part of the two signals in periods I and III in Figure 8.

[0058] The state transitions from turning the charging voltage output ON (output) for a certain period of time, turning the output OFF (non-output), and then turning the output ON again are represented as Period I (time t30 to time t31), Period II (time t31 to time t32), and Period III (time t32 and after). Figure 8 shows that the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD changes each time PRI_VOL_CONT transitions from OFF to ON. That is, in Period I, the sampling timing and the rising edge of PRI_VOL_CONT (e.g., time t33) are approximately the same, and the phase difference Δ5 is approximately zero. Also, in Period I, the sampling timing coincides with the timing at which coupling noise occurs in PRI_CUR_AD. On the other hand, in Period III, the phase difference between the sampling point (e.g., time t34) and the rising edge of PRI_VOL_CONT (e.g., time t35) is Δ6, which is different from Δ5.

[0059] Figure 9 shows that even when PRI_VOL_CONT transitions from output OFF to output ON, the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD remains constant when the PRI_VOL_CONT output is ON. PRI_VOL_CONT in Figures 8 and 9 alternates between the Hi-Z state and low level when the charging voltage output is ON, and maintains the Hi-Z state when the charging voltage output is OFF. PRI_CUR_AD samples the AD value when the charging voltage output is ON, and stops sampling when the charging voltage output is OFF. Coupling noise occurs in PRI_CUR_AD when PRI_VOL_CONT switches from low level to Hi-Z state and when it switches from Hi-Z state to low level.

[0060] In Figure 8, the phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD changes each time PRI_VOL_CONT transitions from output OFF to output ON. In such cases, the sampling timing of PRI_CUR_AD sometimes overlaps with the timing of coupling noise occurrence and sometimes does not. In Figure 8, during period I, the sampling timing of PRI_CUR_AD and the timing of coupling noise occurrence overlap. On the other hand, during period III, they do not overlap.

[0061] Therefore, every time the charging voltage output is switched from the OFF state to the ON state, PRI_CUR_AD sometimes detects a voltage value that includes voltage fluctuations due to coupling noise, and sometimes detects a voltage value that does not, leading to a decrease in the detection accuracy of the AD voltage. To reduce this decrease in the detection accuracy of the AD voltage, in the second embodiment, the following control is performed. Even if PRI_VOL_CONT transitions from output OFF to output ON, when the output of PRI_VOL_CONT is in the ON state, control is performed to always maintain a constant phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD.

[0062] In FIG. 9A, Δ7, which is a first value, is the difference between the period of the control signal PRI_VOL_CONT and the sampling period during period I. Δ8, which is a second value, is the difference between the period of the control signal PRI_VOL_CONT and the sampling period during period III. As shown in FIG. 9A, when PRI_VOL_CONT is in the output ON state, the control unit 200 maintains a constant phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD. In this case, the phase difference between the sampling timing of PRI_CUR_AD and the timing at which coupling noise occurs is the same (Δ7 = Δ8) during periods I (Δ7) and III (Δ8). Note that, although Δ7 and Δ8 are set to the same value in the second embodiment, this is not limiting. The control unit 200 may also control the charging voltage generation circuit 132b during period III so that the absolute value of the difference between Δ7 and Δ8 is smaller than a predetermined threshold value. This allows PRI_CUR_AD to be sampled while avoiding the timing at which coupling noise occurs.

[0063] Therefore, even if the charging voltage output is repeatedly switched from OFF to ON, the sampling timing of PRI_CUR_AD and the timing when coupling noise occurs will always be different. PRI_CUR_AD detects voltage at a timing that is not affected by coupling noise, thereby reducing the decrease in accuracy of the detected voltage.

[0064] (Variation) Furthermore, multiple conditions for maintaining a constant phase difference between the phase of PRI_VOL_CONT and the sampling timing of PRI_CUR_AD may be set. That is, multiple phase differences may be provided. This allows the timing of coupling noise occurrence and the sampling timing of PRI_CUR_AD to be substantially synchronized when PRI_VOL_CONT is in the output ON state, as shown in FIG. 9(b). That is, it is possible to control the sampling timing to substantially coincide with the rising edge of PRI_VOL_CONT in both Period I and Period III. This means setting the phase difference Δ9 in Period I and the phase difference Δ10 in Period III to 0. In FIG. 9(b), the control unit 200 always detects voltage values ​​that include voltage fluctuations due to coupling noise. This improves the detection accuracy of the AD voltage compared to the case in FIG. 8 where voltage values ​​that include voltage fluctuations due to coupling noise are detected and voltage values ​​that do not include the coupling noise are detected.

[0065] As described above, according to the second embodiment, coupling noise occurs in the input signal due to an AC control signal close to the input signal. However, it is possible to detect the input signal while avoiding the generated coupling noise, and there is no need to add circuits or components to deal with the coupling noise. In the second embodiment, the frequency of the AC control signal and the sampling frequency of the input signal may be in a multiplication relationship.

[0066] In addition, in the second embodiment, an example was shown in which the input signal PRI_CUR_AD is affected by coupling noise resulting from the control signal PRI_VOL_CONT of the charging voltage generation circuit 132b, but the present invention is not limited to this. For example, the input signal PRI_CUR_AD can be applied as long as it is a signal transmitted through two adjacent signal lines in an FFC cable, such as an AC control signal of the toner supply roller circuit 134b and an AC control signal of the blade circuit 135b.

[0067] As described above, according to the second embodiment, it is possible to reduce the influence of coupling noise without requiring complex control while realizing miniaturization.

[0068] <Other embodiments> The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0069] The disclosure of this embodiment includes the following configuration. (Configuration 1) a first voltage generating circuit that outputs a first voltage; a first member to which the first voltage is applied; a second voltage generating circuit that outputs a second voltage; a second member to which the second voltage is applied; a control unit that outputs a first signal to control the first voltage generation circuit so that the first voltage generation circuit outputs a first target voltage, and outputs a second signal to control the second voltage generation circuit so that the second voltage generation circuit outputs a second target voltage; Equipped with a first period is a period during which the first voltage generating circuit is controlled to output the first target voltage and the second voltage generating circuit is controlled to output the second target voltage; The period following the first period is a second period, a third period is a period following the second period, in which the first voltage generating circuit is controlled to output the first target voltage and the second voltage generating circuit is controlled to output the second target voltage; a difference between a period of the first signal and a period of the second signal in the first period is set to a first value; a difference between the period of the first signal and the period of the second signal in the third period is set to a second value; the control unit controls the first voltage generation circuit and the second voltage generation circuit in the third period so that an absolute value of a difference between the first value and the second value is smaller than a predetermined threshold value. An image forming apparatus characterized by: (Configuration 2) The first value and the second value are values ​​from a rising edge of the first signal to a first rising edge of the second signal after the rising edge of the first signal. Or, The first value and the second value are values ​​from a falling edge of the first signal to a first falling edge of the second signal after the falling edge of the first signal. 2. The image forming apparatus according to claim 1, (Configuration 3) the first signal and the second signal are PWM signals; a first signal line through which the first signal is transmitted; a second signal line through which the second signal is transmitted; Equipped with the first signal line and the second signal line run parallel to each other at a distance such that noise generated in each signal is carried on each other; a first comparator to which the first signal line is connected and to which the smoothed first signal is input; a second comparator to which the second signal line is connected and to which the smoothed second signal is input; Equipped with the first comparator compares the first voltage with a voltage obtained by smoothing the first signal, and controls the first voltage to become the first target voltage; the second comparator compares the second voltage with a voltage obtained by smoothing the second signal, and controls the second voltage to become the second target voltage. 3. The image forming apparatus according to claim 1, wherein: (Configuration 4) a storage device that stores information that associates the frequencies and duties of the first signal and the second signal with the first value and the second value; the control unit determines the first value and the second value according to the information stored in the storage device and the frequencies and duties of the first signal and the second signal. 4. The image forming apparatus according to any one of configurations 1 to 3. (Configuration 5) a photoreceptor carrying a latent image; a charging roller for uniformly charging the photosensitive member; a developing roller for developing the latent image with toner to form a toner image; a toner supply roller for supplying toner to the developing roller; a developing blade for regulating the amount of toner on the developing roller; Equipped with the first member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade; the second member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade, excluding the first member; 5. The image forming apparatus according to any one of configurations 1 to 4. (Configuration 6) a voltage generating circuit that outputs an output voltage; a member to which the output voltage is applied; a control unit that outputs a control signal to control the voltage generating circuit so that the voltage generating circuit outputs a target voltage; a detection circuit that inputs an input signal corresponding to the current flowing through the member to the control unit; Equipped with a period during which the voltage generating circuit is controlled to output the target voltage is defined as a first period; The period following the first period is a second period, a third period is a period following the second period during which the voltage generating circuit is controlled to output the target voltage; the control unit detects the current by sampling the input signal input from the detection circuit at a sampling period; a difference between the cycle of the control signal and the sampling cycle in the first period is set to a first value; a difference between the cycle of the control signal and the sampling cycle in the third period is set to a second value; the control unit controls the voltage generating circuit during the third period so that an absolute value of a difference between the first value and the second value is smaller than a predetermined threshold value. An image forming apparatus characterized by: (Configuration 7) The first value and the second value are values ​​from the rising edge of the control signal to the first sampling point after the rising edge of the control signal. Or, the first value and the second value are values ​​from the falling edge of the control signal to the first sampling point after the falling edge of the control signal. 7. The image forming apparatus according to configuration 6, (Configuration 8) the control signal is a PWM signal, the input signal is an AD input signal; a first signal line through which the control signal is transmitted; a second signal line through which the input signal is transmitted; Equipped with The first signal line and the second signal line run parallel to each other at a distance such that noise generated in the control signal is carried on the input signal. 8. The image forming apparatus according to claim 6 or 7, (Configuration 9) the control unit samples the input signal during the first period and the third period, and does not sample the input signal during the second period. 9. The image forming apparatus according to any one of configurations 6 to 8, wherein: (Configuration 10) a storage device that stores information that associates the frequency and duty of the control signal and the sampling frequency of the input signal with the first value and the second value; the control unit determines the first value and the second value according to the information stored in the storage device, the frequency and duty of the control signal, and the sampling frequency of the input signal. 10. The image forming apparatus according to any one of configurations 6 to 9, wherein: (Configuration 11) a photoreceptor carrying a latent image; a charging roller for uniformly charging the photosensitive member; a developing roller for developing the latent image with toner to form a toner image; a toner supply roller for supplying toner to the developing roller; a developing blade for regulating the amount of toner on the developing roller; Equipped with the member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade; 11. The image forming apparatus according to any one of configurations 6 to 10. [Explanation of symbols]

[0070] 132a Charging roller 132b Charge voltage generation circuit 133a Developing roller 133b Development voltage generation circuit 200 control section

Claims

1. a first voltage generating circuit that outputs a first voltage; a first member to which the first voltage is applied; a second voltage generating circuit that outputs a second voltage; a second member to which the second voltage is applied; a control unit that outputs a first signal to control the first voltage generation circuit so that the first voltage generation circuit outputs a first target voltage, and outputs a second signal to control the second voltage generation circuit so that the second voltage generation circuit outputs a second target voltage; Equipped with a period during which the first voltage generating circuit is controlled to output the first target voltage and the second voltage generating circuit is controlled to output the second target voltage is defined as a first period; a period following the first period is a second period, a third period is a period following the second period, in which the first voltage generating circuit is controlled to output the first target voltage and the second voltage generating circuit is controlled to output the second target voltage; a difference between a period of the first signal and a period of the second signal in the first period is set to a first value; a difference between the period of the first signal and the period of the second signal in the third period is set to a second value; the control unit controls the first voltage generation circuit and the second voltage generation circuit in the third period so that an absolute value of a difference between the first value and the second value is smaller than a predetermined threshold value. An image forming apparatus characterized by:

2. the first value and the second value are values ​​from a rising edge of the first signal to a first rising edge of the second signal after the rising edge of the first signal, Or, the first value and the second value are values ​​from a falling edge of the first signal to a first falling edge of the second signal after the falling edge of the first signal, 2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

3. the first signal and the second signal are PWM signals, a first signal line through which the first signal is transmitted; a second signal line through which the second signal is transmitted; Equipped with the first signal line and the second signal line run parallel to each other at a distance such that noise generated in each signal is carried on each other's signals, a first comparator to which the first signal line is connected and to which the smoothed first signal is input; a second comparator to which the second signal line is connected and to which the smoothed second signal is input; Equipped with the first comparator compares the first voltage with a voltage obtained by smoothing the first signal, and controls the first voltage to become the first target voltage; the second comparator compares the second voltage with a voltage obtained by smoothing the second signal, and controls the second voltage to become the second target voltage.

2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

4. a storage device that stores information that associates the frequencies and duties of the first signal and the second signal with the first value and the second value, the control unit determines the first value and the second value according to the information stored in the storage device and the frequencies and duties of the first signal and the second signal.

2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

5. a photoreceptor carrying a latent image; a charging roller for uniformly charging the photosensitive member; a developing roller for developing the latent image with toner to form a toner image; a toner supply roller for supplying toner to the developing roller; a developing blade for regulating the amount of toner on the developing roller; Equipped with the first member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade; the second member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade, excluding the first member; 2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

6. a voltage generating circuit that outputs an output voltage; a member to which the output voltage is applied; a control unit that outputs a control signal to control the voltage generating circuit so that the voltage generating circuit outputs a target voltage; a detection circuit that inputs an input signal corresponding to the current flowing through the member to the control unit; Equipped with a period during which the voltage generating circuit is controlled to output the target voltage is defined as a first period; a period following the first period is a second period, a third period is a period following the second period during which the voltage generating circuit is controlled to output the target voltage; the control unit detects the current by sampling the input signal input from the detection circuit at a sampling period; a difference between a cycle of the control signal and the sampling cycle in the first period is set to a first value; a difference between the cycle of the control signal and the sampling cycle in the third period is set to a second value; the control unit controls the voltage generating circuit so that an absolute value of a difference between the first value and the second value is smaller than a predetermined threshold value during the third period. An image forming apparatus characterized by:

7. the first value and the second value are values ​​from a rising edge of the control signal to a first sampling point after the rising edge of the control signal; Or, the first value and the second value are values ​​from the falling edge of the control signal to the first sampling point after the falling edge of the control signal; 7. The image forming apparatus according to claim 6, wherein the image forming apparatus is a recording medium.

8. the control signal is a PWM signal, the input signal is an AD input signal, a first signal line through which the control signal is transmitted; a second signal line through which the input signal is transmitted; Equipped with The first signal line and the second signal line run parallel to each other at a distance such that noise generated in the control signal is carried on the input signal.

7. The image forming apparatus according to claim 6, wherein the image forming apparatus is a recording medium.

9. the control unit samples the input signal during the first period and the third period, and does not sample the input signal during the second period; 7. The image forming apparatus according to claim 6, wherein the image forming apparatus is a recording medium.

10. a storage device that stores information that associates the frequency and duty of the control signal and the sampling frequency of the input signal with the first value and the second value; the control unit determines the first value and the second value in accordance with the information stored in the storage device, the frequency and duty of the control signal, and the sampling frequency of the input signal.

7. The image forming apparatus according to claim 6, wherein the image forming apparatus is a recording medium.

11. a photoreceptor carrying a latent image; a charging roller for uniformly charging the photosensitive member; a developing roller for developing the latent image with toner to form a toner image; a toner supply roller for supplying toner to the developing roller; a developing blade for regulating the amount of toner on the developing roller; Equipped with the member is any one of the charging roller, the developing roller, the toner supply roller, and the developing blade; 7. The image forming apparatus according to claim 6, wherein the image forming apparatus is a recording medium.

Images