Quantum computing support program, quantum computing support method, and information processing device.

Abstract

This enables noise amplification in proportion to the number of quantum gates. [Solution] The information processing device 10 generates second quantum circuits 3a to 3c by converting the first 2-qubit gate 2a in the first quantum circuit 2 into a series of 2-qubit gates 4a to 4c that repeat the gate operation of the first 2-qubit gate 2a a predetermined number of times. The information processing device 10 converts some of the second 2-qubit gates in the 2-qubit gate groups 4a to 4c within the second quantum circuits 3a to 3c into a first equivalent circuit 5a that represents a gate operation of the first global phase. The information processing device 10 also converts some of the third 2-qubit gates in the 2-qubit gate groups 4a to 4c into a second equivalent circuit 5b that represents a gate operation of the second global phase. This generates third quantum circuits 6a to 6c. The information processing device 10 then causes the quantum computer 1 to execute the third quantum circuits 6a to 6c.

Description

[Technical Field]

[0001] The present invention relates to a quantum computing support program, a quantum computing support method, and an information processing device. [Background technology]

[0002] Currently, available quantum computers are of the NISQ (Noisy Intermediate-Scale Quantum Computer) type, which uses superconducting or ion-trap qubits. These quantum devices have an error rate of about 1% and the number of qubits is around 10-100. Such small-scale quantum computers cannot completely correct errors. Therefore, when performing quantum calculations on a quantum computer, algorithms that reduce quantum errors, called quantum error suppression or mitigation, are applied.

[0003] Furthermore, quantum computers implement single-qubit gates and double-qubit gates as quantum gates that can be used to manipulate qubits. These quantum gates that can be executed on quantum computers are called native gates. In current NISQ devices, the noise of a double-qubit gate is about an order of magnitude larger than that of a single-qubit gate. Therefore, double-qubit gates have a greater impact on measurement results than single-qubit gates.

[0004] One of the main types of noise generated during quantum gate operations is coherent noise, which is caused by over-rotation. Over-rotation noise is a noise component resulting from an excess or deficiency in the rotation angle of a rotating gate. Over-rotation noise is always present during gate operations of a rotating gate and is different from noise components that occur probabilistically.

[0005] In NISQ devices, over-rotation of the gate rotation angle occurs. Therefore, coherent errors caused by the implemented quantum gates occur. These coherent errors may be amplified depending on the circuit combination and the quantum state. Quantum error mitigation is performed to suppress such error amplification.

[0006] As a countermeasure against noise, for example, ZNE (Zero-Noise Extrapolation) can be utilized. ZNE is a technique that amplifies noise by inserting extra quantum gates into a quantum circuit and extrapolates and estimates the noise-free state.

[0007] As techniques for dealing with quantum errors caused by noise, for example, an error reduction method by circuit gauge selection has been proposed. A control device that improves the performance of quantum error suppression has also been proposed. A diagnostic method for physical quantum devices that enables simple and comprehensive diagnosis has also been proposed. A quantum error correction technique in a microwave integrated quantum circuit has also been proposed. Furthermore, a quantum error mitigation method combining RC (Randomized Compiling) and ZNE has also been proposed. RC is a technique that executes a plurality of equivalent circuits and suppresses the maximization of coherent errors by obtaining their average probability.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Non-Patent Documents

[0009] [Non-Patent Document 1] Tomochika Kurita, Hammam Qassim, Masatoshi Ishii1, Hirotaka Oshima, Shintaro Sato, and Joseph Emerson, "Synergetic quantum error mitigation by randomized compiling and zero-noise extrapolation for the variational quantum eigensolver" Quantum, 2023-11-20, volume 7, page 1184 [Overview of the project] [Problems that the invention aims to solve]

[0010] While reducing noise is not easy in quantum computers, amplifying noise is relatively easy. For noise other than coherent noise, increasing the number of quantum gates generating the noise can monotonically increase its magnitude. On the other hand, coherent noise is highly dependent on the internal quantum state, so increasing the number of gates does not necessarily result in monotonically increasing noise. Therefore, the influence of coherent noise makes it difficult to amplify noise proportionally to the number of quantum gates. This is one reason for the reduced accuracy of calculations of physical quantities (observables) using extrapolation methods, for example.

[0011] In one aspect, this project aims to enable noise amplification in proportion to the number of quantum gates. [Means for solving the problem]

[0012] One proposal provides a quantum computing support program that instructs a computer to perform the following processes: The computer generates a second quantum circuit by converting the first two-qubit gate in the first quantum circuit into a sequence of two-qubit gates that repeat the gate operation of the first two-qubit gate a predetermined number of times. The computer then converts a second two-qubit gate, which is part of the sequence of two-qubit gates in the second quantum circuit, into a first equivalent circuit that represents the gate operation of the first global phase, and converts a third two-qubit gate, which is part of the sequence of two-qubit gates and is different from the second two-qubit gate, into a second equivalent circuit that represents the gate operation of the second global phase, which is different from the first global phase, thereby generating a third quantum circuit. Finally, the computer has a quantum computer execute the third quantum circuit. [Effects of the Invention]

[0013] According to one embodiment, it becomes possible to amplify noise according to the number of quantum gates. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows an example of a quantum computing support method according to the first embodiment. [Figure 2] This figure shows an example of the configuration of a quantum computing system. [Figure 3] This figure shows an example of the computer hardware used in this embodiment. [Figure 4] This figure shows an example of ZNE. [Figure 5] This figure shows an example of a Bloch sphere that represents the state of a qubit. [Figure 6] This figure shows examples of multiple equivalent circuits for CX gates with different global phases. [Figure 7] This figure shows an example of how to implement the RZX gate. [Figure 8] This figure shows an example of a CX gate conversion method for canceling only coherent noise. [Figure 9] This figure shows an example of how to implement ZNE. [Figure 10]This diagram shows an example of the functions of a classical computer. [Figure 11] This is a flowchart illustrating an example of a quantum computing procedure. [Figure 12] This shows an example of how to implement multiple quantum circuits with different numbers of consecutive CX gates. [Figure 13] This diagram shows the error situation when only over-rotation noise is occurring. [Figure 14] This diagram shows the error situation when only relaxation noise is occurring. [Figure 15] This figure shows the error situation when both over-rotation noise and relaxation noise are present. [Figure 16] This diagram shows the error situation when five CX gates are in sequence. [Modes for carrying out the invention]

[0015] The following description of this embodiment will be made with reference to the drawings. Note that each embodiment can be implemented by combining multiple embodiments within a reasonable scope. [First Embodiment] The first embodiment is a quantum computing support method that enables quantum computing in which the effects of coherent noise are reduced and noise other than coherent noise is amplified.

[0016] Figure 1 shows an example of a quantum computing support method according to the first embodiment. Figure 1 shows an information processing device 10 for implementing the quantum computing support method. The information processing device 10 can implement the quantum computing support method according to the first embodiment by, for example, executing a quantum computing support program.

[0017] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or storage device of the information processing device 10. The processing unit 12 is, for example, a processor of the information processing device 10. The information processing device 10 may have multiple processors. Some of the multiple processes performed by the information processing device 10 may be executed on different processors.

[0018] The memory unit 11 stores, for example, the first quantum circuit 2. The first quantum circuit 2 is information that defines the gate operation procedure for finding the solution to the problem to be solved by quantum computation. The processing unit 12 causes the quantum computer 1 to perform a quantum computation based on the first quantum circuit 2. At that time, the processing unit 12 performs the following processing in order to reduce the effect of coherent noise and monotonically amplify noise other than coherent noise.

[0019] The processing unit 12 generates second quantum circuits 3a to 3c by converting the first two-qubit gate 2a in the first quantum circuit 2 into a sequence of two-qubit gates 4a to 4c that repeat the gate operation of the first two-qubit gate 2a a predetermined number of times. The first two-qubit gate 2a is, for example, a controlled NOT gate (CX gate). The processing unit 12 generates second quantum circuits 3a to 3c for each of a plurality of numerical values ​​that represent the predetermined number of times "n" the gate operation of the first two-qubit gate 2a is repeated. n is an odd number greater than or equal to 1. In the example in Figure 1, "1, 3, 5" are set as the plurality of numerical values ​​that represent the predetermined number "n".

[0020] The processing unit 12 generates third quantum circuits 6a to 6c based on the second quantum circuits 3a to 3c. For example, the processing unit 12 converts some of the second two-qubit gates in the two-qubit gate group 4a to 4c within the second quantum circuits 3a to 3c into a first equivalent circuit 5a that represents a gate operation in the first global phase. The processing unit 12 also converts some of the third two-qubit gates in the two-qubit gate group 4a to 4c, which are different from the second two-qubit gates, into a second equivalent circuit 5b. The second equivalent circuit 5b represents a gate operation in the second global phase, which is different from the first global phase. The processing unit 12 performs such conversion processes for a predetermined number of times "n" is repeated, for example, the gate operation of the first two-qubit gate 2a. This generates the third quantum circuits 6a to 6c.

[0021] The processing unit 12 causes the quantum computer 1 to execute the generated third quantum circuits 6a to 6c. Based on the execution results of the third quantum circuits 6a to 6c by the quantum computer 1, for example, the processing unit 12 determines the physical quantity (also called an observable) in the absence of noise using the observable method.

[0022] By implementing this quantum computing support method, quantum computations are performed on quantum computer 1 that reduce the influence of coherent noise (e.g., over-rotation noise) and increase the influence of noise other than coherent noise (e.g., relaxation noise). Specifically, by converting a 2-qubit gate into multiple consecutive 2-qubit gates and implementing the converted 2-qubit gates with a mixture of equivalent circuits having different global phases, the coherent noise cancels each other out. On the other hand, noise other than coherent noise increases in proportion to the number of consecutive 2-qubit gates.

[0023] Since the effect of noise increases with the number of consecutive 2-qubit gates, by having quantum computer 1 execute multiple third quantum circuits 6a to 6c, each with a different number of consecutive 2-qubit gates, it is possible to obtain calculation results when the amount of noise is monotonically increasing. Based on the measurement results from quantum computer 1, the physical quantities in the absence of noise can be determined with high accuracy using the external method.

[0024] In other words, coherent noise does not increase monotonically with respect to the number of consecutive 2-qubit gates because it is highly dependent on the internal quantum state, while noise other than coherent noise increases monotonically with respect to the number of consecutive 2-qubit gates. By suppressing the effects of coherent noise and obtaining quantum computation results in which only noise other than coherent noise increases monotonically, the accuracy of calculations of physical quantities by extrapolation is improved.

[0025] Furthermore, the predetermined number "n" for repeating the gate operation of the first two-qubit gate 2a is, for example, an odd number greater than or equal to 1. In other words, an even number of CX gates are added to the state of a single CX gate. The gate operation of an even number of CX gates does not cause a change in the qubit state before and after the operation, assuming noise is ignored. As a result, when the first two-qubit gate 2a is, for example, a CX gate, repeating the gate operation by the CX gate can increase only a predetermined amount of noise without changing the content of the quantum computation.

[0026] Furthermore, if the first quantum circuit 2 contains two-qubit gates other than CX gates, the processing unit 12 may convert those two-qubit gates into an equivalent circuit using CX gates. In that case, the processing unit 12 converts the CX gates included in the converted first quantum circuit 2 into a group of consecutive CX gates as the first two-qubit gates. This makes it possible to appropriately increase or decrease the noise when the entire first quantum circuit 2 is executed.

[0027] When generating the third quantum circuits 6a to 6c, the processing unit 12 converts, for example, the second two-qubit gate into a first equivalent circuit 5a using a first ECR (Echoed Cross-Resonance) gate with a rotation angle of 90 degrees. The processing unit 12 also converts the third two-qubit gate into a second equivalent circuit 5b using a second ECR gate with a rotation angle of -90 degrees. This makes it possible to execute the third quantum circuits 6a to 6c in many quantum computers 1 that employ a superconducting method, for example.

[0028] Note that while quantum computer 1 can execute ECR gates with a rotation angle of 90 degrees, it may not be able to execute ECR gates with a rotation angle of -90 degrees. In that case, the processing unit 12 constructs the second ECR gate using a third ECR gate with a rotation angle of 90 degrees and Z gates positioned before and after the third ECR gate for each of the two qubits targeted by the third ECR gate. This makes it possible to execute the third quantum circuits 6a to 6c even in quantum computer 1, which cannot execute ECR gates with a -90 degree rotation angle.

[0029] The processing unit 12 converts q second 2-qubit gates into the first equivalent circuit 5a when, for example, the number of 2-qubit gates in a group of 2-qubit gates is n (where n is an odd number greater than or equal to 1), and the quotient obtained by integer division by n / 2 is q (where q is an integer greater than or equal to 0). In this case, the processing unit 12 converts q+1 third 2-qubit gates into the second equivalent circuit 5b. This minimizes the difference between the number of gates implemented in the first equivalent circuit 5a and the number of gates implemented in the second equivalent circuit 5b, thereby reliably reducing coherent noise.

[0030] [Second Embodiment] Figure 2 shows an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system that performs calculations using, for example, the principles of quantum mechanics. The quantum computing system 300 has a classical computer 100 and a quantum computer 200. The classical computer 100 is a von Neumann type computer. The quantum computer 200 is a non-von Neumann type computer using a quantum gate method that performs quantum calculations by applying quantum gates to qubits.

[0031] A terminal device 30 is connected to the classical computer 100 via a network 20. The terminal device 30 is a computer used by users who request quantum computations from the quantum computing system 300. The classical computer 100 accepts quantum computation requests, including quantum circuits, from terminal devices 30, for example. A quantum circuit is a quantum computing model that shows the sequence of gate operations on qubits by the arrangement of elements such as quantum gates. A qubit is a bit that can represent a superposition state between a "0" state and a "1" state.

[0032] The classical computer 100 instructs the quantum computer 200 to perform gate operations on qubits according to the quantum computation request received from the terminal device 30. The classical computer 100 also obtains the measurement results for each qubit from the quantum computer 200.

[0033] The quantum computer 200 performs gate operations on qubits according to instructions from the classical computer 100. The quantum computer 200 also measures the state of the quantum gate and transmits the measurement results to the classical computer 100.

[0034] Figure 3 shows an example of the computer hardware used in this embodiment. The classical computer 100 is controlled as a whole by a processor 101. The processor 101 is connected to memory 102 and several peripheral devices via bus 100a.

[0035] The classical computer 100 may be a multiprocessor system having multiple processors. A collection of multiple processors in a multiprocessor system can be called a processor 101. A processor 101 may also be called a processor circuitry. Each of the multiple processors can execute some or all of the processes performed by the classical computer 100. When there are related processes, two or more of these processes may be executed by different processors.

[0036] The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor). At least some of the functions that the processor 101 implements by executing a program may be implemented by electronic circuits such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0037] Memory 102 is used as the main memory of the classical computer 100. Memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs that are to be executed by the processor 101. Memory 102 also stores various data used for processing by the processor 101. For memory 102, a volatile semiconductor memory device such as RAM (Random Access Memory) is used.

[0038] Peripheral devices connected to bus 100a include a storage device 103, a graphics controller 104, an input interface 105, an optical drive device 106, a device connection interface 107, a network interface 108, and a communication interface 109.

[0039] The storage device 103 electrically or magnetically writes and reads data from its built-in recording medium. The storage device 103 is used as an auxiliary storage device for the classical computer 100. The storage device 103 stores the OS program, application programs, and various data. For example, the storage device 103 can be an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0040] The graphics controller 104 is an arithmetic unit that performs image processing. The graphics controller 104 is, for example, a GPU (Graphics Processing Unit). A monitor 21 is connected to the graphics controller 104. The graphics controller 104 displays images on the screen of the monitor 21 according to instructions from the processor 101. The monitor 21 can be an OLED (Electroluminescence) display device or a liquid crystal display device. If a GPU is used as the graphics controller 104, the graphics controller 104 can also perform complex numerical calculations such as matrix calculations.

[0041] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals from the keyboard 22 and mouse 23 to the processor 101. Note that the mouse 23 is just one example of a pointing device; other pointing devices can also be used. Other pointing devices include touch panels, tablets, touchpads, and trackballs.

[0042] The optical drive device 106 uses laser light or the like to read data recorded on the optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded in a way that makes it readable by the reflection of light. Examples of optical discs 24 include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), and CD-R (Recordable) / RW (ReWritable).

[0043] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer 100. For example, a memory device 25 and a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a communication function with the device connection interface 107. The memory reader / writer 26 is a device that writes data to or reads data from the memory card 27. The memory card 27 is a card-type recording medium.

[0044] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface, for example, connected by cable to a wired communication device such as a switch or router. Alternatively, the network interface 108 may be a wireless communication interface, connected by radio waves to a wireless communication device such as a base station or access point.

[0045] The communication interface 109 is connected to the quantum computer 200. The communication interface 109 communicates with the quantum computer 200. For example, the communication interface 109 sends quantum gate operation instructions based on quantum circuits to the quantum computer 200. The communication interface 109 also receives the execution results of quantum circuits from the quantum computer 200.

[0046] The classical computer 100 can realize the processing functions of the second embodiment with the hardware described above. The information processing device 10 shown in the first embodiment can also be realized with the same hardware as the classical computer 100 shown in Figure 3.

[0047] The classical computer 100 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in the storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. Alternatively, the program to be executed by the classical computer 100 can be recorded on a portable recording medium such as an optical disc 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed in the storage device 103, for example, under control from the processor 101. The processor 101 can also directly read and execute the program from the portable recording medium.

[0048] The quantum computer 200 comprises a control device 201 and a qubit device 202. The control device 201 performs gate operations on the qubits in the qubit device 202 according to instructions from the classical computer 100. For example, the control device 201 performs a gate operation on a qubit by irradiating it with microwaves of a predetermined frequency.

[0049] The qubit device 202 has multiple qubits. The qubit device may have qubits of various types, such as superconducting, ion trapping, or cold atom architectures. The qubit device 202 is sometimes also called a QPU (Quantum Processing Unit).

[0050] A user of the quantum computing system 300 uses a terminal device 30 to generate a quantum circuit for solving a problem, for example, using quantum computation. When the user instructs the terminal device 30 to execute a quantum computation, the terminal device 30 transmits a quantum computation request, including the generated quantum circuit, to the quantum computing system 300.

[0051] In the quantum computing system 300, the classical computer 100 prompts the quantum computer 200 to perform quantum computations based on quantum circuits in response to quantum computation requests. At this time, the classical computer 100 converts the quantum circuit to be executed into a quantum circuit using executable quantum gates, in accordance with the hardware specifications of the quantum computer 200 (such as native gates corresponding to the qubit device).

[0052] In the quantum computing system 300, in order to mitigate the effects of noise, for example, by using ZNE with extrapolation, it is possible to calculate physical quantities with the effects of noise removed from the physical quantities shown in the measurement results.

[0053] Figure 4 shows an example of a ZNE. In quantum computer 200, it is difficult to reduce noise, but it is easy to amplify it. For example, if the noise is not coherent noise (called relaxation noise or decoherent noise), it can be amplified by repeating the same quantum gate operation. Therefore, classical computer 100 has quantum computer 200 perform multiple quantum calculations with different noise levels, and obtains physical quantities corresponding to the noise level from the measurement results of these quantum calculations.

[0054] In the example in Figure 4, the error rate (physical error probability) of the errors generated in the first quantum computation by quantum computer 200 is "ε0". In this case, the physical quantity obtained from the measurement result is " <o>Let (ε0) be the error rate of the error generated in the second quantum computation by quantum computer 200. In this case, the physical quantity obtained from the measurement result is " <o>Let (λε0) be the case.

[0055] Classical computer 100 calculates the physical quantity when the error is "0" using ZNE, based on the results of multiple measurements with different error magnitudes. For example, classical computer 100 calculates the physical quantity when the error is "0" using extrapolation methods such as linear extrapolation, Richardson extrapolation, and exponential extrapolation.

[0056] For example, classical computer 100 defines a function whose variable is the error rate and whose result is a physical quantity. This function includes a constant whose value is undetermined. Classical computer 100 determines the value of the constant in the function such that the line 91 representing the function passes through the points representing the physical quantity obtained for each error rate. Then, classical computer 100 outputs the function value when the error rate, which is a variable in the function, is set to "0" as the calculation result representing the physical quantity in the absence of noise.

[0057] Thus, ZNE makes it possible to calculate physical quantities in the absence of noise. In other words, if the noise generated in quantum computation is only decoherent noise and not coherent noise, then ZNE can accurately calculate physical quantities in the absence of noise.

[0058] However, coherent noise is highly dependent on the internal quantum state, and its magnitude does not increase proportionally to the number of quantum gates. Moreover, coherent noise is always generated during quantum gate operations. Therefore, coherent noise is a factor that degrades the computational accuracy of ZNEs.

[0059] Therefore, in the quantum computing system 300, the gate operation of the CX gate in the quantum circuit being executed is realized by a combination of equivalent circuits with different global phases, thereby canceling out over-rotation noise, which is a common type of coherent noise.

[0060] The global phase is one of the parameters that represent the superposition state of |0> and |1> for a qubit. The state of a qubit is often visualized using a Bloch sphere.

[0061] Figure 5 shows an example of a Bloch sphere representing the state of a qubit. The state of the qubit |ψ> is expressed by the following equation (1).

[0062]

number

[0063] In equation (1), θ, φ, and γ are real parameters. The coefficient "e" on the right-hand side of equation (1) iγ This is the global phase. When the state of a qubit |ψ> is represented by the Bloch sphere 31, the value in parentheses on the right side of equation (1) can be visualized using θ and φ. In contrast, the global phase cannot be represented by the Bloch sphere 31.

[0064] When observing the state of a qubit, the global phase is usually ignored. That is, in each measurement of the quantum state |ψ>, either state |0> or |1> is measured probabilistically. By determining the probability of occurrence of |0> and |1>, the state of the qubit can be accurately determined. The global phase, which is the coefficient multiplied by the entire right-hand side of equation (1), does not affect the probability of occurrence of |0> and |1>. Therefore, in quantum computation that does not consider noise, the global phase can be ignored.

[0065] When considering the effects of noise, it is possible to cancel or amplify noise by appropriately setting the global phase. For example, for a CX gate, there are multiple equivalent circuits that are logically equivalent but have different global phases. By combining these multiple equivalent circuits with different global phases, it is possible to reduce coherent noise and increase decoherent noise other than coherent noise.

[0066] FIG. 6 is a diagram showing an example of a plurality of equivalent circuits of a CX gate with different global phases. The matrix representing the gate operation of the CX gate 32 is as follows.

[0067]

Number

[0068] The CX gate 32 can be converted into a plurality of equivalent circuits 33 and 34 using the R ZX gate. The R ZX gate is sometimes called an Echoed Cross-Resonance (ECR) gate. The R ZX gate is generally used as an entanglement gate for superconducting devices.

[0069] In the equivalent circuit 33, an R ZX gate 33a with a rotation angle of "90" acting on the control qubit "q0" and the target qubit "q1" of the CX gate 32 is arranged. Next, in the equivalent circuit 33, an R Z gate 33b (R Z (-90)) with a rotation angle of "-90" acting on "q0" and an R X gate 33c (R X (-90)) with a rotation angle of "-90" acting on "q1" are arranged. The R Z gate 33b is a quantum gate that rotates -90 degrees around the Z axis, and the R X gate 33c is a quantum gate that rotates -90 degrees around the X axis.

[0070] In the equivalent circuit 34, an R ZX gate 34a with a rotation angle of "-90" acting on the control qubit "q0" and the target qubit "q1" of the CX gate 32 is arranged. Next, in the equivalent circuit 34, an R Z gate 34b (R Z (90)) with a rotation angle of "90" acting on "q0" and an R X gate 34c (R X (90)) with a rotation angle of "90" acting on "q1" are arranged. The R Z Gate 34b is a quantum gate that rotates 90 degrees around the Z axis, R X Gate 34c is a quantum gate that rotates a quantum object 90 degrees around the X-axis.

[0071] Here, the gate operation by the equivalent circuit 33 is expressed by the following equation (3).

[0072]

number

[0073] Furthermore, the gate operation by the equivalent circuit 34 is expressed by the following equation (4).

[0074]

number

[0075] Equation (3) "e -(iπ / 4) " and equation (4) "ie -(iπ / 4) This represents the global phase. Thus, the two equivalent circuits 33 and 34 of the CX gate 32 have different global phases. R ZX A gate operation using a gate is expressed by the following equation (5), where θ is the rotation angle.

[0076]

number

[0077] In many superconducting devices, the rotation angle R is 90 degrees. ZX Gate "R" ZX (90) can be executed as a native gate, but the rotation angle R is "-90". ZX Gate "R" ZX (-90) cannot be executed. ZX For (-90), R ZX This can be done by converting it to an equivalent circuit using (90).

[0078] Below, R ZX (90), R Z (-90), R X The equivalent circuit 33, which is composed of (-90), is designated as the "0" equivalent circuit. Also, R ZX (-90), R Z (90), R X The equivalent circuit 34 composed of (90) is designated as equivalent circuit "1".

[0079] Figure 7 shows R ZX This figure shows an example of how to implement a gate. R is a rotation angle of "90". ZX Gate 35 is executed directly on quantum computer 200. This R ZX The gate operation by gate 35 is expressed by the following equation (6).

[0080]

number

[0081] R with rotation angle "-90" ZX Gate 36 is converted into an equivalent circuit 37 and executed by the quantum computer 200. In the equivalent circuit 37, first, Z gates 37a and 37b are placed in each of the two qubits. Next, R with a rotation angle of "90" ZX Gate 37c is placed there. Furthermore, Z gates 37d and 37e are placed in each of the two qubits. This R ZX The gate operation by gate 36 (and similarly in the equivalent circuit 37) is expressed by the following equation (7).

[0082]

number

[0083] Thus, R ZX By using gates, multiple equivalent circuits 33 and 34 with different global phases relative to the CX gate can be generated. When two consecutive gate operations are performed on two qubits using a CX gate, the state of those qubits returns to its original state. Therefore, if a quantum circuit has one CX gate, replacing that CX gate with three consecutive CX gates will have the same effect on the qubits being operated on, assuming noise is not considered. However, there will be a difference in the magnitude of the noise between a gate operation with one CX gate and a gate operation with three CX gates.

[0084] In this case, the noise level can be adjusted by replacing consecutive CX gates with either the equivalent circuit of "0" or "1". For example, to suppress coherent noise while amplifying decoherent noise, consecutive CX gates can be implemented by combining the equivalent circuits of "0" and "1".

[0085] Figure 8 shows an example of a method for transforming CX gates to cancel out only coherent noise. For example, when classical computer 100 has one CX gate 41 in the quantum circuit to be executed, it transforms that CX gate 41 into three consecutive CX gates 42a to 42c. Classical computer 100 then transforms the three CX gates 42a to 42c into a circuit that combines equivalent circuits with different global phases. In the example in Figure 8, each of the CX gates 42a to 42c is transformed into equivalent circuits 43a to 43c, numbered "0", "1", and "0". Hereafter, such an arrangement of equivalent circuits will be represented by the equivalent circuit number sequence "010".

[0086] The equivalent circuit 43b for "1" contains R ZX (-90) gate is included. Therefore, the classical computer 100 has equivalent circuit 43b, R ZX (90) Converts to an equivalent circuit 43d using a gate.

[0087] In the example in Figure 8, one CX gate 41 is converted into three CX gates 42a to 42c, but the number of CX gates can be increased to five, seven, or more. As the number of CX gates increases, the decoherent noise increases. On the other hand, much of the coherent noise is canceled out by the mixing of gate operations with different global phases. By suppressing coherent noise, the calculation accuracy of ZNE is improved.

[0088] Figure 9 shows an example of a ZNE implementation method. For example, suppose classical computer 100 has decided on a gate number pattern of "1,3,5" for the CX gates included in the quantum circuit. In that case, classical computer 100 first performs R on the CX gate 44 included in the quantum circuit to be executed. ZX The quantum circuit is converted into an equivalent circuit using gates (for example, equivalent circuit "0"), and then the quantum computer 200 is made to execute the quantum circuit.

[0089] Next, the classical computer 100 converts the CX gate 44 of the quantum circuit into three CX gates 45a to 45c. Furthermore, the classical computer 100 converts each of the CX gates 45a to 45c into R ZX The quantum circuit is converted into an equivalent circuit using gates. In this process, the classical computer 100 combines equivalent circuits with different global phases. In the example in Figure 9, the two CX gates 45a and 45c are converted into equivalent circuit "0", and the single CX gate 45b is converted into equivalent circuit "1". The classical computer 100 then has the quantum computer 200 execute the quantum circuit after replacing the CX gates 45a to 45c with equivalent circuits.

[0090] Next, the classical computer 100 converts the CX gate 44 of the quantum circuit into five CX gates 46a to 46e. Furthermore, the classical computer 100 converts each of the CX gates 46a to 46e into R ZX The quantum circuit is converted into an equivalent circuit using gates. In this process, the classical computer 100 combines equivalent circuits with different global phases. In the example in Figure 9, the three CX gates 46a, 46c, and 46e are converted into equivalent circuit "0", and the two CX gates 46b and 46d are converted into equivalent circuit "1". The classical computer 100 then has the quantum computer 200 execute the quantum circuit after replacing the CX gates 46a to 46e with equivalent circuits.

[0091] When implementing a quantum circuit with one CX gate, the effect of decoherent noise is greater when there are three CX gates compared to when there is one, but the effect of coherent noise is reduced. Furthermore, when implementing a quantum circuit with one CX gate, the effect of decoherent noise is greater when there are five CX gates compared to when there are three, but the effect of coherent noise is reduced. As a result, the physical quantities obtained from the execution results of the quantum circuit will have errors due to the effect of decoherent noise. Therefore, the classical computer 100 calculates the physical quantities in the noise-free state by extrapolating based on the physical quantities obtained from the results of multiple quantum computations performed repeatedly with different numbers of CX gates.

[0092] For example, if we plot points corresponding to the calculation results for each number of CX gates on graph 47, where the horizontal axis is the number of CX gates and the vertical axis is a physical quantity, we obtain a line 47a that passes through the neighborhoods of those points. The classical computer 100 finds the function that represents this line 47a. For example, if the noise increases in proportion to the number of CX gates, the value of the function when the number of CX gates is "0" will be the calculation result of the physical quantity when there is no noise.

[0093] Figure 10 shows an example of the functions of a classical computer. The classical computer 100 has a computation request receiving unit 110, a quantum circuit generation unit 120, and a quantum computation control unit 130.

[0094] The calculation request receiving unit 110 receives a quantum computation request from the terminal device 30. The calculation request receiving unit 110 requests the quantum circuit generation unit 120 to generate a quantum circuit corresponding to the specified quantum computation. When the calculation request receiving unit 110 receives the computation result from the quantum computation control unit 130, it transmits the computation result to the terminal device 30 that sent the computation request.

[0095] The quantum circuit generation unit 120 generates a quantum circuit to perform the quantum computation specified by the computation request reception unit 110. For example, if the quantum computation request does not include a quantum circuit, the quantum circuit generation unit 120 generates a quantum circuit based on the information indicated in the quantum computation request, while also allowing the use of quantum gates other than native gates.

[0096] The quantum circuit generation unit 120 then converts the quantum circuit included in the quantum computation request, or the quantum circuit generated in response to the quantum computation request, into a quantum circuit using native gates. For example, the quantum circuit generation unit 120 converts a 2-qubit gate included in the quantum circuit into an equivalent circuit using CX gates. Furthermore, the quantum circuit generation unit 120 determines a numerical sequence indicating the number of CX gates to be implemented in the quantum circuit. Then, the quantum circuit generation unit 120 determines R, which corresponds to the number of CX gates indicated by each numerical value in the determined numerical sequence. ZX Multiple quantum circuits are generated using gates. The quantum circuit generation unit 120 sequentially transmits the generated quantum circuits to the quantum computation control unit 130.

[0097] The quantum computing control unit 130 instructs the quantum computer 200 to perform gate operations on qubits according to each of the multiple quantum circuits obtained from the quantum circuit generation unit 120. The quantum computing control unit 130 receives measurement results of the qubit state from the quantum computer 200 each time a gate operation according to the quantum circuit is completed. The quantum computing control unit 130 calculates the solution to the problem to be solved from the measurement results obtained from each of the multiple quantum circuits. For example, the quantum computing control unit 130 calculates the physical quantity in the absence of noise using ZNE based on the calculation results of the physical quantity based on each of the multiple quantum circuits with different numbers of CX gates. Then, the quantum computing control unit 130 calculates the solution to the problem to be solved based on the calculation results. The quantum computing control unit 130 transmits the obtained solution to the calculation request reception unit 110.

[0098] The functions of each element shown in Figure 10 can be realized, for example, by having a computer execute the program module corresponding to that element. Figure 11 is a flowchart illustrating an example of a quantum computing procedure. The process shown in Figure 11 will be explained below according to the step numbers.

[0099] [Step S101] The computation request receiving unit 110 receives a quantum computation request from the terminal device 30. The computation request receiving unit 110 then instructs the quantum circuit generation unit 120 to generate a quantum circuit. In response to the instruction, the quantum circuit generation unit 120 generates a quantum circuit corresponding to the problem to be solved. The generated quantum circuit is permitted to include quantum gates other than native gates. If the quantum computation request includes a quantum circuit, the quantum circuit generation unit 120 acquires that quantum circuit.

[0100] [Step S102] The quantum circuit generation unit 120 converts all entanglement gates (2-qubit gates) into equivalent circuits using CX gates. [Step S103] The quantum circuit generation unit 120 determines a numerical sequence of the number of consecutive CX gates n in the ZNE (n is an odd number greater than or equal to 1). For example, the quantum circuit generation unit 120 determines {n=1,3,5}.

[0101] [Step S104] The quantum circuit generation unit 120 sets the initial value of n to "1" (n=1). [Step S105] The quantum circuit generation unit 120 determines whether the value of n is less than or equal to the maximum value of the numerical sequence of n determined in step S103 (in the example in Figure 11, this value is "5"). If the value of n is less than or equal to the maximum value, the quantum circuit generation unit 120 proceeds to step S106. If the value of n exceeds the maximum value, the quantum circuit generation unit 120 proceeds to step S111.

[0102] [Step S106] The quantum circuit generation unit 120 converts each CX gate included in the quantum circuit into n consecutive CX gates. [Step S107] The quantum circuit generation unit 120 rotates each of the n consecutive CX gates, which are "n / / 2" consecutive CX gates, by an R rotation angle of "90". ZX Gate (R ZX Convert to an equivalent circuit using (90)) (" / / " indicates truncation division).

[0103] [Step S108] The quantum circuit generation unit 120 rotates each of the n consecutive CX gates, which are "n / / 2+1" consecutive CX gates, by an R rotation angle of "-90". ZX Gate (R ZX The quantum circuit is converted into an equivalent circuit using (-90). Then, the quantum circuit generation unit 120 transmits the generated quantum circuit to the quantum computation control unit 130.

[0104] [Step S109] The quantum computing control unit 130 instructs the quantum computer 200 to execute the generated quantum circuit. The quantum computer 200 executes the quantum circuit according to the instruction and transmits the measurement results of the qubits to the quantum computing control unit 130. The quantum computing control unit 130 calculates a predetermined physical quantity based on the measurement results obtained from the quantum computer 200.

[0105] [Step S110] The quantum circuit generation unit 120 updates the value of n. For example, the quantum circuit generation unit 120 adds "2" to n (n = n + 2). After that, the quantum circuit generation unit 120 proceeds to step S105.

[0106] [Step S111] The quantum computation control unit 130 calculates the error-free physical quantity by extrapolation based on the number of consecutive CX gates and the physical quantity at that time. In this way, highly accurate calculations using ZNE become possible. Specifically, when a CX gate is replaced with multiple consecutive CX gates, the consecutive CX gates are implemented as equivalent circuits with different global phases. As a result, the effect of coherent noise, where noise does not necessarily increase even when the number of quantum gates increases, is reduced, and only the effect of decoherent noise, where noise increases as the number of quantum gates increases, remains. Consequently, calculations of physical quantities using ZNE become possible without being affected by coherent noise, improving calculation accuracy.

[0107] In the process shown in Figure 11, n / / 2 of the consecutive CX gates rotate at an R angle of 90 degrees. ZX It is implemented using an equivalent circuit with gates (equivalent circuit "0"). In addition, "n / / 2+1" CX gates among the consecutive CX gates have a rotation angle of "-90" R ZX It is implemented using an equivalent circuit with gates (equivalent circuit "1"). As a result, the difference between the number of equivalent circuits "0" and the number of equivalent circuits "1" in consecutive CX gates is at least "1".

[0108] Figure 12 shows an example of an implementation method for multiple quantum circuits with different numbers of consecutive CX gates. Figure 12 also shows an example of calculating the energy in a Variational Quantum Eigensolver (VQE) with high accuracy using a ZNE.

[0109] The quantum circuit 51 for VQE calculation contains six CX gates. According to the process in Figure 11, when "n=1", each CX gate in the quantum circuit 51 has a rotation angle of "-90" R ZX It is implemented using an equivalent circuit with gates (equivalent circuit "1").

[0110] When "n=3", a quantum circuit 52 is generated in which each CX gate in quantum circuit 51 is transformed into three consecutive CX gates. Then, one of the three consecutive CX gates in quantum circuit 52 is a R with a rotation angle of "90". ZX It is implemented using an equivalent circuit with gates (equivalent circuit "0"). Then, the remaining two of the three consecutive CX gates are R with a rotation angle of "-90". ZX It is implemented using an equivalent circuit with gates (equivalent circuit "1").

[0111] When "n=5", a quantum circuit 53 is generated in which each CX gate in quantum circuit 51 is transformed into five consecutive CX gates. Then, of the five consecutive CX gates in quantum circuit 53, two CX gates have a rotation angle of "90" R ZX It is implemented using an equivalent circuit with gates (equivalent circuit "0"). Then, the remaining three of the five consecutive CX gates are R with a rotation angle of "-90". ZX It is implemented using an equivalent circuit with gates (equivalent circuit "1").

[0112] In this way, by minimizing the difference between the number of CX gates implemented in equivalent circuit "0" and the number of CX gates implemented in equivalent circuit "1", the coherent noise corresponding to the direction of rotation is canceled out. As a result, the effect of coherent noise is significantly reduced.

[0113] The following describes the simulation results of error occurrence for each type of noise generated during gate operations of consecutive CX gates, referring to Figures 13 to 16. Figure 13 shows the error situation when only over-rotation noise is present. Table 61 shows the relationship between the input and output of the CX gate when there is no noise. In Table 61, the horizontal axis represents the input state to the CX gate (|00>, |01>, |10>, |11>), and the vertical axis represents the output state of the CX gate (|00>, |01>, |10>, |11>). In Table 61, the darker the color, the higher the probability of the corresponding output state occurring when the corresponding input state is present.

[0114] Table 62 shows the magnitude of errors when over-rotation noise occurs. In Table 62, the horizontal axis represents the input state to the CX gate, and the vertical axis represents the output state of the CX gate. In Table 62, darker colors indicate a larger error when the corresponding input state results in the corresponding output state.

[0115] Tables 63a to 63h show the magnitude of the error after gate operation by three consecutive CX gates when the errors shown in Table 62 occur in each of those gates. In Tables 63a to 63h, the horizontal axis represents the input state to the CX gate, and the vertical axis represents the output state of the CX gate. In Tables 63a to 63h, darker colors indicate a larger error when the corresponding input state results in the corresponding output state.

[0116] Table 63a shows an example where three consecutive CX gates are implemented using the equivalent circuit "0". Table 63b shows an example where the first two of three consecutive CX gates are implemented using the equivalent circuit "0", and the last one is implemented using the equivalent circuit "1". Table 63c shows an example where the first and last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the middle one is implemented using the equivalent circuit "1". Table 63d shows an example where the first of three consecutive CX gates is implemented using the equivalent circuit "0", and the last two are implemented using the equivalent circuit "1". Table 63e shows an example where the last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the first one is implemented using the equivalent circuit "1". Table 63f shows an example where the middle of three consecutive CX gates is implemented with equivalent circuit "0", and the first and last two are implemented with equivalent circuit "1". Table 63g shows an example where the last of three consecutive CX gates is implemented with equivalent circuit "0", and the first two are implemented with equivalent circuit "1". Table 63h shows an example where all three consecutive CX gates are implemented with equivalent circuit "1".

[0117] As shown in Tables 63a and 63h, implementing three consecutive CX gates with the same equivalent circuit results in a strong over-rotation noise effect. In contrast, as shown in Tables 63b to 63g, combining the equivalent circuit labeled "0" and the equivalent circuit labeled "1" significantly reduces the over-rotation noise effect.

[0118] Figure 14 shows the error situation when only relaxation noise is present. Tables 64a to 64h show the magnitude of the error after gate operation by three consecutive CX gates when an error occurs in each of them due to relaxation noise alone. In Tables 64a to 64h, the horizontal axis represents the input state to the CX gate, and the vertical axis represents the output state of the CX gate. In Tables 64a to 64h, the darker the color, the greater the error when the corresponding input state results in the corresponding output state.

[0119] Table 64a shows an example where three consecutive CX gates are implemented using the equivalent circuit "0". Table 64b shows an example where the first two of three consecutive CX gates are implemented using the equivalent circuit "0", and the last one is implemented using the equivalent circuit "1". Table 64c shows an example where the first and last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the middle one is implemented using the equivalent circuit "1". Table 64d shows an example where the first of three consecutive CX gates is implemented using the equivalent circuit "0", and the last two are implemented using the equivalent circuit "1". Table 64e shows an example where the last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the first one is implemented using the equivalent circuit "1". Table 64f shows an example where the middle of three consecutive CX gates is implemented with equivalent circuit "0", and the first and last two are implemented with equivalent circuit "1". Table 64g shows an example where the last of three consecutive CX gates is implemented with equivalent circuit "0", and the first two are implemented with equivalent circuit "1". Table 64h shows an example where all three consecutive CX gates are implemented with equivalent circuit "1".

[0120] As shown in Tables 64a to 64h, even when a series of CX gates are implemented by combining the equivalent circuit of "0" and the equivalent circuit of "1", there is no change in the effect of relaxation noise. Figure 15 shows the error situation when both over-rotation noise and relaxation noise are present. Tables 65a to 65h show the magnitude of the error after gate operation by three consecutive CX gates when errors due to over-rotation noise and relaxation noise occur in each of those CX gates. In Tables 65a to 65h, the horizontal axis represents the input state to the CX gate, and the vertical axis represents the output state of the CX gate. In Tables 65a to 65h, the darker the color, the greater the error when the corresponding input state results in the corresponding output state.

[0121] Table 65a shows an example where three consecutive CX gates are implemented using the equivalent circuit "0". Table 65b shows an example where the first two of three consecutive CX gates are implemented using the equivalent circuit "0", and the last one is implemented using the equivalent circuit "1". Table 65c shows an example where the first and last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the middle one is implemented using the equivalent circuit "1". Table 65d shows an example where the first of three consecutive CX gates is implemented using the equivalent circuit "0", and the last two are implemented using the equivalent circuit "1". Table 65e shows an example where the last two of three consecutive CX gates are implemented using the equivalent circuit "0", and the first one is implemented using the equivalent circuit "1". Table 65f shows an example where the middle of three consecutive CX gates is implemented with equivalent circuit "0", and the first and last two are implemented with equivalent circuit "1". Table 65g shows an example where the last of three consecutive CX gates is implemented with equivalent circuit "0", and the first two are implemented with equivalent circuit "1". Table 65h shows an example where all three consecutive CX gates are implemented with equivalent circuit "1".

[0122] As shown in Tables 65a and 65h, when three consecutive CX gates are implemented with the same equivalent circuit, the effect of over-rotation noise remains strong. In contrast, as shown in Tables 65b to 65g, when three consecutive CX gates are implemented by combining the equivalent circuit of "0" and the equivalent circuit of "1", the effect of over-rotation noise is greatly reduced, and the effect of relaxation noise remains.

[0123] Figure 16 shows the error occurrence when five CX gates are used in succession. Tables 66a-66z and 66A-66F show the error occurrence when only over-rotation noise occurs during the gate operation of five consecutive CX gates. In Tables 66a-66z and 66A-66F, the horizontal axis represents the input state to the CX gate, and the vertical axis represents the output state of the CX gate. In Tables 66a-66z and 66A-66F, the darker the color, the greater the error when the corresponding input state results in the corresponding output state.

[0124] Table 66a shows an example where five consecutive CX gates are all implemented with equivalent circuit "0". Tables 66b, 66c, 66e, 66i, and 66q show an example where four of the five consecutive CX gates are implemented with equivalent circuit "0" and the other one is implemented with equivalent circuit "1". Tables 66d, 66f, 66g, 66j, 66k, 66m, 66r, 66s, 66u, and 66y show an example where three of the five consecutive CX gates are implemented with equivalent circuit "0" and the other two are implemented with equivalent circuit "1". Tables 66h, 66l, 66n, 66o, 66t, 66v, 66w, 66z, 66A, and 66C show examples where two of five consecutive CX gates are implemented with equivalent circuit "0" and the other three with equivalent circuit "1". Tables 66p, 66x, 66B, 66D, and 66E show examples where one of five consecutive CX gates is implemented with equivalent circuit "0" and the other four with equivalent circuit "1". Table 66F shows an example where all five consecutive CX gates are implemented with equivalent circuit "1".

[0125] As shown in Tables 66a and 66F, when three consecutive CX gates are implemented using the same equivalent circuit, errors due to over-rotation noise remain strong. As shown in Tables 66b, 66c, 66e, 66i, 66p, 66q, 66x, 66B, 66D, and 66E, if the difference between the number of implementations in equivalent circuit "0" and equivalent circuit "1" is large, errors due to over-rotation noise still remain. In other cases, if the difference between the number of implementations in equivalent circuit "0" and equivalent circuit "1" is "1" (one equivalent circuit has "n / / 2" units and the other has "n / / 2+1" units), errors due to over-rotation noise are greatly reduced.

[0126] In this way, the quantum computing system 300 can reduce the influence of coherent noise by canceling out the effects of overrotation noise. As a result, it becomes possible to selectively amplify noise other than overrotation, improving the accuracy of physical quantity calculations using ZNE.

[0127] [Other embodiments] In the example above, R is used as the equivalent circuit for the CX gate. ZX An example of an equivalent circuit using a gate has been shown, but if it is possible to create an equivalent circuit with a different global phase, R ZX Other quantum gates may also be used.

[0128] Also R ZX We showed an example of a superconducting quantum computer 200 that can run gates as native gates, but R ZX If the gates can be executed, quantum computer 200 can also be used using methods other than superconductivity.

[0129] Although embodiments have been illustrated above, the configurations of each part shown in the embodiments can be replaced with others having similar functions. Furthermore, other arbitrary components or processes may be added. Moreover, any two or more configurations (features) from the embodiments described above may be combined. [Explanation of Symbols]

[0130] 1. Quantum computer 2. The First Quantum Circuit 2a First 2-qubit gate 3a~3c The second quantum circuit 4a~4c 2-qubit gate group 5a First equivalent circuit 5b Second equivalent circuit 6a~6c The Third Quantum Circuit 10 Information Processing Devices 11 Storage section 12 Processing Units< / o> < / o>

Claims

1. A second quantum circuit is generated by converting the first two-qubit gate in the first quantum circuit into a group of consecutive two-qubit gates that repeat the gate operation of the first two-qubit gate a predetermined number of times. A third quantum circuit is generated by converting a second two-qubit gate, which is part of the group of two-qubit gates in the second quantum circuit, into a first equivalent circuit representing a gate operation of the first global phase, and converting a third two-qubit gate, which is part of the group of two-qubit gates and is different from the second two-qubit gate, into a second equivalent circuit representing a gate operation of the second global phase which is different from the first global phase. The third quantum circuit is to be executed by a quantum computer. A quantum computing support program that allows a computer to perform a process.

2. Based on the execution results of the third quantum circuit by the quantum computer, the physical quantity in the absence of noise is determined by the external method. The quantum computing support program according to claim 1, which causes the computer to perform further processing.

3. For each of the plurality of numerical values ​​indicating the predetermined number of times the gate operation of the first two-qubit gate is repeated, the process of generating the second quantum circuit, the process of generating the third quantum circuit, and the process of causing the quantum computer to execute the third quantum circuit are performed. Based on the execution results of the third quantum circuit for each of the aforementioned multiple numerical values, the physical quantity in the absence of noise is determined by the external method. The quantum computing support program according to claim 2.

4. In the process of generating the second quantum circuit, one or more odd numbers are used to represent the plurality of numerical values ​​indicating the predetermined number of times. The quantum computing support program according to claim 3.

5. In the process of generating the second quantum circuit, each two-qubit gate in the first quantum circuit is converted into an equivalent circuit using a controlled NOT gate, and the controlled NOT gate included in the converted first quantum circuit becomes the first two-qubit gate. The quantum computing support program according to claim 1.

6. In the process of generating the third quantum circuit, the second two-qubit gate is converted into the first equivalent circuit using a first ECR (Echoed Cross-Resonance) gate with a rotation angle of 90 degrees, and the third two-qubit gate is converted into the second equivalent circuit using a second ECR gate with a rotation angle of -90 degrees. The quantum computing support program according to claim 1.

7. In the process of generating the third quantum circuit, the second ECR gate is composed of a third ECR gate with a rotation angle of 90 degrees and Z gates positioned before and after the third ECR gate for each of the two qubits that the third ECR gate is targeting. The quantum computing support program according to claim 6.

8. In the process of generating the third quantum circuit, when the number of 2-qubit gates in the 2-qubit gate group is n (where n is an odd number greater than or equal to 1), and the quotient obtained by integer division by n / 2 is q (where q is an integer greater than or equal to 0), then q of the second 2-qubit gates are converted into the first equivalent circuit, and q+1 of the third 2-qubit gates are converted into the second equivalent circuit. The quantum computing support program according to claim 1.

9. A second quantum circuit is generated by converting the first two-qubit gate in the first quantum circuit into a group of consecutive two-qubit gates that repeat the gate operation of the first two-qubit gate a predetermined number of times. A third quantum circuit is generated by converting a second two-qubit gate, which is part of the group of two-qubit gates in the second quantum circuit, into a first equivalent circuit representing a gate operation of the first global phase, and converting a third two-qubit gate, which is part of the group of two-qubit gates and is different from the second two-qubit gate, into a second equivalent circuit representing a gate operation of the second global phase which is different from the first global phase. The third quantum circuit is to be executed by a quantum computer. A quantum computing support method in which a computer performs the processing.

10. A processing unit generates a second quantum circuit by converting a first two-qubit gate in the first quantum circuit into a continuous group of two-qubit gates that repeat the gate operation of the first two-qubit gate a predetermined number of times; converts a second two-qubit gate, which is part of the group of two-qubit gates in the second quantum circuit, into a first equivalent circuit that shows a gate operation of the first global phase; converts a third two-qubit gate, which is part of the group of two-qubit gates and is different from the second two-qubit gate, into a second equivalent circuit that shows a gate operation of the second global phase which is different from the first global phase; and causes a quantum computer to execute the third quantum circuit. An information processing device having

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