Test equipment

Abstract

We provide a test device that can create a latency environment equivalent to that of an actual satellite communication environment. [Solution] The test apparatus is a test apparatus that provides a test environment that simulates a satellite communication environment, and is characterized in that it takes an IF signal in satellite communication as an input signal, includes a delay circuit that gives the IF signal a signal delay equivalent to the satellite communication delay, and uses the delayed IF signal as an output signal.

Description

Technical Field

[0001] The present invention relates to a test apparatus, and more particularly to a test apparatus for pseudo-constructing a satellite communication environment.

Background Art

[0002] In recent years, IP (Internet Protocol) relay devices have been used in the transmission of video and audio of news and programs. IP relay can transmit live image information and the like at high speed by using an Internet line or a plurality of mobile communication lines, and its use is expected to expand further in the future. Furthermore, transmission via satellite communication is also being carried out using these IP relay devices.

[0003] However, when performing IP relay via satellite communication, there is a signal transmission delay (about 250 ms) that necessarily occurs in the satellite communication section, and the conditions are different compared to the operation using only mobile communication lines. Therefore, it is necessary to conduct sufficient tests and evaluations in a satellite communication environment for IP relay devices used in satellite communication.

[0004] Conventionally, the evaluation of devices used in satellite communication has been performed by satellite actual communication tests using the lines of actual communication satellites. Then, the events occurring in the satellite actual communication test are analyzed, and adjustments are repeated for performance improvement, and the development of the satellite transmission mode of the device has been promoted. However, in order to conduct satellite actual communication, it is necessary to obtain a radio license for the earth station, which takes time and cost.

[0005] On the other hand, it has been proposed to test and evaluate a device with a simulation system that pseudo-generates a satellite communication environment (Patent Document 1). In Patent Document 1, a satellite communication simulation system is configured by a pseudo-satellite communication device, a master device, and a slave device that perform two-way communication via the pseudo-satellite communication device. The master device has a delay time generation device inside, and reflects the delay of the transmission time that occurs in an actual satellite communication line for a control signal sent from an external terminal, and transmits the signal to the master device control device.

[0006] Figure 7 shows an example of a conventional test apparatus that simulates a satellite communication environment. This test apparatus reflects the transmission time delay that occurs in the satellite communication line for IP signals, based on the same design concept as Patent Document 1. The test apparatus 200 in Figure 7 is a device for testing a modulator 10 that modulates an input digital signal into an IF (Intermediate Frequency) signal in satellite communication, and a demodulator 20 that demodulates the IF signal into a digital signal. Although the IF signal in satellite communication has a wide frequency band, for example, when assuming Ku-band (14GHz band) satellite communication, the IF signal uses a frequency band of tens of MHz to several GHz.

[0007] The test apparatus 200 simulates a satellite communication environment by combining multiple test devices and includes IP delay devices 211 and 212, a level adjuster 220, a transmit frequency converter 230, a receive frequency converter 240, and a noise adder 250.

[0008] The input signal to the modulator 10 under test is obtained using the outputs of the IP relay transmitter 1 and ENC (Encoder) 2, and the output signal of the demodulator 20 under test is received by the IP relay receiver 3 and DEC (Decoder) 4 for verification. However, an IP delay device 211 is inserted on the input side of the modulator 10. The IP relay transmitter 1 transmits and receives IP signals with the modulator 10 under test via the IP delay device 211. ENC 2 outputs a TS (Transport Stream) signal to the modulator 10 under test. An IP delay device 212 is also inserted on the output side of the demodulator 20. The IP relay receiver 3 transmits and receives IP signals with the demodulator 20 under test via the IP delay device 212. The TS signal is input to DEC 4 from the demodulator 20 under test.

[0009] The individual components of the test apparatus 200 will be described below.

[0010] The IP delay device 211 delays the IP signal from the IP relay transmitter 1 for a predetermined time and outputs the delayed IP signal to the modulator 10 under test. This predetermined time is equal to the time it takes for the signal to be transmitted from the ground station to the communication satellite, and in this embodiment, it is 125 ms. The IP delay device 211 can simulate the satellite delay during transmission.

[0011] The IP delay device 212 delays the IP signal from the demodulator 20 under test for a predetermined time and outputs the delayed IP signal to the IP relay receiver 3. This predetermined time is equal to the time it takes for the signal to be transmitted from the communication satellite to the ground station, and in this embodiment, it is 125 ms. The IP delay device 211 can simulate the satellite delay at the time of reception.

[0012] Furthermore, the test apparatus 200 does not include a delay device in the signal path of the TS signal. This is because, since the TS signal flows in one direction, whether or not a delay device is included does not significantly affect the performance testing and evaluation of the modulator and demodulator.

[0013] The level adjuster 220 adjusts the IF signal output from the modulator 10 under test to the desired signal level. The level adjuster 220 is composed of an amplifier (AMP) and / or an attenuator (ATT) and adjusts the IF signal so that it is processed at an appropriate signal level, output from the test device 200, and input to the demodulator 20 under test.

[0014] The transmission frequency converter 230 converts the IF signal into an RF (Radio Frequency) signal, which is the frequency band for satellite communication. For example, assuming the use of a Ku-band satellite, the transmission frequency converter 230 performs frequency conversion to the 14GHz band.

[0015] The receiving frequency converter 240 converts RF signals, which are in the satellite communication frequency band, into IF signals. For example, it frequency-converts Ku-band signals into IF signals. The receiving frequency converter 240 outputs the IF signal obtained by frequency conversion to the noise adder 250.

[0016] The noise adder 250 adds noise to the input IF signal that simulates noise generated when using satellite communication (for example, noise received in the atmosphere). The noise-added IF signal is then output to the demodulator 20 under test. By providing the demodulator 20 with an IF signal that has been artificially noise-added, it is possible to verify whether the demodulator 20 can restore the original digital signal from the noise-containing IF signal, that is, whether it can perform appropriate noise handling.

[0017] Thus, the conventional test apparatus 200 can largely reproduce a satellite communication environment. [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] Patent No. 6142395 [Overview of the project] [Problems that the invention aims to solve]

[0019] However, conventional test equipment 200 inserts IP delay devices 211 and 212 on the input side of the modulator 10 and the output side of the demodulator 20, respectively, to simulate the signal delay that occurs in satellite communications, thereby adding a signal delay to the IP signal. On the other hand, the delay of the IF signal between the modulator and demodulator is effectively 0ms. As a result, delays different from those in actual satellite communications may occur.

[0020] Modulators and demodulators used for IP communication generally have a built-in accelerator, which acts as a proxy responder for TCP / IP (Transmission Control Protocol / Internet Protocol) communication and improves communication speed. Regarding the function of the accelerator, operational verification with IP signals delayed by delay devices 211 and 212 resulted in the addition of unnecessary delays that do not occur in actual satellite communication.

[0021] Figure 8 shows the IP communication flow when using the conventional test device 200. Specifically, in a TCP connection initiated from IP relay transmitter 1, the ACK (ACKnowledgement) response from IP relay transmitter 1 is delayed twice by the IP delay device 211, taking a total of 250ms. In addition, the ACK response to IP relay receiver 3 takes a total of 500ms. This means that the test environment differs from the actual satellite communication environment, making it impossible to properly verify the accelerator's functionality. Thus, with the conventional test device 200, it was sometimes impossible to fully evaluate the quality of the equipment in a satellite communication environment.

[0022] Therefore, in view of the above-mentioned problems, the object of the present invention is to provide a test apparatus that can construct a delay environment equivalent to that of an actual satellite communication environment. [Means for solving the problem]

[0023] To solve the above problems, the test apparatus according to the present invention is (1) A test device that provides a test environment simulating a satellite communication environment, wherein the test device takes an IF signal in satellite communication as an input signal, includes a delay circuit that applies a signal delay equivalent to the satellite communication delay to the IF signal, and outputs the delayed IF signal.

[0024] (2) The test apparatus described in (1) above is further preferably equipped with a frequency conversion unit that provides a frequency shift equivalent to the frequency difference between the transmission frequency and the reception frequency in satellite communication, and the frequency-shifted IF signal is used as the output signal.

[0025] (3) The test apparatus of (1) or (2) above preferably further includes a noise adder inside or outside the test apparatus.

[0026] (4) Any of the test apparatuses of (1) to (3) above includes a downconverter unit that lowers the frequency of the input signal to a predetermined frequency, and an upconverter unit that raises the frequency of the signal at the predetermined frequency to the frequency of the output signal, and performs a delay process that gives the signal delay to the signal at the predetermined frequency, and it is preferable to frequency-shift the input signal by the difference in frequency conversion between the downconverter unit and the upconverter unit.

[0027] (5) Any of the test apparatuses of (1) to (4) above preferably further uses at least one of a modulator that modulates an IP signal into an IF signal and a demodulator that demodulates an IF signal into an IP signal as the test target apparatus.

[0028] (6) In the test apparatus of (5) above, it is preferable that the test target apparatus incorporates an accelerator.

Advantages of the Invention

[0029] According to the test apparatus in the present invention, a delay environment equivalent to the actual satellite communication environment can be constructed. Thereby, the test and evaluation in the development of satellite communication equipment that performs IP communication can be performed more accurately.

Brief Description of the Drawings

[0030] [Figure 1] It is a diagram showing an example of a test and evaluation system using the test apparatus of the present invention. [Figure 2A] It is a diagram showing an example of the configuration of a modulator to be tested. [Figure 2B] It is a diagram showing an example of the configuration of a demodulator to be tested. [Figure 3] It is an example of a block diagram conceptually showing the configuration of the test apparatus of the present invention. [Figure 4]This is an example of a block diagram showing the circuit configuration of one embodiment of a test apparatus. [Figure 5] This figure shows an example of a specific circuit configuration in the block diagram of the test apparatus shown in Figure 4. [Figure 6] This figure shows the IP communication flow when using the test apparatus of this embodiment. [Figure 7] This is an example of a conventional test device that simulates a satellite communication environment. [Figure 8] This diagram shows the IP communication flow when using a conventional test device. [Modes for carrying out the invention]

[0031] Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals. In the description of each embodiment, the description of the same or corresponding parts will be omitted or simplified as appropriate.

[0032] Figure 1 shows an example of a test and evaluation system using the test apparatus of the present invention.

[0033] The modulator 10 under test receives, for example, an IP signal from the IP relay transmitter 1 and a TS signal from the ENC2. The IF signal, which is the output of the modulator 10, is input to the test device 100. The IF signal output from the test device 100 is then input to the demodulator 20 under test. The IP signal and TS signal output from the demodulator 20 are received and evaluated by the IP relay receiver 3 and DEC4, respectively. Bidirectional communication may be performed between the IP relay transmitter 1 and the modulator 10, and between the demodulator 20 and the IP relay receiver 3.

[0034] The test device 100 includes an IF delay function that provides a signal delay equivalent to the satellite communication delay, a frequency conversion function that provides a frequency shift equivalent to the frequency difference between the transmission frequency and the reception frequency in satellite communication, and a level adjustment function that reproduces the signal level changes in satellite communication. The test device 100 may also include an internal noise addition function (noise adder) that adds noise generated in satellite communication, or a noise adder (not shown) that adds noise to the IF signal output by the test device 100 may be provided externally (downstream) of the test device 100. The configuration of the test device 100 will be described later.

[0035] In this embodiment, the test device 100, as an IF delay function, applies a delay amount (approximately 250 ms) to the IF signal that corresponds to the signal delay that occurs from transmission to reception when using a geostationary satellite. As a result, the IF signal output by the modulator 10 under test (the IF signal input to the test device 100) is output as an IF signal delayed by 250 ms and input to the demodulator 20 under test. In other words, the test device 100 functions as an IF delay device.

[0036] Furthermore, the test device 100 of this embodiment performs frequency conversion on the IF signal, assuming satellite use (for example, a 20MHz shift for a Ku-band IF signal), as a frequency conversion function. Then, as a level adjustment function, the test device 100 simulates the results of transmission and reception to a communication satellite and applies the signal level fluctuations that occur after passing through a satellite repeater to the IF signal output.

[0037] Therefore, the test apparatus 100 of this embodiment implements an IF delay function that imparts signal delay in satellite communication to the IF signal, and a frequency conversion function that corresponds to the frequency shift of the IF signal during satellite communication, thereby creating an environment equivalent to that of an actual satellite communication environment. This allows the equipment under test to be tested and evaluated in an environment equivalent to that of an actual satellite communication environment.

[0038] Figure 2A shows an example of the configuration of the modulator under test. The modulator 10 comprises an IP interface (I / F) section 11, an ASI interface (I / F) section 12, a built-in accelerator 13, and an IF modulation section 14.

[0039] The IP interface (I / F) unit 11 is a block that functions as an interface for IP signals, and it performs input and output of IP signals, as well as outputting the IP signals input to the modulator 10 to the IF modulation unit 14 via the built-in accelerator 13.

[0040] The ASI interface (I / F) section 12 is a block that functions as an ASI (Asynchronous Serial Interface) interface for the TS signal, and outputs the TS signal input to the modulator 10 to the IF modulation section 14.

[0041] The built-in accelerator 13 performs proxy ACK responses in TCP / IP communication, optimizes the window size, and improves communication speed. In other words, it operates in the same way as WAN (Wide Area Network) acceleration devices used in the backbone of international network lines. For example, it is used in environments with high latency to servers, and is also commonly used when performing IP communication using satellites. In this embodiment, the built-in accelerator 13 performs proxy ACK responses to input IP signals. It may also send a SACK (Selective ACK) when it detects TCP data loss.

[0042] The IF modulation unit 14 modulates the digital signals of the input IP signal and TS signal into an IF signal, which is an intermediate frequency signal (for example, 950MHz to 1450MHz). The IF modulation unit 14 then outputs this IF signal as the output signal of the modulator 10.

[0043] Figure 2B shows an example of the configuration of the demodulator under test. The demodulator 20 comprises an IF demodulator 21, an internal accelerator 22, an IP interface (I / F) unit 23, and an ASI interface (I / F) unit 24.

[0044] The IF demodulation unit 21 demodulates the IF signal, which is an intermediate frequency signal (for example, 950MHz to 1450MHz) input to the demodulator 20, into digital signals of the IP signal and the TS signal. The IF demodulation unit 21 then outputs the IP signal to the built-in accelerator 22 and the TS signal to the ASI interface (I / F) unit 24.

[0045] The function of the built-in accelerator 22 is basically the same as that of the built-in accelerator 13 of the modulator 10, and it improves the communication speed by performing proxy ACK responses in TCP / IP communication. In this embodiment, the built-in accelerator 22 outputs the IP signal input from the IF demodulation unit 21 via the IP interface (I / F) unit 23, and also performs proxy ACK responses to the IP signal input from the IP relay receiver 3.

[0046] The IP interface (I / F) unit 23 is a block that functions as an interface for IP signals, and it performs input and output of IP signals, as well as outputting the IP signals from the demodulation unit 21 as output signals of the demodulator 20 via the built-in accelerator 22.

[0047] The ASI interface (I / F) section 24 is a block that functions as an ASI interface for TS signals and outputs the TS signal from the demodulation section 21 as the output signal of the demodulator 20.

[0048] It should be noted that the device under test in the test apparatus 100 of the present invention is not limited to the modulator 10 and demodulator 20 described above. The test apparatus 100 of the present invention can test and evaluate any device that outputs or inputs an IF signal in a test environment that simulates a satellite communication environment.

[0049] Next, the configuration of the test apparatus 100 of the present invention will be described.

[0050] Figure 3 is an example of a block diagram conceptually showing the configuration of the test apparatus 100 of the present invention. The test apparatus 100 comprises a level adjustment unit 110, a delay circuit unit 120, a frequency conversion unit 130, and a level adjustment unit 140. Note that each functional block is conceptual and is not necessarily configured independently.

[0051] The level adjustment unit 110 adjusts the signal level of the input IF signal to a level appropriate for signal processing within the test apparatus 100. The level adjustment unit 110 is configured, for example, by combining an amplifier (AMP) and / or an attenuator (ATT). The level-adjusted IF signal is input to the delay circuit unit 120.

[0052] The delay circuit 120 generates a delay amount (approximately 250 ms) equivalent to the signal delay that occurs from transmission to reception when using a geostationary satellite. As a result, the input IF signal is output as an IF signal delayed by 250 ms.

[0053] In this embodiment, the frequency conversion unit 130 performs frequency conversion (frequency shifting) assuming the use of Ku-band satellites. For Ku-band transmission, the upconverter (U / C) generates a 14GHz band signal from the IF signal and transmits it to the communication satellite. For Ku-band reception, a 12GHz band signal is received from the communication satellite and converted into an IF signal by the low-noise converter (LNC). At this time, by selecting the LOCAL frequency for frequency conversion, the received IF signal is shifted by 20MHz plus from the transmission frequency of the transmitted IF signal.

[0054] For example, if a local frequency of 13.05 GHz is used for frequency conversion during transmission and a local frequency of 11.30 GHz is used for frequency conversion during reception, the frequency shift of the IF signal will be as follows: [Modulator OUT:IF] 1.015GHz + [U / C Lo frequency] 13.05GHz = [Transmit frequency:RF] 14.0650GHz [Receiver frequency: RF] 12.3350 GHz - [LNC Lo frequency] 11.30 GHz = [Demodulator IN: IF] 1.035 GHz Frequency conversion value: 1.035 GHz - 1.015 GHz = 0.02 GHz = 20 MHz

[0055] The frequency conversion unit 130 replicates this frequency conversion and shifts the frequency of the IF signal output to 20 MHz plus relative to the IF signal input.

[0056] The level adjustment unit 140 consists of an amplifier (AMP) and the like, and adjusts the level of the IF signal output so that the signal level fluctuations that occur in the process of converting the IF signal input into a transmit RF signal, transmitting and receiving to and from the communication satellite, and converting the received RF signal into an IF signal output are reproduced.

[0057] The test apparatus 100 may be composed of individual circuit components, or it may be composed of logic circuits such as an FPGA (Field Programmable Gate Array). It may also include a software control unit (not shown) that controls each block.

[0058] Therefore, the test apparatus 100 of this embodiment implements an IF delay function that applies the signal delay in satellite communication using geostationary satellites to the IF signal, and a frequency conversion function for the IF signal corresponding to the Ku band, making it possible to create an environment equivalent to an actual satellite communication environment. Accordingly, the test apparatus 100 can be used for evaluating equipment or products related to satellite communication, and furthermore, for verifying and evaluating portable earth stations such as satellite news gathering vehicles (SNGs).

[0059] Furthermore, this embodiment has the effect of consolidating the testing apparatus, which was conventionally composed of a combination of multiple testers as shown in Figure 7, into as many devices as possible.

[0060] Figure 4 is an example of a block diagram showing the circuit configuration of one embodiment of the test apparatus 100. The test apparatus 100 comprises a down converter unit 150, a digital processing unit 160, an up converter unit 170, and a local unit 180.

[0061] The downconverter unit 150 adjusts the signal level of the input IF signal and performs downconversion to lower its frequency. For example, the downconverter unit 150 downconverts an IF signal input with a frequency of 950MHz to 1300MHz to a signal with a predetermined frequency of, for example, 37.15MHz. Note that this predetermined frequency is not limited to 37.15MHz and can be set arbitrarily. The IF signal converted to the predetermined frequency is input to the digital processing unit 160.

[0062] The digital processing unit 160 performs A / D (analog / digital) conversion on the input IF signal, processes the digital signal internally, then performs D / A (digital / analog) conversion, converts it back to an IF signal of a predetermined frequency, and outputs it to the upconverter unit 170. The digital processing unit 160 is equipped with an internal delay circuit and applies a signal delay equivalent to the satellite communication delay to the output IF signal through digital processing.

[0063] The upconverter unit 170 adjusts the signal level of the input IF signal and performs upconversion to increase its frequency. During upconversion, the frequency of the IF signal output is shifted by 20 MHz relative to the IF signal input. For example, the upconverter unit 170 upconverts a signal with a predetermined frequency of 37.15 MHz to an IF signal output with a frequency of, for example, 970 MHz to 1320 MHz. This frequency shift is set to 20 MHz assuming Ku-band satellite communication, but it is not limited to 20 MHz and can be set arbitrarily. The upconverted IF signal is output as the IF signal output of the test device 100.

[0064] The local section 180 incorporates internal PLL (Phase Locked Loop) circuits and functions as a local oscillator. The local section 180 outputs the frequency signals necessary for frequency conversion to the downconverter section 150 and the upconverter section 170, respectively.

[0065] The test apparatus 100 may also include a CPU (Central Processing Unit) / software control unit (not shown) for controlling each circuit block, a display unit (not shown) for displaying the signal processing content, a power supply circuit unit (not shown) for supplying power to each block, and the like.

[0066] Figure 5 shows an example of a specific circuit configuration of the block diagram of the test apparatus 100 shown in Figure 4.

[0067] The down converter section 150 includes an amplifier (AMP) 151, a mixer circuit (MIX) 152, a bandpass filter (BPF) 153, an amplifier (AMP) 154, a mixer circuit (MIX) 155, an amplifier (AMP) 156, and a detection circuit (DET) 157.

[0068] The input IF signal (for example, frequency 954.50MHz to 1295.50MHz, signal power -60dBm to 0dBm) is amplified to a predetermined level by the amplifier (AMP) 151.

[0069] The mixer circuit (MIX) 152 lowers the frequency of the input signal by multiplying a predetermined frequency signal input from the LOCAL section 180 with the amplified IF signal. For example, the mixer circuit (MIX) 152 receives a signal with a frequency of 1358.5MHz to 1699.5MHz from the LOCAL section 180 and multiplies this with the IF signal to generate a signal with a frequency of approximately 400MHz.

[0070] The bandpass filter (BPF) 153 allows only signals within a predetermined frequency band to pass through the signal output from the mixer circuit (MIX) 152. For example, the bandpass filter (BPF) 153 allows signals in a band centered around 404 MHz to pass through.

[0071] The amplifier (AMP) 154 amplifies the signal that has passed through the bandpass filter (BPF) 153 and outputs it to the mixer circuit (MIX) 155.

[0072] The mixer circuit (MIX) 155 multiplies a predetermined frequency signal input from the LOCAL unit 180 with the amplified IF signal to further lower the frequency of the input signal. For example, the mixer circuit (MIX) 155 receives a signal with a frequency of 441.15 MHz from the LOCAL unit 180, multiplies this with a 404 MHz IF signal to generate a signal with a frequency of 37.15 MHz, and outputs this to the digital processing unit 160. The detection circuit (DET) 157 is used to verify the IF signal input.

[0073] In this way, the downconverter unit 150 lowers the frequency of the input IF signal through a two-stage frequency conversion process to obtain an IF signal of a predetermined frequency. For example, an input IF signal with a frequency of 954.50MHz to 1295.50MHz is output as an IF signal with a frequency of 37.15MHz. Note that the two-stage frequency conversion process is a measure to perform frequency conversion with high accuracy, and the conversion could also be performed with a single-stage frequency conversion process.

[0074] The digital processing unit 160 includes an analog-to-digital conversion circuit (A / D) 161, a quadrature demodulation circuit (QDEM) 162, a decipherment filter (DECIMATION FILTER) 163, a delay circuit 164, an interpolation filter (INTERPOLATION FILTER) 165, a quadrature modulation circuit (QMOD) 166, a digital-to-analog conversion circuit (D / A) 167, and a voltage-controlled crystal oscillator (VCXO) 168.

[0075] The analog-to-digital conversion circuit (A / D) 161 converts the input analog IF signal into a digital signal. The sampling clock for the A / D conversion uses a clock input from the voltage-controlled crystal oscillator (VCXO) 168, for example, a 120MHz clock.

[0076] The quadrature demodulation circuit (QDEM) 162 demodulates the digitized IF signal into quadrature signals, generating the I signal and the Q signal.

[0077] The Decimation Filter 163 downsamples the signal, which has been digitized by sampling and quadrature-demodulated, to a ratio of, for example, 8:1. The downsampled signal is output to the delay circuit 164.

[0078] The delay circuit 164 is a circuit that delays an input signal for a predetermined time before outputting it. In this embodiment, the delay circuit 164 performs a delay of, for example, 250ms. There are various ways to implement delay processing, but for example, the signal can be delayed by temporarily storing the input signal (input data sequence) in a memory device and reading it out after a predetermined time. By adjusting the timing of reading the data stored in the memory device, it is possible to perform delay processing for any desired time.

[0079] The interpolation filter 165 upsamples the signal after the delay processing, in contrast to the downsampling performed before the delay processing. The upsampling can be, for example, 1:4.

[0080] The quadrature modulation circuit (QMOD) 166 quadrature modulates the I signal and the Q signal and converts them into an IF signal. Then, the digital-to-analog converter (D / A) 167 converts the input digital signal into an analog IF signal and outputs it.

[0081] As a result, the digital processing unit 160 outputs the input IF signal (e.g., 37.15 MHz) as an IF signal (e.g., 37.15 MHz) that has been delayed by a predetermined time.

[0082] The upconverter (UP CONVERTER) section 170 includes an amplifier (AMP) 171, a mixer circuit (MIX) 172, a bandpass filter (BPF) 173, an amplifier (AMP) 174, a mixer circuit (MIX) 175, a bandpass filter (BPF) 176, an amplifier (AMP) 177, and a detection circuit (DET) 178.

[0083] The input IF signal (for example, frequency 37.15 MHz, signal power -80 dBm to -20 dBm) is amplified to a predetermined level by the amplifier (AMP) 171.

[0084] The mixer circuit (MIX) 172 increases the frequency of the input signal by multiplying a predetermined frequency signal input from the LOCAL section 180 with the amplified IF signal. For example, the mixer circuit (MIX) 172 receives a signal with a frequency of 441.15 MHz from the LOCAL section 180 and multiplies this with the IF signal to generate a signal with a frequency of approximately 400 MHz.

[0085] The bandpass filter (BPF) 173 allows only signals within a predetermined frequency band to pass through the signal output from the mixer circuit (MIX) 172. For example, the bandpass filter (BPF) 173 allows signals in a band centered around 404 MHz to pass through.

[0086] The amplifier (AMP) 174 amplifies the signal that has passed through the bandpass filter (BPF) 173 and outputs it to the mixer circuit (MIX) 175.

[0087] The mixer circuit (MIX) 175 multiplies a predetermined frequency signal input from the LOCAL section 180 with an amplified IF signal to further increase the frequency of the input signal. For example, the mixer circuit (MIX) 175 receives a signal with a frequency of 1378.5MHz to 1719.5MHz from the LOCAL section 180, multiplies this with a 404MHz IF signal to generate a signal with a frequency of approximately 970MHz to 1320MHz.

[0088] The generated high-frequency signal is converted into an IF signal of a predetermined frequency band by a bandpass filter (BPF) 176, which is then amplified by an amplifier (AMP) 177 and output. The detection circuit (DET) 178 is used to verify the output of the IF signal.

[0089] In this way, the upconverter unit 170 increases the frequency of a predetermined IF signal through a two-stage frequency conversion process to produce an output IF signal. For example, an input 37.15MHz IF signal is output as a signal with frequencies from 974.50MHz to 1315.50MHz. Note that the two-stage frequency conversion process is a measure to perform frequency conversion with high accuracy, and the conversion could also be performed with a single-stage frequency conversion process.

[0090] The local (LOCAL) section 180 includes a voltage-controlled crystal oscillator (VCXO) 181, a distributor (HYB) 182, phase-locked loop circuits (PLLs) 183-185, and another distributor (HYB) 186.

[0091] The voltage-controlled crystal oscillator (VCXO) 181 outputs a fundamental frequency signal, which is then distributed by the distributor (HYB) 182 to the phase-locked loop circuits (PLLs) 183-185.

[0092] Phase-locked loop circuit (PLL) 183 generates signals with frequencies of, for example, 1358.5 MHz to 1699.5 MHz, phase-locked loop circuit (PLL) 184 generates signals with frequencies of, for example, 441.15 MHz, and phase-locked loop circuit (PLL) 185 generates signals with frequencies of 1378.5 MHz to 1719.5 MHz. These respective frequency signals are output to the downconverter section 150 and the upconverter section 170. The 441.15 MHz signal is distributed by the distributor (HYB) 186 and supplied to the mixer circuits (MIX) 155 and 172.

[0093] The circuit configuration shown in Figure 5 is just one example, but the test apparatus 100 of this embodiment can be realized with such a circuit configuration.

[0094] Figure 6 shows the IP communication flow when using the test apparatus 100 of this embodiment. In a TCP connection initiated from IP relay transmitter 1, the ACK response from IP relay transmitter 1 is approximately 1-2 ms, and the ACK response to IP relay receiver 3 is approximately 252 ms. In a TCP connection initiated from IP relay receiver 3, the ACK response from IP relay transmitter 1 is also approximately 252 ms, demonstrating that the same operation as actual satellite communication can be achieved.

[0095] In this embodiment, the test device 100 is designed assuming the use of geostationary satellites and the Ku-band. However, by changing the design parameters, it can also be used for other satellite communication bands, as well as for testing and evaluating low-Earth orbit satellites and high-capacity, high-speed satellites.

[0096] In the above embodiment, the configuration and operation of the test apparatus 100 have been described, but the present invention is not limited thereto, and the test apparatus 100 may be configured as a test method for testing a modulator and / or demodulator. That is, the test method may be configured to include a step of delaying the IF signal output from the modulator and inputting it to the demodulator, according to the signal flow in Figure 1.

[0097] Although the embodiments described above are representative examples, it will be apparent to those skilled in the art that many modifications and substitutions are possible within the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited by the embodiments described above, and various modifications or changes are possible without departing from the scope of the claims. For example, the functions, etc., included in each block, step, etc., described in the embodiments can be rearranged in a logically consistent manner, and multiple constituent blocks, steps, etc., can be combined into one or divided. [Explanation of Symbols]

[0098] 1 IP relay transmitter 2 ENC (Encoder) 3 IP relay receivers 4 DEC (Decoder) 10 Modulator under test 11. IP Interface (I / F) Section 12. ASI Interface (I / F) Section 13. Built-in accelerator 14 IF Modulation Section 20 Demodulators under test 21 IF Demodulation Unit 22. Built-in accelerator 23 IP Interface (I / F) Section 24 ASI Interface (I / F) Section 100 Test equipment 110 Level adjustment section 120 Delay Circuit Section 130 Frequency conversion section 140 Level adjustment section 150 Downconverter section 160 Digital Processing Unit 170 Upconverter section 180 Local Section 200 Test equipment 211 IP Delay Device 212 IP Delay Device 220 Level Adjuster 230 Transmitting Frequency Converter 240 Receiving frequency converter 250 Noise Adder

Claims

1. A test device that provides a test environment simulating a satellite communication environment, Using the IF signal in satellite communications as the input signal, The system includes a delay circuit that provides a signal delay equivalent to the satellite communication delay to the aforementioned IF signal. A test device that uses a delayed IF signal as its output signal.

2. In the test apparatus described in claim 1, Furthermore, it includes a frequency conversion unit that provides a frequency shift equivalent to the frequency difference between the transmission frequency and the reception frequency in satellite communications. A test device that uses a frequency-shifted IF signal as its output signal.

3. In the test apparatus described in claim 2, Furthermore, the test apparatus includes a noise adder either inside or outside the test apparatus.

4. In the test apparatus described in claim 2, A downconverter unit that lowers the frequency of the input signal to a predetermined frequency, The system includes an upconverter unit that increases the frequency of the predetermined frequency signal to match the frequency of the output signal. A delay process is performed to impose the signal delay on the signal of the predetermined frequency. A test apparatus that shifts the frequency of the input signal by the difference in frequency conversion between the downconverter section and the upconverter section.

5. In the test apparatus according to any one of claims 1 to 4, A test apparatus comprising at least one of a modulator that modulates an IP signal into an IF signal, and a demodulator that demodulates an IF signal into an IP signal, as the device under test.

6. In the test apparatus described in claim 5, The aforementioned test device is a test device that incorporates an accelerator.

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