A method for optimizing the scheduling of operations in quantum chips and quantum circuits on quantum chips.

Abstract

A quantum chip and a method for optimizing the scheduling of quantum circuit operations on the quantum chip are provided. The quantum chip may include at least one magic state factory including a plurality of qubits configured to enable the implementation of one or more non-Clifford gates and one or more distillation ports, a plurality of data qubits, and a quantum bus including qubits adjacent to and operably coupled to each of the one or more distillation ports of the at least one magic state factory and each of the qubits among the plurality of data qubits, wherein the quantum bus is used to connect the at least one magic state factory to at least one of the plurality of data qubits using the one or more distillation ports. The method may include the step of obtaining a quantum circuit, as well as a layout representing the qubit types and arrangement of the qubits on the quantum chip.

Description

Technical Field

[0001] Cross-reference This application claims the benefit of U.S. Provisional Application No. 63 / 500,908, filed May 8, 2023, U.S. Provisional Application No. 63 / 620,333, filed Jan. 12, 2024, and U.S. Provisional Application No. 63 / 557,334, filed Feb. 23, 2024, each of which is hereby incorporated by reference in its entirety. Technical Background

[0002] Fault-tolerant quantum computation (FTQC) can be useful for unlocking the proposed benefits for quantum computing, but applicable FTQC technologies have not yet been developed. FTQC devices theoretically manage errors that accumulate during computation, and finding ways to make physical FTQC hardware more realizable can help bridge the gap between application development and hardware development.

Summary of the Invention

[0003] Exemplary techniques for making FTQC hardware more feasible include reducing the accumulation of errors caused by computational latencies or other issues. For example, one approach to reducing error accumulation is to optimize the scheduling of quantum operations in a quantum circuit by (i) designing the quantum chip layout to use fewer qubits, and (ii) minimizing the number of time steps used to execute a given quantum algorithm. The quantum chip layout problem (i) and the scheduling problem of operations in the quantum circuit (ii) may be interdependent and can be solved together as a quantum compilation problem (Beverland et al., “Surface Code Compilation via Edge-Disjoint Paths,” PRX Quantum 3, 020342, 2022; this document is incorporated herein by reference in its entirety). One objective in solving this problem is to reduce the overall space-time cost of the quantum system without infringing on the logical constraints of the quantum circuit or the physical constraints of the quantum hardware.

[0004] This disclosure provides a method and system for solving quantum compilation problems by optimizing the scheduling of operations in quantum circuits on a quantum chip comprising at least one magic state factory, a plurality of data qubits, and a quantum bus. One focus is on the design of quantum chip layouts using quantum error correction schemes for FTQC, and algorithms for generating scheduling of quantum operations in quantum circuits using quantum chip layout designs that reduce quantum computation time within reasonable classical computation time. This disclosure may improve existing methods for optimizing scheduling of operations in quantum chip layouts and quantum circuits on them by using a modular quantum chip layout topology. For example, the magic state factory may be surrounded by other qubit types (data, auxiliary, storage, and bus) and form modules that can be tiled together for large quantum chips. In some cases, the layout may include dedicated blocks, one block containing data qubits, another containing a magic state factory, and a third block proposed to mediate connections between other blocks using magic state storage qubits, with a quantum bus connecting all the blocks. These designs can be used to generate quantum chips in which quantum operations can be performed in parallel. The scheduling of quantum operations can be generated using optimization procedures used to solve problems including the maximum independent set problem, Steiner tree problems, and integer programming problems, which model the original optimization problems.Examples of such procedures may include topology sorting, heuristics, and branch-and-bound methods.

[0005] The systems and methods of this disclosure, as well as the disclosed quantum chips, may offer at least some of the following advantages: The disclosed quantum chip layout may use a quantum bus to enable the connection of qubits through multiple auxiliary patches, allowing the compiler to schedule multiple quantum operations requiring the connection of any number of qubits within a single time step, thus reducing the expected quantum computation time for quantum circuits. By using magic state storage qubits, the distillation process for higher fidelity magic states may be restarted more quickly, resulting in an improved distillation rate. This, in turn, may reduce the number of magic state factories required, and therefore the number of logical qubits needed for optimal scheduling. A quantum chip with designated blocks for magic state storage may increase the robustness of the compiler's proposed schedule, because it allows the auxiliary patches generated during the compilation process to remain valid when considering uncertainties involved in the magic state distillation process. Frequently connected qubits may be placed closer to each other in the quantum chip layout to reduce the size of the auxiliary patches required to connect them. This can reduce the number of qubits blocked by auxiliary patches in the current time step, increasing the possibility of parallelizing quantum operations.

[0006] In one embodiment, the Disclosure provides a quantum chip comprising: (a) at least one magic state factory comprising a plurality of qubits configured to implement one or more non-Clifford gates and one or more distilling ports; (b) a plurality of data qubits; and (c) a quantum bus comprising a bus qubit adjacent to and operably coupled to each of the one or more distilling ports of the at least one magic state factory and to one or more of the plurality of data qubits, wherein the quantum bus is configured to connect the at least one magic state factory to at least one of the plurality of data qubits using the one or more distilling ports.

[0007] In some embodiments, the quantum bus includes at least one non-contractible sub-bus. In some embodiments, the at least one magic state factory includes two or more magic state factories arranged at multiple distillation levels. In some embodiments, the quantum chip further comprises one or more magic state storage qubits. In some embodiments, the quantum bus is configured to connect the at least one magic state factory to at least one of the multiple data qubits using the one or more distillation ports mediated through the magic state storage qubits.

[0008] In some embodiments, the quantum chip further includes one or more qubit resizing spaces, which are configured to perform quantum operations of resizing one or more qubits. In some embodiments, the one or more non-Clifford gates include at least one member selected from the group consisting of Toffoli gates, π / 8 Z-rotation gates (T-gates), and quantum rotation gates.

[0009] In some embodiments, the quantum chip has a layout representing a qubit type and its arrangement on the quantum chip, the layout including at least one member selected from the group consisting of tiles, triangles, hexagons, and rectangles. In some embodiments, the quantum chip has a qubit type including at least one member selected from the group consisting of bus qubits, data qubits, magic state storage qubits, auxiliary qubits, distillation ports, magic state factory qubits, magic state factory bus qubits, magic state factory data qubits, magic state factory storage qubits, and magic state factory auxiliary qubits. In some embodiments, the quantum chip has a layout including two or more magic state factory qubits surrounded by one or more distillation ports and two or more qubits of any qubit selected from the group consisting of bus qubits, data qubits, magic state storage qubits, and auxiliary qubits, the layout further including two or more bus qubits surrounding the two or more qubits. In some embodiments, the quantum chip has a layout that includes a first block of qubits having one or more data qubits surrounded by one or more bus qubits; a second block of qubits adjacent to the first block, the second block comprising one or more magic state storage qubits and one or more bus qubits; and a third block of qubits adjacent to the second block, the third block comprising one or more distillation ports and at least one magic state factory comprising a plurality of magic state factory qubits.

[0010] In some embodiments, the quantum chip has a layout that includes building blocks of a tileable subsystem. In some embodiments, the quantum chip has a layout that includes one or more blocks of four data qubits arranged adjacent to each other in a 2x2 table and surrounded by twelve bus qubits. In some embodiments, the quantum chip has a layout that includes a qubit lattice corresponding to a topological quantum code. In some embodiments, the topological quantum code is a surface code, a rotating surface code, or a color code.

[0011] In another aspect, the Disclosure provides a method for scheduling operations in a quantum circuit on a quantum chip, which includes at least one magic state factory, a plurality of data qubits, and a quantum bus. The method includes (a) acquiring a quantum circuit and layout, wherein the layout represents one or more qubit types and arrangements of qubits on the quantum chip, and the quantum circuit includes one or more quantum operations; (b) optimizing the scheduling of the one or more quantum operations, wherein the scheduling is subject to one or more constraints, which are at least partially based on the layout and depend on the quantum circuit, and the optimizing step includes solving at least a vertex-disjoint tree packing problem; and (c) reporting an optimized quantum circuit, which includes the optimized scheduling of the one or more quantum operations. Includes.

[0012] In some embodiments, (b) includes optimizing the quantum circuit by removing at least one of the one or more quantum operations, where at least one of the one or more quantum operations includes a Clifford gate. In some embodiments, (b) includes minimizing the computation time of the one or more quantum operations. In some embodiments, the layout includes a qubit grid corresponding to a topological quantum code. In some embodiments, the topological quantum code is a surface code, a rotating surface code, or a color code. In some embodiments, the layout includes at least one member selected from the group consisting of tiles, triangles, hexagons, and rectangles.

[0013] In some embodiments, the one or more qubit types include at least one member of the group consisting of bus qubits, data qubits, magic state storage qubits, auxiliary qubits, distillation ports, magic state factory qubits, magic state factory bus qubits, magic state factory data qubits, magic state factory storage qubits, and magic state factory auxiliary qubits. In some embodiments, the layout includes two or more magic state factory qubits surrounded by one or more distillation ports, and two or more qubits of any qubit selected from the group consisting of bus qubits, data qubits, magic state storage qubits, and auxiliary qubits, and the layout further includes two or more bus qubits surrounding the two or more qubits. In some embodiments, the layout includes a first block of qubits comprising one or more data qubits surrounded by one or more bus qubits; a second block of qubits adjacent to the first block, the second block comprising one or more magic state storage qubits and one or more bus qubits; and a third block of qubits adjacent to the second block, the third block comprising at least one magic state factory comprising one or more distillation ports, and a plurality of magic state factory qubits.

[0014] In some embodiments, the above arrangement of qubits includes building blocks for tileable subsystems. In some embodiments, the quantum circuit includes a sequence of quantum operations comprising at least one member selected from the group consisting of Toffoli gates, π / 8 Z rotation gates, and quantum rotation gates.

[0015] In some embodiments, the method further includes the step of implementing and executing the optimized quantum circuit. In some embodiments, (b) includes (b1) transforming the quantum circuit, which includes one or more quantum operations, into a dependency graph; (b2) defining an optimization problem using the dependency graph and the layout; and (b3) solving the optimization problem using an optimization procedure to schedule the one or more quantum operations of the quantum circuit. In some embodiments, the optimization procedure includes at least one member of the group consisting of maximum independent sets, Steiner trees, topology sorting, integer programming, branch-and-cut, and interior-point. In some embodiments, the optimization problem includes an objective function that minimizes quantum computation time, logical constraints of the quantum circuit, and physical constraints of the quantum hardware. In some embodiments, (b3) includes solving an allocation problem to determine a plurality of available data qubits to be used.

[0016] In another embodiment, the Disclosure provides a system for optimizing the scheduling of operations in a quantum circuit on a quantum chip comprising at least one magic state factory, a plurality of data qubits, and a quantum bus. The system comprises a memory having instructions configured to perform at runtime at least (i) acquire a quantum circuit and layout, wherein the layout represents one or more qubit types and arrangements of qubits on the quantum chip, and the quantum circuit comprises one or more quantum operations; (ii) optimize the scheduling of the one or more quantum operations, wherein the scheduling is subject to one or more constraints, and the one or more constraints are at least partially based on the layout and the quantum circuit, and the optimization includes solving at least a point-element tree packing problem; and (iii) report an optimized quantum circuit comprising the optimized scheduling of the one or more quantum operations, wherein the digital computer may be communicatively coupled to a quantum computer, and the quantum computer is configured to implement the scheduled quantum circuit.

[0017] In some embodiments, the system further comprises the quantum computer. In some embodiments, the quantum computer includes a quantum chip of any form or embodiment. In some embodiments, the system further comprises a special-purpose computing platform, which is configured to receive and execute instructions for implementing at least an optimization procedure for solving an optimization problem for optimizing operations in the quantum circuit, and the special-purpose computing platform is communicably coupled to the digital computer or the quantum computer or both. In some embodiments, the special-purpose computing platform includes a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a tensor processing unit (TPU), and a tensor streaming processor (TSP). It includes at least one member of the group consisting of .

[0018] In another embodiment, the Disclosure provides a system for scheduling operations in a quantum circuit on a quantum chip, comprising at least one magic state factory, a plurality of data qubits, and a quantum bus. The system is a quantum computer comprising a quantum chip, comprising: (i) at least one magic state factory comprising a plurality of qubits configured to implement one or more non-Clifford and one or more distillation ports; (ii) a plurality of data qubits; and (iii) a quantum bus comprising bus qubits adjacent to and operably coupled to each of the one or more distillation ports of the at least one magic state factory and to one or more qubits of the plurality of data qubits, wherein the quantum computer is configured to perform operations in the quantum circuit, and the quantum computer is communicably coupled to a digital computer, the digital computer is configured to optimize the scheduling of operations in the quantum circuit on the quantum chip.

[0019] In some embodiments, the system further comprises a digital computer. In some embodiments, the digital computer is configured to carry out any method of any aspect or embodiment.

[0020] In some embodiments, the system further comprises a dedicated computing platform configured to receive and execute instructions for implementing at least optimization procedures to solve optimization problems for optimizing operations in the quantum circuit, and the dedicated computing platform is communicably coupled to the digital computer or the quantum computer or both. In some embodiments, the dedicated computing platform includes at least one member of the group consisting of a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a tensor processing unit (TPU), and a tensor streaming processor (TSP).

[0021] While only exemplary embodiments of this disclosure have been shown and described, further aspects and advantages of this disclosure will be readily apparent to those skilled in the art from the following detailed description. As will be understood, other different embodiments of this disclosure are possible, and some of their details can be modified in various obvious ways without departing from this disclosure. Accordingly, the drawings and description should be considered illustrative and not restrictive.

[0022] Reference All publications, patents, and patent applications referenced herein are incorporated by reference to the same extent that each individual publication, patent, or patent application is specifically and individually indicated as being incorporated by reference. To the extent that any publications and patents or patent applications incorporated by reference are in conflict with the disclosures contained herein, this Specified is intended to supersede and / or take precedence over any such incongruous material. [Brief explanation of the drawing]

[0023] Novel features of the present invention are described in detail in the appended claims. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of exemplary embodiments in which the principles of the invention are utilized, and to the accompanying drawings (also referred to herein as "Figures" and "FIGs"). [Figure 1A] FIG. is a diagram of an exemplary quantum chip layout comprising at least one magic state factory surrounded by a plurality of data qubits and quantum buses. [Figure 1B] FIG. is a diagram of an exemplary quantum chip layout comprising a block having at least one magic state factory, a block having at least one magic state storage qubit, and a block having a plurality of data qubits and quantum buses. [Figure 1A] [Figure 1C] FIG. is a diagram of an exemplary quantum chip layout comprising a triangular color code having at least one magic state factory, a plurality of data qubits, and a quantum bus. [Figure 2] FIG. is a diagram of an exemplary quantum chip layout disclosed with respect to FIG. 1B having a number of auxiliary patches that can be used to connect a plurality of qubits to execute quantum operations in parallel. [Figure 1B] [Figure 3] FIG. is a schematic diagram of an exemplary system for optimizing the scheduling of operations in a quantum circuit on a quantum chip comprising at least one magic state factory, a plurality of data qubits, and a quantum bus, according to some embodiments disclosed herein. [Figure 4] FIG. is a flowchart of an exemplary method for optimizing the scheduling of operations in a quantum circuit on a quantum chip comprising at least one magic state factory, a plurality of data qubits, and a quantum bus, according to some embodiments disclosed herein. [Figure 1C] [Figure 5] FIG. is a flowchart of an exemplary procedure used by the method disclosed with respect to FIG. 4 for optimizing the scheduling of operations in a quantum circuit on a quantum chip, according to some embodiments disclosed herein. Detailed Description of the Invention

[0024] Although various embodiments of the present invention are shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, modifications, and substitutions may occur to those skilled in the art without departing from the present invention. It should be understood that various alternatives to the embodiments of the present invention described herein may be employed.

[0025] Neither the title of the invention nor the abstract shall be construed as limiting the scope of the disclosed invention. The title of the invention of this application and the headings of the sections provided in this application are for convenience only and shall in no way be construed as limiting the present disclosure.

[0026] Unless otherwise defined, all technical terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. When used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. Any reference to “or” in this specification is intended to include “and / or” unless specifically stated otherwise.

[0027] The term “plurality” generally refers to “two or more” unless specifically stated otherwise.

[0028] The terms "e.g." and similar terms mean "for example" and therefore do not limit the terms or phrases they describe. For example, in the sentence "A computer transmits data (e.g., instructions, data structures) over the internet," the term "e.g." also describes that "instructions" are examples of "data" that a computer can transmit over the internet, and that "data structures" are examples of "data" that a computer can transmit over the internet. However, both "instructions" and "data structures" are merely examples of "data," and other things besides "instructions" and "data structures" can also be "data."

[0029] Whenever the terms “at least,” “greater than,” or “greater than or equal to” precede a first number in a set of two or more numbers, the terms “at least,” “greater than,” or “greater than or equal to” apply to each number in the set. For example, 1, 2, or 3 or more corresponds to 1 or more, 2 or more, or 3 or more.

[0030] Whenever the terms “no more than,” “less than,” or “less than or equal to” precede a first number in a set of two or more numbers, the terms “no more than,” “less than,” or “less than or equal to” apply to each number in the set. For example, 3, 2, or 1 or less corresponds to 3 or less, 2 or less, or 1 or less.

[0031] Where a value is described as a range, this disclosure includes all possible subranges within such range, as well as disclosures of any specific numerical value that falls within such range, whether or not a particular numerical value or a particular subrange is explicitly described.

[0032] The specific inventorial embodiments described herein involve numerical ranges. Where a range exists, it includes its endpoints. Furthermore, any subranges and the values ​​within them exist as if they were explicitly described.

[0033] The terms “about” or “approximately” can mean a range of error within which a particular value is permissible, and this depends in part on how that value is measured or determined, for example, on the limitations of the measurement system. For example, “about” may mean within or more than one standard deviation, according to convention in the art. Alternatively, “about” may mean a range of up to 20%, up to 10%, up to 5%, or up to 1% of a given value. Where a particular value is described in this application and claims, unless otherwise specified, the term “about” may be assumed to mean a range of error within which that particular value is permissible.

[0034] The systems and methods of this disclosure provide optimization procedures for improving the scheduling of operations in quantum circuits on a quantum chip having a layout. While some progress has been made to solve these optimization problems, significant shortcomings remain. Two recent studies by Litinski ("A Game of Surface Codes: Large-Scale Quantum Computing with Lattice Surgery," Quantum 3, p.128, 2019; this paper is incorporated herein by reference in its entirety) and Beverland et al. ("Surface Code Compilation via Edge-Disjoint Paths," PRX Quantum 3, 020342, 2022; this paper is incorporated herein by reference in its entirety) have proposed optimization procedures. However, these approaches may have limitations.

[0035] For example, a quantum chip layout having a collapseable quantum bus can restrict the scheduling of quantum operations to occur in serially, since only a single multi-qubit auxiliary patch can be generated at a time. In another example, the systems and methods of the present disclosure may provide a quantum bus that is non-collapsed or has at least one non-collapsed sub-bus. A non-collapsed quantum bus may include a layout of bus qubits in which at least one cycle exists. For example, a graph is considered non-collapsed because it does not have the mathematical property of being collapseable (i.e., the graph contains cycles), where two vertices are connected when the vertices correspond to individual bus tile and the corresponding bus tiles share an edge (i.e., are adjacent to each other).

[0036] In another example, the systems and methods disclosed herein may allow for flexibility in the allocation of magic state storage qubits. For example, a magic state storage qubit may not be dedicated to a particular magic state factory. A drawback of dedicating a magic state storage qubit to a magic state factory, though not limited by theory, is that when magic state distillation cannot send a magic state to that storage, a quantum operation scheduled to use an empty magic state storage qubit may have to be rescheduled to use another magic state storage qubit or distillation port, or wait until a magic state becomes available in that magic state storage qubit, increasing either classical or quantum computation time.

[0037] The systems and methods disclosed herein can integrate the quantum corrections required for non-Clifford gates. In some cases, the quantum corrections used for non-Clifford gates can be moved to the ends of the quantum circuit and incorporated into the final qubit measurement. Although not limited by theory, moving the quantum corrections used for non-Clifford gates to the ends may require updating subsequent quantum operations in the circuit, which involves significant classical computational overhead. As a result, applying this technique in real time may not always be feasible.

[0038] This specification recognizes the need for improved methods and systems that can overcome at least one of the shortcomings identified above.

[0039] Quantum computing Quantum computing can be a method of computing that utilizes the concepts of quantum superposition and entanglement to manipulate information. In contrast, classical computers can use binary bits, i.e., 0s and 1s. Quantum entanglement can be a phenomenon in which, when multiple qubits interact with each other, their quantum states become entangled and can no longer be represented individually. Quantum superposition can be the principle that the quantum state of a qubit can be represented by adding two or more different quantum states, each associated with a probability. In some cases, the sum of the probabilities of all states is 1. Quantum circuits containing one or more quantum gates can be designed to perform quantum computations, such as factoring large prime numbers, which may be impossible or highly inefficient for classical computers. Quantum gates can also contain logical operators, which contain one or more qubits that can be used to perform logical operations.

[0040] In contrast to quantum computing, classical computing can be computation performed using binary values ​​with discrete bits, without using quantum mechanical superposition and quantum mechanical entanglement. A classical computer can be a digital computer, such as a computer that uses discrete bits (e.g., multiple 0s or 1s), without using quantum mechanical superposition and quantum mechanical entanglement. A non-classical computer may have any method or system for performing computational procedures outside the paradigm of classical computing.

[0041] A quantum device can be any device or system for performing computations using any quantum mechanical phenomenon, such as quantum superposition and quantum mechanical entanglement. Quantum computation, quantum procedures, quantum operations, and quantum computers described herein may comprise any method or system for performing computations using quantum mechanical operations on Hilbert space represented by a quantum device (such as unitary transforms on quantum channels or completely positive trace-preserving (CPTP) maps). A quantum chip can be a physical device capable of leveraging quantum phenomena that enable the execution of quantum gates for computing purposes.

[0042] A qubit, an abbreviation for quantum bit, can be the fundamental unit of quantum information. A qubit can contain a quantum state that includes a complex unit vector of dimension 2. These two dimensions can be called 0 and 1. A physical qubit can be a physical implementation of a qubit. For example, a superconducting qubit can be a physical qubit implemented using superconducting electronic circuits. When quantum error correction is used, a logic qubit can be a set of physical qubits that encode a single fault-tolerant qubit. A data qubit can be one of the qubits used to encode quantum information for quantum computation. It can contain part of the input state or part of the output state. When quantum error correction is used, it can be a logic qubit; otherwise, it can be a physical qubit. An auxiliary qubit can be one of the additional qubits used to perform quantum operations more efficiently or to perform intermediate computations. If quantum error correction is used, it may include logical qubits; otherwise, it may include physical qubits.

[0043] A circuit can contain a representation of a computational model in which the computation involves a sequence of gates. In some cases, a circuit can be used in gate-model quantum computing. In some cases, a circuit can be a quantum circuit, such as a sequence of qubit gates used in gate-model quantum computing. A quantum circuit can contain the preparation of an initial state for a set of qudits, followed by the performance of gate operations and measurements on it. A quantum circuit can comprise a sequence of quantum gates that perform some quantum computations on a set of qubits. The sequence may contain several small sets of gates, but may also contain more complex operations.

[0044] A quantum gate operation can include a quantum gate, a sequence of quantum gates, or a combination of quantum gates and quantum measurements that perform isometry on the quantum states of a qubit. For example, a quantum gate can be implemented between data qubits through a quantum operation involving a data qubit, an auxiliary qubit, a magic state storage qubit, and a bus qubit connecting these qubits. Two-qubit gates and one-qubit gates can include quantum logic gates used to perform logical operations. A two-qubit gate can have two qubits. A one-qubit gate can have one qubit.

[0045] A quantum chip may include a physical device that can utilize quantum phenomena to enable the execution of quantum gates for computing purposes. A quantum chip may feature a quantum machine system in which well-defined quantum operations are performed to carry out several quantum computations. For example, ion-trap systems and super-conducting devices are currently mainstream in this field, but other implementations exist and can be constructed.

[0046] Quantum measurement may involve processes for extracting classical information from quantum states generated on a quantum device. Quantum computing devices may use quantum gates. A quantum gate can be a qubit operation that can be represented by a unitary operation on the quantum state of a qubit. Quantum gate operations may include quantum gates, sequences of quantum gates, or combinations of quantum gates and quantum measurements that perform isometry on the quantum state of a qubit. For example, a gate, a two-qubit gate, and a one-qubit gate may be used to perform logical operations. A one-qubit gate may contain one qubit. A two-qubit gate may contain two qubits.

[0047] Error Correction Quantum correction, or quantum error correction, may involve additional quantum operations that can be performed to reduce error rates in a quantum computing system. For example, if a measurement indicates that the resulting quantum state is different from the quantum state required to continue the computation correctly, error correction may be performed after the measurement.

[0048] A quantum code may include a mathematical framework for encoding quantum data into a larger Hilbert space to protect against errors. This error protection may involve using multiple physical qubits to encode a single logical qubit. Therefore, an error-corrected quantum code may be more costly than a straight-forward computation. In some cases, only a subset of all quantum gates may be executed against these quantum codes, and thus it becomes necessary to decide how to perform arbitrary computations while remaining within the encoded subspace. In some cases, this can be done by augmenting a set of quantum gates that can be implemented using magic states, which are qubit states that can enable additional fault-tolerant quantum behavior.

[0049] Topological quantum codes can include types of quantum codes where data is topologically protected. Many state-of-the-art codes, such as surface codes and color codes, are of this type. Generally, these codes have quantum error correction schemes.

[0050] Examples of quantum error correction schemes for FTQC include surface codes, revolving surface codes, and color codes (Fowler et al., “Surface codes: Towards practical large-scale quantum computing,” Physical Review A 86, 032324, 2012, and Bombin, “Topological code”, in Lidar and Brun (Eds.), Quantum Error Correction, pp. 455-481, Cambridge University Press, 2013: each of these publications is incorporated herein by reference in its entirety). These schemes may use a two-dimensional grid of coded logic qubit patches that constitute the layout of the quantum chip. Logic operations of the quantum circuit may be performed by connecting the qubits required by each quantum operation. Connecting multiple qubits that are far apart may be done using auxiliary regions.

[0051] A qubit containing an auxiliary region may contain bus qubits. A quantum bus may contain bus qubits. A quantum bus may contain a set of bus qubits. Auxiliary patches may be generated either inside or outside the magic state factory to facilitate the movement and connection of data qubits, auxiliary qubits, magic state storage qubits, and distillation ports. A quantum bus may contain at least one subbus consisting of at least one subset of bus qubits disconnected from at least one other bus qubit.

[0052] Auxiliary patches may include a tree-like structure used to connect multiple qubits within a quantum chip to perform quantum operations. Auxiliary patches may also include the use of multiple bus qubits from a quantum bus when the connected qubits are far apart. Auxiliary patches can be generated without using bus qubits to connect the coupled qubits. Auxiliary patches can be used in a variety of quantum operations.

[0053] Some operations that implement Clifford gates in quantum circuits may involve connecting only data qubits, or connecting data qubits to auxiliary qubits. In some cases, operations that implement non-Clifford gates may also involve connecting data qubits to magic state qubits. Clifford gates may include Hadamard gates, phase gates S (e.g., Z rotation), also called S gates, and one of the quantum gates mathematically defined as those produced by CNOT (controlled not) operations between qubits. Some operations that implement Clifford gates may involve using auxiliary patches to connect at least two data qubits or at least one data qubit to an auxiliary qubit. Non-Clifford gates may include one of the quantum gates other than those included in the Clifford group. Examples of non-Clifford gates include Toffoli gates (controlled gates, uncontrolled gates), phase gates T (also called T gates and π / 8 Z rotation gates), and arbitrary Z rotations. In some cases, a non-Clifford gate may be implemented by a quantum operation that uses one or more magic states, which may include an operation that implements a Clifford gate for quantum correction. The magic states may include qubit states that enable fault-tolerant quantum operations, including the non-Clifford gate. The non-Clifford gate may include using an auxiliary patch to connect at least one data qubit to one qubit in the magic state, which is either a distillation port or a magic state storage qubit.

[0054] FTQC may involve distilling before using higher fidelity magic states to reduce the probability of errors. Higher fidelity magic states can be distilled from lower fidelity magic states using a magic state distillation protocol. The magic state protocol may specify the number of lower fidelity magic states required to distill the higher fidelity ones, the number of higher fidelity magic states to be distilled, and at least some or all of the set of quantum operations required for distillation, which may determine the duration of the distillation process. Magic state distillation may involve transforming a group of magic states with some given error probabilities into fewer magic states with smaller error probabilities. Several such magic state distillation protocols exist, including the 15:1 protocol, which takes 15 T-state magic states as input and outputs 1 T-state magic state; the 8:1 Toffoli protocol, which takes 8 T-state magic states as input and outputs 1 Toffoli-state magic state; and the 3k+8:k protocol, which takes 3k+8T state magic states as input and outputs k T-state magic states. As is clear from these examples, it is possible to output multiple magic states during this process, as well as to change the type of magic states during this process. The magic state distillation process may fail, and fewer magic states than expected may be distilled.

[0055] The magic state distillation protocol can be time-consuming. To reduce this time, magic state distillation can be performed in a magic state factory where qubits are arranged to efficiently execute the protocol. The magic state factory may have a dedicated block of tiles on a quantum chip, and the protocol for magic state distillation is used to distill magic states with higher fidelity. It may include a group of qubits and quantum buses used for distilling magic states, and a group of distillation ports, where the distilled magic states can be transmitted after distillation and accessed by qubits outside the magic state factory using an external quantum bus.

[0056] In some cases, higher-fidelity magic states can be distilled by a factory in a distillation port qubit located at the boundary between the magic state factory and the rest of the chip. The distillation port may include a qubit within the quantum chip located in the magic state factory, acting as an interface between the magic state factory and the rest of the chip. The distillation port may hold the magic states distilled in its magic state factory, allowing the magic states to be transferred or used elsewhere within the quantum chip.

[0057] In some cases, a magic state may remain in the distillation port until used by an operation implementing a non-Clifford gate, or it may be transferred to a magic state storage qubit whenever convenient. A magic state storage qubit may comprise a qubit within a quantum chip used to store magic states. Magic states may be transferred from a distillation port or another magic state storage qubit to another magic state storage qubit. Magic state storage qubits may be connected to other qubits to consume their magic states and execute non-Clifford gates. Magic state storage qubits may be connected to auxiliary qubits using auxiliary patches to be restored after their use so that they can store another magic state again.

[0058] Quantum chip layout problems and computation scheduling problems in quantum circuits may each include optimization problems. An optimization problem may include any problem involving minimizing or maximizing an objective function defined on a given domain. An optimization procedure may include a protocol, algorithm, or method for solving an optimization problem exactly or heuristically. An optimization problem may minimize or maximize the objective function to an absolute maximum or absolute minimum value. An optimization problem may minimize or maximize the objective function to a relative maximum or relative minimum value. An optimization problem may decrease or increase the objective function to a quantity approaching an absolute maximum or absolute minimum value. In some cases, an optimization problem may approximate an absolute maximum or absolute minimum value. In some cases, minimization and maximization as used herein may include mathematical operations of maximization or minimization. In some cases, mathematical operations of maximization or minimization may result in reaching an exact maximum or minimum value. In some cases, mathematical operations of maximization or minimization may result in reaching an approximate maximum or approximate minimum value.

[0059] Classical computation time can include the time spent using classical devices to execute computational procedures, such as optimization procedures for solving optimization problems. Quantum computation time can include the time required to execute quantum algorithms using quantum devices. For example, the time spent following a solution found for an optimization problem, such as scheduling quantum operations from a quantum circuit representing a quantum algorithm.

[0060] Solving the quantum chip layout problem is a challenging task, as it may involve specifying the arrangement of qubits within the chip, taking into account the fundamental quantum operations for scheduling calculations in quantum circuits. In some cases, a modular approach to qubit arrangement for large-scale quantum computing on surface code can be implemented. A module may consist of data blocks containing data qubits and quantum buses, and distillation blocks containing magic state factories, which together represent a full quantum chip. The data blocks may be arranged so that data qubits and distillation ports are connected using the quantum bus. The proposed compact layout may increase the density of data qubits within the quantum chip, but may require extra operations to rotate these qubits so that all quantum operators requiring these qubits can be executed. Other proposed layouts may avoid these extra operations by reducing the density of data qubits. An alternative arrangement of data blocks may include individual data qubits surrounded by a quantum bus, resulting in a layout with a lower density of data qubits but more space on the quantum bus for parallelizing scheduled quantum operations (Horsman et al., “Surface code quantum computing by lattice surgery,” New Journal of Physics 14, 123014, 2012; this document is incorporated herein by reference in its entirety).

[0061] To solve the computation scheduling problem in quantum circuits, a compiler can be used to generate instructions that minimize quantum computation time. This time can be measured by the number of time steps required to perform all quantum operations, scheduled to satisfy the constraints imposed by the quantum chip layout. Since quantum operations often involve measuring distant qubits, distant qubits can be made to interact through ancilla patches. Parallelizable quantum operations, according to the logic constraints of the quantum circuit, can be scheduled to run in the same time steps, provided that ancilla patches can be generated for quantum operations that do not violate the physical constraints of the quantum hardware, such as not sharing any bus qubits simultaneously. Generating numerous auxiliary patches to connect multiple qubits in the same time step may involve solving an NP-hard optimization problem, also known as the vertex-disjoint tree packing problem, which may be impractical for large-scale quantum computing (Herr et al., “Optimization of lattice surgery is NP-hard,” npj Quantum Information 3, no.35, 2017; this paper is incorporated herein by reference in its entirety).

[0062] In some cases, to address this optimization problem, heuristic algorithms can be used to reduce the classical computation time required to generate the quantum circuit schedule. For example, quantum operations can be scheduled sequentially, which avoids the explicit generation of auxiliary patches to evaluate the feasibility of parallelization. In some cases, specific data block layouts can also be proposed to enable the parallel scheduling of two quantum operations by generating auxiliary patches that are guaranteed not to violate physical constraints. In some cases, auxiliary patches can be generated to connect multiple parallelizable quantum operations.

[0063] Quantum devices / quantum hardware Any type of quantum hardware may be suitable for the technologies disclosed herein. Quantum processors or quantum computers include one or more quantum gate arrays, one-way quantum computers, topological quantum computers, superconductor-based quantum computers, trapped ion quantum computers, trapped atom quantum computers, optical lattices, quantum dot computers, spin-based quantum computers, spatial-based quantum computers, Loss-DiVincenzo quantum computers, nuclear magnetic resonance (NMR)-based quantum computers, solution-state NMR quantum computers, solid-state NMR quantum computers, solid-state NMR Kane quantum computers, and electrons-on-helium quantum computers. quantum computers, cavity-quantum-electrodynamics based quantum computers, molecular magnet quantum computers, fullerene-based quantum computers, linear optical quantum computersQuantum processors or quantum computers may include diamond-based quantum computers, nitrogen-vacancy (NV) diamond-based quantum computers, Bose-Einstein condensate-based quantum computers, transistor-based quantum computers, and rare-earth-metal-ion-doped inorganic crystal-based quantum computers. A quantum processor or quantum computer may include one or more of the following: quantum annealers, Ising solvers, optical parametric oscillators (OPOs), and gate model quantum computers.

[0064] A quantum processor or quantum computer may contain one or more qubits. These qubits include superconducting qubits, trapped ion qubits, trapped atom qubits, photon qubits, quantum dot qubits, electron spin-based qubits, nuclear spin-based qubits, molecular magnet qubits, fullerene-based qubits, diamond-based qubits, nitrogen-vacancy (NV) diamond-based qubits, Bose-Einstein condensate-based qubits, and transistor-based qubits. This may include qubits, or rare-earth-metal-ion-doped inorganic crystal-based qubits.

[0065] In some cases, quantum devices having limitations on the two-dimensional structure of the quantum chip, or limitations on how many adjacent qubits each qubit can connect to, may benefit from the methods and systems disclosed herein. In accordance with the description herein, suitable quantum computers include, as non-limiting examples, superconducting quantum computers (qubits implemented as small superconducting circuits-Josephson junctions) (Clarke et al., “Superconducting quantum bits”, Nature 453, no.7198, pp.1031-1042, 2008), trapped ion quantum computers (qubits implemented as states of trapped ions) (Kielpinski et al., “Architecture for a large-scale ion-trap quantum computer”, Nature 417, no.6890, pp.709-711, 2002), and optical lattice quantum computers (qubits implemented as states of neutral atoms trapped in an optical lattice) (Deutsch et al., “Quantum computing with neutral atoms in an optical lattice”, Fortschritte der Physik: Progress of Physics). 48, no.9-11, pp.925-943, 2000), spin-based quantum dot computers (qubits implemented as the spin states of trapped electrons) (Imamoglu et al., “Quantum information processing using quantum dot spins and cavity QED”, Physical Review Letters 83, no.20, p.4204, 1999), spatial-based quantum dot computers (qubits implemented as electron positions in double quantum dots) (Fedichkin et al., “Novel coherent quantum bit using spatial quantization levels in semiconductor quantum dot”, arXiv:quant-ph / 0006097, 2000), coupled quantum wires (qubits implemented as pairs of quantum wires coupled by quantum point contact) (Bertoni et al., “Quantum logic gates based on coherent electron transport in quantum wires”, Physical Review Letters 84, no.25, p.5912, 2000), nuclear magnetic resonance quantum computers (qubits implemented as nuclear spins and explored by radio waves) (Cory et al., “Nuclear magnetic resonance spectroscopy: An experimentally accessible paradigm for quantum "computing", arXiv:quant-ph / 9709001, 1997), Solid-state NMR Kane quantum computer (qubits implemented as nuclear spin states of phosphorus donors in silicon) (Kane, "A silicon-based nuclear spin quantum computer", Nature 393, no.6681, pp.133-137, 1998), electrons-on-helium quantum computers (qubits implemented as electron spins) (Lyon, "Spin-based quantum computing using electrons on liquid helium", arXiv:cond-mat / 0301581, 2006), cavity quantum electrodynamics-based quantum computers (qubits implemented as states of trapped atoms coupled to high-finesse cavities) (Burell, "An Introduction to Quantum Computing using Cavity QED concepts", arXiv:1210.6512, 2012), molecular magnet-based quantum computers (qubits implemented as spin states) (Leuenberger et al., "Quantum Computing in Molecular Magnets, arXiv:cond-mat / 0011415, 2001), fullerene-based electron spin resonance (ESR) quantum computers (qubits implemented as electron spins of atoms or molecules encased in fullerenes) (Harneit, “Quantum Computing with Endohedral Fullerenes”, arXiv:1708.09298, 2017), linear optical quantum computers (qubits implemented as processing different modes of optical states through linear optical elements such as mirrors, beam splitters, and phase shifters) (Knill et al."Efficient linear optics quantum computation", rXiv:quant-ph / 0006088, 2000), diamond-based quantum computers (qubits implemented as electron or nuclear spins at nitrogen vacancy (NV) centers in diamond) (Nizovtsev et al., "A quantum computer based on NV centers in diamond: optically detected nutations of single electron and nuclear spins", Optics and spectroscopy 99, no.2, pp.233-244, 2005), Bose-Einstein condensate-based quantum computers (qubits implemented as two-component Bose-Einstein condensates) (Byrnes et al., "Macroscopic quantum computation using Bose-Einstein condensates", arXiv:quantum-ph / 1103.5512, 2011), transistor-based quantum computers (nanophotonic cavity (Quantum bits implemented as semiconductors coupled to cavities) (Sun et al., “A single-photon switch and transistor enabled by a solid-state quantum memory”, arXiv:quant-ph / 1805.01964, 2018), rare-earth metal ion-doped inorganic crystal-based quantum computers (quantum bits implemented as hyperfine levels of the atomic ground state in rare-earth ion-doped inorganic crystals) (Ohlsson et al. “Quantum computer hardware based on rare-earth-ion-doped inorganic crystals”, Optics Communications 201, no.1-3, pp.71-77, 2002), and metal-like carbon nanosphere-based quantum computers (qubits implemented as electron spins in conducting carbon nanospheres) (Nafradi et al., “Room temperature manipulation of long lifetime spins in metallic-like carbon nanospheres”, arXiv:cond-mat / 1611.07690, 2016), topological quantum computers (qubits implemented as non-Abelian anyons) (Nayak et al., “Non-Abelian Anyons and Topological Quantum Computation,” arXiv:0707.1889, 2007), photonic continuous-variable quantum computing hardware (quadrature operators of quantum harmonic oscillators in quantum optical modes) Quantum variables represented by operators) (Arrazola et al., “quantum circuits with many photons on a programmable nanophotonic chip”, Nature 591, pp.54-60, 2021), photonic qubit-based quantum hardware (qubits implemented on pairs of optical paths) (O'Brien et al., “Photonic quantum technologies”, Nature Photonics 3, pp.687-695, 2009), quantum computing hardware based on bosonic codes (error-protected qubits are formed by embedding a finite-dimensional code space within an infinite-dimensional Fock space associated with a bosonic quantum field mode), examples include Gottesman-Kitaev-Preskill (GKP) codes, cat codes, and binary codes, respectively (Gottesman et al., “Encoding a qubit in a oscillator”, Physical Review A 64, 012310, 2001), Chamberland et al., “Building a Fault-Tolerant Quantum Computer Using Concatenated Cat Codes,” PRX Quantum 3, 010329, 2022; Michael et al., “New Class of Quantum Error-Correcting Codes for a Bosonic Mode,” Physical Review X 6, (031006, 2016), quantum hardware based on coherent network computing (a network of optical parametric oscillators with all-to-all connectivity) achieves low Ising Hamiltonian by encoding spin. By sampling energy eigenstates, computations can be performed, and future architectures may utilize quantum entanglement for computation (Inui et al., “Entanglement and quantum discord in optically coupled coherent Ising machines,” Physical Review A 102, 062419, 2020, and Yanagimoto et al., “Embedding entanglement generation within a measurement-feedback coherent Ising machine,” arXiv:1906.04902, 2019), each of these publications is incorporated herein by reference for all purposes.

[0066] High-Performance Computing Device Computing devices that can interact with the quantum computing devices disclosed herein and enhance the dedicated computing platforms disclosed herein may be high-performance computing (HPC) devices. HPC devices may comprise one or more of the following: graphics processing units (GPUs), tensor processing units (TPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and tensor streaming processors (TSPs). Any other suitable processing unit capable of performing matrix multiplication may be used. Certain computing devices may be more efficient in operations such as matrix multiplication. These computing devices may offer further efficiency improvements over other computing systems. For example, a matrix multiplier device may be a GPU. A GPU may be a specialized electronic circuit optimized for high throughput that can perform the same set of operations in parallel on a large number of data blocks at once. For example, a matrix multiplier device may be a TPU. A TPU may be a type of ASIC developed by Google Inc. for low-bit precision processing. For example, a matrix multiplier device may be an FPGA. An FPGA may be an integrated circuit chip containing configurable logic blocks and programmable interconnects. It can be programmed to run custom algorithms after manufacturing. For example, a matrix multiplication device could be an ASIC. An ASIC can be an integrated circuit chip customized to perform a specific algorithm. In some cases, it is not possible to program an ASIC after it has been manufactured. For example, a matrix multiplication device could be a TSP. A TSP can be a domain-specific programmable integrated chip designed for linear algebra computations, where linear algebra computations may be performed in artificial intelligence applications. An example of this can be found in Gwennap, “Groq Rocks Neural Networks,” Microprocessor Report, Tech.Rep., Jan., 2020, which is incorporated herein by reference in its entirety.

[0067] Digital computer In some cases, a digital computer has one or more hardware central processing units (CPUs) that perform the functions of a classical computer. In some cases, a classical computer further has an operating system (OS) configured to execute executable instructions. In some cases, a classical computer is connected to a computer network.

[0068] In some cases, a classic computer is connected to a computer network. In some cases, a classic computer is connected to the Internet to access the World Wide Web. In some cases, a classic computer is connected to one or more computer servers, which can enable distributed computing, such as cloud computing infrastructure. In some cases, a classic computer is connected to an intranet and / or extranet, or an intranet and / or extranet that communicates with the Internet. In some cases, a classic computer is connected to a data storage device. In some cases, the network is a telecommunications and / or data network. In some cases, the network is a peer-to-peer network, which can allow devices connected to a computer system to behave as clients or servers.

[0069] In accordance with the description herein, suitable classic computers may include, in non-limiting examples, server computers, desktop computers, laptop computers, notebook computers, subnotebook computers, netbook computers, netpad computers, set-top computers, media streaming devices, handheld computers, internet appliances, mobile smartphones, tablet computers, personal digital assistants, video game consoles, and vehicles. Smartphones may be suitable for use with the methods and systems described herein. In some cases, with computer network connectivity, selections of televisions, video players, and digital music players may be suitable for use in the systems and methods described herein. Suitable tablet computers may include those having booklet, slate, and convertible configurations.

[0070] In some cases, a classic computer includes an operating system configured to execute executable instructions. An operating system can be, for example, software containing programs and data that manages the device's hardware and provides services for running applications. Suitable server operating systems, in non-exclusive examples, include FreeBSD, OpenBSD, NetBSD®, Linux®, Apple® Mac OS X Server®, Oracle® Solaris®, Windows Server®, and Novell® NetWare®. Suitable personal computer operating systems, in non-exclusive examples, may include Microsoft® Windows®, Apple® Mac OS X®, Apple® macOS®, UNIX®, and UNIX®-like operating systems such as GNU / Linux®. In some cases, the operating system is provided by cloud computing. Appropriate mobile smartphone operating systems may include, but are not limited to, Nokia® Symbian® OS, Apple® iOS®, Research In Motion® BlackBerry OS®, Google® Android®, Microsoft® Windows Phone® OS, Microsoft® Windows Mobile® OS, Linux®, Palm®, and WebOS®.Suitable media streaming device operating systems may include, but are not limited to, Apple TV®, Roku®, Boxee®, Google TV®, Google Chromecast®, Amazon Fire®, and Samsung® HomeSync®. Suitable video game console operating systems may include, but are not limited to, Sony® PS3®, Sony® PS4®, Microsoft® Xbox 360®, Microsoft® Xbox One®, Nintendo® Wii®, Nintendo® Wii U®, and Ouya®.

[0071] In some cases, a classic computer includes storage devices and / or memory devices. In some cases, storage devices and / or memory devices are one or more physical devices used to temporarily or permanently store data or programs. In some cases, storage devices and / or memory devices may have one or more additional data storage units located outside the classic computer, for example, on a remote server communicating with the classic computer via an intranet or the internet. In some cases, the device has volatile memory and requires power to maintain the stored information. In some cases, the device has non-volatile memory and retains the stored information when the classic computer is not powered. In some cases, the non-volatile memory is flash memory. In some cases, the non-volatile memory is dynamic random-access memory (DRAM). In some cases, the non-volatile memory is ferroelectric random-access memory (FRAM). In some cases, the non-volatile memory is phase-change random-access memory (PRAM). In some cases, non-volatile memory includes resistive random-access memory (RRAM). In some cases, the device includes a storage device, which in non-limiting examples include CD-ROMs, DVDs, flash memory devices, magnetic disk drives, magnetic tape drives, optical disk drives, and cloud computing-based storage. In some cases, the storage device and / or memory device includes a combination of devices such as those disclosed herein.

[0072] In some cases, a classical computer includes a display for transmitting visual information to the user. In some cases, the display is a cathode ray tube (CRT). In some cases, the display is a liquid crystal display (LCD). In some cases, the display is a thin-film transistor liquid crystal display (TFT-LCD). In some cases, the display is an organic light-emitting diode (OLED) display. In some cases, the OLED display is a passive-matrix OLED (PMOLED) or an active-matrix OLED (AMOLED) display. In some cases, the display is a plasma display. In some cases, the display is a video projector. In some cases, the display is a combination of devices such as those disclosed herein.

[0073] In some cases, a classic computer includes an input device for receiving information from a user. In some cases, the input device is a keyboard. In some cases, the input device is a pointing device, including, in non-limiting examples, a mouse, trackball, trackpad, joystick, game controller, or stylus. In some cases, the input device is a touchscreen or multi-touchscreen. In some cases, the input device is a microphone for capturing voice or other audio input. In some cases, the input device is a video camera or other sensor for capturing motion or visual input. In some cases, the input device is Kinect®, Leap Motion®, etc. In some cases, the input device is a combination of devices such as those disclosed herein.

[0074] The following detailed description refers to the accompanying drawings, which form part of this specification. In the drawings, unless otherwise indicated in the context, similar symbols generally identify similar components. The exemplary embodiments described in the detailed description, drawings, and claims are not intended to be limiting. Other embodiments may be used and other modifications may be made without departing from the scope of the subject matter presented herein. As generally described herein and illustrated in the figures, aspects of this disclosure can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are expressly intended herein.

[0075] Referring here to Figure 1A, a diagram of an exemplary quantum chip layout is shown, which includes at least one magic state factory surrounded by multiple data qubits and quantum buses. In some cases, the quantum chip may include one or more distillation ports and two or more magic state factory qubits surrounded by two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, and auxiliary qubits, and the layout may further include two or more bus qubits surrounding two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, auxiliary qubits, etc.

[0076] The quantum chip disclosed with respect to Figure 1A may include at least one magic state factory (110, 112, 114, 116) which may contain two or more qubits that enable the implementation of one or more non-Clifford gates using a predefined magic state distillation protocol. The one or more non-Clifford gates may include, for example, a Toffoli gate, a π / 8 Z rotation gate (T gate), and a quantum rotation gate. For example, the magic state factory (110) may implement a 20:4 protocol that takes 20 T-state magic states as input, executes a T gate using multiple qubits including the magic state factory (110), and outputs four T-state magic states in distillation ports (D1, D2, D3, D4). This protocol may be self-contained so as to prevent conflicting use of resources with the compilation of the quantum circuit and so as to allow the distillation protocol and layout to be optimized independently of the implementation of the quantum circuit.

[0077] Continuing to refer to Figure 1A, at least one magic state factory (110, 112, 114, 116) may include magic state factory data qubits (Fq1, Fq2, ..., Fq12), magic state factory auxiliary qubits (Fa1, Fa2, ..., Fa4), magic state factory storage qubits (Fs1, Fs2, ..., Fs4), one or more distillation ports (D1, D2, ..., D16), and an internal quantum bus containing multiple magic state factory bus qubits connecting the internal qubits. For example, magic state factory (114) may include a quantum bus (130) connecting magic state factory data qubits (Fq4, Fq5, Fq6), magic state factory auxiliary qubit (Fa3), magic state factory storage qubit (Fs2), and distillation ports (D9, D10, D11, D12). The distillation ports (D1, D2, ..., D16) of at least one magic state factory (110, 112, 114, 116) are arranged apart from each other in Figure 1A to allow for different access points for the magic states distilled by the factory, thereby, This increases the likelihood of generating auxiliary patches to connect the qubits required by parallel scheduled quantum operations without violating the physical constraints of quantum hardware.

[0078] The quantum chip disclosed in relation to Figure 1A may comprise a plurality of data qubits (q1, q2, ..., q128) and a quantum bus (140) having a plurality of bus qubits. The quantum bus (140) may comprise bus qubits adjacent to and operablely coupled to each of the one or more distillation ports (D1, D2, ..., D16) of at least one magic state factory (110, 112, 114, 116) and each of the multiple data qubits (q1, q2, ..., q128). The quantum bus (140) may be used to connect at least one magic state factory (110, 112, 114, 116) to at least one of the multiple data qubits (q1, q2, ..., q128) using one or more distillation ports (D1, D2, ..., D16). The quantum bus (140) may be non-contractible and / or may include at least one non-contractible subbus. The quantum bus (140) could enable multiple ways of connecting sets of qubits within a quantum chip, increasing the possibility of generating auxiliary patches to connect qubits required by parallel scheduled quantum operations without violating the physical constraints of quantum hardware.

[0079] Continuing to refer to Figure 1A, the quantum chip may include magic state storage qubits (s1, s2, ..., s16). One of the magic state storage qubits (s1, s2, ..., s16) may be connected to one of the distillation ports (D1, D2, ..., D16) after the magic state has been distilled at said distillation ports in order to store the magic state. If the magic state is stored in one of the magic state storage qubits (s1, s2, ..., s16), the magic state storage qubit may be connected to at least one of a plurality of data qubits (q1, q2, ..., q128) using an auxiliary patch to perform quantum operations. The magic state storage qubits (s1, s2, ..., s16) can be coupled to at least one of the distillation ports (D1, D2, ..., D16), thereby enabling the easy transfer of the distilled magic state within the distillation port to the magic state of the storage qubit without generating auxiliary patches that use bus qubits in the quantum bus, and thus avoiding blocking other quantum operations that may be scheduled in parallel.

[0080] Continuing to refer to Figure 1A, the quantum chip may include auxiliary qubits (an1, an2, ..., an16). The auxiliary qubits (an1, an2, ..., an16) may be used to perform additional quantum operations more efficiently or to perform intermediate calculations. For example, a π / 4 rotation on a quantum circuit may require connecting at least one of several data qubits (q1, q2, ..., q128) or one of the magic state storage qubits (s1, s2, ..., s16) to one of the auxiliary qubits (an1, an2, ..., an16). Since auxiliary qubits are typically rotated on a Y basis, the auxiliary qubits (an1, an2, ..., an16) may be represented by two-tile qubits to allow Y basis rotations to be performed in a single time step when using a surface code quantum error correction scheme. At least one data qubit can also be represented by a 2-tile qubit for the same benefit. Alternatively, single-tile qubits can be connected to two or more adjacent bus qubits for the same benefit, such as data qubits (q1, q2, q7). Auxiliary qubits (an1, an2, ..., an16) can be placed far apart from each other to increase the possibility of scheduling quantum operations in parallel. Auxiliary qubits (an1, an2, ..., an16) can also be placed close to the magic state storage qubits (s1, s2, ..., s16) for the same reason, as the magic state storage qubit may frequently require connection to the auxiliary qubits.

[0081] Continuing to refer to Figure 1A, each qubit can be represented by at least one tile within a quantum chip. For example, qubit (q1) is a single-tile qubit, while qubit (an1) may be a two-tile qubit. Straight lines, represented as edges on the boundary of a qubit, can represent X basis connections, which may allow the qubit to rotate in the X basis, while dashed lines, represented as edges on the boundary of a qubit, can represent Z basis connections, which may allow the qubit to rotate in the Z basis. The X, Y, and Z basis can have standard decompositions of a single qubit into orthogonal reference states. Each of these three basis sets is a decomposition into different pairs of states, each basis may be useful for describing rotations in that basis, and the two ground states undergo different phases.

[0082] When using a surface-coded quantum error correction scheme, quantum operations requiring qubit rotations in the Y basis can be performed by generating auxiliary patches that can connect both the X and Z basis of the qubit. Therefore, it may be advantageous to couple at least some qubits to at least two bus qubits so that rotations in all basis can be performed in a single time step. For example, a qubit coupled to two bus qubits, such as (q1) disclosed with respect to Figure 1A, can enable rotations in all basis to be performed in a single time step. On the other hand, a qubit coupled to a single bus qubit, such as (q3) disclosed with respect to Figure 1A, can enable rotations in either the X or Z basis to be performed in a single time step. Since qubit (q3) has only a Z basis connection to the quantum bus in the state of the quantum system disclosed with respect to Figure 1A, the tile representing qubit (q3) can be rotated 90 degrees to change to an X basis connection to the quantum bus.

[0083] Referring now to Figure 1B, a diagram of an exemplary quantum chip layout is shown. The layout may include a first qubit block (i.e., a data block) containing one or more data qubits surrounded by one or more bus qubits; a second block of qubits adjacent to the first block (i.e., a magic state storage block) containing one or more magic state storage qubits and one or more bus qubits; and a third block of qubits adjacent to the second block (i.e., a magic state factory block) containing one or more distillation ports and at least one magic state factory containing a plurality of magic state factory qubits.

[0084] The magic state factory block (30) within the quantum chip disclosed in relation to Figure 1B may include at least one magic state factory, such as (118 and 120), which may include two or more qubits that enable the implementation of one or more non-Clifford gates using a given magic state distillation protocol. The one or more non-Clifford gates may include, for example, Toffoli gates, T gates, quantum rotation gates, etc. For example, the magic state factory (118) may implement a 15:1 protocol that takes 15 T-state magic states as input, and uses multiple qubits, including the magic state factory (118), to execute a T gate and output one T-state magic state to the distillation port (D17). This protocol may be self-contained so as to run in parallel with the actual quantum computation and to prevent resource usage conflicts with the compilation of the quantum circuit, and so as to allow the distillation protocol and layout to be optimized independently of the implementation of the quantum circuit.

[0085] The magic state factory block (30) within the quantum chip disclosed in relation to Figure 1B may include magic state factories arranged at multiple distillation levels, where lower-level magic state factories, such as magic state factory (120), may supply magic states to higher-level magic state factories, such as magic state factory (118). Qubits at different levels in the magic state factories and other blocks may be of different sizes. Operations to resize qubits may be performed in regions such as (190 and 192) to allow qubits to be of the desired size before interacting with qubits in other spaces within the device connected to these resizing spaces. For example, a magic state distilled in magic state factory (120) may be sent to one of the magic state storage qubits (s24, s25, ..., s35) in the resizing space (190). When a magic state storage qubit containing a magic state is resized, the magic state can be used by a higher-level magic state factory, such as the magic state factory (118), to distill a newer magic state. When a newer magic state is distilled at one of the distillation ports (D17, D18, D19, D20), the newer magic state can be sent to the magic state storage qubits (s21, s22, s23) in the resizing region (192) to be resized before being sent to the magic state storage block (20).

[0086] At least one magic state factory, such as the magic state factory (118) in the quantum chip disclosed with respect to Figure 1B, may include magic state factory data qubits such as (Fq13, Fq14, ..., Fq28), magic state factory auxiliary qubits such as (Fa5, Fa6, ..., Fa8), one or more distillation ports such as (D17, D18, D19, D20), and an internal quantum bus (150) which includes a plurality of magic state factory bus qubits connecting the internal qubits. For example, the magic state factory (118) includes a quantum bus (150) which connects the magic state factory data qubits (Fq13, Fq14, Fq15, Fq16), the magic state factory auxiliary qubit (Fa5), the magic state factory storage qubit (Fs5, Fs6), and the distillation port (D17).

[0087] Continuing to refer to Figure 1B, the magic state storage block (20) may include magic state storage qubits (s17, s18, s19, s20) and auxiliary qubits (an19, an20). The magic state storage block (20) may include at least one magic state storage subblock, each containing at least one of the magic state storage qubits. Each magic state storage subblock may contain at least one of the auxiliary qubits. Each subblock may be connected to a data block and a magic state factory block via at least one bus qubit from a quantum bus. Two magic state storage subblocks are disclosed with respect to Figure 1B. For example, the magic state storage subblock (170) may include magic state storage qubits (s17, s18) and auxiliary qubit (an19). The magic state storage subblock (170) may be connected to the data block (10) via bus qubits (180) and to the magic state factory block (30) via rows of bus qubits between them.

[0088] Using a single bus qubit (180) to connect the data block (10) to the magic state storage subblock (170) may allow the auxiliary patch used to connect at least one of the multiple data qubits (q129, q130, ..., q144) to one of the magic state storage qubits (s17, s18) within the magic state storage subblock (170) to be generated in two steps.

[0089] Continuing to refer to Figure 1B, each qubit can be represented by at least one tile within the quantum chip. For example, qubit (q129) is a single-tile qubit, and auxiliary qubit (an17) is a two-tile qubit. Straight lines, represented as edges on the boundary of a qubit, can represent X-basis connections, which may allow the qubit to be rotated in the X-basis, while dashed lines, represented as edges on the boundary of a qubit, can represent Z-basis connections, which may allow the qubit to be rotated in the Z-basis. When using a surface-coded quantum error correction scheme, quantum operations requiring qubit rotation in the Y-basis can be performed by generating auxiliary patches that can connect both the X-basis and Z-basis of the qubit. Thus, it may be advantageous to couple at least some qubits to at least two bus qubits so that rotations in all basis can be performed in a single time step. All data qubits (q129, q130, ..., q144) and auxiliary qubits (an17, an18) within the data block (10) disclosed in relation to Figure 1B can be coupled to two bus qubits, thereby enabling rotations in all basis to be performed in a single time step.

[0090] Referring here to Figure 2, a diagram of an exemplary chip layout disclosed with respect to Figure 1B is shown, having many auxiliary patches that can be used to connect multiple qubits in order to perform quantum operations in parallel. All qubits, blocks, areas, and other elements disclosed with respect to Figure 1B will be understood to be present in Figure 2 and have the same labels elsewhere in this specification. During the compilation of the quantum circuit, the brighter segments of the auxiliary patches (p1, p2, p3, p4) may be determined. However, the darker segments of the auxiliary patches (p3, p4, ..., p11) may be precomputed during compilation time, but the particular patches used may be uncertain due to the unpredictability of which magic state storage qubits will hold the magic state during the quantum computation.

[0091] For example, the auxiliary patch (p3) disclosed with respect to Figure 2 connects a data qubit (q142) to a magic state storage qubit (s18) in a magic state storage subblock (170), and can be divided into two auxiliary patches. The lighter segment within auxiliary patch (p3) can connect the data qubit (q142) to a single bus qubit (180) that can connect the data block (10) to the magic state storage subblock (170). The lighter segment can be determined during the compilation of the quantum circuit. The darker segment within auxiliary patch (p3) can connect a single bus qubit (180) to a magic state storage qubit (s18) located in the magic state storage subblock (170). Due to uncertainty about which of the magic state storage qubits (s17, s18) has the magic state stored during quantum computation, it may not be possible to determine the darker segment during the compilation of the quantum circuit. Using a single bus qubit to connect a magic state storage subblock to a data block allows for the pre-computation of all possible auxiliary patches, enabling the single bus qubit to connect to any of the magic state storage qubits within the subblock, thus allowing for rapid retrieval of necessary auxiliary patches from a classical computer during quantum computation.

[0092] Returning to the magic state storage block (20) disclosed with respect to Figure 1B, the qubits within the magic state storage subblock may be configured to enable parallelization of common quantum operations that require connecting qubits. For example, considering a magic state storage subblock (170), a resized magic state within a magic state storage qubit (s22) may be transmitted to a magic state storage qubit (s17) of the magic state storage subblock (170) using an auxiliary patch (p7) disclosed with respect to Figure 2. In the same time step, an auxiliary patch (p3) disclosed with respect to Figure 2 may be generated to connect a magic state storage qubit (s18) of the magic state storage subblock (170) to a data qubit (q142) without violating the physical constraints of the quantum hardware. A third auxiliary patch (p5) disclosed with respect to Figure 2 may also be generated simultaneously, if necessary, to connect a magic state storage qubit (s18) to an auxiliary qubit (an19) to perform quantum correction, still without violating the physical constraints of the quantum hardware.

[0093] A data block (10) within a quantum chip may contain multiple data qubits (q129, q130, ..., q144). The data qubits may be coupled to at least two bus qubits from a quantum bus (160). This may allow data qubit rotations in all basis planes to be performed in a single time step. For example, as disclosed with respect to Figure 2, an auxiliary patch (p2) may connect a data qubit (q134) to the quantum bus by its X and Z basis connections, meaning that the auxiliary patch (p2) may be used for quantum operations that may require rotating the data qubit q(134) in the Y basis plane. In the quantum chip disclosed with respect to Figure 1B, all data qubits (q129, q130, ..., q144) are configured to have this same advantage.

[0094] Non-Clifford gates can be scheduled in parallel using different magic state storage sub-blocks. For example, referring to Figure 2, auxiliary patches (p3 and p4) can be used to execute two non-Clifford gates in the same time step. Auxiliary patch (p3) can be used to execute a non-Clifford gate that may require rotating a data qubit (q142) in the Z basis. Meanwhile, auxiliary patch (p4) can be used to execute another non-Clifford gate that may require rotating data qubits (q132 and q140) in the X basis.

[0095] Continuing to refer to Figure 1B, the quantum chip includes a quantum bus (160) containing multiple bus qubits. The quantum bus (160) can be arranged adjacent to and operablely coupled to each of the multiple data qubits (q129, q130, ..., q144) and each of the multiple storage qubits (s17, s18, s19, s20). Rows of bus qubits can be placed between the magic state factory block and the resizing space (192) to allow multiple magic states to be transmitted in parallel from the distillation port to the magic state storage subblock. If the resizing space is not required, rows of bus qubits can connect the magic state factory block to the distillation port in the magic state factory. For example, rows of bus qubits can be placed between the magic state factory block (30) and the magic state storage block (20). Referring to Figure 2, an auxiliary patch (p7) may be generated using a row of bus qubits to transmit the magic state in the magic state storage qubit (s22) to the magic storage qubit (s17). In the same time step, auxiliary patches (p8 and p9) may be generated using another row of bus qubits to transmit the magic state in the distillation ports (D18 and D20) to the magic state storage qubits (s21 and s23), respectively. If the magic state factory block (30) has multiple magic state distillation levels, other auxiliary patches such as (p10 and p11) may be generated in parallel to allow the magic state to move between different distillation levels. The quantum bus (160) may include at least one non-collapsed subbus.

[0096] Continuing to refer to Figure 1B, the quantum chip includes auxiliary qubits (an17, an18, an19, an20). Auxiliary qubits such as (an17, an18) may be placed in data blocks to be connected to data qubits when performing π / 4 rotations. For example, as disclosed with respect to Figure 2, an auxiliary patch (p1) may connect the auxiliary qubit (an17) to data qubits (q131, q133, and q137) to enable performing π / 4 rotations on the data qubits (q131, q133, and q137) in the X basis.

[0097] The qubit types could include, for example, bus qubits, data qubits, magic state storage qubits, auxiliary qubits, distillation ports, magic state factory qubits, magic state factory bus qubits, magic state factory data qubits, magic state factory storage qubits, and magic state factory auxiliary qubits.

[0098] A quantum chip may have a layout that represents the type of qubit and its arrangement on the quantum chip. The layout may include, for example, tiles, triangles, hexagons, rectangles, etc. Different tile shapes arise from different underlying topology codes, as the connections inherent in these codes create different tileable structures (for example, surface codes have square tiling, while triangular color codes have triangular tiling).

[0099] Referring here to Figure 1C, an exemplary quantum chip layout is shown. The quantum chip layout may include a triangular color code and therefore may have a triangular tiling. The quantum chip may comprise at least one magic state factory (220), a plurality of data qubits including data qubits (230), and a quantum bus (200).

[0100] The layout of a quantum chip may include building blocks of tileable subsystems, meaning that multiple modular layouts can be tiled together to create a larger quantum chip while all qubits on the modular layout remain accessible. For example, Figure 1A reveals four equal modules, each containing one of several magic state factories (110, 112, 114, 116) surrounded by multiple data qubits and quantum buses, which can be tiled together to form a larger quantum chip while all qubits remain accessible.

[0101] In some cases, the layout of a quantum chip may comprise two or more magic state factory qubits, one or more distillation ports, which together form a magic state factory surrounded by two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, and auxiliary qubits. The layout may further comprise two or more bus qubits surrounding two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, and auxiliary qubits. In some cases, the layout of a quantum chip may comprise a first block of qubits comprising one or more data qubits surrounded by one or more bus qubits, and one or more auxiliary qubits, a second block of qubits adjacent to the first block, and a third block adjacent to the second block. The second block may comprise one or more magic state storage qubits, one or more bus qubits, and one or more auxiliary qubits. The third block may comprise one or more distillation ports and at least one magic state factory comprising multiple magic state factory qubits.

[0102] The layout of a quantum chip may include a qubit lattice corresponding to a topological quantum code. In some cases, the topological quantum code may be a surface code, a revolving surface code, or a color code. (Fowler et al., “Surface codes: Towards practical large-scale quantum computing,” Physical Review A 86, 032324, 2012; and Bombin, “Topological codes,” in Lidar and Brun (Eds.), Quantum Error Correction, pp. 455-481, Cambridge University Press, 2013; these publications are incorporated herein by reference in their entirety). Thus, each logical qubit in the chip layout can correspond to multiple physical qubits on the underlying physical system, and the logical qubits are coded within a topological quantum code. Furthermore, only some qubit operations may be available to the compiler, and their implementation by lattice surgery may depend on the coding.

[0103] Referring now to Figure 3, a schematic diagram of an exemplary system for optimizing the scheduling of operations in a quantum circuit on a quantum chip, comprising at least one magic state factory, multiple data qubits, and a quantum bus.

[0104] The system may include a digital computer (300) and a quantum computer (304). The digital computer (300) may include at least one processing device (306), a display device (308), an input device (310), a communication port (314), and a memory (312) containing a computer program executable by the processing device (306). The digital computer (300) may be of various types, including any digital computer disclosed elsewhere in this specification.

[0105] Refer to Figure 3, the quantum computer (304) comprises a quantum chip (320) having at least one magic state factory, a plurality of data qubits, and a quantum bus. The quantum chip (320) can be of various types, such as the quantum chip disclosed herein with respect to Figure 1A, Figure 1B, or Figure 1C. The at least one magic state factory can be of various types, such as the magic state factory described herein with respect to Figure 1A, Figure 1B, or Figure 1C. The data qubits can be of various types, such as the data qubits described herein with respect to Figure 1A, Figure 1B, or Figure 1C. The quantum bus can be of various types, such as the quantum bus described herein with respect to Figure 1A, Figure 1B, or Figure 1C.

[0106] In some cases, the quantum computer (304) may include a readout control system (322) for quantum measurement readouts. The quantum computer (304) may be operably connected to a digital computer (300) by a connection between the readout control system (322) and a communication port (314). The quantum computer (304) may include any quantum computer, such as any quantum device disclosed elsewhere in this specification.

[0107] In some cases, a digital computer (300) may be used to provide instructions to a quantum computer (304) using a communication port (314) and a read control system (322).

[0108] Continuing to refer to Figure 3, the system may include a dedicated computing platform (not shown in Figure 3) for receiving and executing instructions that use optimization procedures to solve optimization problems for optimizing the scheduling of operations in quantum circuits. The dedicated computing platform may include HPC hardware. The dedicated computing platform may be operably coupled to a digital computer (300), a quantum computer (304), or both. The dedicated computing platform may include, for example, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a tensor processing unit (TPU), a tensor streaming processor (TSP), and so on.

[0109] Referring now to Figure 4, a flowchart is shown illustrating an exemplary method for optimizing the scheduling of operations in a quantum circuit on a quantum chip comprising at least one magic state factory, multiple data qubits, and a quantum bus.

[0110] A processing operation (402) is performed to obtain a quantum circuit and a layout representing the type and arrangement of qubits on a quantum chip. The quantum chip may comprise at least one magic state factory, a plurality of data qubits, and a quantum bus. The quantum chip can be of various types, such as the quantum chip disclosed herein with respect to Figure 1A, Figure 1B, or Figure 1C.

[0111] A quantum circuit may include one or more quantum operations. One or more quantum operations may comprise one or more quantum gates. In some cases, a quantum gate may include one or more non-Clifford gates. Non-Clifford gates may include, for example, Toffoli gates, π / 8 Z rotation gates (T gates), or quantum rotation gates. Each gate may be implemented by one or more quantum operations.

[0112] In some cases, the qubit type may include, for example, bus qubits, data qubits, magic state storage qubits, auxiliary qubits, distillation ports, magic state factory qubits, magic state factory bus qubits, magic state factory data qubits, magic state factory storage qubits, magic state factory auxiliary qubits, and so on.

[0113] In some cases, the layout representing the qubit types and their arrangement on a quantum chip may include a qubit lattice corresponding to a topological quantum code. In some cases, the topological quantum code may be a surface code, a revolving surface code, or a color code. (Fowler et al., “Surface codes: Towards practical large-scale quantum computing,” Physical Review A 86, 032324, 2012; and Bombin, “Topological codes,” in Lidar and Brun (Eds.), Quantum Error Correction, pp. 455-481, Cambridge University Press, 2013; each of these references is incorporated herein by reference in its entirety.) Thus, each logical qubit in the chip layout may correspond to multiple physical qubits on the underlying physical system, and the logical qubits are coded within the topological quantum code. Furthermore, only some qubit operations may be available to the compiler, and their implementation by lattice surgery may depend on the coding.

[0114] In some cases, the layout of a quantum chip may comprise two or more magic state factory qubits and one or more distillation ports, together forming a magic state factory surrounded by two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, and auxiliary qubits. The layout may further comprise two or more bus qubits surrounding two or more qubits of any qubit type, e.g., bus qubits, data qubits, magic state storage qubits, and auxiliary qubits. In some cases, the layout of a quantum chip may comprise a first block of qubits comprising one or more data qubits surrounded by one or more bus qubits and one or more auxiliary qubits, a second block of qubits adjacent to the first block, and a third block adjacent to the second block. The second block may comprise one or more magic state storage qubits, one or more bus qubits, and one or more auxiliary qubits. The third block may comprise one or more distillation ports and at least one magic state factory comprising multiple magic state factory qubits.

[0115] In some cases, the layout of a quantum chip may include building blocks of tileable subsystems. Layouts representing the types of qubits and their arrangement on a quantum chip may include, for example, tiles, triangles, hexagons, rectangles, etc. The tileable subsystems may be determined by the underlying topology code used, since the code can determine the connections on which the tiles form. For example, a surface code might utilize a square lattice, and a triangular color code might utilize a triangular lattice.

[0116] In some cases, a quantum circuit can be optimized by removing a quantum operation, including a Clifford gate, from the quantum circuit. Quantum circuits can be optimized in various ways. In some cases, a tableau representation of the Clifford operation can be implemented. Optimization of a quantum circuit may further involve iterating over the operation of the resulting quantum circuit while maintaining the tableau representation of the Clifford operation, and updating a given operation via a conjugate with the retained Clifford operation, or updating the retained Clifford operation and removing the given operation from the quantum circuit.

[0117] Continuing to refer to Figure 4, according to processing operation (404), the scheduling of one or more quantum operations is optimized so that the scheduling satisfies the logical constraints of the quantum circuit and the physical constraints of the quantum hardware, including layout constraints. Optimizing the scheduling of one or more quantum operations may be done to minimize quantum computation time. In some cases, quantum computation time can be reduced by executing quantum operations in parallel in the quantum circuit while adhering to the logical constraints of the quantum circuit and the physical constraints of the quantum hardware. Optimizing the scheduling of one or more quantum operations may involve solving a tactile tree packing problem (also called a "forest packing problem"). In some cases, a tactile tree packing problem may be solved to find a set of quantum operations that can be executed in parallel at time steps that satisfy the logical constraints of the quantum circuit and the physical constraints of the quantum hardware. In the tactile tree packing problem to be solved, the adjacency graph representing the arrangement of qubits in the quantum chip for a given time step may be given along with several distinct subsets of its vertices called terminals. Each set of endpoints can represent qubits that need to be connected by quantum operations that may be candidates to be scheduled in parallel at a time step, taken from a dependency graph that may represent the precedence constraints of the scheduled quantum operations. If a quantum operation requires connecting more than one qubit, it may be necessary to find a tree that connects the endpoints of the quantum operation. This tree can represent auxiliary patches and can be a subgraph of the adjacency graph. Physical constraints of the quantum hardware may impose that all endpoints are leaves in their trees. In addition, the trees must be point-meme, meaning they do not share vertices corresponding to bus qubits in the adjacency graph used to generate them. The goal of this optimization problem is to maximize the number of quantum operations that can be scheduled at a time step, and each quantum operation may require point-meme trees to be packed into the adjacency graph.

[0118] Continuing to refer to Figure 4, an optimized quantum circuit is reported, including an optimized scheduling of one or more quantum operations, according to processing operation (406). The optimized quantum circuit can be reported in various ways. In some cases, the optimized quantum circuit, which may include the order in which each parallelizable quantum operation is scheduled, and the auxiliary patches required to perform each quantum operation, can be reported to a classical device such as a digital computer (300) disclosed with respect to Figure 3. This optimized schedule can then be combined with the quantum error correction schedule of the underlying hardware and translated into a sequence of operations (in parallel) on physical hardware. This combined sequence can then be sent to a control electronic device for a quantum computer, such as a quantum computer (304) disclosed with respect to Figure 3, which can implement the translated set of operations on a quantum device.

[0119] In some cases, optimized quantum circuits can be implemented and executed. In some cases, optimized quantum circuits can be implemented and executed on a system comprising a quantum computer, such as the system disclosed herein with respect to Figure 3. The quantum computer can be of various types, such as any quantum computer disclosed elsewhere herein.

[0120] Referring now to Figure 5, a flowchart of an exemplary procedure for optimizing the scheduling of operations in a quantum circuit on a quantum chip is shown. This procedure may be used by the method disclosed herein with respect to Figure 4.

[0121] According to processing operation (502), a quantum circuit having one or more quantum operations is transformed into a dependency graph. The dependency graph may include priority constraints of the scheduled quantum operations. The dependency graph may be represented by a directed acyclic graph, where the vertices represent the quantum operations to be scheduled and the directed arcs represent the dependency constraints (i.e., directed arcs connect quantum operations that need to be executed earlier to quantum operations that need to be executed later in the quantum circuit). If one of the quantum operations must precede another, a dependency constraint may exist between the two quantum operations, and therefore the former must be executed in an earlier time step than the latter. For example, a dependency constraint may exist if the operations do not commit. Operations commit when they can be applied in any order without affecting the final quantum state. For example, a commitation check may involve checking whether operations that need to be executed with the same qubits required by different operations are compatible in that they can be executed in the same time step. Dependency constraints can be imposed even when operations are swapped to generate dependency graphs computationally faster, for example, by requiring that the same qubit cannot be connected by multiple quantum operations at the same time step. When dependency constraints are considered by either non-commutation or imposition, the dependency graph includes a directed arc that connects vertices representing two quantum operations directly or indirectly through other vertices. If no dependency constraints exist directly or indirectly between quantum operations, they may be parallelizable. Whether any set of quantum operations can actually be executed in parallel may depend not only on the logical constraints of the quantum circuits represented in the dependency graph, but also on the physical constraints of the quantum hardware.

[0122] Continuing to refer to Figure 5, according to processing operation (504), a dependency graph, as well as a layout representing the qubit types and their arrangement on the quantum chip, are used to define the optimization problem. In some cases, this layout representing the qubit types and their arrangement on the quantum chip may be represented by an adjacency graph. In some cases, the adjacency graph may be used to verify the physical constraints of the quantum hardware in an encoded quantum error correction scheme, such as a surface code, a rotating surface code, or a triangular color code used within the quantum chip. The vertices of this adjacency graph may represent qubits, and the qubits are associated with their respective qubit types. The edges of this adjacency graph may represent connections between coupled qubits. A vertex or edge may be associated with an X basis, a Y basis, or a Z basis, indicating that connections between X basis, Y basis, or Z basis exist between adjacent qubits, respectively. For example, as disclosed with respect to Figure 1B, a qubit (q129) is connected to two bus qubits. The qubit (q129) is coupled to a bus qubit on its left, with an X basis connection between them, which is coupled to a bus qubit above it, and a Z basis connection between them. Therefore, the adjacency graph representing the qubit types and their arrangement on the quantum chip layout shown in Figure 1B includes vertices representing the qubit (q129) and the bus qubit coupled to it. The adjacency graph includes an edge related to the X basis connecting the vertex representing the qubit (q129) to the bus qubit to its left, and the adjacency graph may include another edge related to the Z basis connecting the vertex representing the qubit (q129) to the bus qubit above it. Qubits may only be directly coupled to adjacent qubits. If qubits are not adjacent, they may require auxiliary patches to interact.

[0123] In some cases, the optimization problem may involve scheduling problems in which quantum operations within a quantum circuit (generally called "jobs") are scheduled to minimize the quantum computation time, which can be measured by the total number of time steps required to perform the quantum operations (called "makespan"). As defined elsewhere in this specification, if a job requires connecting more than one endpoint, a tree representing auxiliary patches may be generated in the adjacency graph to connect its endpoints in order to schedule the job. For example, as disclosed with respect to the adjacency graph representing the quantum chip layout shown in Figure 2, seven jobs are scheduled in parallel, and each job is represented by a tree in the figure. A tree connecting only two endpoints may be called a path. If a job requires only a single endpoint, a tree does not need to be generated, but the job can still be scheduled if all constraints are met. Terminals representing data qubits may be predefined, while endpoints representing auxiliary qubits, magic state storage qubits, and distillation ports may be selected from vertices representing these qubit types if those types of qubits are required by the job. The tree connecting endpoints may include intermediate vertices of type "bus qubit". Endpoints are required to be leaves in the generated tree. Referring to the previous example disclosed in Figure 2, the tree (p1) (auxiliary patch (p1)) connects four endpoints, three of which are data qubits and one is an auxiliary qubit, and all endpoints are leaves of the tree. Different auxiliary qubits may be selected to connect to data qubits in order to schedule this quantum operation using different trees. The tree consists of vertices that are not used to execute another job scheduled in either the current time step or the previous time step in the time step in which the current job is scheduled.

[0124] The jobs that can be scheduled at a given time step are the roots of the dependency graph at that time step. The roots of the dependency graph represent jobs that have not yet been scheduled and have no other scheduled jobs that need to precede them. These jobs can be candidates for scheduling in parallel. A set of jobs can, in fact, be scheduled to run in parallel if the tree generated to connect the endpoints of each job in the set is a ptisme tree, meaning they do not share vertices corresponding to bus qubits in adjacent graphs used to generate them. For example, the tree disclosed with respect to Figure 2 is a ptisme tree. Generating a tree of candidate jobs that can be scheduled in parallel is an optimization problem called the ptisme tree packing problem, which is part of the scheduling problem. The scheduling problem is thought to be solved when all jobs, including quantum operations in quantum circuits, are scheduled.

[0125] Optimization problems can involve various types of jobs: qubit measurement, π / 2 turn, π / 4 turn, π / 8 turn, magic state store, magic state storage replenishment, qubit tile turn, and magic state factory replenishment. The qubit measurement, π / 2 turn, π / 4 turn, and π / 8 turn jobs involve quantum operations in quantum circuits. The qubit measurement, π / 2 turn, and π / 4 turn jobs involve Clifford gates, while the π / 8 turn job involves non-Clifford gates. The magic state store job involves the process of storing distilled magic states from a distillation port into magic state storage qubits. The magic state storage replenishment job involves the process of replenishing magic state storage qubits after magic states stored in them have been used by non-Clifford gates. A type qubit tile turn job involves turning a qubit tile so that it has different edges accessed only by a quantum bus, via one of the edges of the qubit tile, and as a result, operations on different bases (X, Y, or Z) may be performed. A type magic state factory replenishment job involves a magic state distillation process performed in a magic state factory to distill new magic states in the distillation port. Other operations that may not involve auxiliary patch generation may be considered, such as qubit expansion, qubit contraction, and edges rebasing.

[0126] A scheduled job may require the generation of auxiliary patches that connect its endpoints using a quantum bus, making the qubits represented by these endpoints unavailable for scheduling new quantum operations over several time steps. A type qubit measurement and π / 2 rotation job requires connecting a defined set of data qubits, which makes all connected qubits unavailable for one time step. The tree (p2) (auxiliary patch (p2)) disclosed with respect to Figure 2 represents the connections made in a type qubit measurement and π / 2 rotation job. A type π / 4 rotation job requires connecting a defined set of data qubits to arbitrary auxiliary qubits, making all connected qubits unavailable for one time step. The tree (p1) (auxiliary patch (p1)) disclosed with respect to Figure 2 represents the connections made in a type π / 4 rotation job. A type π / 8 rotation job may require up to three scheduled steps. The first step is to connect a defined set of data qubits to an arbitrary distillation port or magic state storage qubit containing a magic state, which makes all connected qubits unavailable for one time step (i.e., they are unavailable only during the scheduled time step). The trees (p3 and p4) (auxiliary patches (p3 and p4)) disclosed with respect to Figure 2 represent the connections made in the first step, which are described for a job of type π / 8 rotation. The second step is a quantum correction that may be required after the first step, which requires the execution of a job of type π / 4 rotation, which is described elsewhere in this specification. The third step is another quantum correction that may be required after the second step, which requires the execution of a job of type π / 2 rotation, which is described elsewhere in this specification.The job of type magic state storage requires connecting a distillation port to a magic state storage qubit, which makes the distillation port unavailable for one time step and the magic state storage qubit unavailable for two time steps (i.e., one time step to receive the magic state and another time step to prepare the base of its edge). The trees (p5 and p7) disclosed with respect to Figure 2 represent the connections made in the job of type magic state storage. The job of type magic state storage replenishment requires connecting a magic state storage qubit to an auxiliary qubit, which makes both unavailable for one time step. The tree (p6) (auxiliary patch (p6)) disclosed with respect to Figure 2 represents the connections made in the job of type magic state storage replenishment. The job of type qubit tile turn does not require an auxiliary patch, but instead requires using a bus qubit adjacent to the qubit being turned, which makes both the qubit being turned and the bus qubit used unavailable for three time steps. The qubit tile turn type job is not shown in Figure 2 because it does not require qubits to turn when using the layout disclosed with respect to Figures 1B and 2. The type magic state factory replenishment job makes all distillation ports connected to the magic state factory on which the magic state distillation protocol is performed unavailable for a number of time steps corresponding to the magic state distillation protocol performed in the magic state factory. The type magic state storage replenishment job is also not shown in Figure 2 because it does not require tree generation. Quantum error correction can be performed within the magic state factory when distilling a new magic state, so the exact number of time steps required to distill a new magic state can be probabilistic. Replenishing magic states in the factory may fail to distill a new magic state.

[0127] In some cases, the procedure for generating auxiliary patches to connect endpoints for a job may be carried out in multiple steps. In each step, a segment of the auxiliary patch may be generated. Each segment may connect some endpoints to intermediate bus qubits, or intermediate bus qubits to other intermediate bus qubits. The connections of the segments may form a valid auxiliary patch that connects all the endpoints required for the job. Some of these segments may be determined during compilation time. Some of these segments may not be determined during compilation time due to uncertainty about which endpoints are available for selection during quantum computation time. In this case, a given segment may be generated during compilation time, and these segments may be quickly retrieved by the quantum computer during quantum computation time to execute the job. The brighter segments of the tree disclosed with respect to Figure 2 may be determined during compilation time, while the darker segments of the tree in the figure may be generated during compilation time but require to be retrieved by the quantum computer during quantum computation time, following information revealed about the distillation process during quantum computation.

[0128] Continuing to refer to Figure 5, according to processing operation (506), an optimization procedure is used to solve the optimization problem and optimize the scheduling of one or more quantum operations of a quantum circuit. The optimization procedure can be of various types. In some cases, the optimization procedure may include a routine for solving the scheduling problem and / or a subroutine tree packing problem arising from the quantum operations that are candidates to be scheduled in parallel at different time steps. In some cases, the routine used as the optimization procedure may include solving problems involving integer programming, maximum independent sets, Steiner trees, and topology sorts, among other possible procedures. The optimization procedure can be considered an integer programming problem-solving procedure if it may include the use of mathematical programming to model the scheduling problem and / or the ptismine tree packing problem, which are solved by any general procedure used to search for an optimal solution, such as the branch-and-bound method, the branch-cut method, and the interior-point method. An optimization procedure can be considered a Steiner tree problem-solving procedure if it involves generating a Steiner tree for a packing problem using procedures other than mathematical programming, such as heuristic algorithms. An optimization procedure can be considered a maximum independent set problem-solving procedure if it involves using an adjacent graph to generate separate trees to schedule a set of parallelizable quantum operations, and then finding the set of pointmee trees with the highest cardinality from the graph constructed from all the trees to solve the packing problem. An optimization procedure can be considered a topology sort problem-solving procedure if it involves using an arbitrary procedure to sort quantum operations in a dependency graph either deterministically or stochastically, and then scheduling the quantum operations in the sorted order, using the concept of queuing systems or simulations, without directly generating trees that connect qubits.

[0129] In some cases, the optimization problem may involve an objective function that minimizes the makepan over quantum computation time, which is affected by the logical constraints of the quantum circuit and the physical constraints of the quantum hardware.

[0130] In some cases, the allocation problem for determining which data qubits to use can be solved. The optimization problem may first involve allocating the most requested data qubits to the most desirable tiles within the quantum chip. Tiles may be considered more desirable if they provide multiple avenues for accessing the quantum bus, thereby allowing quantum operations on any basis (X, Y, or Z) to be performed in a single time step. In some cases, the allocation of qubits to tiles of similar desirability may be determined using procedures that may include, for example, random assignment or cluster assignment. A random assignment procedure may involve randomly sorting the tiles for allocation to data qubits. A cluster assignment procedure may involve sorting topological regions of the quantum chip layout, which can be used to form clusters of qubits based on request-based metrics, and then allocating the formed clusters of qubits to separate topological regions of the quantum chip layout.

[0131] While preferred embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided only as examples. The present invention is not intended to be limited by any specific examples provided herein. While the description and illustration of embodiments herein have been made with reference to the preceding specification, they are not intended to be constrained. Numerous variations, alterations, and substitutions will be conceivable to those skilled in the art without departing from the present invention. Furthermore, it should be understood that all aspects of the present invention are not limited to any specific depictions, configurations, or relative proportions described herein, which will vary depending on various conditions and variables. It should be understood that various alternative forms of the embodiments of the present invention described herein may be employed when carrying out the present invention. Thus, it is intended that the present invention will further encompass any such alternatives, modifications, alterations, or equivalents. The following claims define the scope of the present invention, and the methods and structures within these claims, as well as their equivalents, are intended to be encompassed thereby.

Claims

1. It is a quantum chip, (a) at least one magic state factory comprising multiple qubits configured to implement one or more non-Clifford and one or more distillation ports, (b) Multiple data qubits, (c) A quantum bus comprising bus qubits adjacent to and operably coupled to each of the one or more distillation ports of the at least one magic state factory and to one or more qubits of the plurality of data qubits, wherein the quantum bus is configured to connect the at least one magic state factory to at least one of the plurality of data qubits using the one or more distillation ports A quantum chip, including...

2. The quantum chip according to claim 1, wherein the quantum bus includes at least one non-contracting subbus.

3. The quantum chip according to claim 1, wherein the at least one magic state factory comprises two or more magic state factories arranged at multiple distillation levels.

4. The quantum chip according to claim 1, further comprising one or more magic state storage qubits.

5. The quantum chip according to claim 4, wherein the quantum bus is configured to connect the at least one magic state factory to at least one of the plurality of data qubits using one or more distillation ports mediated via the magic state storage qubit.

6. The quantum chip according to claim 1, wherein the quantum chip further includes a resizing space for one or more qubits, and the resizing space for one or more qubits is configured to perform a resizing quantum operation for one or more qubits.

7. The quantum chip according to claim 1, wherein the one or more non-Clifford gates include at least one member selected from the group consisting of Toffoli gates, π / 8 Z rotation gates (T gates), and quantum rotation gates.

8. The quantum chip according to claim 1, wherein the quantum chip has a layout representing a qubit type and its arrangement on the quantum chip, and the layout includes at least one member selected from the group consisting of tiles, triangles, hexagons, and rectangles.

9. The quantum chip according to claim 1, wherein the quantum chip has a qubit type comprising at least one member selected from the group consisting of a bus qubit, a data qubit, a magic state storage qubit, an auxiliary qubit, a distillation port, a magic state factory qubit, a magic state factory bus qubit, a magic state factory data qubit, a magic state factory storage qubit, and a magic state factory auxiliary qubit.

10. The quantum chip according to claim 1, wherein the quantum chip has a layout comprising two or more magic state factory qubits surrounded by one or more distillation ports, and two or more qubits of any qubit type selected from the group consisting of bus qubits, data qubits, magic state storage qubits, and auxiliary qubits, and the layout further comprises two or more bus qubits surrounding the two or more qubits.

11. The quantum chip according to claim 1, wherein the quantum chip has a layout comprising: a first block of qubits including one or more data qubits surrounded by one or more bus qubits; a second block of qubits adjacent to the first block, the second block including one or more magic state storage qubits and one or more bus qubits; and a third block of qubits adjacent to the second block, the third block including at least one magic state factory including one or more distillation ports and a plurality of magic state factory qubits.

12. The quantum chip according to claim 1, wherein the quantum chip has a layout including building blocks of tileable subsystems.

13. The quantum chip according to claim 1, wherein the quantum chip has a layout that includes one or more blocks of four data qubits arranged adjacent to each other in a 2x2 table and surrounded by twelve bus qubits.

14. The quantum chip according to claim 1, wherein the quantum chip has a layout including a qubit lattice corresponding to a topological quantum code.

15. The quantum chip according to claim 14, wherein the topology quantum code is a surface code, a rotating surface code, or a color code.

16. A method for scheduling quantum circuit operations on a quantum chip comprising at least one magic state factory, a plurality of data qubits, and a quantum bus, wherein the method is (a) A step of obtaining a quantum circuit and layout, wherein the layout represents one or more qubit types and arrangements of qubits on the quantum chip, and the quantum circuit includes one or more quantum operations, (b) A step of optimizing the scheduling of one or more quantum operations, wherein the scheduling is subject to one or more constraints, the one or more constraints are based at least in part on the layout and on the quantum circuit, and the optimization step includes solving at least a vertex-disjoint tree packing problem. (c) A step of reporting an optimized quantum circuit, which includes the optimized scheduling of one or more quantum operations. Includes.

17. The method according to claim 16, wherein (b) optimizes the quantum circuit by removing at least one of the one or more quantum operations, the at least one of the one or more quantum operations includes a Clifford gate.

18. The method according to claim 16, wherein (b) minimizes the computation time of one or more quantum operations.

19. The method according to claim 16, wherein the layout includes a qubit lattice corresponding to a topological quantum code.

20. The method according to claim 19, wherein the topology quantum code is a surface code, a surface of rotation code, or a color code.

21. The method according to claim 16, wherein the layout includes at least one member selected from the group consisting of tiles, triangles, hexagons, and rectangles.

22. The method according to claim 16, wherein the one or more qubit types include at least one member of the group consisting of bus qubits, data qubits, magic state storage qubits, auxiliary qubits, distillation ports, magic state factory qubits, magic state factory bus qubits, magic state factory data qubits, magic state factory storage qubits, and magic state factory auxiliary qubits.

23. The method according to claim 16, wherein the layout comprises two or more magic state factory qubits surrounded by one or more distillation ports, and two or more qubits of any qubit type selected from the group consisting of bus qubits, data qubits, magic state storage qubits, and auxiliary qubits, and the layout further comprises two or more bus qubits surrounding the two or more qubits.

24. The method according to claim 16, wherein the layout comprises a first block of qubits including one or more data qubits surrounded by one or more bus qubits; a second block of qubits adjacent to the first block, the second block including one or more magic state storage qubits and one or more bus qubits; and a third block of qubits adjacent to the second block, the third block including one or more distillation ports and at least one magic state factory including a plurality of magic state factory qubits.

25. The method according to claim 16, wherein the arrangement of the qubits includes building blocks of a tileable subsystem.

26. The method according to claim 16, wherein the quantum circuit includes a sequence of quantum operations comprising at least one member selected from the group consisting of Toffoli gates, π / 8 Z rotation gates, and quantum rotation gates.

27. The method according to claim 16, further comprising the step of implementing and executing the optimized quantum circuit.

28. (b) is, (b1) Converting the quantum circuit, which includes one or more quantum operations, into a dependency graph, (b2) Defining an optimization problem using the dependency graph and the layout, (b3) Using an optimization procedure to solve the optimization problem and schedule one or more quantum operations of the quantum circuit. The method according to claim 16, including the method described in claim 16.

29. The method according to claim 28, wherein the optimization procedure includes at least one member of the group consisting of maximum independent sets, Steiner trees, topology sorting, integer programming, branch-and-bound, branch-and-cut, and interior-point.

30. The method according to claim 28, wherein the optimization problem includes an objective function that minimizes the quantum computation time, the logical constraints of the quantum circuit, and the physical constraints of the quantum hardware.

31. The method of claim 28, wherein (b3) comprises solving an allocation problem to determine a plurality of available data qubits to be used.

32. A system for optimizing the scheduling of quantum circuit operations on a quantum chip, comprising at least one magic state factory, a plurality of data qubits, and a quantum bus, wherein the system is A digital computer, which at runtime, (i) Obtaining a quantum circuit and layout, wherein the layout represents one or more qubit types and arrangements of qubits on the quantum chip, and the quantum circuit includes one or more quantum operations. (ii) Optimizing the scheduling of one or more quantum operations, wherein the scheduling is subject to one or more constraints, the one or more constraints are at least partially based on the layout and the quantum circuit, and the optimization includes solving at least a point-element tree packing problem. (iii) To report an optimized quantum circuit including the optimized scheduling of one or more quantum operations. A memory having instructions configured to perform the following actions: The digital computer is communicatively coupled to a quantum computer, and the quantum computer is configured to implement the scheduled quantum circuit. A system that includes these features.

33. The system according to claim 32, further comprising the aforementioned quantum computer.

34. The system according to claim 33, wherein the quantum computer comprises a quantum chip according to any one of claims 1 to 15.

35. A system for scheduling quantum circuit operations on a quantum chip, comprising at least one magic state factory, a plurality of data qubits, and a quantum bus, wherein the system is A quantum computer equipped with a quantum chip, (i) at least one magic state factory including multiple qubits configured to implement one or more non-Clifford and one or more distillation ports, (ii) Multiple data qubits, (iii) A quantum bus comprising bus qubits adjacent to and operably coupled to one or more qubits of the plurality of data qubits, to each of the one or more distillation ports of the at least one magic state factory Includes, The quantum computer is configured to perform the quantum circuit operations, The quantum computer is communicatively coupled to a digital computer, and the digital computer is configured to optimize the scheduling of the quantum circuit operations on the quantum chip. A system that includes these features.

36. The system according to claim 35, further comprising the aforementioned digital computer.

37. The system according to claim 36, wherein the digital computer is configured to carry out the method described in any one of claims 16 to 31.

38. The system according to any one of claims 32 to 37, further comprising a dedicated computing platform, wherein the dedicated computing platform is configured to receive and execute instructions for implementing at least an optimization procedure for solving an optimization problem for optimizing the quantum circuit operation, and the dedicated computing platform is communicably coupled to the digital computer, the quantum computer, or both.

39. The system according to claim 38, wherein the dedicated computing platform includes at least one member of the group consisting of a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a tensor processing unit (TPU), and a tensor streaming processor (TSP).

Images