A synchronization method and system that enables coherent synthesis of physically distributed assemblies.

Abstract

The synchronization method involves the operation of a timing source and remote timing circuits, each communicatively coupled to the timing source. In the timing source, a reference signal having a reference frequency is generated, a multitone waveform is generated, and the reference signal and the waveform are combined to generate a synchronization signal in which a second time portion containing the waveform is interspersed with a first time portion containing the reference signal but not the waveform. The synchronization signal is transmitted to the timing circuits via each of a plurality of signal paths, each having a different propagation delay. Each timing circuit determines the phase difference between the received tones to determine the propagation delay of the connected signal path. Each reference signal is individually delayed in the timing circuits, at least based on the propagation delay, and the timing circuits provide phase-aligned output reference signals.

Description

Technical Field

[0001] The present disclosure generally relates to synchronization methods, and more particularly to synchronization methods for electronically operable antenna array systems having physically distributed antenna assemblies.

Background Art

[0002] The problem of providing reference signals synchronized at different physical locations can occur in various communication systems. One example occurs in electronically operable antenna arrays (e.g., phased arrays). In this array, digital beamforming is utilized to form transmit and / or receive beams.

[0003] A conventional (purely analog configuration) antenna array with N antenna elements forms a transmit beam by routing an input RF transmit signal through a combiner / splitter network (“distribution network”) and splitting the transmit signal into N “element signals”. In an array with distributed transceivers, the N element signals are typically amplified and / or phase-shifted in the RF front-end between the antenna elements and the distribution network. In the receive path, a composite receive signal is obtained by combining the N element signals received by the N antenna elements using the same or different combiner / splitter networks in the reverse process. In the distribution network, in many cases, accurate calibration is required such that all N propagation paths from the RF input port to the N antenna elements during transmission and between the N antenna elements and the RF output port during reception have calibrated insertion phases (typically the same insertion phase). However, at microwave and millimeter-wave frequencies, such calibration is costly and complex due to the small wavelengths involved.

[0004] Therefore, in recent years, attempts have been made to provide an antenna array consisting of antenna element assemblies or antenna sub-array assemblies that are not RF-coupled to each other by a distributed network. Each assembly may implement digital beamforming and have its own oscillator for generating individual transmission signals and / or individual reception signals. During transmission, it is necessary to synchronize the individual transmission signals in terms of time and frequency in order to collectively generate a coherent beam from the assemblies. In the reception path, it is necessary to sample the received signals within each of the assemblies to generate a digital output stream. The sampling needs to be synchronized between the assemblies so that the processor can combine the sampled outputs to obtain a composite reception signal. However, synthesizing the received signals from physically separated receivers (similarly, synthesizing the transmission signals from physically separated transmitters in the far-field) requires frequency / phase coherence and time alignment of the physically separated units, which is difficult to achieve. Summary of the Invention

[0005] In one aspect of the present disclosure, the synchronization method includes operations in a timing source and remote timing circuits each communicatively coupled to the timing source. In the timing source, a reference signal having a reference frequency is generated, a waveform having a plurality of tones is generated, the reference signal and the waveform are combined, and a synchronization signal is generated in which time portions including the waveform are interspersed in a first time portion including the reference signal and not including the waveform. The synchronization signal is transmitted to each of the plurality of timing circuits via a plurality of signal paths having different propagation delays. The first timing circuit determines a phase difference between at least two of the received tones, delays the reference signal by a delay based at least in part on the phase difference, and provides a first output reference signal having the same phase as a second output reference signal provided by the second timing circuit.

[0006] Multiple tones in a waveform can be subcarriers of an orthogonal frequency-division multiplexing (OFDM) signal modulating a reference signal. Each subcarrier can be digitally modulated by a known pseudo-noise (PN) code to facilitate waveform detection in timing circuits.

[0007] In another embodiment, the synchronization system includes a timing source, which includes an oscillator that generates a reference signal (Sref) having a reference frequency (Fref), one or more processors that generate a digital signal composed of multiple tones, a digital-to-analog converter (DAC) that converts the digital signal into a waveform, and a combiner that combines the reference signal with the waveform to generate a synchronization signal in which a second time portion containing the waveform is interspersed with a first time portion containing the reference signal but not the waveform. The system further includes N timing circuits and N signal paths between the timing source and each of the N timing circuits, the N signal paths each having a different propagation delay. The timing source transmits the synchronization signal to the N timing circuits via the N signal paths, and phase matching of the output reference signal can be achieved in the same manner outlined above.

[0008] In another embodiment, the antenna system includes a digital beamforming (DBF) processor and a plurality of subassemblies, each RF-coupled to one or more antenna elements. The antenna system further includes the synchronization system outlined above, where each subassembly includes one of the respective timing circuits. Each of the plurality of subassemblies uses one of the output reference signals to generate a transmit path signal in a coherent manner with the others of the subassembly and / or receives a receive path signal, and collectively forms a transmit beam and / or receive beam through digital beamforming controlled by the digital beamforming processor. [Brief explanation of the drawing]

[0009] The above and other aspects and features of the disclosed technology will become clearer by reading the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, similar reference letters indicate similar elements or features. Different elements of the same or similar type may be distinguished by adding an underscore / dash to the reference label and a second label that distinguishes the same / similar elements (e.g., _1, _2), or by directly adding the second label to the reference label. However, if the given description uses only the first reference label, it may apply to any one of the same / similar elements having the same first reference label, regardless of the second label. In the drawings, elements and features may not be depicted in constant proportions.

[0010] [Figure 1] Figure 1 is a block diagram of a time and frequency synchronization system according to an embodiment. [Figure 2] Figure 2 illustrates an exemplary synchronization signal transmitted from a timing source to a remote timing unit of a synchronization system. [Figure 3] Figure 3A shows a simplified frequency spectrum of the waveform portion of an example synchronization signal, and Figure 3B shows a simulated example of the frequency spectrum of the waveform portion of the synchronization signal including modulated OFDM subcarriers. [Figure 4] Figure 4 is a flowchart of the synchronization method according to the embodiment. [Figure 5] Figure 5 is a flowchart of a synchronization method including the exchange of time-of-day (ToD) measurements according to an embodiment. [Figure 6] Figure 6 is a timing diagram illustrating exemplary signals and concepts in the methods of Figures 4 and 5. [Figure 7] Figure 7A is a block diagram showing exemplary timing source and timing circuitry in the synchronous system of Figure 1. Figure 7B is a schematic diagram of an exemplary combiner in the timing source of Figure 7A. [Figure 8] This is a schematic diagram showing an antenna system incorporating the synchronization system shown in Figure 1. [Modes for carrying out the invention]

[0011] The following description is provided, with reference to the accompanying drawings, to aid in a comprehensive understanding of certain exemplary embodiments of the art disclosed herein for illustrative purposes. While this description includes various specific details that will be helpful to those skilled in the art in understanding the art, these details should be considered illustrative only. For the sake of simplicity and clarity, descriptions of well-known features and structures may be omitted where their inclusion would obscure the understanding of the art by those skilled in the art.

[0012] Figure 1 is a block diagram of a time and frequency synchronization system 100 according to an embodiment. The synchronization system 100 includes a timing source 102, a 1:N divider (here N=2 or greater) 104, signal paths P_1 to P_N, timing units (here interchangeably referred to as “timing circuits”) 110_1 to 110_N, and a communication network (or link) 140 (e.g., a wired packet network or an independent link). Each timing unit 110 may be located in its own physically distributed assembly (e.g., a modularized subarray assembly, or an antenna element assembly including transceivers and modems for a phased array antenna system). The function of the timing units 110_1 to 110_N is to synchronize the output reference signal S RO1 ~S RON It may be possible to provide these reference signals S RO1 ~S RON This can be used for synchronous sampling of radio frequency (RF) signals in the receiving and / or transmitting paths to facilitate digital beamforming. Output reference signal S RO1 ~S RON These signals can also be upconverted to generate synchronous transmit signals that collectively form a transmit beam.

[0013] Timing source 102 outputs a synchronization signal Sy. The synchronization signal Sy includes a first time portion (described below) with a reference signal Sref having a reference frequency Fref. The signal Sy is divided by a 1:N divider 104 into N path signals Sy_1 to Sy_N, which are applied as inputs to signal paths P_1 to P_N. The signal paths P_1 to P_N may have different lengths and / or characteristics, and each of the signal paths has a different insertion phase (“propagation phase”). As a result, the signals Sy_1 to Sy_N at the outputs of the signal paths P_1 to P_N reach the timing unit 110 at different times T IN and unsynchronized, i.e., they can arrive at different instantaneous phases. Each timing unit 110_i (where i is any of 1 to N) can be configured to delay each received or applied signal Sy_i by a delay sufficient to provide an output signal S RO that is phase coherent with other output signals S ROi from other timing units 110. Briefly, this can be achieved by including a multi-tone waveform Sw (shown in FIG. 2) within a second time portion of the signal Sy. An example of the waveform Sw is a signal formed by a plurality of sub-carriers of an OFDM signal generated using Sref as a carrier. Each timing circuit 110_i can compare the phases of at least two tones of the waveform to determine the phase difference between the tones. From the phase difference(s), the propagation delay τ P on the signal path P_i can be determined. And the difference in propagation delays between the signal paths P_1 to P_N can be determined, for example, by the timing source 102. Knowing the different propagation delays, the individual delays τ RO to be applied to each timing unit 110 can be determined to achieve synchronization between the output reference signals S A . Then, the phase of the reference signal Sref portion of Sy can be adjusted corresponding to the delay determined for that timing unit. Thus, the phase of Sref can be adjusted based at least in part on the phase difference to provide a reference output signal S RO that is phase-aligned with those of the other timing units (e.g., a delayed version of Sref).

[0014] Messages can be transmitted between the timing source 102 and the timing units 110 via the network 140 to facilitate the synchronization process. For example, the timing source 102 may send a message to each of the timing units 110 indicating the next global time ToD1 when the waveform will be transmitted. Each of the timing units 110 may determine a local time ToD2 measured at the time it detects the reception of the waveform. Each may then report the determined ToD2, or the ToD difference between ToD1 and ToD2, to the timing source 102. ToD difference and propagation delay τ P Based on this, the timing source 102 outputs the signal S RO1 ~S RON The respective delay τ for timing units 110_1 to 110_N that should be applied to synchronize them with each other A It is possible to determine this.

[0015] According to the approach of this embodiment, signal paths P_1 to P_N can be embodied as low-cost, easily connected and deployed wired paths. Examples include Ethernet cables, optical fibers, coaxial cables, and twisted pairs, which are easy to deploy and connect and do not require insertion phase calibration. Furthermore, the delay adjustment process by the timing unit can be dynamic by using periodic phase measurement and adjustment, thus enabling performance targets to be achieved across various environmental conditions (e.g., changing temperature and humidity) that can cause variations in the insertion phase of the signal path. As a result, communication / antenna systems incorporating the synchronization system 100 can be manufactured at a lower cost and achieve performance targets that would otherwise be unattainable. For example, the reference signal frequency Fref may be around 100 MHz, while the final transmitted signal or sampled input received signal may be in the range of 10 to 1000 times higher than Fref. In one application example, this embodiment enables a digital beamforming system to use a phase-aligned output reference signal S RO1 ~S RONThis allows for configuration to form transmit / receive beams at higher frequencies without the need for calibrated combiners / dividers.

[0016] Figure 2 shows an exemplary synchronization signal Sy transmitted from the timing source 102 to the remote timing unit 110 of the synchronization system 100. The signal Sy may be a composite signal in which a "first time portion" containing only a reference signal Sref (tone signal at frequency Fref) is interspersed with a "second time portion" having a waveform signal ("waveform") Sw, and the waveform S W This is a multitone signal. In the example in Figure 2, waveform Sw is an orthogonal frequency division multiplexing (OFDM) signal in which phase-shifted modulation (PSK) modulated subcarriers collectively represent the PN code. Figure 2 shows only one second time portion between times t1 and t2, and two first time portions (one immediately before time t1 and one immediately after time t2), but other portions may exist in the signal Sy. The duration of the second time portion may be at least an order of magnitude shorter than that of the first time portion. In one example, Fref is approximately 100 MHz, and the period of waveform Sw (t2-t1) is approximately 2.5 μs. Because waveform Sw can be designed with a much higher peak-to-average power (e.g., at least 10 times higher) than that of the reference signal Sref, the associated signal processing that detects and analyzes waveform Sw can be idle for most of the time to conserve power.

[0017] Figure 3A shows a simplified frequency spectrum of the waveform Sw of a synchronization signal Sy in one example. In this example, the waveform Sw contains a reference (carrier) signal Sref at frequency Fref = 100 MHz, which is OFDM modulated with subcarrier interval f Δ This generates a subcarrier 302 (shown unmodulated in Figure 3A) having the following characteristics. One or more central subcarriers on either side are turned off to prevent phase disturbances from occurring near the reference signal Sref. As a result, the nearest subcarrier 302 is at least 2f from the reference signal Sref. Δ They can only move away by that much. In Figure 3A, the two central subcarriers on both sides are turned off.

[0018] Figure 3B shows a simulated example of the frequency spectrum of waveform Sw of a synchronization signal Sy with modulated OFDM subcarriers. Here, the subcarriers of waveform Sw are two-phase shift modulation (BPSK) modulated with a low-correlation sidelobe code (e.g., a known pseudo-noise (PN) code in timing unit 110, the Chu sequence in this example). Modulation of the subcarriers with a known code facilitates detection of waveform Sw by timing unit 110. Figure 3B shows the simulation results for an example with Sref at 100 MHz, 128 subcarriers separated by 0.5 MHz, a symbol period of 2 μs, and the eight central subcarriers turned off to prevent phase disturbances near Sref. A code rate of 50 mbps may be achievable with at least 100 subcarriers.

[0019] Figure 4 is a flowchart of a synchronization method 400 implemented by a synchronization system 100 according to an embodiment. Note that the sequence of operations of method 400, and of other flowcharts(s) herein, may differ as needed in other embodiments. Furthermore, illustrated operations may be excluded, and unillustrated operations may be added. In method 400, timing source 102 generates a tone reference signal Sref at frequency Fref (operation S402). Timing source 102 may also generate a multitone waveform Sw through OFDM modulation using Sref, for example (S404). The reference signal Sref may then be combined with the waveform Sw to generate a synchronization signal Sy. The synchronization signal Sy has a first time portion of Sref only, and a second time portion containing the waveform Sw, alternating or otherwise interspersed (S406). Next, the synchronization signal Sy can be transmitted to N timing units 110_1 to 110_N along N signal paths P_1 to P_N, each having a different propagation delay (S408). Note that each signal path P_i can be assumed to include the propagation distance from the circuit point for creating the signal Sy in the timing source 102, through the 1:N divider 104, to the input of the signal path P_i shown in Figure 1. In other words, each of the signal paths P_1 to P_N in Figure 1 can be assumed to include the propagation delay through the 1:N divider 104 and some related path length in the timing source 102.

[0020] Each timing unit 110_i first determines the phase difference between at least two of the tones in the waveform Sw, thereby determining the propagation delay τ for each signal path P_i. P The following can be calculated (S410). Alternatively, the phase difference is reported to timing source 102, which performs propagation delay calculation as described above. Using digital signal processing, the "delay" can be extracted from the received waveform in the following way. The waveform Sw (hereinafter denoted as w(t)) can be modeled as a sum of sinusoidal curves according to the following equation. In formula TIFF2026521463000002.tif8170, time t is from 0 to the waveform period Ts (for example, (t2-t1) in Figure 2), the total index value i represents any of the M subcarriers of the waveform Sw, and f i τ is the frequency of subcarrier i, and τ is the propagation delay τ P And θ i This represents the initial phase of the subcarrier at t+τ=0.

[0021] The initial phase of each subcarrier is set to zero, and the M subcarriers have a frequency of f Δ If they are arranged at equal intervals, the phase difference φ between adjacent subcarriers Δ This can be written as follows: TIFF2026521463000003.tif8170TIFF2026521463000004.tif8170

[0022] Since the subcarrier frequency is known in the timing unit 110, the propagation delay τ P The received waveform S W This can be calculated by performing a Fast Fourier Transform (FFT) and comparing the phase differences between subcarriers. Here, the minimum value of the single phase difference between two subcarriers is τ P While this may be sufficient for calculation, note that higher accuracy can be obtained by using two or more phase differences between two or more subcarriers and averaging them.

[0023] The timing unit 110 controls the propagation delay τ P This is reported to the timing source 102 via the network 140 (S412). The timing source 102 then receives the delay τ P Based at least partially on this, each of the N timing units 110_1 to 110_N applies its respective delay τ to the reference signal Sref it receives. A Calculate (S414). Alternatively, delay τ AThe (N-1) timing units 110 are sent to and applied by them, with one of the timing units 110 being used as the reference (applied delay = 0). Then, each timing circuit 110 receives the delay τ A SRef is delayed based on this, and all output reference signals S RO1 -S RON Align the phases (S416). In some embodiments, delay τ A This can be determined and applied by each timing unit 110.

[0024] Figure 5 is a flowchart of the synchronization method 500, which, according to the embodiment, involves exchanging time (ToD) measurements to achieve ToD synchronization. Method 500 is described below in relation to the exemplary signals shown in Figure 6. In some applications, it is desirable or necessary that each timing unit 110 includes a ToD counter, which is synchronized with the ToD counters of other timing units. This can facilitate achieving the desired result of synchronous sampling of signals in both transmit and receive operations. When the antenna system has physically distributed assemblies, and each assembly has a timing unit 110, such ToD synchronization is achieved by outputting a reference signal S RO1 ~S RON Combined with synchronization, each assembly can sample the received signal precisely and simultaneously, enabling coherent reception and proper formation of the received beam by the assembly. Similar synchronous sampling can be performed in transmission operations to generate a coherent transmitted signal.

[0025] Each ToD counter in the timing unit 110 may not be synchronized with one another initially. Therefore, as shown in Figure 6, the ToD counters may initially output different counts CT_1…CT_N (representing time) during power-up initialization, and initially output unsynchronized local ToDs. In method 500, the ToD value measured at the time an instance of waveform Sw is detected, as well as the calculated propagation delay value or phase difference value, may be reported by the timing unit 110 to the timing source 102. Alternatively, autonomous adjustment of the local clock may be performed in the timing unit, and only the propagation delay may be reported to the timing source, as described below. This allows the timing source 102 to calculate the respective delays that the timing unit 110 applies to achieve both ToD synchronization and reference signal synchronization.

[0026] Therefore, in operation S502, the timing source 102 may send a "ToD Sync" message via the network 140 to notify each of the timing units 110 of the next time ToD1 (measured at the clock of the timing source 102) when the next pulse waveform Sw of the synchronization signal Sy will be sent to the timing unit 110. For example, as shown in Figure 2, the time (t1 to t2) may be considered as the period of one instance of the waveform Sw ("one pulse" of the signal Sy), and before time t1, the timing source 102 may send a ToD Sync message indicating ToD1=t1. As shown in Figure 6, the waveform Sw may be a signal with a periodic pulse Swp, each periodic pulse Swp having the same or similar time-varying amplitude as in Figure 2 (the duration of each pulse is (t2-t1)). The timing source 102 may have a counter that increments a count CS representing the "global" time. The count CS may be incremented in each cycle of Sref (i.e., at the frequency of Fref). The count can be reset at time t1 when the next pulse Swp is sent.

[0027] The timing source 102 may generate a synchronization signal Sy having the next pulse Swp of waveform Sw starting at time ToD1 (= t1 shown in Figure 6) and transmit it to the timing unit 110 (S508). To do this, the signal Sy may be generated in the same manner as described above for operations S402-S408 in Figure 4. Each timing unit 110_i may receive the signal Sy (including Sw), detect the next waveform pulse Swp of signal Sy, and determine the local time ToD2 at which it was received (S520). In some embodiments, each timing unit reports the determined ToD2 to the timing source 102 (as indicated by the return arrow S511). In other embodiments, each timing unit 110_i performs autonomous adjustment of its clock or clock count with the aim of achieving a rough alignment of the local clocks among all timing units 110_1-110_N. The local time ToD2 of the timing unit 110_i may be represented by the clock count of a ToD timer running in the timing unit 110_i, and the ToD timer may have the same characteristics as a counter in the timing source 102.

[0028] For example, as shown in Figure 6, the respective counts CT_1, CT_k, and CT_N initially output by the counters of timing units 110_1, 110_k, and 110_N may differ significantly due to initial random counter errors (e.g., during power-up initialization). Upon detection of the next Swp pulse (after receiving the ToD Sync message), each of the timing units may have a different count due to the initial random counter errors. Therefore, each timing unit 110 may output a significantly different ToD2 when the expected Swp pulse is detected. As mentioned above, in some embodiments, each timing unit 110 reports the measured ToD2 to the timing source 102. In this case, the timing source 102 can then calculate the ToD-based delay applied by each timing unit 110 to achieve a rough match of the ToD counters. (In Figure 5, the applied ToD delay may be sent in a separate transmission or between S516 and S518 as described below.) A (May be sent as part of a transmission.)

[0029] In other embodiments, at S510, each timing unit 110 autonomously adjusts its count based on the difference (ToD2-ToD1), where ToD2 is the locally measured time when the expected Swp pulse is detected. As a result of the individual count adjustments, a rough alignment is achieved between the ToD counters, which is shown in Figure 6 for both of the above embodiments. The different delays of ToD delay 1, ToD delay k…ToD delay N in the timing unit 110 (each relative to the locally determined Swp start) are due to random counter errors. After offset adjustments due to different ToD2s (either based on commands from the timing source 102 or performed autonomously), a rough alignment of the counters is achieved, and the counters output closer aligned counts CT-1', CT-k', and CT-N'. This rough alignment does not take into account different propagation delays, which are typically significantly smaller than the initial random timing error.

[0030] Here, because the propagation delays across paths P_1 to P_N are different, even if there are no initial random counter errors in each of the timing unit counters, the measured ToD2 will be different for each timing unit 110_1 to 110_N. The different propagation delays are due to τ P Delay 1, τ P Delay k...τ P The delay N is illustrated in Figure 6. As shown in Figure 6, by performing waveform calculation (FFT analysis) of the received pulse Swp followed by fine-tuning of ToD, different propagation delays can be calculated across the signal path P_1 to P_N.

[0031] Therefore, each timing unit 110 can determine the phase difference between at least two of the tones in the waveform pulse Swp and calculate the propagation delay of the signal path P_i, similar to what was described above for method 400 (S512). Then, the propagation delay τ P This can be reported to the timing source 102 (S514). The timing source 102 then reports each delay τ applied by the timing unit 110. A The delay τ can be calculated and transmitted to the timing unit (S516). Here, in some embodiments, the delay τ A is the propagation delay τ P This is calculated based on both the difference between each measured local time ToD2 and global time ToD1 (ToD2-ToD1). In another embodiment, if the timing unit 110 performs its own autonomous adjustment to ToD as described above, the applied delay τ A is the propagation delay τ P It can only be calculated based on this.

[0032] Next, each timing unit 110 receives the input reference signal Sref and the respective delay τ sent by the timing source 102. A Delay only by the output reference signal S RO1 ~S RON The phases of these can be aligned (S518).

[0033] Figure 7A is a block diagram showing an exemplary timing source 102 and timing unit 110_i in the synchronization system of Figure 1. The timing source 102 includes both a highly stable oscillator that generates a reference signal Sref and digital signal processing that generates an OFDM timing waveform Sw that is phase-coherent with Sref. Both are sent to their respective timing units 110_i as part of the synchronization signal Sy through the exact same path P_i. To do this, the timing source 102 may include a highly stable oscillator 704 (e.g., an oven-controlled crystal oscillator (OCXO)), a phase-locked loop (PLL) 722, one or more processors 720 (hereinafter simply referred to as "processor 720"), a digital-to-analog converter (DAC) 730, a memory 739, a combiner 732, and a bandpass filter (BPF) 734. The processor 720 may include a pseudo-noise (PN) code generator 722, an inverse fast Fourier transform (IFFT) engine 724, and a time-of-day (ToD) counter 725. Oscillator 704 generates a reference signal Sref at frequency Fref. This can be applied to PLL 706, ToD counter 725, and combiner 732. ToD counter 725 can increment its count by each cycle (period) of signal Sref.

[0034] The PLL 706 can convert the signal Sref into a clock signal Fs. The PN code generator 722 uses this as a timing reference to generate a low-correlated sidelobe code (e.g., the Chu sequence). This code is applied to the IFFT engine 724. The IFFT engine 724 can generate a digital OFDM signal (e.g., a time-varying complex sine wave representing the code). The complex sine wave can be represented by two output streams, an in-phase (I) signal stream and a quadrature-phase (Q) signal stream. The digital OFDM signal may have time-domain variations corresponding to the frequency-to-time conversion of a predetermined number of subcarriers (e.g., 128), each digitally modulated using appropriate techniques (e.g., PSK, amplitude-shifted modulation (ASK), quadrature amplitude modulation (QAM), etc.).

[0035] The OFDM signal generated by the IFFT engine 724 is converted to an analog signal by the DAC 730 and applied to the combiner 732. Here, the DAC 730 can output a common-phase (I) analog signal Sw_I and a quadrature-phase (Q) analog signal Sw_Q in parallel. The combiner 732 can combine the analog signal with the signal Sref from the oscillator 704 to generate a synchronization signal Sy having the characteristics described above (for example, as shown in Figure 2). To do this, as shown in Figure 7B, the combiner 732 may include a first mixer 771 that upconverts the I signal Sw_I using Sref, a 90° delay element 774 for delaying Sref, a second mixer 772 that upconverts the Q signal Sw_Q using the 90° delayed Sref, an adder 780 that adds the upconverted I and Q signals to generate a waveform Sw as a quadrature modulated signal, and a multiplexer 790 that multiplexes the waveform Sw with the reference signal Sref to form a synchronization signal Sy. The signal Sy is output to a bandpass filter 734, and its filtered output is applied to a 1:N divider 104. The 1:N divider 104 can divide Sy evenly into N signal paths P_1 to P_N.

[0036] Figure 7A further shows an exemplary configuration for a single timing unit 110_1. Each timing unit 110_1 to 110_N may have the same configuration. Timing unit 110_1 may include a bandpass filter 740, a splitter 742, an analog-to-digital converter (ADC) 744, a variable delay 748, a cleanup PLL 746, a processor 750, and a memory 769. The processor 750 may include a digital downconverter (DDC) 752, an FFT computer 756, a PN code decoder 758, a propagation delay computer 759, and a time-of-day (ToD) counter 755.

[0037] The bandpass filter 740 filters the input signal Sy_1, and the filtered output signal is split by the splitter 742. The first output of the splitter 742 is applied to the cleanup PLL 746. The cleanup PLL 746 can lock onto Sref and multiply it by Sref to generate a higher frequency tone signal Sref', thereby removing the subcarriers. The frequency of the tone signal Sref' is Fs = (k x Fref), where k can be an integer (e.g., 2 or greater) or a non-integer. The variable delay 748 receives Sref' from the timing source 102 through the processor 750 with an applied delay τ A It can be delayed by only a small amount. The ADC744 can use the delayed signal Sref' to convert the other output signal of the splitter 742 into a digital signal by sampling at the frequency Fs of Sref'. The delayed signal Sref' can also be used with the output reference signal S RO1 It can be output as follows.

[0038] The digital signal output from ADC744 is digitally downconverted by DDC752 and then applied to FFT computer 756. FFT computer 756 can derive complex values ​​representing the amplitude and phase of each or some of the subcarriers of signal Sy_1, respectively. PN code decoder 758 can decode the output of FFT computer 756 to detect whether a PN code has been detected. If a PN code is detected, propagation delay computer 759 uses the same FFT output value associated with the PN code to calculate the propagation delay τ based on the phase difference between at least one pair of subcarriers, for example, according to equations (1) to (3) described above. P The processor 750 can calculate the propagation delay τ. P This can be reported to the timing source 102 via the network 140.

[0039] A reference signal (i.e., Sref or Sref') output from the PLL 746 can be applied to the ToD counter 755. The ToD counter 755 can increment its count for each cycle of the reference signal. As previously mentioned in relation to Figure 5, the ToD counter 755 can output a count corresponding to the local time value ToD2 at the time the synchronization signal Sy is detected. To do this, when the PN code decoder 758 detects that the PN code has been received, the process running within the processor 750 can obtain the count from the ToD counter 755. The processor 750 can then report ToD2 (or the raw count only) to the timing source 102. The processor 720 of the timing source 102, as previously mentioned, τ P Based on ToD2, τ A Calculate τ A The individual values ​​of these can be reported to their respective timing units 110_1 to 110_N.

[0040] Figure 8 schematically shows an exemplary antenna system 800 incorporating the synchronization system of Figure 1. The antenna system 800 includes a plurality of N physically separated subassemblies 810_1 to 810_N. These are radio frequency (RF) coupled to antenna elements 802_1 to 802_N and each includes timing units 110_1 to 110_N. The antenna system 800 may further include a communication network 140, a timing source 102, a 1:N splitter 104, signal paths P_1 to P_N coupled to timing units 110_1 and 110_N as described above, and a digital beamforming (DBF) processor 820. Each subassembly 810 may further include an RF front end 804 and a modem 806. The timing source 102 and timing units 110_1 to 110_N operate as described above to produce a synchronized output reference signal S RO1 ~S RON It can generate the following. The antenna system 800 can be configured as a transmitting system, a receiving system, or a transceiver system. Simply put, each of the subassemblies 810 generates the output reference signal S derived therein.RO It is possible to generate a transmit path signal and / or receive a receive path signal in a coherent manner with other subassemblies 810. The coherent operation collectively forms at least one transmit / receive beam through digital beamforming controlled by the digital beamforming processor 820. Note that while each subassembly 810 is coupled to a single antenna element 802 as an example in the illustration, in other examples each subassembly 810 may be coupled to multiple antenna elements 802, for example to provide polarization diversity and / or to generate multiple simultaneous beams.

[0041] During transmission, subassemblies 810_1 to 810_N are reference signal S RO1 ~S RON Using this, a coherent transmission signal S is transmitted through antenna elements 802_1~802_N. T1 ~S TN Each of these can be generated and transmitted. Signal S T1 ~S TN Because it is coherent, antenna elements 802_1~802_N can collectively operate as a single antenna array and form one or more transmit beams. To do this, the reference signal S RO This can be upconverted to a coherent microwave or millimeter-wave carrier signal using a mixer and local oscillator within the RF front-end 804. In addition to or instead of this, a reference signal S ROThis can be used as a timing signal for sampling within the modem 806 and, in combination with the DBF processor 820, to generate a modulated data signal. In either case, each RF front-end 804 may include one or more amplifiers, switches, and / or one or more phase shifters for implementing transmit beam steering, allowing the antenna system 800 to operate as an electronically operated antenna or a phased array antenna. Note that because the antenna system 800 transmits a coherent transmit signal using digital beamforming, a calibrated combiner / divider network designed for microwave / millimeter frequencies may be omitted. Such a combiner / divider network is typically used in conventional antenna systems to split a single RF transmit signal into N divided phase-aligned RF signals (with or without distributed amplification / phase shift) and route them directly to the antenna element 802.

[0042] Upon reception, subassemblies 810_1 to 810_N receive the reference signal S. RO1 ~S RON The received signal S coming in through antenna element 802 is used with this method. R1 ~S RN This can be received in a coherent manner. To do this, the reference signal S RO The RF front end 804 and modem 806 receive the signal S R1 ~S RN This can be used as a timing signal for coherently downconverting and sampling. The modem 806 then outputs the digital baseband received signals to the DBF processor 820, and by combining them, one or more virtual received beams can be formed. Similar to the transmission path example described above, each RF front end 804 includes a mixer(s), a switch, a local oscillator(s), a bandpass filter(s), a low-noise amplifier(s), a phase shifter(s), and a reference signal S with dynamic amplification / phase shift for received beam steering. RODown-conversion can be performed using this method. Antenna system 800 uses digital beamforming to coherently receive and combine incoming received path signals, thus eliminating the need for a calibrated combiner / divider network designed for microwave / millimeter frequencies, and allowing the combined analog received signal to be obtained in other ways.

[0043] Various exemplary logic blocks, units, engines, computers, modules, and circuits described in connection with this disclosure may be implemented or carried out using processing circuits (e.g., processors 720 and 750) within a timing source 102 and / or timing circuit 110 that can read and execute instructions from non-temporary recording media (e.g., memories 739 and 769). Processing circuits may include general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate array signals (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0044] In one or more embodiments, the functions described above may be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, the functions may be stored as one or more instructions or codes on a non-temporary computer-readable medium (e.g., memory 739 or 769). Examples of computer-readable mediums include both computer storage media and communication media, and include any medium that facilitates the transfer of computer programs from one location to another. The storage medium may be any available medium accessible to the computer / processing circuit.

[0045] Although the technologies described herein have been illustrated and described in particular with reference to exemplary embodiments, various modifications in form and detail may be made without departing from the spirit and scope of the subject matter set forth in the claims, as defined by the following claims and their equivalents, as will be apparent to those skilled in the art.

Claims

1. The synchronization method is (400, 500), In timing sources, To generate a reference signal having a reference frequency (S402), To generate a waveform containing multiple tones (S404), The reference signal is combined with the waveform to generate a synchronization signal in which a second time portion containing the waveform is interspersed within a first time portion containing the reference signal but not containing the waveform (S406, S508). The synchronization signal is transmitted to multiple timing circuits via multiple signal paths, each having a different propagation delay (S408, S508, S512, S518). In the first circuit (110_1) of the aforementioned timing circuits, The phase difference between at least two of the plurality of tones of the received waveform is determined. The reference signal is delayed by a delay that is at least partially based on the phase difference, and a first output reference signal is provided that is in phase with the second output reference signal provided by the second circuit (110_N) of the timing circuit (S410, S416, S512, S518). Synchronization methods including (400, 500).

2. Each of the timing circuits determines at least one phase difference between at least two of the plurality of tones and a propagation delay corresponding to the at least one phase difference (S410, S512). Each of the aforementioned timing circuits reports the propagation delay determined thereto to the timing source (S412, S514), In the timing source, the propagation delay is received from each of the timing circuits, and at least partially based thereon, the timing circuits determine their respective delays for synchronizing the output reference signal, and transmits these respective delays to the timing circuits (S414, S516). The synchronization method according to claim 1 (400, 500), further comprising the above.

3. The synchronization method (400, 500) according to claim 2, wherein the reporting to the timing source by each of the timing circuits is performed via a packet network (140).

4. The synchronization method according to claim 1 (400, 500), wherein the plurality of tones of the waveform are subcarriers of an orthogonal frequency division multiplexing (OFDM) signal.

5. The synchronization method (400, 500) according to claim 4, wherein each of the subcarriers is modulated by a pseudo-noise code.

6. The synchronization method according to claim 5 (400, 500), wherein each of the subcarriers is modulated by phase shift modulation (PSK), amplitude shift modulation (ASK), or quadrature amplitude shift modulation (QAM).

7. Each of the aforementioned subcarriers is separated from at least one adjacent subcarrier by a spacing frequency f Δ They are separated by only a small amount. Of the subcarriers, the one closest to the reference frequency is at least 2f Δ The synchronization method (400, 500) according to claim 4, wherein the distance between them is only that much.

8. The synchronization method (400, 500) according to claim 1, wherein the plurality of signal paths include at least one of Ethernet cables, optical fibers, and coaxial cables.

9. In the timing source, a message (ToD Sync) indicating the global time (ToD1) at which the next pulse (Swp) of the waveform is transmitted is transmitted to each of the timing circuits via the network (140) (S508). In each of the timing circuits, the local time (ToD2) measured at the time of detecting the reception of the next pulse of the waveform is determined, and the local clock is adjusted according to the difference between ToD2 and ToD1 (S510). The synchronization method (400, 500) according to claim 2, further comprising the above.

10. The synchronization method according to claim 9 (400, 500), further comprising incrementing the counter count for each cycle of the received reference signal in each of the timing circuits, and determining ToD2 as corresponding to the count at the time the next pulse of the waveform is received (S510).

11. The synchronization method according to claim 10 (400, 500), further comprising: in the timing source, incrementing the count of the timing source counter for each cycle of the reference signal, and determining ToD1 as corresponding to the count of the timing source counter at the time of transmitting the next instance of the waveform (S502).

12. Each of the aforementioned timing circuits reports the local time (ToD2) to the timing source (S510), In the aforementioned timing source, Each of the timing circuits receives its respective ToD2, and based on the respective ToD2 and the propagation delay, The timing circuit has a delay (τ) for each of the output signals to synchronize the output signals. Ａ (S516) Determine the respective delays and transmit them to the timing circuit. The synchronization method according to claim 9 (400, 500), further comprising the above.

13. The synchronization method according to claim 10 (400, 500), further comprising resetting the count to an initial value in each of the timing circuits after the count has been determined at the time the waveform has been received.

14. Each of the timing circuits determines at least one phase difference between at least two of the plurality of tones, Each of the timing circuits reports the at least one phase difference to the timing source, The timing source receives at least one phase difference from each of the timing circuits, and at least partially based thereon determines the respective delays for the timing circuits to synchronize the output reference signal in the timing circuits, and transmits the respective delays to the timing circuits. The synchronization method according to claim 1 (400, 500), further comprising the above.

15. A synchronization system (100), Timing source (102), An oscillator (704) that generates a reference signal (Sref) having a reference frequency (Fref), One or more processors (720) that generate a digital signal composed of multiple tones, A digital-to-analog converter (DAC) (730) that converts the aforementioned digital signal into a waveform (Sw), A timing source (102) includes a combiner (732) that combines the reference signal with the waveform to generate a synchronization signal (Sy) in which a second time portion including the waveform is interspersed within a first time portion including the reference signal but not including the waveform, N timing circuits (110_1 to 110_N) (where N is at least 2), The N signal paths (P_1 to P_N) between the timing source and each of the N timing circuits, wherein each of the N signal paths has a different propagation delay, and the N signal paths (P_1 to P_N) include The timing source transmits the synchronization signal through the N signal paths to the N timing circuits, the first circuit (110_1) of the timing circuits determines the phase difference between at least two of the plurality of tones of the waveform received there, delays the reference signal by a delay at least partially based on the phase difference, and the second output reference signal (S) provided by the second circuit (110_N) of the timing circuits ＲＯＮ ) and a first output reference signal (S) that is in phase with it ＲＯ１ ) is configured to provide Synchronization system (100).

16. The synchronization system (100) according to claim 15, further comprising an inverse fast Fourier transform (IFFT) engine (724) that generates the digital signal as an orthogonal frequency division multiplexing (OFDM) signal representing a predetermined code.

17. The synchronization system (100) according to claim 16, wherein the predetermined code is a pseudo-noise code.

18. Antenna system (800), A plurality of subassemblies (810), each of which radio frequencies (RF) are coupled to one or more antenna elements (802), Timing source (102), An oscillator (704) that generates a reference signal (Sref) having a reference frequency (Fref), One or more processors (720) that generate a digital signal composed of multiple tones, A digital-to-analog converter (DAC) (730) that converts the aforementioned digital signal into a waveform (Sw), A timing source (102) includes a combiner (732) that combines the reference signal with the waveform to generate a synchronization signal (Sy) in which a second time portion including the waveform is interspersed within a first time portion including the reference signal but not including the waveform, N timing circuits (110_1 to 110_N), each of which is located within one of the subassemblies, N signal paths (P_1 to P_N) between the timing source and each of the N timing circuits, wherein each of the N signal paths has a different propagation delay, Includes a digital beamforming processor (820), The timing source transmits the synchronization signal through the N signal paths to the N timing circuits, the first circuit (110_1) of the timing circuits determines the phase difference between at least two of the plurality of tones of the waveform received there, delays the reference signal by a delay at least partially based on the phase difference, and the second output reference signal (S) provided by the second circuit (110_N) of the timing circuits ＲＯＮ ) and a first output reference signal (S) that is in phase with it ＲＯ１ ) is configured to provide, Each of the plurality of subassemblies uses one of the output reference signals to generate a transmit path signal and / or receive a receive path signal in a coherent manner with the others of the subassembly, and collectively forms a transmit beam and / or receive beam through digital beamforming controlled by the digital beamforming processor. Antenna system (800).

19. The antenna system (800) according to claim 18, further comprising an inverse fast Fourier transform (IFFT) engine (724) that generates the digital signal as an orthogonal frequency division multiplexing (OFDM) signal representing a predetermined code.

20. The antenna system (800) according to claim 19, wherein the predetermined code is a pseudo-noise code.

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