Method and structure for high-strength asymmetric dielectrics in hybrid coupling
By employing asymmetric dielectric hybrid bonding in semiconductor devices, the challenges of pitch scaling and bonding strength are addressed, enabling reduced pitch and higher metal pad density for advanced semiconductor devices.
Patent Information
- Application Number
- JP2026513282
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-01
- Filing Date
- 2024-08-29
- Publication Date
- 2026-09-08
AI Technical Summary
Conventional hybrid bonding techniques face limitations in pitch scaling, leading to insufficient bonding strength and reduced dielectric surface area, which restricts further miniaturization and integration of semiconductor devices.
A semiconductor device structure involving asymmetric dielectrics is formed by hybrid bonding, where a first structure with a first dielectric layer and copper-containing material is bonded to a second structure with a different dielectric layer and copper-containing material, enhancing bonding strength through asymmetric dielectric junctions.
The method increases bonding strength and allows for reduced pitch and higher metal pad density between wafers, facilitating the development of advanced semiconductor devices with improved performance and miniaturization.