Array substrate and display device

Abstract

To provide a highly reliable array substrate and a display device having the array substrate.SOLUTION: The array substrate according to an embodiment includes: a semiconductor layer; a signal line in contact with the semiconductor layer; a relay electrode separate from the signal line, the relay electrode being in contact with the semiconductor layer; a first insulating layer covering the signal line and the relay electrode; and a gate electrode arranged above the first insulating layer, the gate electrode facing the semiconductor layer. The semiconductor layer has an opening between the signal line and the relay electrode in planer view.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The embodiments of the present invention relate to an array substrate and a display device. [Background technology]

[0002] Display devices such as electrophoretic display devices and liquid crystal display devices include an array substrate on which thin-film transistors are formed. A plurality of thin-film transistors may be arranged closely to each other on the array substrate. If an insulating layer between two conductive layers arranged above the semiconductor layer becomes locally thin due to a step caused by the semiconductor layer of each thin-film transistor, dielectric breakdown may occur. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-126218 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide an array substrate with excellent reliability and a display device including the array substrate. [Means for solving the problem]

[0005] An array substrate according to one embodiment includes a semiconductor layer, a signal line in contact with the semiconductor layer, a relay electrode spaced apart from the signal line and in contact with the semiconductor layer, a first insulating layer covering the signal line and the relay electrode, a gate electrode disposed above the first insulating layer and facing the semiconductor layer, a second insulating layer disposed below the first insulating layer and covering the semiconductor layer; The semiconductor layer has an opening located between the signal line and the relay electrode in a plan view. The second insulating layer has a first opening and a second opening overlapping the semiconductor layer, the first electrode contacts the semiconductor layer through the first opening, and the second electrode contacts the semiconductor layer through the second opening. According to another aspect of the embodiment, the array substrate includes a semiconductor layer, a first electrode in contact with the semiconductor layer, a second electrode spaced apart from the first electrode and in contact with the semiconductor layer, a first insulating layer covering the first electrode and the second electrode, a gate electrode disposed above the first insulating layer and facing the semiconductor layer, and a scanning line disposed below the semiconductor layer, connected to the gate electrode, and extending in a first direction. The first electrode and the second electrode are aligned in the first direction. The semiconductor layer has a first side and a second side parallel to a second direction intersecting with the first direction, a third side and a fourth side parallel to the first direction, and an opening located between the first electrode and the second electrode in a plan view. Furthermore, the scanning line has a protrusion protruding toward the third side at a position overlapping the semiconductor layer.

[0006] A display device according to one embodiment includes the array substrate, a counter substrate facing the array substrate, and a display function layer disposed between the array substrate and the counter substrate. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing the configuration of the display device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic circuit diagram of the display device according to the first embodiment. [Diagram 3] FIG. 3 is an equivalent circuit diagram applicable to the pixel shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of a display panel included in the display device according to the first embodiment. [Diagram 5] FIG. 5 is a schematic plan view of main elements arranged on the array substrate according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged view of the switching element in FIG. [Figure 7] FIG. 7 is a schematic plan view of the semiconductor layers and the scan lines in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the array substrate taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the array substrate taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a schematic plan view of a switching element according to a comparative example. [Figure 11] FIG. 11 is a schematic cross-sectional view of an array substrate according to a comparative example. [Figure 12] FIG. 12 is a schematic plan view of a switching element according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Several embodiments will now be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while keeping the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be represented more diagrammatically than the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In each figure, the reference numerals may be omitted for identical or similar elements arranged consecutively. In addition, in this specification and each figure, the same reference numerals may be used for components that perform the same or similar functions as those described above with respect to the previous figures, and duplicate detailed descriptions may be omitted.

[0009] In each embodiment, an electrophoretic display device and an array substrate provided in the display device are disclosed as an example. However, each embodiment does not prevent the application of each technical idea disclosed in each embodiment to other types of display devices. Examples of other types of display devices include a liquid crystal display device having a liquid crystal layer, an organic EL display device in which a light-emitting layer is arranged in each pixel, and an LED display device in which a small LED is arranged in each pixel. In addition, the array substrate disclosed in each embodiment can be applied to various electronic devices that do not have a display function.

[0010] When the configurations disclosed in the respective embodiments are applied to a liquid crystal display device, the display device may be a so-called polymer dispersed liquid crystal display device (PDLC). This type of liquid crystal display device displays an image by switching the liquid crystal layer of each pixel between a scattering state in which light is scattered and a transparent state in which light is transmitted. This polymer dispersed liquid crystal display device (PDLC) is used as a transparent display in which the background on the rear side of the panel is visible when viewed from the image display surface (panel front surface) side, and similarly, the background on the image display surface side is visible when viewed from the rear side of the panel.

[0011] [First embodiment] FIG. 1 is a plan view showing the configuration of a display device DSP according to a first embodiment. As shown in FIG. 1, a first direction X, a second direction Y, and a third direction Z are defined. In this embodiment, the first direction X, the second direction Y, and the third direction Z are mutually orthogonal. However, the first direction X, the second direction Y, and the third direction Z may intersect at an angle other than 90 degrees. The first direction X and the second direction Y are parallel to the main surface of each substrate included in the display device DSP. The third direction Z corresponds to the thickness direction of each element included in the display device DSP.

[0012] In the following description, when "a second member above a first member" and "a second member below a first member" are described, the second member may be in contact with the first member or may be separated from the first member. In the latter case, another member may be interposed between the first member and the second member. In addition, viewing the display device DSP and its components parallel to the third direction Z is referred to as a planar view.

[0013] The display device DSP includes an active matrix display panel PNL, a wiring substrate CB, and a controller CTL. The display panel PNL includes an array substrate AR and a counter substrate CT facing the array substrate AR in the third direction Z. In the example of Fig. 1, the array substrate AR and the counter substrate CT are rectangular with short sides parallel to the first direction X and long sides parallel to the second direction Y. However, the shapes of the array substrate AR and the counter substrate CT are not limited to this example.

[0014] The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. In this embodiment, the peripheral area SA is frame-shaped. The display panel PNL further includes gate drivers GD1 and GD2 and a source driver SD. The gate drivers GD1 and GD2 supply scanning signals to scanning lines, which will be described later. The source driver SD supplies image signals to signal lines, which will be described later.

[0015] The wiring board CB is connected to the array board AR. The controller CTL is, for example, an IC chip, and is mounted on the wiring board CB. The controller CTL supplies driving signals to the gate drivers GD1 and GD2 and the source driver SD via the wiring board CB or the like. The controller CTL may be mounted in another position, for example, on the array board AR or the like.

[0016] Fig. 2 is a schematic circuit diagram of the display device DSP. Fig. 3 is an equivalent circuit diagram applicable to the pixel PX shown in Fig. 2. As shown in Figs. 2 and 3, the display panel PNL includes a first substrate 1, a plurality of pixels PX, a plurality of scanning lines G, a plurality of signal lines S, a plurality of capacitance wirings CW, and a common electrode CE. The plurality of pixels PX are arranged in a matrix in the display area DA. The plurality of pixels PX, the plurality of scanning lines G, the plurality of signal lines S, and the plurality of capacitance wirings CW are disposed above the first substrate 1.

[0017] The multiple scanning lines G extend in the first direction X and are aligned in the second direction Y. Each scanning line G is connected to one of the gate drivers GD1 and GD2, and is also connected to multiple pixels PX aligned in the first direction X. The multiple signal lines S extend in the second direction Y and are aligned in the first direction X. Each signal line S is connected to the source driver SD and is also connected to multiple pixels PX aligned in the second direction Y. The multiple capacitance lines CW extend in the second direction Y and are aligned in the first direction X. Each capacitance line CW is connected to the controller CTL and is also connected to multiple pixels PX aligned in the second direction Y.

[0018] The gate drivers GD1 and GD2 supply a scanning signal SG to the scanning lines G. The controller CTL supplies an image signal (or video signal) Vsig to the source driver SD. The source driver SD supplies the image signal Vsig to the corresponding signal line S. The controller CTL supplies a voltage Vpc to the capacitance line CW. The controller CTL also supplies a common voltage Vcom to the common electrode CE. For example, the voltage Vpc and the common voltage Vcom are at the same potential.

[0019] 3, each pixel PX includes a switching element SW, a first capacitance C1, a second capacitance C2, and a pixel electrode PE. In this embodiment, the switching element SW includes a first transistor Tr1 and a second transistor Tr2.

[0020] The first transistor Tr1 and the second transistor Tr2 are configured with thin film transistors (TFTs) of the same conductivity type, for example, P-channel type. The semiconductor layers of the first transistor Tr1 and the second transistor Tr2 are formed of an oxide semiconductor. Note that the semiconductor layers may be made of semiconductors other than oxide semiconductors, such as polycrystalline silicon, such as low-temperature polycrystalline silicon, or amorphous silicon. The first transistor Tr1 and the second transistor Tr2 may be configured with N-channel type TFTs.

[0021] The first transistor Tr1 and the second transistor Tr2 are both thin film transistors (TFTs) and have a first electrode E1, a second electrode E2, and a gate electrode GE. One of the first electrode E1 and the second electrode E2 functions as a source electrode, and the other functions as a drain electrode. The first transistor Tr1 and the second transistor Tr2 are connected in parallel between the signal line S and the pixel electrode PE.

[0022] In each of the first transistor Tr1 and the second transistor Tr2, the first electrode E1 is connected to the signal line S, the second electrode E2 is connected to the pixel electrode PE, and the gate electrode GE is connected to the scanning line G. As a result, each of the first transistor Tr1 and the second transistor Tr2 is switched to a conductive state or a non-conductive state by a scanning signal SG provided to the scanning line G. An image signal Vsig is supplied to the pixel electrode PE via the signal line S and the conductive transistors Tr1 and Tr2.

[0023] The first capacitor C1 is connected to the pixel electrode PE and the capacitor line CW, and the second capacitor C2 is connected to the pixel electrode PE and the common electrode CE.

[0024] Fig. 4 is a schematic cross-sectional view of the display panel PNL. Here, attention is focused on one pixel PX. As shown in Fig. 4, the array substrate AR includes a first substrate 1 and a pixel electrode PE provided on the first substrate 1. The counter substrate CT includes a second substrate 2 and a common electrode CE facing the pixel electrode PE. For example, the common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0025] The first substrate 1 and the second substrate 2 are formed of an insulating material such as plastic or glass. In this embodiment, the second substrate 2 is located on the screen side (observation side) and has optical transparency. The first substrate 1 is located on the opposite side of the screen, and may be opaque or transparent.

[0026] The display panel PNL includes a display function layer DL disposed between an array substrate AR and a counter substrate CT. A voltage applied between the pixel electrodes PE and a common electrode CE acts on the display function layer DL. In this embodiment, the display function layer DL is an electrophoretic layer and includes a plurality of microcapsules 30 arranged with almost no gaps in the XY plane.

[0027] The microcapsules 30 are spherical bodies having a particle size of, for example, about 20 μm to 70 μm. In the illustrated example, many microcapsules 30 are arranged between one pixel electrode PE and the common electrode CE. However, the number of microcapsules 30 arranged between one pixel electrode PE and the common electrode CE may be less than that in the illustrated example.

[0028] The microcapsule 30 includes a dispersion medium 31, a plurality of black particles 32, a plurality of white particles 33, and an outer shell 34. The black particles 32 and the white particles 33 are sometimes called electrophoretic particles. The outer shell 34 is formed using a transparent resin such as an acrylic resin. The dispersion medium 31 is a liquid that disperses the black particles 32 and the white particles 33 in the microcapsule 30.

[0029] The black particles 32 are particles (polymer or colloid) made of a black pigment such as aniline black, and are positively charged in one example. The white particles 33 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, and are negatively charged in one example. Various additives can be added to these pigments as necessary. In place of the black particles 32 and the white particles 33, pigments such as red, green, blue, yellow, cyan, and magenta may be used.

[0030] In the display function layer DL having the above configuration, when the pixel PX is displayed in black, the pixel electrode PE is held at a relatively higher potential than the common electrode CE. That is, when the potential of the common electrode CE is taken as a reference potential, the pixel electrode PE is held at a positive polarity. As a result, the positively charged black particles 32 are attracted to the common electrode CE, while the negatively charged white particles 33 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed from the common electrode CE side, black is visually recognized. On the other hand, when the pixel PX is displayed in white, when the potential of the common electrode CE is taken as a reference potential, the pixel electrode PE is held at a negative polarity. As a result, the negatively charged white particles 33 are attracted to the common electrode CE side, while the positively charged black particles 32 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed, white is visually recognized.

[0031] 5 is a schematic plan view of the main elements arranged on the array substrate AR. In this figure, one pixel PX and its surrounding structure are shown. As described above, the scanning line G extends in the first direction X. The signal line S extends in the second direction Y and crosses the scanning line G.

[0032] The pixel electrode PE has a first pixel electrode PE1 and a second pixel electrode PE2 that are electrically connected to each other. In the example of Fig. 5, the second pixel electrode PE2 is disposed in an area surrounded by two scanning lines G and two signal lines S. Most of the first pixel electrode PE1 is also located in the area, but a part of it overlaps with the scanning line G below in the figure.

[0033] The switching element SW is disposed at a position where the scanning line G and the signal line S intersect. The switching element SW includes a semiconductor layer SC. A first electrode E1 and a second electrode E2 are in contact with the semiconductor layer SC. For example, the first electrode E1 may be called a source electrode, and the second electrode E2 may be called a drain electrode. In this embodiment, the first electrode E1 is a part of the signal line S. The second electrode E2 is spaced apart from the signal line S in the first direction X and extends in the second direction Y. A part of the second electrode E2 overlaps with the second pixel electrode PE2.

[0034] The semiconductor layer SC overlaps with the first gate electrode GE1 and the second gate electrode GE2. The first gate electrode GE1 and the second gate electrode GE2 configure the gate electrode GE1 shown in FIG. 3. The semiconductor layer SC is located between the first gate electrode GE1 and the second gate electrode GE2 in the third direction Z. In this embodiment, the first gate electrode GE1 is a part of the scanning line G.

[0035] A first relay electrode RE1 is disposed in the vicinity of the second gate electrode GE2. The first relay electrode RE1 is connected to the scanning line G through a contact hole CH1. The second gate electrode GE2 is connected to the first relay electrode RE1 through a contact hole CH2.

[0036] A capacitance electrode OE is disposed in the pixel PX. The capacitance electrode OE overlaps with the first pixel electrode PE1 and the second pixel electrode PE2. In this embodiment, the entire capacitance electrode OE is located inside the outline of the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view.

[0037] The capacitance electrodes OE arranged in the pixels PX adjacent to each other in the second direction Y are connected by a connection wiring NW. The connection wiring NW extends elongatedly in the second direction Y and intersects with the scanning lines G. A plurality of connection wirings NW and a plurality of capacitance electrodes OE arranged in the second direction Y form the capacitance wiring CW shown in FIG.

[0038] The second electrode E2 is connected to the second pixel electrode PE2 through a contact hole CH3. A second relay electrode RE2 is disposed between the second electrode E2 and the first pixel electrode PE1 in the third direction Z. The second relay electrode RE2 is connected to the second electrode E2 through a contact hole CH4. The second relay electrode RE2 is connected to the first pixel electrode PE1 through a contact hole CH5. In this manner, the second electrode E2, the second relay electrode RE2, the first pixel electrode PE1, and the second pixel electrode PE2 are electrically connected.

[0039] The scanning line G and the second pixel electrode PE2 are formed in the same layer using the same material. The signal line S, the second electrode E2, the first relay electrode RE1, and the capacitance electrode OE are formed in the same layer using the same material. The second gate electrode GE2, the second relay electrode RE2, and the connection wiring NW are formed in the same layer using the same material.

[0040] For example, the scanning line G, the second pixel electrode PE2, the signal line S, the second electrode E2, the first relay electrode RE1, the second relay electrode RE2, the capacitance electrode OE, the connection wiring NW, and the second gate electrode GE2 are formed of a metal material such as Al (aluminum), Ti (titanium), Ag (silver), Mo (molybdenum), W (tungsten), Cu (copper), Cr (chromium), or an alloy combining these metal materials, etc. These elements such as the scanning line G may have a single-layer structure of a metal material or an alloy, or may have a multi-layer structure.

[0041] The first pixel electrode PE1 is composed of, for example, a transparent conductive layer or a light reflective layer, or a laminate of a transparent conductive layer and a light reflective layer. The transparent conductive layer, like the common electrode CE, can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0042] Fig. 6 is a schematic plan view showing an enlarged view of the switching element SW in Fig. 5. Fig. 7 is a schematic plan view of the semiconductor layer SC and the scanning line G. In Fig. 6, the second gate electrode GE2 is indicated by a chain line.

[0043] 6 and 7, the semiconductor layer SC has a rectangular shape having a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 and the second side S2 are long sides parallel to the second direction Y, and the third side S3 and the fourth side S4 are short sides parallel to the first direction X. However, the shape of the semiconductor layer SC is not limited to a rectangular shape.

[0044] In this embodiment, the semiconductor layer SC has an opening AP at its center. The opening AP is located between the signal line S (first electrode E1) and the second electrode E2 in the first direction X. In the examples of Fig. 6 and Fig. 7, the opening AP has a rectangular shape that is elongated in the first direction X. However, the opening AP may have a circular or elliptical shape.

[0045] The scanning line G (first gate electrode GE1) has a protrusion PT protruding toward the third side S3 at a position overlapping with the semiconductor layer SC. In the example of FIG. 6, the protrusion PT protrudes upward beyond the third side S3 in the figure. By providing such a protrusion PT, most of the semiconductor layer SC overlaps with the scanning line G. The opening AP also overlaps with the scanning line G.

[0046] However, the scanning line G (first gate electrode GE1) may have a structure in which the opening AP does not overlap the scanning line G (first gate electrode GE1) as long as it overlaps with the semiconductor layer SC, particularly with the channel region (first channel region CR1 and second channel region CR2 described later). In the case of a structure in which the opening AP does not overlap with the scanning line G (first gate electrode GE1), for example, the scanning line G (first gate electrode GE1) may have an opening that overlaps with the opening AP.

[0047] The second gate electrode GE2 has a widened portion WP at a position overlapping with the semiconductor layer SC. The widened portion WP is rectangular, for example, as shown in FIG. 6, and overlaps with most of the semiconductor layer SC. In the example of FIG. 6, the widened portion WP protrudes upward from the third side S3 in the figure. Furthermore, the widened portion WP protrudes downward from the fourth side S4 in the figure. The opening AP also overlaps with the widened portion WP.

[0048] However, the widened portion WP may have a structure in which the opening AP and the widened portion WP do not overlap as long as they overlap the semiconductor layer SC, particularly the channel region (first channel region CR1 and second channel region CR2 described later). In the case where the opening AP and the widened portion WP do not overlap, for example, the widened portion WP may have an opening that overlaps with the opening AP.

[0049] As described above, the first gate electrode GE1 and the second gate electrode GE2 only need to overlap the channel region (the first channel region CR1 and the second channel region CR2 described later) of the semiconductor layer SC, and either or both of the first gate electrode GE1 and the second gate electrode GE2 may have a structure having an opening in a region overlapping with the opening AP of the semiconductor layer SC.

[0050] The advantage of the structure in which the first gate electrode GE1 and the second gate electrode GE2 overlap the opening AP of the semiconductor layer SC is that it is possible to suppress light leakage and shifts in the threshold voltage Vth caused by light from an external light source entering the semiconductor layer SC, thereby further improving the display quality.

[0051] On the other hand, the advantage of the structure in which the first gate electrode GE1 and the second gate electrode GE2 do not overlap the aperture AP of the semiconductor SC is that the parasitic capacitance of the transistors Tr1 and Tr2 can be reduced, the panel size can be increased, the frame rate can be increased, and power consumption can be reduced. Furthermore, when the structure according to this embodiment is applied to the above-mentioned transparent display, the transparency of the transparent display can be further improved by providing an aperture in the region where the first gate electrode GE1 and the second gate electrode GE2 overlap the aperture AP of the semiconductor layer SC.

[0052] Whether or not an opening is provided in at least one or both of the first gate electrode GE1 and the second gate electrode GE2 in a region overlapping with the opening AP of the semiconductor layer SC may be determined depending on the specifications of the display device.

[0053] 7 shows the shapes of a first opening EAP1 and a second opening EAP2 of an insulating layer 12 described later. The first opening EAP1 and the second opening EAP2 both have a shape that is elongated in the second direction Y. The first opening EAP1 overlaps with an end of the semiconductor layer SC that includes the first side S1. The second opening EAP2 overlaps with an end of the semiconductor layer SC that includes the second side S2. The opening AP is located between the first opening EAP1 and the second opening EAP2 in the first direction X.

[0054] The semiconductor layer SC has a first region R1 (source region) in contact with the signal line S, and a second region R2 (drain region) in contact with the second electrode E2. In Fig. 7, the first region R1 and the second region R2 are indicated by hatched patterns. For example, the first region R1 and the second region R2 have an elongated shape extending between the third side S3 and the fourth side S4.

[0055] The semiconductor layer SC further has a first channel region CR1 and a second channel region CR2 aligned in the second direction Y. The first channel region CR1 is located between the first region R1 and the second region R2 in the first direction X, and is located between the opening AP and the third side S3 in the second direction Y. The second channel region CR2 is located between the first region R1 and the second region R2 in the first direction X, and is located between the opening AP and the fourth side S4 in the second direction Y. Both the first channel region CR1 and the second channel region CR2 entirely overlap with the scanning line G and the second gate electrode GE2.

[0056] The first channel region CR1, together with the scanning line G, the second gate electrode GE2, the signal line S, and a part of the second electrode E2, constitutes a first transistor Tr1. The second channel region CR2, together with the scanning line G, the second gate electrode GE2, the signal line S, and another part of the second electrode E2, constitutes a second transistor Tr2.

[0057] The first channel region CR1 has a first channel width W1 in the second direction Y. The second channel region CR2 has a second channel width W2 in the second direction Y. The first channel width W1 and the second channel width W2 are, for example, the same.

[0058] In the first direction X, the opening AP is located between the first region R1 and the second region R2. In the second direction Y, the opening AP is located between the first channel region CR1 and the second channel region CR2.

[0059] The opening AP has a width Wx in the first direction X. In the example of Fig. 7, the width Wx is greater than a distance D1 in the first direction X between the opening AP and the first region R1 (Wx>D1). The width Wx is also greater than a distance D2 in the first direction X between the opening AP and the second region R2 (Wx>D2). The distances D1 and D2 are, for example, the same.

[0060] The opening AP has a width Wy in the second direction Y. In the example of FIG. 7, the width Wy is sufficiently smaller than the first channel width W1 and the second channel width W2 (Wy <W1,W2)。

[0061] Fig. 8 is a schematic cross-sectional view of the array substrate AR taken along line VIII-VIII in Fig. 7. Fig. 9 is a schematic cross-sectional view of the array substrate AR taken along line IX-IX in Fig. 7. The array substrate AR includes insulating layers 11, 12, 13, and 14 in addition to the above-mentioned first base material 1 and the elements shown in Figs. 5 to 7. In this embodiment, the insulating layer 13 is an example of a first insulating layer, and the insulating layer 12 is an example of a second insulating layer.

[0062] The scanning lines G are disposed on the first base material 1. The insulating layer 11 covers the scanning lines G. The semiconductor layer SC is disposed on the insulating layer 11. The insulating layer 12 covers the semiconductor layer SC and the insulating layer 11.

[0063] The signal line S and the second electrode E2 are disposed on the insulating layer 12. The insulating layer 12 has the above-mentioned first opening EAP1 and second opening EAP2. The signal line S is in contact with the first region R1 of the semiconductor layer SC through the first opening EAP1. The second electrode E2 is in contact with the second region R2 of the semiconductor layer SC through the second opening EAP2.

[0064] The insulating layer 13 covers the signal line S, the second electrode E2, and the insulating layer 12. The second gate electrode GE2 is disposed on the insulating layer 13. The insulating layer 14 covers the second gate electrode GE2 and the insulating layer 13.

[0065] The first pixel electrode PE1 is disposed on the insulating layer 14. The first pixel electrode PE1 overlaps with the aperture AP in the third direction Z. Note that the first pixel electrode PE1 shown in FIG. 8 is not included in the pixel PX including the semiconductor layer SC shown in FIG. 8, but is included in the adjacent pixel PX (see FIG. 5). Although layers above the first pixel electrode PE1 are not shown in FIG. 8, the first pixel electrode PE1 may be covered with an insulating layer.

[0066] The insulating layers 11, 12, and 13 are formed of an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). The insulating layers 11, 12, and 13 may each have a single-layer structure or a multilayer structure. The insulating layer 14 is formed of an organic insulating material such as an acrylic resin. The insulating layer 14 serves as a planarizing layer that planarizes unevenness caused by the switching elements SW and the like.

[0067] It should be noted that the contact holes CH1 and CH3 shown in FIG. 5 are provided in the insulating layers 11 and 12, the contact holes CH2 and CH4 are provided in the insulating layer 13, and the contact hole CH5 is provided in the insulating layer .

[0068] The insulating layer 12 is formed in a region excluding the first opening EAP1 and the second opening EAP2. That is, the insulating layer 12 covers the first channel region CR1 and the second channel region CR2 shown in FIG. 7. In the example of FIG. 8, the insulating layer 12 overlaps with the opening AP of the semiconductor layer SC in the third direction Z. Specifically, the insulating layer 12 fills the inside of the opening AP. Since the cross section of FIG. 9 corresponds to the first opening EAP1, the cross section does not include the insulating layer 12. The cross-sectional structure of the array substrate AR in the second region R2 is similar to the cross-sectional structure in the first region R1 shown in FIG. 9.

[0069] When forming the semiconductor layer SC, the signal line S, and the second electrode E2, the semiconductor layer SC is first formed on the insulating layer 11, and a conductive layer that will be the base of the signal line S and the second electrode E2 is formed above it. After that, the conductive layer is patterned by, for example, dry etching, and the signal line S and the second electrode E2 having a predetermined shape are formed.

[0070] The insulating layer 12 plays a role in protecting the channel regions CR1 and CR2 of the semiconductor layer SC during this patterning. In other words, if the insulating layer 12 does not exist, the channel regions CR1 and CR2 may be damaged by etching during the formation of the signal line S and the second electrode E2, which may adversely affect the characteristics of the transistors Tr1 and Tr2. In contrast, if the insulating layer 12 having the first opening EAP1 and the second opening EAP2 is formed on the semiconductor layer SC as in this embodiment, and the signal line S and the second electrode E2 are in contact with the semiconductor layer SC through these openings EAP1 and EAP2, the insulating layer 12 can protect the channel regions CR1 and CR2 from the above-mentioned etching.

[0071] The thicknesses of the elements shown in Figures 8 and 9 are not particularly limited, but as an example, the first substrate 1 has a thickness of 0.5 mm, the scanning line G has a thickness of 400 nm, the insulating layer 11 has a thickness of 500 nm, the semiconductor layer SC has a thickness of 70 nm, the signal line S and the second electrode E2 have a thickness of 600 nm, the insulating layer 13 has a thickness of 300 nm, the second gate electrode GE2 has a thickness of 150 nm, the insulating layer 14 has a thickness of 3000 nm, and the first pixel electrode PE1 has a thickness of 50 nm.

[0072] Next, an example of the effect achieved by this embodiment will be described. 10 is a schematic plan view of a switching element SWex according to a comparative example. This switching element SWex includes two semiconductor layers SC1 and SC2 arranged side by side in the second direction Y. A gap GP is formed between the semiconductor layers SC1 and SC2. The semiconductor layer SC1 constitutes a first transistor Tr1, and the semiconductor layer SC2 constitutes a second transistor Tr2.

[0073] Fig. 11 is a schematic cross-sectional view of an array substrate ARex according to a comparative example taken along line XI-XI in Fig. 10. In this comparative example, since a gap GP exists between the semiconductor layers SC1 and SC2, the signal line S (first electrode E1), the insulating layer 13, and the second gate electrode GE2 are recessed according to the shape of the gap GP.

[0074] When such a depression occurs, the thickness of the insulating layer 13 is not constant. That is, the thickness t2 of the insulating layer 13 located above the ends (tapered portions) of the semiconductor layers SC1 and SC2 may be reduced compared to the thickness t1 of the insulating layer 13 located above the flat surfaces of the semiconductor layers SC1 and SC2 (t1>t2). In particular, the insulating layer 13 and the like are deformed in a complex manner above the gap GP, so that a difference between the thicknesses t1 and t2 is likely to occur.

[0075] In the portion where the thickness of the insulating layer 13 is reduced, the dielectric strength voltage between the signal line S and the second gate electrode GE2 becomes lower than in other portions, so there is a risk of dielectric breakdown. If dielectric breakdown occurs, the signal line S and the second gate electrode GE2 will be conductive, resulting in a display defect. The risk of dielectric breakdown also occurs between the second electrode E2 and the second gate electrode GE2.

[0076] In contrast, in this embodiment, as shown in FIG. 9, the semiconductor layer SC does not have a structure corresponding to the gap GP below the signal line S and the second gate electrode GE2. Similarly, the semiconductor layer SC does not have a structure corresponding to the gap GP below the second electrode E2 and the second gate electrode GE2. That is, the semiconductor layer SC has a shape in which both ends in the first direction X of the semiconductor layers SC1 and SC2 shown in FIG. 10 are connected. With this configuration, thin portions are unlikely to occur in the insulating layer 13 between the signal line S and the second gate electrode GE2 and between the second electrode E2 and the second gate electrode GE2. As a result, the risk of dielectric breakdown can be reduced, and the reliability of the array substrate AR and the display device DSP can be improved.

[0077] The opening AP is located between the first region R1 and the second region R2 as shown in Fig. 7. More specifically, the opening AP is located between the signal line S and the second electrode E2 as shown in Fig. 6. In this configuration, the signal line S and the second electrode E2 are not present in the portion where the opening AP creates a step in the insulating layer 13. Therefore, it is possible to suppress the occurrence of dielectric breakdown of the insulating layer 13 due to the opening AP.

[0078] If the opening AP is not provided in the semiconductor layer SC, one transistor with a large channel width is formed. In this case, a large current is likely to flow through the semiconductor layer SC. If the current becomes too large, the semiconductor layer SC may be destroyed. In contrast, if the opening AP is provided in the semiconductor layer SC as in this embodiment, two channel regions CR1 and CR2 with small channel widths are formed in the semiconductor layer SC. With this configuration, a large current is unlikely to flow through the semiconductor layer SC, and as a result, destruction of the semiconductor layer SC can be suppressed. Also, from the viewpoint of promoting heat dissipation of the semiconductor layer SC, it is preferable to form two channel regions CR1 and CR2 with small channel widths in the semiconductor layer SC, compared to the case of using one transistor with a large channel width. In addition to the above, various other advantageous effects can be obtained from this embodiment.

[0079] [Second embodiment] A description will now be given of the second embodiment. In this embodiment, the configurations of the array substrate AR and the display device DSP, which are not particularly mentioned, are the same as those in the first embodiment.

[0080] 12 is a schematic plan view of a switching element SW according to the second embodiment. In the example of this figure, the semiconductor layer SC has two openings AP (AP1, AP2). These openings AP1, AP2 have, for example, the same shape and are arranged at an interval in the second direction Y.

[0081] 12, the switching element SW includes a first transistor Tr1 including a first channel region CR1 between the third side S3 and an opening AP1, a second transistor Tr2 including a second channel region CR2 between the openings AP1 and AP2, and a third transistor Tr3 including a third channel region CR3 between the opening AP2 and a fourth side S4. These transistors Tr1, Tr2, and Tr3 are connected in parallel.

[0082] The number of openings AP in the semiconductor layer SC is not limited to two, and may be three or more. Even in the case where the semiconductor layer SC has a plurality of openings AP as in this embodiment, the same effects as those in the first embodiment can be obtained.

[0083] All display devices and array substrates that can be implemented by those skilled in the art by making appropriate design modifications based on the display device and array substrate described above as embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.

[0084] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0085] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0086] DSP...display device, AR...array substrate, CT...counter substrate, DL...display function layer, SW...switching element, Tr1...first transistor, Tr2...second transistor, SC...semiconductor layer, AP...opening, G...scanning line, S...signal line, E1...first electrode, E2...second electrode, GE1...first gate electrode, GE2...second gate electrode, R1...first region, R2...second region, CR1...first channel region, CR2...second channel region.

Claims

1. A semiconductor layer; a first electrode in contact with the semiconductor layer; a second electrode spaced apart from the first electrode and in contact with the semiconductor layer; a first insulating layer covering the first electrode and the second electrode; a gate electrode disposed above the first insulating layer and facing the semiconductor layer; a second insulating layer disposed below the first insulating layer and covering the semiconductor layer; Equipped with the semiconductor layer has an opening located between the first electrode and the second electrode in a plan view; the second insulating layer has a first opening and a second opening overlapping the semiconductor layer; the first electrode contacts the semiconductor layer through the first opening; The second electrode is in contact with the semiconductor layer through the second opening. Array board.

2. a scanning line located below the semiconductor layer and connected to the gate electrode; The semiconductor layer overlaps the gate electrode and the scanning line. The array substrate according to claim 1 .

3. The gate electrode overlaps the opening.

3. The array substrate according to claim 1.

4. The first electrode and the second electrode are aligned in a first direction, The semiconductor layer is a first region in contact with the first electrode; a second region in contact with the second electrode; a first channel region and a second channel region located between the first region and the second region in the first direction and aligned in a second direction intersecting the first direction; having the opening is located between the first channel region and the second channel region in the second direction.

4. The array substrate according to claim 1.

5. a width of the opening in the first direction is greater than a distance in the first direction between the opening and the first region; 5. The array substrate according to claim 4.

6. a width of the opening in the first direction is greater than a distance in the first direction between the opening and the second region; 6. The array substrate according to claim 4.

7. The semiconductor layer has a plurality of the openings aligned in the second direction.

7. The array substrate according to claim 4, wherein the first and second electrodes are electrically connected to each other.

8. The opening in the semiconductor layer overlaps the second insulating layer. The array substrate according to claim 1 .

9. A semiconductor layer, a first electrode in contact with the semiconductor layer; a second electrode spaced apart from the first electrode and in contact with the semiconductor layer; a first insulating layer covering the first electrode and the second electrode; a gate electrode disposed above the first insulating layer and facing the semiconductor layer; a scanning line disposed below the semiconductor layer, connected to the gate electrode, and extending in a first direction; Equipped with the first electrode and the second electrode are aligned in the first direction, the semiconductor layer has first and second sides parallel to a second direction intersecting the first direction, third and fourth sides parallel to the first direction, and an opening located between the first electrode and the second electrode in a plan view; the scanning line has a protrusion protruding toward the third side at a position overlapping the semiconductor layer; Array board.

10. The gate electrode has a widened portion overlapping the semiconductor layer, The widened portion overlaps the opening, the third side, and the fourth side. The array substrate according to claim 9 .

11. An array substrate according to any one of claims 1 to 10; an opposing substrate opposed to the array substrate; a display function layer disposed between the array substrate and the counter substrate; A display device comprising:

12. the array substrate includes a pixel electrode connected to the second electrode; The opposing substrate includes a common electrode facing the pixel electrodes. The display device according to claim 11.

13. The display function layer is an electrophoretic layer. The display device according to claim 11 or 12.

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