Information transmission and reception method and device

Abstract

To provide information transmission / reception method and device that effectively indicate a time and a frequency domain resource location of a control resource set without affecting the combined reception of a physical broadcast channel (PBCH).SOLUTION: A transmission method includes conveying configuration information of a control resource set on a physical broadcast channel (S102). At least one of time domain location information and frequency domain location information of the control resource set is indicated to a terminal using the configuration information. The transmission method further includes transmitting the control resource set to the terminal according to the configuration information (S104).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from Chinese Patent Application No. 201711148126.3, filed on November 17, 2017, the entire contents of which are incorporated herein by reference.

[0002] Technical Field The present application relates to the field of communications, for example, methods and apparatus for transmitting and receiving information. [Background technology]

[0003] background In the new generation wireless communication system (New Radio: NR), system information is a minimum system The minimum system information is classified into "master system information (minimum SI)" and other system information (other SI). The minimum system information is classified into "master information block (MIB)" carried on the physical broadcast channel (PBCH) and "remaining minimum system information (remaining minimum SI)" carried on the physical downlink shared channel. The master system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the transmission configuration of an initial access request and the message reception configuration of an initial access response. The other system information that needs to be broadcast is called other system information.

[0004] RMSI is the Physical Downlink Control Channel (PD The RMSI scheduling information is scheduled by the PBCH (Primary Control Channel) and carried on the Physical Downlink Shared Channel (PDSCH). The time and frequency domain location of the common control-resource set (CORESET) where the RMSI scheduling information resides may be indicated in the PBCH.

[0005] In an NR system, the PBCH is carried and transmitted in a synchronization signal (SS) / physical broadcast channel block (PBCH block), one synchronization period includes multiple SS / PBCH blocks, and different SS / PBCH blocks may transmit synchronization broadcast signals of the same or different beam directions or ports together to achieve complete coverage of the expected area. Because the PBCHs of different beam directions and ports require combined reception, it is necessary to ensure that the information content is the same when considering inserting indication information into the PBCH.

[0006] In order to ensure flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI common control resource sets may be different, and there is no effective solution in the related art for how to effectively indicate the time domain positions of the RMSI common control resource sets without affecting the combined reception of the PBCH. Summary of the Invention [Problem to be solved by the invention]

[0007] overview The embodiments of the present application provide an information transmission and reception method and apparatus to at least solve the technical problem in the related art of being unable to effectively indicate the time and frequency domain resource locations of a control resource set without affecting the combined reception of the PBCH.

[0008] According to one embodiment of the present application, there is provided an information transmission method, the method including: conveying configuration information of a control resource set on a physical broadcast channel, wherein at least one of time domain location information and frequency domain location information of the control resource set is indicated to a terminal using the configuration information; and the method further includes transmitting the control resource set to the terminal according to the configuration information.

[0009] According to an embodiment of the present application, another information reception method is provided, the method including: receiving configuration information of a control resource set, the configuration information of the control resource set being carried on a physical broadcast channel, and using the configuration information to indicate at least one of time domain location information and frequency domain location information of the control resource set, and the method further includes receiving the control resource set according to the configuration information.

[0010] According to another embodiment of the present application, an information transmission device is provided, the device including: a configuration module configured to convey configuration information of a control resource set on a physical broadcast channel, and using the configuration information, at least one of time domain location information and frequency domain location information of the control resource set is indicated to a terminal, and the device further includes a transmission module configured to transmit the control resource set according to the configuration information.

[0011] According to another embodiment of the present application, another information receiving apparatus is provided, the apparatus including: a first receiving module configured to receive configuration information of a control resource set, the configuration information of the control resource set being carried on a physical broadcast channel, and using the configuration information, at least one of time domain location information and frequency domain location information of the control resource set is indicated, and the apparatus further includes a second receiving module configured to receive the control resource set according to the configuration information.

[0012] According to a further embodiment of the present application, there is further provided a storage medium, the storage medium including a program stored thereon, the program being operable, when run, to perform any of the methods described above.

[0013] According to a further embodiment of the present application there is further provided a processor, the processor being configured to run a program which, when run, performs any of the methods described above.

[0014] The drawings described in this specification are used to provide a further understanding of the present application and form a part of the present application, and the exemplary embodiments and the description thereof are used to explain the present application and are not intended to limit the present application. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a flowchart of an information transmission method according to an embodiment of the present application. [Diagram 2] FIG. 2 is a flowchart of an information receiving method according to an embodiment of the present application. [Diagram 3] FIG. 2 is a structural block diagram of an information transmission device according to an embodiment of the present application; [Figure 4] FIG. 2 is a structural block diagram of an information receiving device according to an embodiment of the present application; [Diagram 5] FIG. 2 is a schematic diagram of a synchronization signal block according to the present embodiment. [Figure 6] 1 is a schematic diagram I in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block; [Figure 7] Schematic diagram II in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. [Figure 8] Schematic diagram III in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. [Figure 9] 4 is a schematic diagram IV in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. [Figure 10]Schematic diagram V in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. [Figure 11] 6 is a schematic diagram VI in which the frequency domain location according to the embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. [Figure 12] 1 is a schematic structural diagram in which a CORESET according to this embodiment is transmitted only in slots in which an SSB exists. [Figure 13] FIG. 2 is a schematic diagram of the use of multiple synchronization signal block transmission periods according to the present embodiment. [Figure 14] 1 is a schematic diagram of a current mapping pattern of synchronization signal blocks (SSBs) to slots in accordance with an embodiment of the present invention. [Figure 15] FIG. 13 is a schematic diagram I of positional information of symbols occupied by a CORESET in a slot according to the present embodiment. [Figure 16] FIG. 2 is a schematic diagram II showing positional information of symbols occupied by a CORESET in a slot according to the present embodiment. [Figure 17] 1 is a schematic diagram I showing the CORESET of this embodiment being mapped to slots outside of SSB. [Figure 18] Schematic diagram II showing the CORESET of this embodiment being mapped to slots outside of SSB. [Figure 19] 1 is a schematic diagram showing a CORESET according to the present embodiment being transmitted in a slot including a synchronization signal block. [Figure 20] 1 is a schematic diagram showing a CORESET according to the present embodiment being transmitted in a slot not including a synchronization signal block. [Figure 21] 11 is a schematic diagram showing a CORESET according to the present embodiment being transmitted in a slot including a synchronization signal block and in a slot not including a synchronization signal block. FIG. [Figure 22] 1 is a schematic diagram showing a CORESET according to the present embodiment being transmitted in a slot in which a synchronization signal block exists; [Figure 23]FIG. 13 is a schematic diagram I showing a case in which a CORESET according to this embodiment is transmitted in a slot that does not include a synchronization signal block. [Figure 24] FIG. 2 is a schematic diagram II showing a case in which a CORESET according to this embodiment is transmitted in a slot that does not include a synchronization signal block. [Diagram 25] FIG. 13 is a schematic diagram showing an embodiment in which all synchronization signal blocks correspond to the same CORESET monitoring window; [Figure 26] 1 is a schematic diagram showing a plurality of synchronization signal blocks corresponding to one CORESET monitoring window according to the present embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Description of the embodiments The present application will be described in detail below with reference to the drawings together with the embodiments. Note that the embodiments and features in the embodiments of the present application can be combined with each other to the extent that no contradiction occurs. Note that the terms "first", "second" and the like in the specification, claims and accompanying drawings of the present application are intended to distinguish between similar items and do not necessarily indicate a specific order or sequence.

[0017] EMBODIMENT 1 In an embodiment of the present application, a viable network architecture includes a base station and a terminal, and information is exchanged between the base station and the terminal.

[0018] An information transmission method applied to the above network architecture is provided in this embodiment. 1 is a flow chart of an information transmission method according to an embodiment of the present application, and as shown in FIG 1, the flow includes steps S102 and S104. In step S102, configuration information of a control resource set is carried on a physical broadcast channel.

[0019] Using the configuration information, at least one of time domain location information and frequency domain location information of the control resource set is indicated to the terminal.

[0020] In step S104, the control resource set is sent to the terminal according to the configuration information.

[0021] Through the above steps, by carrying the configuration information of the control resource set on the physical broadcast channel and transmitting the control resource set to the terminal according to the configuration information, the technical problem in the related art that the time and frequency domain resource location of the control resource set cannot be effectively indicated without affecting the combined reception of the PBCH is solved, and the flexibility of data transmission is improved.

[0022] In one embodiment, the execution body of the above steps may be, but is not limited to, a network side such as a base station.

[0023] In one embodiment, the configuration information of the control resource set includes bandwidth information of the control resource set.

[0024] In one embodiment, the bandwidth information includes at least one of a minimum channel bandwidth and a minimum terminal bandwidth.

[0025] In one embodiment, the configuration information of the control resource set includes frequency domain location information of the control resource set, where the frequency domain location information is indicated by a frequency offset between the control resource set and the synchronization signal block.

[0026] In one embodiment, the frequency domain location information of the control resource set is: M×SC SSB The center frequency of the control resource set and the center frequency of the synchronization signal block are The offset between the number (B.W. CORESET -B.W. SSB ) / 2-M×SC SSB The center frequency of the control resource set is the offset between the number and the center frequency of the synchronization signal block; (B.W. CORESET -B.W. SSB ) / 2-(12×SCCORESET -M×SC SSB ) the offset between the center frequency of the control resource set and the center frequency of the synchronization signal block, (B.W. CORESET +BW SSB ) / 2+M×SC SSB The center frequency of the control resource set is the offset between the number and the center frequency of the synchronization signal block, and (B.W. CORESET +BW SSB ) / 2+(12×SC CORESET +M×SC SSB ) the offset between the center frequency of the control resource set and the center frequency of the synchronization signal block where M is the number of synchronization signal block subcarriers in the frequency domain offset between the synchronization signal block and the carrier physical resource block grid (PRB grid), M is an integer, and SC CORESET is the frequency of the control resource set subcarrier The number of regions is wide, and SC SSB is the frequency domain width of the synchronization signal block subcarrier, BW CORESET is the control resource set bandwidth, BW SSB is the sync block bandwidth.

[0027] In one embodiment, the configuration information of the control resource set includes time domain location information of the control resource set, which includes the following information: information of the slot in which the control resource set exists, and location information of the symbol occupied by the control resource set in the slot. The information contained herein includes at least one of the following:

[0028] In one embodiment, the location information of the symbols occupied by the control resource set in the slot includes: a starting symbol index of the symbols occupied by the control resource set in the slot and a number of symbols occupied by the control resource set in the slot.

[0029] In one embodiment, the information of the slot in which the control resource set exists is: The control resource set is transmitted in a slot including a synchronization signal block; The control resource set is transmitted in a slot that does not contain a synchronization signal block; and The control resource set is transmitted in a slot including a synchronization signal block and in a slot not including a synchronization signal block. Includes one of the following.

[0030] In one embodiment, the configuration information of the control resource set is further used to indicate whether the control resource set is transmitted in a slot that includes a synchronization signal block or whether the control resource set is transmitted in a slot that does not include a synchronization signal block.

[0031] In one embodiment, when a control resource set is transmitted in a slot that includes a synchronization signal block and in a slot that does not include a synchronization signal block, the same resource mapping rule is adopted for the control resource set in the slot that includes the synchronization signal block and in the slot that does not include the synchronization signal block.

[0032] In one embodiment, the configuration information of the control resource set includes monitoring window configuration information of the control resource set, where the monitoring window configuration information of the control resource set includes at least one of the following information: a monitoring period of the control resource set, a time domain duration of the monitoring window, a time domain offset between adjacent monitoring windows, and a starting position of the monitoring window, and the monitoring window of the control resource set includes at least one monitoring opportunity of the control resource set.

[0033] In one embodiment, the monitoring window of a control resource set corresponds to a synchronization signal block.

[0034] In one embodiment, the time domain duration of a monitoring window for a control resource set is one slot or more.

[0035] In one embodiment, the time domain offset between adjacent monitoring windows comprises at least one of 0, the time domain duration of the monitoring window, and 1 / X of the time domain duration of the monitoring window, where X is an integer greater than 1, and the value of X is predefined by a predetermined protocol or indicated by signaling.

[0036] In one embodiment, if the time domain duration of a monitoring window of a control resource set is 1 slot, then the time domain offset between adjacent monitoring windows is the time domain duration of the monitoring window or 1 / X of the time domain duration of the monitoring window, and if the time domain duration of a monitoring window of a control resource set is longer than 1 slot, then the time domain offset between adjacent monitoring windows is 0 or 1 / X of the time domain duration of the monitoring window.

[0037] In one embodiment, the starting position of the monitoring window is indicated by a time domain offset between the starting position of the monitoring window and the starting slot of the synchronization signal block, or the starting position of the monitoring window is fixedly configured.

[0038] In one embodiment, the control resource set is one of a common control resource set for the remaining minimum system information RMSI and a common control resource set for the paging information.

[0039] An information receiving method applied to the above network architecture is provided in this embodiment. Figure 2 is a flow chart of the information receiving method according to an embodiment of the present application, as shown in Figure 2, the flow includes the following steps: step S202 and step S204.

[0040] In step S202, configuration information of a control resource set is received. Configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information indicates at least one of time domain location information and frequency domain location information of the control resource set.

[0041] In step S204, a control resource set is received according to the configuration information. In one embodiment, the configuration information of the control resource set includes bandwidth information of the control resource set.

[0042] In one embodiment, the configuration information of the control resource set includes frequency domain location information of the control resource set, where the frequency domain location information is indicated by a frequency offset between the control resource set and the synchronization signal block.

[0043] In one embodiment, the frequency domain location information of the control resource set is: M×SC SSB The center frequency of the control resource set and the center frequency of the synchronization signal block are The offset between the number (B.W. CORESET -B.W. SSB ) / 2-M×SC SSB The center frequency of the control resource set is the offset between the number and the center frequency of the synchronization signal block; (B.W. CORESET -B.W. SSB ) / 2-(12×SC CORESET -M×SC SSB ) the offset between the center frequency of the control resource set and the center frequency of the synchronization signal block, (B.W. CORESET +BW SSB ) / 2+M×SC SSB The center frequency of the control resource set is the offset between the number and the center frequency of the synchronization signal block, and (B.W. CORESET +BW SSB ) / 2+(12×SC CORESET +M×SC SSB) the offset between the center frequency of the control resource set and the center frequency of the synchronization signal block where M is the number of synchronization signal block subcarriers in the frequency domain offset between the synchronization signal block and the carrier physical resource block grid (PRB grid), M is an integer, and SC CORESET is the frequency of the control resource set subcarrier The number of regions is wide, and SC SSB is the frequency domain width of the synchronization signal block subcarrier, BW CORESET is the control resource set bandwidth, BW SSB is the sync block bandwidth.

[0044] In one embodiment, the configuration information of the control resource set includes time domain location information of the control resource set, and the time domain location information includes at least one of the following information: information of the slot in which the control resource set exists, and location information of the symbol occupied by the control resource set within the slot.

[0045] In one embodiment, the configuration information of the control resource set includes monitoring window configuration information of the control resource set, and the monitoring window configuration information of the control resource set includes: The monitoring window includes at least one of the following information: a monitoring period for the control resource set, a time domain duration of the monitoring window, a time domain offset between adjacent monitoring windows, and a starting position of the monitoring window, and the monitoring window for the control resource set includes at least one monitoring opportunity for the control resource set.

[0046] From the above description of the implementation, a person skilled in the art can clearly understand that the present application can be realized by software together with the necessary general-purpose hardware according to the method of the above embodiment, and can certainly be achieved by hardware alone, but the former is preferred. Based on such understanding, the technical solution of the present application substantially, or a part of the present application that contributes to the prior art, may be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and the storage medium includes a number of instructions that enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the method according to the embodiment of the present application.

[0047] EMBODIMENT 2 In this embodiment, an information transmitting and receiving device is further provided, which is configured to realize the above-mentioned embodiment and preferred implementation, and what has already been described will not be repeated. The term "module" used below may realize at least one of software and hardware for a predetermined function. The device described in the following embodiment is preferably realized by software, but it is also possible and expected to be realized by hardware or a combination of software and hardware.

[0048] FIG. 3 is a structural block diagram of an information transmitting device according to an embodiment of the present application, which can be applied to a network element on the network side, such as a base station. As shown in FIG. 3, the device includes: a configuration module 30 and a transmitting module 32.

[0049] The configuration module 30 is configured to convey configuration information of the control resource sets on the physical broadcast channel, where at least one of time domain location information and frequency domain location information of the control resource sets is indicated to the terminals by means of the configuration information.

[0050] The transmitting module 32 is configured to transmit the control resource set according to the configuration information.

[0051] FIG. 4 is a structural block diagram of an information receiving device according to an embodiment of the present application, which can be applied to a terminal, and as shown in FIG. 4, the device includes a first receiving module 40 and a second receiving module 42.

[0052] The first receiving module 40 is configured to receive configuration information of the control resource set, where the configuration information of the control resource set is carried on a physical broadcast channel, and the configuration information is used to indicate at least one of time domain location information and frequency domain location information of the control resource set.

[0053] The second receiving module 42 is configured to receive the control resource set according to the configuration information.

[0054] It should be noted that each of the above modules may be implemented by software or hardware, the latter of which may be implemented in the following manner, but is not limited thereto, and that the above modules may be present in the same processor, or each of the above modules may be present in different processors in any combination. Each exists in a processor.

[0055] EMBODIMENT 3 In order to ensure the flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI common control resource sets may be different, and how to effectively indicate the time domain positions of the RMSI common control resource sets without affecting the combined reception of the PBCH is an issue that must be considered and solved.

[0056] In the new generation wireless communication system NR, system information is classified into minimum system information (minimum SI) and other system information (other SI). The minimum system information is further classified into "master system information (MIB)" carried on the physical broadcast channel (PBCH) and "remaining minimum system information" carried on the physical downlink shared channel, where the master system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the transmission configuration of an initial access request and the message reception configuration of an initial access response. The other system information that needs to be broadcast is called other system information.

[0057] The RMSI is scheduled by the physical downlink control channel PDCCH and is carried on the physical downlink shared channel PDSCH. The time and frequency domain location of the common control resource set CORESET where the RMSI scheduling information resides may be indicated in the PBCH.

[0058] In an NR system, the PBCH is carried and transmitted in a synchronization signal / physical broadcast channel block (SS / PBCH block), one synchronization period includes multiple SS / PBCH blocks, and different SS / PBCH blocks may transmit synchronization broadcast signals of the same or different beam directions or ports together to achieve complete coverage of the expected area. Because the PBCHs of different beam directions and ports require combined reception, it is necessary to ensure that the information content is the same when considering inserting indication information into the PBCH.

[0059] In order to ensure the flexibility of data transmission, the relationship between the time domain positions of different SS / PBCH blocks and the time domain positions of their corresponding RMSI common control resource sets may be different, and how to effectively indicate the time domain positions of the RMSI common control resource sets without affecting the combined reception of the PBCH is an issue that must be considered and solved.

[0060] The present application relates to an information transmission method and system, comprising the following aspects: The method includes: at a network side, transmitting configuration information of a control resource set (CORESET) on a physical broadcast channel, and using the configuration information of the control resource set, time and frequency domain location information of the control resource set is indicated to the terminal; and The network side transmits the control resource set CORESET according to the configuration information. The present invention provides an information transmission method and system, including:

[0061] The configuration information for the control resource set is Bandwidth information of the control resource set; Frequency domain location information of the control resource set; Time domain location information of a control resource set, the time domain location information including the following information: information of the slot in which the control resource set exists, and information of the control resource set in the slot. The position information of the symbols occupied by the control resource set in the slot includes at least one of a starting symbol index of the symbols occupied by the control resource set in the slot and a number of the symbols occupied by the control resource set in the slot, and monitoring window configuration information of a control resource set, the monitoring window configuration information of the control resource set including at least one of the following information: a monitoring period of the control resource set, a time domain duration of the monitoring window, a time domain offset between adjacent monitoring windows, and a starting position of the monitoring window; Contains one or more of the following:

[0062] The common control resource set CORESET of this embodiment may include one or more of the following downlink control information, namely, paging downlink control information, scheduling information of the remaining minimum system information, and paging indicator, etc. Since the information needs to realize complete coverage of the expected range, the common control information of a certain downlink port / downlink beam direction is transmitted within a certain CORESET, and one or more CORESETs are included in one sweep transmission period / CORESET monitoring period, and the transmission of the common control information of one or more downlink ports / downlink beam directions realizes the coverage of the expected range.

[0063] Paging downlink control information (paging DCI) is used to indicate scheduling information of a paging message, and is also referred to as paging scheduling downlink control information (paging scheduling DCI).

[0064] In the new generation wireless communication system NR, system information is classified into minimum system information (minimum SI) and other system information (other SI). The minimum system information is further classified into "master system information (MIB)" carried on the physical broadcast channel (PBCH) and "remaining minimum system information" carried on the physical downlink shared channel, where the master system information is used to provide basic system parameters of the cell, and the remaining minimum system information is used to provide configuration information related to initial access, such as the transmission configuration of an initial access request and the message reception configuration of an initial access response. The other system information that needs to be broadcast is called other system information (other SI).

[0065] The RMSI is scheduled by the physical downlink control channel PDCCH and is carried on the physical downlink shared channel PDSCH. The time and frequency domain location of the common control resource set CORESET where the RMSI scheduling information resides may be indicated in the PBCH.

[0066] The paging indicator is used to trigger a terminal to report a preferred beam for the downlink and is also referred to as a paging group indicator.

[0067] A synchronization signal block (SS / PBCH block) is a time and frequency domain resource used to carry access-related signal channels such as synchronization signals and physical broadcast channels (and corresponding demodulation reference signals DMRS). FIG. 5 is a schematic diagram of a synchronization signal block according to this embodiment. As shown in FIG. 5, a synchronization signal block typically includes four symbols, the first and third symbols respectively carry a primary synchronization signal (PSS) and a secondary synchronization signal (SSS), and the synchronization signal sequence is mapped to 127 resource elements (RE) in 12 physical resource blocks (PRBs). As shown in FIG. 5(a), in some configurations, the physical broadcast channel (PBCH) is the first symbol in the synchronization signal block. In the second and fourth symbols, the PBCH is carried only and occupies 24 PRBs, or in other resource configurations, the PBCH is mapped to the second, third and fourth symbols in the synchronization signal block, and on the multiple symbols, the number of occupied PRBs is as follows: 20 PRBs are occupied on the second and fourth symbols, and on the third symbol, the PBCH occupies four PRBs on each side of the secondary synchronization signal, totaling eight PRBs. In the above configurations, the center frequency of the synchronization signal coincides with the center frequency of the PBCH.

[0068] The present embodiment further includes the following implementation aspects. Implementation 1: In this embodiment, the display of the bandwidth information of CORESET is described, which is particularly described as follows: The configuration information of the control resource set includes that the bandwidth information of the control resource set can be the minimum channel bandwidth or the minimum terminal bandwidth.

[0069] The minimum channel bandwidth is defined as the smallest bandwidth supported by a system within a certain frequency range, for example, within the frequency range below 6 GHz, the minimum channel bandwidth is defined as 5 MHz, or within the frequency range above 6 GHz, the minimum channel bandwidth is defined as 50 MHz.

[0070] The minimum terminal bandwidth refers to the maximum bandwidth that all terminals can support. To indicate CORESET bandwidth information, one bit (bit) may be included in the physical broadcast channel to indicate whether the CORESET bandwidth of the current carrier is the minimum channel bandwidth or the minimum terminal bandwidth. For example, 0 indicates that the CORESET bandwidth of the current carrier is the minimum channel bandwidth, and 1 indicates that the CORESET bandwidth of the current carrier is the minimum terminal bandwidth.

[0071] Alternatively, the CORESET bandwidth is predefined based on the frequency band, e.g., the protocol specifies that the CORESET bandwidth of a certain frequency band is equal to the minimum channel bandwidth or the minimum terminal bandwidth. Alternatively, the value of the CORESET bandwidth of a frequency band is given in the protocol, such as 24 PRBs (Physical Transmission Blocks), or 48 PRBs. In this case, there is no need to insert a bandwidth indication bit separately.

[0072] Alternatively, the CORESET bandwidth is implicitly indicated by the number of symbols occupied by the control resource set in the slot. For example, the number of symbols occupied by the CORESET in the slot of 1 corresponds to a CORESET bandwidth of 48 PRBs, and if the number of symbols occupied by the CORESET in the slot is 2, the CORESET bandwidth is 24 PRBs. In this case, there is no need to insert a bandwidth indication bit separately.

[0073] Implementation 2: In this embodiment, the indication of CORESET frequency domain location information is described, which is described as follows: the configuration information of a control resource set includes frequency domain location information of the control resource set, and the frequency domain location is indicated by a frequency offset between the control resource set and the synchronization signal block.

[0074] FIG. 6 is a schematic diagram I in which the frequency domain position according to the present embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block; FIG. 7 is a schematic diagram II in which the frequency domain position according to the present embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block; FIG. 8 is a schematic diagram III in which the frequency domain position according to the present embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block; and FIG. 9 is a schematic diagram I in which the frequency domain position according to the present embodiment is indicated by the frequency offset between the control resource set and the synchronization signal block. FIG. 10 is a schematic diagram IV in which the frequency domain location according to the embodiment is shown by the frequency offset between the control resource set and the synchronization signal block, FIG. 11 is a schematic diagram VI in which the frequency domain location according to the embodiment is shown by the frequency offset between the control resource set and the synchronization signal block. As shown in FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10 and FIG. 11, there may be an offset (as an illustration of the offset) between the physical resource block PRB boundary of the synchronization signal block and the actual PRB boundary of the carrier (physical resource block grid (PRB grid)). Information bits (such as 4 or 5 bits) may be inserted into the physical broadcast channel to explicitly indicate the above offset, which may be predefined as the offset between the physical resource block PRB boundary of the synchronization signal block and the PRB boundary of the carrier at a lower frequency (as shown in FIG. 6, FIG. 8 and FIG. 10) or the offset between the physical resource block PRB boundary of the synchronization signal block and the PRB boundary of the carrier at a higher frequency (as shown in FIG. 7, FIG. 9 and FIG. 11). However, since there is no offset between the transmission of CORESET and the actual PRB boundary of the carrier, this offset must be taken into account when indicating the frequency domain location of CORESET using a frequency offset from the synchronization signal block. The indication manner of the CORESET frequency domain location is described below for the cases where the subcarrier spacing of CORESET is equal to, smaller than, or larger than the subcarrier spacing of the synchronization signal block.

[0075] As shown in Figures 6 and 7, when the subcarrier spacing of CORESET is equal to the subcarrier spacing of the synchronization signal block (e.g., the subcarrier spacing of CORESET and the synchronization signal block is 15 kHz), within the carrier physical resource block grid (PRB grid), one carrier PRB contains 12 synchronization signal block subcarriers in the frequency domain, and therefore there are 12 possible offset values, i.e., the offset value ranges from 0 to 11 subcarriers, and a specific offset number (i.e., the offset value) is indicated by 4 bits in the PBCH.

[0076] As shown in Figures 8 and 9, if the subcarrier spacing of CORESET is smaller than the subcarrier spacing of the synchronization signal block (e.g., the subcarrier spacing of CORESET is 15 kHz and the subcarrier spacing of the synchronization signal block is 30 kHz), the carrier physical resource block grid (PRB grid) is defined by the larger subcarrier spacing (30 kHz), and the smaller subcarrier is nested within the larger subcarrier, i.e., one 30 kHz subcarrier in the frequency domain corresponds to two 15 kHz subcarriers. In this case, in the carrier physical resource block grid (PRB grid), one carrier PRB in the frequency domain includes 12 synchronization signal block subcarriers, the value of the offset (offset) ranges from 0 to 11 synchronization signal block (30 kHz) subcarriers, and the specific offset number (i.e., the value of the offset) is indicated by 4 bits in the PBCH.

[0077] As shown in Figures 10 and 11, if the subcarrier spacing of CORESET is larger than the subcarrier spacing of the synchronization signal block (e.g., the subcarrier spacing of CORESET is 30 kHz and the subcarrier spacing of the synchronization signal block is 15 kHz), the carrier physical resource block grid (PRB grid) is defined by the larger subcarrier spacing (30 kHz), and the smaller subcarrier is nested within the larger subcarrier, i.e., one 30 kHz subcarrier in the frequency domain corresponds to two 15 kHz subcarriers. In this case, within the carrier physical resource block grid (PRB grid), one carrier PRB in the frequency domain includes 24 synchronization signal block subcarriers, the value of the offset (offset) ranges from 0 to 23 synchronization signal block (30 kHz) subcarriers, and the specific offset number (i.e., the value of the offset) is indicated by 5 bits in the PBCH.

[0078] Sub-implementation 2.1: If the offset is defined as the offset between the physical resource block PRB boundary of the synchronization signal block and the PRB boundary of the carrier at the lower frequency (as shown in Figures 6, 8 and 10), the frequency domain location of the CORESET is one of the following frequency domain locations Case 1 to Case 5.

[0079] Case 1: The low frequency boundary of CORESET is lower than the low frequency boundary of the synchronization signal block by M 15 kHz subcarriers. In this case, the offset between the center frequency of CORESET and the center frequency of the synchronization signal block is (BW CORESET -B.W. SSB ) / 2-M×SC SSB It is.

[0080] Case 2: The high frequency boundary of the CORESET is 12 × SC higher than the high frequency boundary of the sync signal block. CORESET -M×SC SSB In this case, the offset between the center frequency of CORESET and the center frequency of the sync signal block is (BW CORESET-B.W. SSB ) / 2-(12×SC CORESET -M×SC SSB ).

[0081] Case 3: The offset between the center frequency of CORESET and the center frequency of the synchronization signal block is M 15 kHz subcarriers, i.e., the absolute offset between the center frequencies is M × SC SSB It is.

[0082] Case 4: The high frequency boundary of CORESET is lower than the low frequency boundary of the synchronization signal block by M 15 kHz subcarriers. In this case, the offset between the center frequency of CORESET and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+M×SC SSB It is.

[0083] Case 5: The low frequency boundary of the CORESET is 12 × SC lower than the high frequency boundary of the sync signal block. CORESET -M×SC SSB In this case, the offset between the center frequency of CORESET and the center frequency of the synchronization signal block is (BW CORESET +BW SSB ) / 2+(12×SC CORESET -M×SC SSB ).

[0084] M is the number of synchronization signal block subcarriers in the frequency domain offset between the synchronization signal block and the PRB boundary, where M is an integer, and if the subcarrier spacing of the CORESET is less than or equal to the subcarrier spacing of the synchronization signal block, the value range of the offset is 0≦M≦11. If the subcarrier spacing of the CORESET is greater than the subcarrier spacing of the synchronization signal block, the value range of the offset is 0≦M≦23. SC CORESET Is controlled is the frequency domain width of the control resource set subcarriers, and SC SSB is a sync signal block sub The frequency domain width of the carrier, BW CORESETis the control resource set bandwidth, BW SSB is the sync block bandwidth.

[0085] In the above five cases, in cases 1, 2 and 3, the frequency domain range of CORESET includes the frequency domain range of the synchronization signal block, and in cases 4 and 5, the frequency domain range of CORESET does not overlap with the frequency domain range of the synchronization signal block.

[0086] Sub-implementation 2.2: Figures 7, 9 and 11 show cases where the offset (offset) is an offset between a physical resource block PRB boundary of a synchronization signal block and a PRB boundary of a carrier at a higher frequency, and there are the following cases 1 to 5, which are similar to the case shown in Figure 6.

[0087] Case 1: The low frequency boundary of the CORESET is 12 × SC lower than the low frequency boundary of the sync signal block. CORESET -M×SC SSB In this case, the offset between the center frequency of CORESET and the center frequency of the sync signal block is (BW CORESET -B.W. SSB ) / 2-(12×SC CORESET -M×SC SSB ).

[0088] Case 2: The high frequency boundary of CORESET is M×SC lower than the high frequency boundary of the synchronization signal block. SSB In this case, C The offset between the center frequency of the ORESET and the center frequency of the sync signal block is (BW CORESET -B.W. SSB ) / 2-M×SC SSB It is.

[0089] Case 3: The offset between the center frequency of CORESET and the center frequency of the synchronization signal block is M 15 kHz subcarriers, i.e., the absolute offset between the center frequencies is M × SCSSB It is.

[0090] Case 4: The high frequency boundary of the CORESET is 12 × SC lower than the low frequency boundary of the sync signal block. CORESET -M×SC SSB In this case, the offset between the center frequency of CORESET and the center frequency of the sync signal block is (BW CORESET +BW SSB ) / 2+(12×SC CORESET -M×SC SSB ).

[0091] Case 5: The low frequency boundary of CORESET is M×SC lower than the high frequency boundary of the synchronization signal block. SSB In this case, C The offset between the center frequency of the ORESET and the center frequency of the sync signal block is (BW CORESET +BW SSB ) / 2+M×SC SSB It is.

[0092] M is the number of synchronization signal block subcarriers in the frequency domain offset between the synchronization signal block and the PRB boundary, where M is an integer, and if the subcarrier spacing of the CORESET is less than or equal to the subcarrier spacing of the synchronization signal block, the value range of the offset is 0≦M≦11. If the subcarrier spacing of the CORESET is greater than the subcarrier spacing of the synchronization signal block, the value range of the offset is 0≦M≦23. SC CORESET Is controlled is the frequency domain width of the control resource set subcarriers, and SC SSB is a sync signal block sub The frequency domain width of the carrier, BW CORESET is the control resource set bandwidth, BW SSB is the sync block bandwidth.

[0093] In the above five cases, in cases 1, 2 and 3, the frequency domain range of CORESET includes the frequency domain range of the synchronization signal block, and in cases 4 and 5, the frequency domain range of CORESET does not overlap with the frequency domain range of the synchronization signal block.

[0094] Any one or more of the above CORESET frequency domain locations may be specified in the protocol, and an indication bit is inserted in the CORESET configuration information indication field of the PBCH to indicate the frequency domain location of the CORESET of the current carrier to the terminal. For example, the protocol specifies that the frequency domain location of the CORESET includes the following four cases, namely, case 1, case 2, case 4, and case 5, and two bits are used in the PBCH to indicate which configuration of the above four frequency domain locations is currently being used.

[0095] Alternatively, as defined below, in cases 1 and 2, it is preferable that the CORESET bandwidth overlaps with the synchronization signal block bandwidth and that the subcarrier spacing of both is the same. Conversely, in cases 4 and 5, it is preferable that the CORESET bandwidth does not overlap with the synchronization signal block bandwidth and that the subcarrier spacing of both is different. Therefore, the subcarrier spacing of the CORESET and the subcarrier spacing of the synchronization signal block are The protocol specifies that if the subcarrier spacing of the CORESET and the subcarrier spacing of the synchronization signal block are different, then one bit is inserted into the PBCH to indicate which configuration of the above frequency domain locations in cases 1 and 2 is currently being used; and if the subcarrier spacing of the CORESET and the subcarrier spacing of the synchronization signal block are different, then one bit is inserted into the PBCH to indicate which configuration of the above frequency domain locations in cases 4 and 5 is currently being used.

[0096] Implementation 3: In this embodiment, a display mode of information on slots in which a control resource set exists will be described.

[0097] There are three cases for the information of the slot where the CORESET exists: Case 1: CORESET is transmitted in a slot containing a synchronization signal block (as shown in (a) of Figure 12, which is a schematic structural diagram in which CORESET in this embodiment is transmitted in a slot in which a synchronization signal block (SSB) exists, i.e., two synchronization signal blocks SSB1 and SSB2 are included in one slot, and the corresponding CORESETs are located in the symbol before the symbol occupied by the SSB).

[0098] Case 2: CORESET is transmitted in a slot containing a synchronization signal block and in a slot not containing a synchronization signal block (as shown in (b) of Figure 12, which is a schematic structural diagram in which CORESET is transmitted in a slot in which an SSB exists and in a slot not containing a synchronization signal block, i.e., two synchronization signal blocks SSB1 and SSB2 are included in one slot, the CORESET corresponding to SSB2 is in the symbol before the symbol occupied by the SSB, and the CORESET corresponding to SSB1 is transmitted in a slot not containing the SSB).

[0099] Case 3: CORESET is transmitted in a slot that does not contain a synchronization signal block (as shown in (c) of Figure 12, which is a schematic structural diagram in which CORESET is transmitted in a slot that does not contain a synchronization signal block, i.e., in one slot that does not contain an SSB, CORESET is respectively mapped to the first and seventh symbols in the slot).

[0100] As shown in Figure 13, there is also another form for transmitting a control resource set in a slot containing a synchronization signal block, i.e., multiple synchronization signal block transmission periods are used. Figure 13 is a schematic diagram of the use of multiple synchronization signal block transmission periods according to this embodiment (in Figure 13, SS burst set periodicity refers to the transmission period of the synchronization signal block). Two synchronization signal blocks are mapped to one slot, and CORESET1 corresponding to the first half SSB is transmitted in the slot where SSB1 exists in the first period, and CORESET2 corresponding to the second half SSB is transmitted in the slot where SSB2 exists in the second period. In this case, the transmission period of CORESET is twice the transmission period of SSB.

[0101] The CORESETs corresponding to which SSBs are transmitted in which SS burst set periods may be predefined by the system, for example, odd-numbered CORESETs corresponding to SSBs are included on radio frames with system frame number SFN mod 4=0, and even-numbered CORESETs corresponding to SSBs are included on radio frames with SFN mod 4=2. Alternatively, odd-numbered CORESETs corresponding to SSBs are included on radio frames with SFN mod 4=0 or 1, and even-numbered CORESETs corresponding to SSBs are included on radio frames with SFN mode 4=2 or 3.

[0102] An indication bit is inserted into the CORESET configuration information indication field of the PBCH, and information on the slot in which the CORESET of the current carrier exists can be indicated to the terminal. For example, two bits are used for indication, and "00" indicates that "the control resource set is transmitted in a slot including a synchronization signal block", "01" indicates that "the control resource set is transmitted in a slot including a synchronization signal block, and is also transmitted in a slot not including a synchronization signal block", "10" indicates that "the control resource set is transmitted in a slot not including a synchronization signal block", and "11" indicates "the aspect of the CORESET transmission span period (corresponding to FIG. 13)".

[0103] Alternatively, one bit is used for indication, with "0" representing "the control resource set is transmitted in a slot containing a synchronization signal block" and "1" representing "the control resource set is transmitted only in a slot not containing a synchronization signal block." In this case, "0" actually includes the three cases shown in FIG. 12(a), FIG. 12(b), and FIG. 13.

[0104] Alternatively, one bit is used for the indication, with "0" representing "the control resource set is transmitted only in slots that include a synchronization signal block" and "1" representing "the control resource set is transmitted in slots that do not include a synchronization signal block." In this case, "0" actually includes the two cases shown in Figures 12(a) and 13, and "1" actually includes the two cases shown in Figures 12(b) and 12(c).

[0105] Alternatively, the protocol specifies that any two of the above four cases are included, with one additional bit in the PBCH to indicate which configuration is specifically used for the current carrier.

[0106] Implementation 4: In this embodiment, a display mode of the position information of the symbols occupied by the CORESET in the slot will be described. The position information of the symbols occupied by the CORESET in the slot includes the starting symbol index of the symbols occupied by the CORESET in the slot and the number of symbols occupied by the CORESET in the slot.

[0107] As shown in Figure 14, Figure 14 is a schematic diagram of the mapping pattern of the current synchronization signal block (SSB) to slots according to this embodiment, where (a) of Figure 14 is applied to mapping a synchronization signal block with a subcarrier interval of 15 kHz or 30 kHz (pattern 2) to a slot, (b) of Figure 14 is applied to mapping a synchronization signal block with a subcarrier interval of 30 kHz (pattern 1) or 120 kHz to a slot, and (c) of Figure 14 is applied to mapping a synchronization signal block with a subcarrier interval of 240 kHz to a slot. The slots in (a) of Figure 14 and (b) of Figure 14 are slots corresponding to the subcarrier interval of the current synchronization signal block, and the slot in (c) of Figure 14 corresponds to the slot of 120 kHz.

[0108] Sub-implementation 4.1: For the mapping of the synchronization signal block of 15 kHz or 30 kHz (pattern 2) shown in (a) of Figure 14, Figure 15 is a schematic diagram I of the position information of the symbol occupied by the CORESET in the slot according to this embodiment. As shown in Figure 15, the position information of the symbol occupied by the CORESET includes that the arrow starting from the SSB points to the corresponding CORESET.

[0109] In the configuration of Figure 15(1), each CORESET occupies one symbol and is in the same slot. where an SSB specifically occupies one symbol before it, i.e., the CORESET corresponding to the first SSB in a slot occupies the second symbol in the slot, the CORESET corresponding to the second SSB in a slot occupies the eighth symbol in the slot, etc.

[0110] In the configuration of Figure 15(2), each CORESET occupies one symbol, the CORESET corresponding to the first SSB in a slot is mapped to the 8th symbol of the slot outside the 5 ms SSB time window, and the CORESET corresponding to the second SSB in a slot is mapped to the slot in which the SSB resides, specifically occupying one symbol before the SSB, i.e. the 8th symbol in the slot.

[0111] In the configuration of Figure 15(3), each CORESET occupies one symbol, the CORESET corresponding to the first SSB in a slot is mapped to the slot in which the SSB resides, and in particular, occupies one symbol before the SSB, i.e., the second symbol in the slot, while the CORESET corresponding to the second SSB in the slot is mapped to the second symbol of the slot outside the 5 ms SSB time window.

[0112] In the configuration of Figure 15(4), each CORESET occupies one symbol and is mapped to a slot in which an SSB resides, with that SSB specifically occupying the first two symbols in the slot, i.e., the CORESET corresponding to the first SSB in a slot occupies the first symbol in the slot, and the CORESET corresponding to the second SSB in a slot occupies the second symbol in the slot.

[0113] In the configuration of Figure 15(5), each CORESET occupies two symbols, and the CORESET corresponding to the first SSB in a slot is mapped to the slot in which that SSB resides, in particular occupying the first two symbols of the slot in which that SSB resides, and the CORESET corresponding to the second SSB in a slot is mapped to the first and second symbols of the slot outside the 5 ms SSB time window.

[0114] In the configuration of Figure 15(6), each CORESET occupies two symbols, the CORESET corresponding to the first SSB in a slot is mapped to the 7th and 8th symbols of a slot outside the 5 ms SSB time window, and the CORESET corresponding to the second SSB in a slot is mapped to the slot in which that SSB resides, and in particular occupies the 7th and 8th symbols of the slot in which that SSB resides.

[0115] In the configuration of Figure 15(7), each CORESET occupies two symbols, with the CORESET corresponding to the first SSB in a slot being mapped to the first and second symbols of the slot outside the 5 ms SSB time window, and the CORESET corresponding to the second SSB in a slot being mapped to the slot in which that SSB resides, and in particular occupying the seventh and eighth symbols of the slot in which that SSB resides.

[0116] In the configuration of Figure 15(8), each CORESET occupies two symbols and is mapped to the same slot, with the SSBs specifically occupying the two symbols preceding the SSB in question, i.e., the CORESET corresponding to the first SSB in a slot occupies the first and second symbols in the slot, and the CORESET corresponding to the second SSB in a slot occupies the seventh and eighth symbols in the slot.

[0117] In the configuration of Figure 15(9), each CORESET occupies one, two, three, or four symbols, and uses Frequency-Division Multiplexing (FDM). A multiplexing scheme is used for the CORESET and the corresponding SSB, i.e. The CORESET corresponding to the first SSB is mapped to the slot the SSB resides in. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the third symbol of the slot the SSB resides in, for two symbols of the CORESET the third and fourth symbols are occupied, for three symbols of the CORESET the third, fourth and fifth symbols are occupied, for four symbols of the CORESET the third, fourth, fifth and sixth symbols are occupied, and the CORESET corresponding to the second SSB in a slot is mapped to the slot the SSB resides in. In one embodiment, if CORESET occupies one symbol, CORESET occupies the 9th symbol of the slot in which SSB resides, for two symbols of CORESET the 9th and 10th symbols are occupied, for three symbols of CORESET the 9th, 10th and 11th symbols are occupied, for four symbols of CORESET the 9th, 10th, 11th and 12th symbols are occupied, and resources other than SSB are occupied in the frequency domain.

[0118] In the configuration of Figure 15 (10), each CORESET occupies one or two or three or four symbols, and FDM multiplexing is used for the CORESET and the corresponding SSB, i.e., the CORESET corresponding to the first SSB in a slot is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the third symbol of the slot in which the SSB resides, for two symbols of the CORESET, the third and fourth symbols are occupied, for three symbols of the CORESET, the third, fourth and fifth symbols are occupied, for four symbols of the CORESET, the third, fourth, fifth and sixth symbols are occupied, and the CORESET corresponding to the second SSB in a slot is mapped to a slot outside the 5 ms SSB time window. In one embodiment, if CORESET occupies one symbol, it occupies the third symbol of the slot in which SSB resides, for two symbols of CORESET the third and fourth symbols are occupied, for three symbols of CORESET the third, fourth and fifth symbols are occupied, for four symbols of CORESET the third, fourth, fifth and sixth symbols are occupied. Resources other than the frequency domain resources corresponding to SSBs are occupied in the frequency domain.

[0119] Sub-implementation 4.2: For the mapping of the 30 kHz (pattern 1) or 120 kHz synchronization signal block shown in (b) of Figure 14, the mapping resource configuration is performed with a period of two slots and four SSBs. Figure 16 is a schematic diagram II of the position information of the symbol occupied by the CORESET in the slot according to this embodiment. As shown in Figure 16, the position information of the symbol occupied by the CORESET includes that the arrow starting from the SSB points to the corresponding CORESET.

[0120] In the configuration of Figure 16(1), each CORESET occupies one symbol, the CORESET of the first SSB occupies the third symbol in the first half slot, the CORESET of the second SSB occupies the fourth symbol in the first half slot, the CORESET of the third SSB occupies the first symbol in the second half slot, and the CORESET of the fourth SSB occupies the second symbol in the second half slot.

[0121] In the configuration of Figure 16(2), each CORESET occupies one symbol, the CORESET of the first SSB occupies the third symbol in the first half slot, the CORESET of the second SSB occupies the fourth symbol in the first half slot, the CORESET of the third SSB occupies the third symbol in the slot outside the 5 ms SSB time window, and the CORESET of the fourth SSB occupies the fourth symbol in the slot outside the 5 ms SSB time window. symbol, and the "interval between the CORESET of the first SSB and the CORESET of the third SSB" is equal to the "interval between the CORESET of the second SSB and the CORESET of the fourth SSB", e.g., the interval is equal to 5 ms.

[0122] In the configuration of Figure 16(3), each CORESET occupies one symbol, the CORESET of the first SSB occupies the fourth symbol in the first half slot, the CORESET of the second SSB occupies the fourth symbol in a slot outside the 5 ms SSB time window, the CORESET of the third SSB occupies the fourth symbol in a slot outside the 5 ms SSB time window, and the "interval between the CORESET of the first SSB and the CORESET of the third SSB" is equal to the "interval between the CORESET of the second SSB and the CORESET of the fourth SSB", e.g., the interval is equal to 5 ms.

[0123] In the configuration of Figure 16(4), each CORESET occupies one symbol, and the CORESETs are each mapped to the first four symbols in the first slot. In one embodiment, the CORESET for the first SSB occupies the first symbol in the first half slot, the CORESET for the second SSB occupies the second symbol in the first half slot, the CORESET for the third SSB occupies the third symbol in the first half slot, and the CORESET for the fourth SSB occupies the fourth symbol in the first half slot.

[0124] In the configuration of Figure 16(5), each CORESET occupies two symbols, the CORESET of the first SSB occupies the first and second symbols in the first half slot, the CORESET of the second SSB occupies the third and fourth symbols in the first half slot, the CORESET of the third SSB occupies the first and second symbols in slots outside the 5 ms SSB time window, and the CORESET of the fourth SSB occupies the third and fourth symbols in slots outside the 5 ms SSB time window, and the "time domain interval between the CORESET of the first SSB and the CORESET of the third SSB" is equal to the "time domain interval between the CORESET of the second SSB and the CORESET of the fourth SSB", e.g., the interval is equal to 5 ms.

[0125] In the configuration of Figure 16(6), each CORESET occupies two symbols, the CORESET of the first SSB occupies the third and fourth symbols in the first half slot, the CORESET of the second SSB occupies the first and second symbols in the second half slot, the CORESET of the third SSB occupies the third and fourth symbols in slots outside the 5 ms SSB time window, and the CORESET of the fourth SSB occupies the first and second symbols in slots outside the 5 ms SSB time window, and the "time domain interval between the CORESET of the first SSB and the CORESET of the third SSB" is equal to the "time domain interval between the CORESET of the second SSB and the CORESET of the fourth SSB", e.g., the interval is equal to 5 ms.

[0126] In the configuration of Figure 16(7), each CORESET occupies two symbols, the CORESET of the first SSB occupies the first and second symbols in the first half slot, the CORESET of the second SSB occupies the third and fourth symbols in the first half slot, the CORESET of the third SSB occupies the first and second symbols in the second half slot, and the CORESET of the fourth SSB occupies the first and second symbols in slots outside the 5 ms SSB time window, and the "time domain interval between the CORESET of the first SSB and the CORESET of the fourth SSB" is equal to 5 ms.

[0127] In the configuration of Figure 16(8), each CORESET occupies two symbols, the CORESET of the first SSB occupies the first and second symbols in the first half slot, and the CORESET of the second SSB occupies the first and second symbols in the first half slot. B's CORESET occupies the 3rd and 4th symbols in the first half slots, the 3rd SSB's CORESET occupies the 1st and 2nd symbols in the first half slots, the 4th SSB's CORESET occupies the 1st and 2nd symbols in slots outside the 5 ms SSB time window, and the "time domain interval between the 2nd SSB's CORESET and the 4th SSB's CORESET" is equal to 5 ms, or the "time domain interval between the 3rd SSB's CORESET and the 4th SSB's CORESET" is equal to 5 ms.

[0128] In the configuration of FIG. 16(9), each CORESET occupies one or two or three or four symbols, and an FDM multiplexing scheme is used for the CORESET and the corresponding SSBs, namely as follows:

[0129] The CORESET corresponding to the first SSB is mapped to the slot the SSB resides in. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the fifth symbol of the slot the SSB resides in, for two symbols of the CORESET the fifth and sixth symbols are occupied, for three symbols of the CORESET the fifth, sixth and seventh symbols are occupied, for four symbols of the CORESET the fifth, sixth, seventh and eighth symbols are occupied, and resources other than the SSB are occupied in the frequency domain.

[0130] The CORESET corresponding to the second SSB is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the 9th symbol of the slot in which the SSB resides, for two symbols of the CORESET, the 9th and 10th symbols are occupied, for three symbols of the CORESET, the 9th, 10th and 11th symbols are occupied, for four symbols of the CORESET, the 9th, 10th, 11th and 12th symbols are occupied, and resources other than the SSB are occupied in the frequency domain.

[0131] The CORESET corresponding to the third SSB is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the third symbol of the slot in which the SSB resides, for two symbols of the CORESET, the third and fourth symbols are occupied, for three symbols of the CORESET, the third, fourth and fifth symbols are occupied, for four symbols of the CORESET, the third, fourth, fifth and sixth symbols are occupied, and resources other than the SSB are occupied in the frequency domain.

[0132] The CORESET corresponding to the fourth SSB is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the seventh symbol of the slot in which the SSB resides, for two symbols of the CORESET, the seventh and eighth symbols are occupied, for three symbols of the CORESET, the seventh, eighth and ninth symbols are occupied, for four symbols of the CORESET, the seventh, eighth, ninth and tenth symbols are occupied, and resources other than the SSBs are occupied in the frequency domain.

[0133] In the configuration of FIG. 16(10), each CORESET occupies one or two or three or four symbols, and FDM multiplexing is used for the CORESET and the corresponding SSBs, namely as follows:

[0134] The CORESET corresponding to the first SSB is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the fifth symbol of the slot in which the SSB resides, and two symbols of the CORESET For the CORESET symbols, the 5th and 6th symbols are occupied, for the CORESET three symbols, the 5th, 6th and 7th symbols are occupied, for the CORESET four symbols, the 5th, 6th, 7th and 8th symbols are occupied, and resources other than SSB are occupied in the frequency domain.

[0135] The CORESET corresponding to the second SSB is mapped to a slot outside the 5 ms time window. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the fifth symbol, for two symbols of the CORESET, the fifth and sixth symbols are occupied, for three symbols of the CORESET, the fifth, sixth and seventh symbols are occupied, for four symbols of the CORESET, the fifth, sixth, seventh and eighth symbols are occupied, and resources other than the frequency domain resources corresponding to the SSBs are occupied in the frequency domain. Also, the "interval between the CORESET of the first SSB and the CORESET of the third SSB" is equal to 5 ms.

[0136] The CORESET corresponding to the third SSB is mapped to the slot in which the SSB resides. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the third symbol of the slot in which the SSB resides, for two symbols of the CORESET, the third and fourth symbols are occupied, for three symbols of the CORESET, the third, fourth and fifth symbols are occupied, for four symbols of the CORESET, the third, fourth, fifth and sixth symbols are occupied, and resources other than the SSB are occupied in the frequency domain.

[0137] The CORESET corresponding to the fourth SSB is mapped to a slot outside the 5 ms time window. In one embodiment, if the CORESET occupies one symbol, the CORESET occupies the seventh symbol, for two symbols of the CORESET, the seventh and eighth symbols are occupied, for three symbols of the CORESET, the seventh, eighth and ninth symbols are occupied, for four symbols of the CORESET, the seventh, eighth, ninth and tenth symbols are occupied, and resources other than the frequency domain resources corresponding to the SSBs are occupied in the frequency domain. Also, the "interval between the CORESET of the second SSB and the CORESET of the fourth SSB" is equal to 5 ms.

[0138] Sub-implementation 4.3: When the CORESET is only mapped to slots outside the SSB, Figure 17 is a schematic diagram I in which the CORESET according to this embodiment is mapped to slots outside the SSB, and Figure 18 is a schematic diagram II in which the CORESET according to this embodiment is mapped to slots outside the SSB. As shown in Figures 17 and 18, the position information of the symbols occupied by the CORESET in the slot includes one or more of the following:

[0139] In the configuration of FIG. 17(1), a slot includes two CORESETs, each of which occupies one symbol, and the CORESETs reside on the first and second symbols respectively in the slot.

[0140] In the configuration of Figure 17(2), a slot contains two CORESETs, each of which occupies two symbols. In one embodiment, one CORESET is mapped to the first and second symbols in the slot, and the other CORESET is mapped to the third and fourth symbols in the slot.

[0141] In the configuration of FIG. 17(3), a slot includes two CORESETs, each of which occupies one symbol, and the CORESETs reside on the first and eighth symbols, respectively, in the slot.

[0142] In the configuration of Figure 17(4), a slot contains two CORESETs, each of which occupies two symbols. In one embodiment, one CORESET is mapped to the first and second symbols in the slot, and the other CORESET is mapped to the eighth and ninth symbols in the slot.

[0143] In the configuration of FIG. 17(5), a slot contains two CORESETs, each of which occupies one symbol, and the CORESETs reside on the third and ninth symbols, respectively, in the slot.

[0144] In the configuration of Figure 17(6), a slot contains two CORESETs, each of which occupies two symbols. In one embodiment, one CORESET is mapped to the third and fourth symbols in the slot, and the other CORESET is mapped to the ninth and tenth symbols in the slot.

[0145] In the configuration of Figure 17(7), a slot contains one CORESET, and the CORESET occupies one symbol. In one embodiment, the CORESET is mapped to the first symbol in a slot.

[0146] In the configuration of Figure 17(8), a slot contains one CORESET, which occupies two symbols. In one embodiment, the CORESET is mapped to the first and second symbols in a slot.

[0147] In the configuration of Figure 18 (1), two slots are used as a configuration period, and four CORESETs are included, each CORESET including one symbol. The first CORESET is mapped to the fifth symbol of the first half slot, the second CORESET is mapped to the ninth symbol of the first half slot, the third CORESET is mapped to the third symbol of the second half slot, and the fourth CORESET is mapped to the seventh symbol of the second half slot.

[0148] In the configuration of Figure 18 (2), two slots are used as a configuration period, and four CORESETs are included, with each CORESET including two symbols. The first CORESET is mapped to the fifth and sixth symbols of the first half slot, the second CORESET is mapped to the ninth and tenth symbols of the first half slot, the third CORESET is mapped to the third and fourth symbols of the second half slot, and the fourth CORESET is mapped to the seventh and eighth symbols of the second half slot.

[0149] In the above configuration, the position of the symbol occupied by the currently used CORESET in the slot can be indicated to the terminal in the following manner.

[0150] According to the CORESET bandwidth configuration described in implementation 1, the terminal can determine the bandwidth of the current CORESET, and when the CORESET bandwidth takes the minimum channel bandwidth, the bandwidth value is relatively small, so the time division multiplexing aspect is preferred for CORESET and SSB.

[0151] Conversely, if the CORESET bandwidth takes on a larger value, ie the minimum UE bandwidth, then the frequency division multiplexing aspect is preferred for CORESET and SSB.

[0152] Furthermore, according to the aspect described in the implementation aspect 3, the terminal can obtain information on the slot in which the CORESET exists.

[0153] The following three tables are defined: Table 1, Table 2 and Table 3. Table 1 is applicable when the CORESET bandwidth is configured as the "minimum channel bandwidth" and the information of the slot in which the CORESET resides is "the control resource set is transmitted in the slot containing the synchronization signal block", and in the PBCH, three bits in particular indicate to the terminal which of the eight configurations in Table 1 is being used.

[0154] Table 2 is applicable when the CORESET bandwidth takes a larger value, i.e. the "minimum UE bandwidth", and the information of the slot in which the CORESET resides is "the control resource set is transmitted in the slot containing the synchronization signal block", and in the PBCH, specifically 3 bits indicate to the terminal which of the 8 configurations in Table 2 is being used.

[0155] Table 3 is applicable when the information of the slot in which the CORESET exists is "the control resource set is transmitted in a slot that does not contain a synchronization signal block" or when the subcarrier spacing of the CORESET and the subcarrier spacing of the synchronization signal block are different and the CORESET and the synchronization signal block belong to different bandwidth parts (BWPs). In the PBCH, three bits in particular indicate to the terminal which of the eight configurations in Table 3 is being used.

[0156] [Table 1]

[0157] [Table 2]

[0158] [Table 3]

[0159] Implementation 5: In this embodiment, a display mode of CORESET monitoring window (PDCCH monitoring window) configuration information will be described.

[0160] The CORESET monitoring window configuration information includes at least one of the following information: a monitoring period of the CORESET, a starting position of the monitoring window, a time-domain duration of the monitoring window, and a time-domain offset between adjacent monitoring windows.

[0161] The CORESET monitoring window is also referred to as a physical downlink control channel (PDCCH) monitoring window, and each monitoring window corresponds to a synchronization signal block. The CORESET monitoring window includes one or more CORESET monitoring opportunities, i.e., one or more resources for transmitting PDCCH. The base station allocates one PDCCH transmission resource in the CORESET monitoring window for PDCCH transmission. The terminal may select a PDCCH transmission resource corresponding to the synchronization signal block on one or more PDCCH transmission resources in the CORESET monitoring window, and the terminal may attempt to receive a PDCCH corresponding to the synchronization signal block on one or more PDCCH transmission resources in the CORESET monitoring window. There is a quasi-co-location (QCL) relationship between the synchronization signal block and the CORESET or the PDCCH in the corresponding monitoring window.

[0162] The monitoring period of the CORESET may be understood as the transmission period of the CORESET, and the value of the period may be predefined, for example, as 40 ms. Multiple monitoring period values, such as 20 ms, 40 ms, etc., may also be predefined in the protocol, and a specific value of the monitoring period of the current carrier is indicated by one bit in the PBCH.

[0163] The start position of the CORESET monitoring window refers to the time domain start position of the first CORESET monitoring window. Taking a CORESET transmission period of 20 ms as an example, when the CORESET is transmitted in a slot including a synchronization signal block, the CORESET start position of the monitoring window is predefined. Figure 19 is a schematic diagram of the CORESET according to this embodiment being transmitted in a slot including a synchronization signal block. As shown in Figure 19, the start position of the CORESET monitoring window is the start point of the radio frame with SFN mod 2=0.

[0164] When the CORESET is transmitted in a slot that does not include a synchronization signal block, the start position of the CORESET in the monitoring window is predefined. Figure 20 is a schematic diagram showing the CORESET according to this embodiment being transmitted in a slot that does not include a synchronization signal block. As shown in Figure 20, the start position of the monitoring window for the CORESET is the sixth subframe (i.e., the second half frame) of the radio frame with SFN mod 2=0.

[0165] When a CORESET is transmitted in a slot including a synchronization signal block and also in a slot not including a synchronization signal block, FIG. 21 is a schematic diagram showing a CORESET according to this embodiment being transmitted in a slot including a synchronization signal block and also in a slot not including a synchronization signal block (as shown in FIG. 21, for a CORESET transmitted in a slot in which a synchronization signal block is present, the start position of its monitoring window is the start position of a radio frame with SFN mod 2=0, and for a CORESET transmitted in a slot not including a synchronization signal block, the start position of its monitoring window is the sixth subframe (i.e., the second half-frame) of a radio frame with SFN mod 2=0).

[0166] The time domain duration of the monitoring window of the CORESET is one or more slots. For example, the time domain duration of the monitoring window is one or more of 1 slot, 2 slots, 4 slots, or M slots, where M is the number of slots occupied by the synchronization signal block in the synchronization signal block transmission period.

[0167] If CORESET is transmitted in a slot where synchronization exists, the time domain duration of the monitoring window is one slot, and if CORESET is transmitted in a slot that does not contain a synchronization signal block, the time domain duration of the monitoring window may be one or more slots.

[0168] An indication bit may be inserted in the CORESET configuration information indication field of the PBCH to indicate the time domain duration of the CORESET monitoring window of the current carrier to the terminal. For example, two bits may be used for indication, with "00" representing "the time domain duration of the monitoring window is 1 slot", "01" representing "the time domain duration of the monitoring window is 2 slots", and "10" representing "no monitoring The time domain duration of the window is M slots" and "11" represents "save state".

[0169] Alternatively, the protocol specifies that only two of the above four types of time domain duration of the CORESET monitoring window are included, and one additional bit is used on the PBCH to indicate which configuration is specifically used for the current carrier, e.g., "0" indicates that the time domain duration of the monitoring window is 1 slot, and "1" indicates that the time domain duration of the monitoring window is 2 slots.

[0170] Alternatively, the protocol specifies that the time domain duration of the CORESET monitoring window may be configured in one of the following three types: 1 slot, 2 slots, and 4 slots, and the time domain transmission resource of the CORESET monitoring window and the time domain duration of the monitoring window are both indicated, occupying a total of 2 bits, e.g. "00": CORESET is transmitted in the slot containing the SS / PBCH block, the length of the CORESET monitoring window is equal to one slot, "01": CORESET is transmitted in slots that do not contain SS / PBCH blocks, the length of the CORESET monitoring window is equal to one slot, "10": CORESET is transmitted in slots that do not contain SS / PBCH blocks, the length of the CORESET monitoring window is equal to 2 slots, "11": CORESET is transmitted in slots that do not contain SS / PBCH blocks, the length of the CORESET monitoring window is equal to 4 slots, The time domain offset between adjacent monitoring windows may include one or more of 0, the time domain duration of the monitoring window, and 1 / X of the time domain duration of the monitoring window, where X is an integer greater than 1, and the value may be predefined in the protocol or indicated by signaling.

[0171] Figure 22 is a schematic diagram of the CORESET according to this embodiment being transmitted in a slot in which a synchronization signal block exists. As shown in Figure 22, when the CORESET is transmitted in a slot in which a synchronization signal block exists, and the CORESET and the corresponding SSB are frequency division multiplexed and transmitted, the time domain duration of the monitoring window is 1 slot, and the time domain offset between adjacent monitoring windows is equal to the time domain duration of the monitoring window, i.e., 1 slot. In this case, the adjacent monitoring windows do not overlap. In Figure 22, the eight included synchronization signal blocks can be used as resources for transmitting the synchronization signal and the physical broadcast channel, and the base station can select some or all of them as the synchronization signal block (actual SSB) to be actually transmitted.

[0172] FIG. 23 is a schematic diagram I of the CORESET according to this embodiment being transmitted in a slot that does not include a synchronization signal block. In FIG. 23, CORESET is transmitted in a slot that does not include a synchronization signal block, i.e., in the second half frame of a radio frame in which a synchronization signal block exists, the time domain duration of the monitoring window is one slot, and the time domain offset between adjacent monitoring windows is equal to the time domain duration of the monitoring window, i.e., one slot. In this case, adjacent monitoring windows do not overlap. The dashed blocks in FIG. 23 are pseudo synchronization signal blocks (pseudo SSBs), and the transmission of CORESET also avoids these pseudo synchronization signal blocks, and the resources occupied by CORESET in a slot are the same as those in FIG. 22. The advantage of this configuration is that when the transmission period of the synchronization signal block is 5 ms, the synchronization signal block of the next period is also transmitted in a slot in which CORESET exists, and the transmission of CORESET is performed in a slot in which CORESET exists. The advantage of this is that there is no collision between the two, even if the transmission period of the synchronization signal block is 5 ms, to avoid resources for transmitting the synchronization signal block. The terminal does not need to know the actual synchronization signal block transmission period of the current carrier.

[0173] FIG. 24 is a schematic diagram II in which the CORESET according to the present embodiment is transmitted in a slot that does not include a synchronization signal block. As shown in FIG. 24, the CORESET is transmitted in a slot that does not include a synchronization signal block, i.e., in the second half frame of the radio frame in which the synchronization signal block exists, the time domain duration of the monitoring window is two slots, and the time domain offset between adjacent monitoring windows is equal to 1 / 2 the time domain duration of the monitoring window, i.e., 1 slot. And the adjacent monitoring windows are partially overlapped. In one embodiment, the second synchronization signal block in slot 1 in which the synchronization signal block exists is actually transmitted, and this synchronization signal block corresponds to monitoring window 1, i.e., the second and third slots of the second half frame, and these two slots include four CORESET transmission resources, and the base station selects one of them to transmit the CORESET corresponding to the synchronization signal block. Similarly, the first synchronization signal block in slot 2 is actually transmitted, which corresponds to monitoring window 2, i.e., the third and fourth slots, and the base station selects one of the CORESET transmission resources in these two slots to transmit the CORESET corresponding to the synchronization signal block.

[0174] Note that CORESETs corresponding to different synchronization signal blocks cannot occupy the same CORESET transmission resource, so when a CORESET transmission resource is selected within the corresponding monitoring window for a subsequent synchronization signal block, the occupied CORESET transmission resource needs to be avoided.

[0175] Figure 25 is a schematic diagram of all synchronization signal blocks according to this embodiment corresponding to the same CORESET monitoring window. As shown in Figure 25, all synchronization signal blocks correspond to the same CORESET monitoring window. In one embodiment, four slots including synchronization signal blocks include eight synchronization signal block resources, in which case only two of the synchronization signal blocks are transmitted, and the eight synchronization signal blocks correspond to the same CORESET monitoring window, and the monitoring window includes eight CORESET transmission resources, and for a terminal, regardless of which synchronization signal block it receives, it is necessary to attempt to receive the corresponding CORESET in eight CORESET monitoring opportunities within this monitoring window.

[0176] FIG. 26 is a schematic diagram of a plurality of synchronization signal blocks according to the present embodiment corresponding to one CORESET monitoring window. As shown in FIG. 26, a plurality of synchronization signal blocks correspond to one CORESET monitoring window. In one embodiment, four slots including synchronization signal blocks include eight synchronization signal block resources, in which the first four synchronization signal blocks are actually transmitted, the four synchronization signal blocks in the first two slots correspond to the first CORESET monitoring window (corresponding to the first two pseudo synchronization signal blocks in the time domain), the four synchronization signal blocks in the last two slots correspond to the second CORESET monitoring window (corresponding to the third and fourth pseudo synchronization signal blocks in the time domain), and for a terminal, if one of the first four SSBs is to be received, it is necessary to attempt to receive the corresponding CORESET in the eight CORESET monitoring opportunities in the monitoring window 1, and if one of the last four SSBs is to be received, it is necessary to attempt to receive the corresponding CORESET in the eight CORESET monitoring opportunities in the monitoring window 2.

[0177] The display bit is inserted in the PBCH CORESET configuration information display field, and the current carrier The time-domain offset between adjacent CORESET monitoring windows of the can be indicated to the terminal. For example, two bits are used for indication, where "00" indicates "the time-domain offset between adjacent monitoring windows is 0", "01" indicates "the time-domain offset between adjacent monitoring windows is the length of the monitoring window", "10" indicates "the time-domain offset between adjacent monitoring windows is 1 / X of the length of the monitoring window", and "11" indicates "state saving", where X is an integer greater than 1, and the value may be specified in the protocol or indicated by signaling.

[0178] In the above indication manner, it is necessary to introduce two bits of indication overhead, and in order to reduce this overhead, the type of time-domain offset between adjacent monitoring windows can also be restricted according to different kinds of time-domain durations of the monitoring windows. For example, when the length of the monitoring window is one slot, it is specified that there are only two possibilities of the time-domain offset between adjacent monitoring windows: the time-domain offset between adjacent monitoring windows is the length of the monitoring window (i.e., the adjacent monitoring windows overlap and are configured contiguously), or the time-domain offset between adjacent monitoring windows is 1 / X of the time-domain duration of the monitoring window (i.e., the adjacent monitoring windows partially overlap). In this case, only one bit is needed to indicate the offset value, for example, "0" indicates "the time-domain offset between adjacent monitoring windows is the length of the monitoring window" and "1" indicates "the time-domain offset between adjacent monitoring windows is 1 / X of the length of the monitoring window". Similarly, X is an integer greater than 1, and its value may be specified in the protocol or indicated by signaling.

[0179] If the length of the monitoring window is greater than one slot, then only two possibilities for the time-domain offset between adjacent monitoring windows are specified: either the time-domain offset between adjacent monitoring windows is 0 (i.e., adjacent monitoring windows completely overlap), or the time-domain offset between adjacent monitoring windows is 1 / X of the monitoring window length (i.e., adjacent monitoring windows partially overlap). In this case, only one bit is needed to indicate the offset value, e.g., "0" represents "the time-domain offset between adjacent monitoring windows is 0" and "1" represents "the time-domain offset between adjacent monitoring windows is 1 / X of the monitoring window length". Similarly, X is an integer greater than 1, and its value may be specified in the protocol or indicated by signaling.

[0180] In this application, the technical features in each implementation can be used in combination in one implementation without causing a contradiction, and each implementation is merely the best implementation of this application.

[0181] This embodiment provides a method for transmitting common control information block configuration information, and this solution can effectively indicate the time and frequency domain resource location of the control resource set without affecting the combined reception of the PBCH (i.e., ensure that the PBCH content in each SS block is the same). Also, by configuring the time domain duration of the control resource set monitoring window and the time domain offset between the monitoring windows corresponding to adjacent SS blocks, the flexibility of the transmission resources of the common control block is increased, and the impact of burst traffic transmission on the common control block transmission is reduced. The noise is successfully avoided.

[0182] EMBODIMENT 4 An embodiment of the present application further provides a storage medium, the storage medium including a program stored thereon, the program being operable, when run, to perform any one of the methods described above.

[0183] In this embodiment, the above-mentioned storage medium may be configured to store program code for executing the following steps S1 and S2.

[0184] In step S1, configuration information of a control resource set is carried on a physical broadcast channel, and at least one of time domain location information and frequency domain location information of the control resource set is indicated to a terminal using the configuration information.

[0185] In step S2, a control resource set is sent to the terminal according to the configuration information. In one embodiment, the storage medium may include any medium capable of storing program code, such as, but not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

[0186] An embodiment of the present application further provides a processor, the processor being configured to run a program, the execution of which, when executed, causes the steps of any one of the above methods to be performed.

[0187] In this embodiment, the following steps S1 and S2 are executed using the above program.

[0188] In step S1, configuration information of a control resource set is carried on a physical broadcast channel, and at least one of time domain location information and frequency domain location information of the control resource set is indicated to a terminal using the configuration information.

[0189] In step S2, a control resource set is sent to the terminal according to the configuration information. In one embodiment, specific examples in this embodiment may refer to the examples described in the above embodiments and best implementation modes, which will not be repeated in this specification.

[0190] Obviously, those skilled in the art will appreciate that the above modules or steps of the present application may be implemented by a general-purpose computing device, may be centralized on a single computing device or distributed over a network of multiple computing devices, in one embodiment may be implemented by executable program code of a computing device, and thus may be stored in a storage device for execution by the computing device, and in some cases, the steps illustrated or described may be performed in a different order than in the order shown herein, or may be assembled into individual integrated circuit modules, or multiple modules or steps may be implemented by assembling them into a single integrated circuit module. Thus, the present disclosure is not limited to any specific combination of hardware and software.

Claims

1. 1. A method comprising: transmitting configuration information of a common control resource set to a terminal on a physical broadcast channel; the common control resource set is for remaining minimum system information (RMSI); The configuration information indicates time domain location information of the common control resource set; The time domain location information of the common control resource set includes: (1) information of a first slot in which the common control resource set exists; (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first slot; and (3) a number of the at least one symbol occupied by the common control resource set in the first slot; the at least one symbol occupied by the common control resource set in the first slot includes at least one of a third symbol, a fifth symbol, a seventh symbol, or a ninth symbol of the first slot; transmitting the common control resource set to the terminal according to the configuration information in the first slot and the second slot, the first slot including a synchronization signal block (SSB) and the second slot not including the SSB; A method according to claim 1, wherein the same resource mapping rule is applied to the common control resource set in both the first slot and the second slot.

2. 2. The method of claim 1, wherein the starting symbol index of the at least one symbol occupied by the common control resource set in the first slot and the starting symbol index of the symbols occupied by the SSB in the first slot are the same.

3. 1. A method comprising: receiving, by a terminal, configuration information of a common control resource set on a physical broadcast channel; the common control resource set is for remaining minimum system information (RMSI); The configuration information indicates time domain location information of the common control resource set; The time domain location information of the common control resource set includes: (1) information of a first slot in which the common control resource set exists; (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first slot; and (3) a number of the at least one symbol occupied by the common control resource set in the first slot; the at least one symbol occupied by the common control resource set in the first slot includes at least one of a third symbol, a fifth symbol, a seventh symbol, or a ninth symbol of the first slot; receiving, by the terminal, the common control resource set in accordance with the configuration information in the first slot and the second slot, the first slot including a synchronization signal block (SSB) and the second slot not including the SSB; A method according to claim 1, wherein the same resource mapping rule is applied to the common control resource set in both the first slot and the second slot.

4. 4. The method of claim 3, wherein the starting symbol index of the at least one symbol occupied by the common control resource set in the first slot and the starting symbol index of the symbols occupied by the SSB in the first slot are the same.

5. 1. A base station comprising a processor, the processor comprising: configured to transmit configuration information of the common control resource set to a terminal on a physical broadcast channel; the common control resource set is for remaining minimum system information (RMSI); The configuration information indicates time domain location information of the common control resource set; The time domain location information of the common control resource set includes: (1) information of a first slot in which the common control resource set exists; (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first slot; and (3) a number of the at least one symbol occupied by the common control resource set in the first slot; the at least one symbol occupied by the common control resource set in the first slot includes at least one of a third symbol, a fifth symbol, a seventh symbol, or a ninth symbol of the first slot; The processor, a base station configured to transmit the common control resource set to the terminal according to the configuration information in the first slot and the second slot, the first slot including a synchronization signal block (SSB), the second slot not including the SSB, and a same resource mapping rule is applied to the common control resource set in both the first slot and the second slot.

6. 6. The base station of claim 5, wherein the starting symbol index of the at least one symbol occupied by the common control resource set in the first slot and the starting symbol index of the symbols occupied by the SSB in the first slot are the same.

7. A terminal including a processor, the processor comprising: configured to receive, on a physical broadcast channel, configuration information of a common control resource set; the common control resource set is for remaining minimum system information (RMSI); The configuration information indicates time domain location information of the common control resource set; The time domain location information of the common control resource set includes: (1) information of a first slot in which the common control resource set exists; (2) a starting symbol index of at least one symbol occupied by the common control resource set in the first slot; and (3) a number of the at least one symbol occupied by the common control resource set in the first slot; the at least one symbol occupied by the common control resource set in the first slot includes at least one of a third symbol, a fifth symbol, a seventh symbol, or a ninth symbol of the first slot; The processor, a terminal configured to receive the common control resource set in accordance with the configuration information in the first slot and the second slot, the first slot including a synchronization signal block (SSB) and the second slot not including the SSB, and a same resource mapping rule is applied to the common control resource set in both the first slot and the second slot.

8. 8. The terminal of claim 7, wherein the starting symbol index of the at least one symbol occupied by the common control resource set in the first slot and the starting symbol index of the symbols occupied by the SSB in the first slot are the same.

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