Noise Mitigation in Single-Ended Links

Abstract

The data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first supply voltage, the transmitter having an input for receiving a data output signal and an output. The second circuit includes a receiver powered by a second supply voltage, the receiver having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms a reference voltage by mixing a first signal generated by the first circuit based on the first supply voltage and a second signal generated by the second circuit based on the second supply voltage.

Description

[Technical field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 232,343, filed August 12, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] Modern single-ended data transmission systems offer significant density advantages at the system level compared to differential signaling. Systems will continue to push single-ended to retain this advantage as we move to higher speeds and higher modulation. Also, the challenges to link performance (e.g. meeting bit error targets, power, area) increase significantly with the need for higher speeds.

[0003] Many of these systems are burst mode in nature. In other words, they remain in a low power state (called idle state) while not in use, and transition to an active state (i.e., normal transmission or reception of data) when necessary. When the physical interface circuit (PHY) goes from an idle state to an active mode, the power delivery network (PDN) deals with the burden of a sudden change in load. The sudden demand for power appears as a step excitation to the PDN, causing a typical network to resonate at its natural frequency. This resonant noise is a major source of error that the link must deal with. [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of a known data transmission system in the background art; [Diagram 2] 1 is a partial block and partial schematic diagram of a data transmission system according to some embodiments. [Diagram 3] 3 is a set of timing diagrams useful in understanding the operation of the data transmission system of FIG. 2. [Figure 4] 3 is a graph showing an example of data eye height and width measured at various data noise frequencies for the data transmission system of FIG. 2; [Diagram 5] 1 is a partial block and partial schematic diagram of a data transmission system useful in a multi-level data transmission system, according to some embodiments; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its associated verbs include both direct and indirect electrical connections by means well known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0006] The data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first supply voltage, the transmitter having an input for receiving a data output signal and an output. The second circuit includes a receiver powered by a second supply voltage, the receiver having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms a reference voltage by mixing a first signal generated by the first circuit based on the first supply voltage and a second signal generated by the second circuit based on the second supply voltage.

[0007] The data transmission system includes a transmitter, a receiver, and a reference voltage generating circuit. The transmitter is powered by a first supply voltage and has an input for receiving a data output signal and an output. The receiver is powered by a second supply voltage and has a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generating circuit includes a driver and a voltage divider. The driver is powered by the first supply voltage and has an input for receiving a predetermined signal and an output. The voltage divider is powered by the second supply voltage and is coupled to the output of the driver and the second input of the receiver, and provides a reference voltage to the receiver.

[0008] The method includes transmitting a data signal from a transmitter of a first integrated circuit operating at a first power supply voltage, the first integrated circuit having a first voltage reference terminal. The data signal is received at a receiver of a second integrated circuit operating at a second power supply voltage, the second integrated circuit having a second voltage reference terminal. Receiving includes comparing the data signal to a voltage at the second voltage reference terminal to provide a received data signal. A shared reference voltage is generated at the first voltage reference terminal and the second voltage reference terminal based on noise in both the first power supply voltage and the second power supply voltage.

[0009] 1 is a block diagram of a known data transmission system 100 in the background art. The data transmission system 100 is a single-ended system and includes an integrated circuit 110, an integrated circuit 120, and a transmission medium .

[0010] The integrated circuit 110 includes a driver 111 and a comparator 112. The driver 111 outputs a signal “DATA OUTA " and an output connected to a terminal of integrated circuit 110, SSA " but not shown in FIG. 1 , forms the overall power supply voltage for integrated circuit 110. DDAComparator 112 has a power supply input for receiving a positive power supply voltage labeled "V REFA a negative input for receiving a reference voltage labeled "DATA"; INA and an output for providing a signal labeled "."

[0011] The integrated circuit 120 includes a driver 121 and a comparator 122. The driver 121 outputs a signal “DATA OUTB " and an output connected to a terminal of integrated circuit 120, SSB " but not shown in FIG. 1 , forms the overall power supply voltage for integrated circuit 120. DDB Comparator 122 has a power supply input for receiving a positive power supply voltage labeled "V REFB a negative input for receiving a reference voltage labeled "DATA"; INB and an output for providing a signal labeled "."

[0012] Transmission medium 130 has a left end connected to a terminal of integrated circuit 110 and a right end connected to a terminal of integrated circuit 120. Transmission medium 130 may be, for example, an integrated circuit trace along a bus in a computer motherboard connected to a microprocessor and its associated memory.

[0013] Each of the drivers 111 and 121 are shown with resistors indicating that they have a drive strength matching the characteristic impedance of the transmission medium 130, and with termination resistors, not shown in FIG. 1, at the inputs to the comparators 112 and 122. Furthermore, the link is bidirectional, with data being transmitted from the integrated circuit 110 to the integrated circuit 120 and vice versa. A typical embodiment of the data transmission system 100 is a physical interface of a graphics processor with a graphics double data rate, version 6 (gDDR6) synchronous dynamic random access memory (SDRAM) and a gDDR6 memory controller. As technology advances, the operating speed of the gDDR memory has increased such that typical gDDR6 data transfer rates are at low (slow speed) to high (fast speed) and high (fast speed) to low (slow speed) transitions of the memory clock, which has a frequency of several GHz. At this high speed, the memory controller needs to train the link by providing precise timing delays so that data can be captured near the center of the "data eye", i.e., in the period and voltage range where data can be reliably captured at the high clock speed.

[0014] The reference voltages at each end of the transmission medium 130 may be calibrated to provide the largest possible data eye. REFA and V REFB However, the noise sources at the ends of the transmission medium 130 are independent from each other, since the power distribution networks are independent as well. These independent noise sources tend to affect the driver and receiver differently, causing the data eye to shrink by reducing both the eye height and the eye width.

[0015] 2 is a partial block and partial schematic diagram of a data transmission system 200 according to some embodiments. The data transmission system 200 generally includes an integrated circuit 210, an integrated circuit 230, and a transmission medium 250.

[0016] The integrated circuit 210 includes a transceiver 211, a data strobe receiver 214, a latch 217, a data strobe driver 218, a voltage divider 220, and a buffer 223. The transceiver 211 includes a transmitter 212 and a receiver 213. The transmitter 212 includes a D OUTA an input for receiving a signal, an output connected to a first terminal of the integrated circuit 210, and a negative power supply voltage V SSA , which together form the overall power supply voltage for integrated circuit 210, “V PHY-A Receiver 213 has a positive input connected to the first integrated circuit terminal and a power supply input labeled "positive power supply voltage V." Receiver 213 has a positive input connected to the first integrated circuit terminal and a reference voltage V REFA a negative input section for receiving a negative input voltage; an output section; and a V PHY-A The data strobe receiver 214 includes a resistor 215 and a comparator 216. The resistor 215 is connected to a power supply input for receiving V PHY-A A comparator 216 operates as a data strobe receiver and has a positive input connected to the second integrated circuit terminal, a reference voltage V REFA a negative input section for receiving a negative input voltage; an output section; and a V PHY-A Latch 217 has a D input connected to the output of receiver 213, a clock input connected to the output of comparator 216, and a D INA Transmitter 218 has an input for receiving the alternating pattern of 1s and 0s labeled "1010" and an output connected to a second integrated circuit terminal.

[0017] The voltage divider 220 includes a resistor 221 and a circuit element 222. The resistor 221 is PHY-Aand a third terminal of the integrated circuit 210 for receiving a voltage V REFA and a second terminal forming a first terminal connected to the second terminal of resistor 221 and a second terminal connected to ground. In some embodiments, circuit element 222 is implemented by an adjustable current source 224 having a first terminal connected to the second terminal of resistor 221 and a second terminal connected to ground. In other embodiments, circuit element 222 is implemented by an adjustable resistor 225 having a first terminal connected to the second terminal of resistor 221 and a second terminal connected to ground. In still other embodiments, circuit element 222 is implemented by a combination of an adjustable current source and an adjustable resistor. Buffer 223 is an optional buffer, shown in dashed lines, having an input connected to the second terminal of resistor 221 and an output connected to the negative inputs of receiver 213 and receiver 216.

[0018] The integrated circuit 230 includes a transceiver 231, a data strobe receiver 234, a latch 237, a data strobe transmitter 238, and a driver 239. The transceiver 231 includes a transmitter 232 and a receiver 233. The transmitter 232 includes a D OUTB an input for receiving a signal and an output connected to a first terminal of the integrated circuit 230, the input being connected to a negative power supply voltage V SSB Together with the V PHY-B Receiver 233 has a power supply input labeled "+" for receiving a positive power supply voltage. Receiver 233 has a positive input connected to the first terminal of integrated circuit 230 and a reference voltage V REFB The data strobe receiver 234 includes a resistor 235 and a comparator 236. The resistor 235 is connected to a resistor V PHY-B a first terminal for receiving a reference voltage V connected to a second terminal of the integrated circuit 230; REFB The receiver 236 has a positive input connected to the second terminal of the integrated circuit 230 and a second terminal forming a reference voltage V REFBLatch 237 has a negative input for receiving a negative input, and an output. Latch 237 has a D input connected to the output of receiver 233, a clock input connected to the output of comparator 236, and a D INB Transmitter 238 has an input for receiving an alternating pattern of 1's and 0's labeled "1010" and an output connected to a second terminal of integrated circuit 230. Driver 239 has an input for receiving a logic high voltage labeled "1" and is connected to a third terminal of integrated circuit 230 and to the negative inputs of receiver 233 and receiver 236, and provides a voltage V REFB and an output section forming V PHY-B and a power input for receiving the power.

[0019] The transmission medium 250 interconnects the integrated circuit 210 and the integrated circuit 230, and includes a set of conductors 251-253. The conductor 251 has a first end connected to a first terminal of the integrated circuit 210 and a second end connected to a first terminal of the integrated circuit 230. The conductor 252 has a first end connected to a second terminal of the integrated circuit 210 and a second end connected to a second terminal of the integrated circuit 230. The conductor 253 has a first end connected to a third terminal of the integrated circuit 210 and a second end connected to a third terminal of the integrated circuit 230.

[0020] As will be described in more detail below, the driver 239 and the voltage divider 220 are connected together by a conductor 253 to form a reference voltage generating circuit 260 .

[0021] The data transmission system 200 bidirectionally interconnects the integrated circuit 210 and the integrated circuit 230 via the transmission medium 250. In the example shown in FIG. 2, the integrated circuit 230 is a data processor with an integrated DDRx memory controller and physical layer interface circuitry, and the integrated circuit 210 is a DDRx memory. The design of the data transmission system 200 varies based on the type of DDRx memory used. For DDR1, as shown in FIG. 1, the integrated circuit 230 uses a data (DQ) signal to send and receive data to and from the integrated circuit 210 based on transitions of a single-ended data strobe signal (DQS). Other generations of DDRx memory include modifications of the data transmission system 200. In another example, the integrated circuit 230 is a graphics processing unit (GPU) with an integrated gDDR memory controller and physical layer interface circuitry, and the integrated circuit 210 is a gDDR memory, such as a gDDR6 SDRAM or a later gDDR version. According to the gDDR6 standard, the data (DQ) terminals are bidirectional terminals, but the clock signals are unidirectional differential signals where the processor provides differential write clock signals (WCK_t and WCK_c) during both read and write cycles. In yet another example, integrated circuit 230 is a central processing unit (CPU) with an integrated DDR memory controller and physical layer interface circuitry, and integrated circuit 210 is a DDR5 SDRAM. According to the DDR5 standard, the data (DQ) terminals are bidirectional terminals that are captured based on a bidirectional differential data strobe signal. At the high speeds at which gDDR6 and DDR5 memory devices can operate, the data processor (GPU or CPU) performs "data eye training" which delays the DQ signal relative to the corresponding clock signal so that the clock signal arrives at the data processor aligned with the center of the data eye of the DQS signal. However, as mentioned above, integrated circuit 210 and integrated circuit 230 are powered by V in the second power domain. PHY-B V in the first power domain that is independent of noise on the power supply PHY-AIt receives power from an independent PDN, such as noise on the power supply. These changes act to close the data eye, i.e., reduce the height and / or width of the data eye.

[0022] However, in accordance with various embodiments disclosed herein, the data transmission system 200 may be configured to operate at a first power supply voltage (e.g., V PHY-A ) based on a first signal generated by a first circuit (e.g., V REFA ) and a second supply voltage (e.g., V PHY-B ) based on a second signal generated by a second circuit (e.g., V generated by driver 239). REFB ) and the reference voltage used in the receiver (e.g., V REFA The reference voltage generating circuit 260 forms a reference voltage V PHY-A and V PHY-B The reference voltage V REFA Next, V REFA are used in receiver 213 and receiver 216 to receive the DQ and DQS signals in integrated circuit 210. Mixing the power supply noise from opposite ends of the communication link to form the reference voltages used in receiving data on a given side of the communication link has the remarkable property of widening the DQ data eye for more robust data reception. REF is V on the PDN of the integrated circuit 210 and the integrated circuit 230. SS In this case, the driver 239 may be V SSB 2. By receiving a logic "0" representing a voltage at its input, voltage divider 220 reverses the order of resistor 221 and circuit element 222 to produce a voltage REFA and V REFB Note that driver 239 has a pull-down drive strength that matches the resistance of resistor 221.

[0023] Furthermore, as will be further explained below, the significantly more robust data reception allows for faster overall data transmission speeds by enabling the implementation of multi-value data transmission and reception systems instead of conventional binary systems. For example, instead of conventional binary data transmission used in existing versions of DDR and graphics DDR standards, a four-value pulse amplitude modulation (PAM4) system may be created, which allows the transmission and reception of two binary bits per clock transition instead of just two. Thus, for a given clock speed, the data transmission bandwidth may be doubled.

[0024] FIG. 3 shows a set of timing diagrams 300 useful for understanding the operation of the data transmission system 200 of FIG. 2. The timing diagrams 300 include data eye diagram 310, data eye diagram 320, data eye diagram 330, and data eye diagram 340. Each data eye diagram has a respective horizontal axis representing time in picoseconds (ps) and a respective vertical axis representing amplitude in volts. Data eye diagram 310, data eye diagram 320, data eye diagram 330, and data eye diagram 340 show waveform clouds resulting from the superposition of both low-to-high and high-to-low transitions with a group of data signals, e.g., bytes, for which the memory controller sets a capture delay. The left column of the diagram, i.e., data eye diagram 311 and data eye diagram 331, show data signals received at integrated circuit 210, where data eye diagram 311 shows the V REF , while data eye diagram 331 illustrates a conventional method of generating V REF Similarly, the right column of the figure, i.e., data eye diagram 321 and data eye diagram 341, show the data signal received at integrated circuit 230, where data eye diagram 321 shows V REF , while data eye diagram 341 illustrates a conventional method of generating V REF As can be clearly seen, the data eye diagram produced using the mixing techniques described herein exhibits a sharper data eye, with a higher eye height and a larger eye width.

[0025] These experimental observations, illustrated in the graph of FIG. 3, confirm the significant improvement in data transmission fidelity using the blending techniques disclosed herein as compared to existing data transmission systems.

[0026] 4 shows a graph 400 illustrating example data eye heights and widths measured at various data noise frequencies for the data transmission system 200 of FIG. 2. In FIG. 4, the horizontal axis represents frequency in Hz, the left vertical axis represents eye height in millivolts (mV), and the right vertical axis represents eye width in ps. Graph 400 includes the V REF Waveform 410 shows the eye height of the data eye using the mixed technique, compared to the conventional V REF FIG. 4 shows a waveform 420 illustrating the eye height of a data eye using the generation technique and the V REF Waveform 430 showing the eye width of the data eye using the mixed technique and the conventional V REF Four waveforms are shown, including waveform 440, which shows the eye height of a data eye using the generation technique. As can be seen from waveforms 410 and 420, the eye height improves by about 37 mV for a 0.8 volt supply through voltage noise frequencies up to about 500 MHz, and then gradually decreases until a crossover point is reached at about 950 MHz. The eye width shows a consistent but less dramatic improvement across all voltage noise frequencies. At the particularly critical voltage noise frequency, i.e., 100 MHz, the eye height improves by 24 mV and the eye width improves by 0.8 ps.

[0027] 5 is a partial block and partial schematic diagram of a data transmission system 500 useful in a multi-level data transmission system, according to some embodiments. The data transmission system 500 includes an integrated circuit 510, an integrated circuit 530, and a transmission medium 550.

[0028] The integrated circuit 510 includes a four-level pulse amplitude modulation (PAM4) receiver 511, a slice level generator 512, and a voltage divider 520. The PAM4 receiver 511 has a signal input connected to a bond pad of the integrated circuit 510, a reference input, and a “D INA an output for providing a decoded voltage signal labeled "V[1:0]"; PHY-A and a power supply input for receiving V. The slice level generator 512 REFA an input for receiving V PHY-A , and an output connected to a second input of the PAM4 receiver 511 and providing three slice levels. The voltage divider 520 includes a resistor 521 and a circuit element 522. The resistor 521 is connected to a power supply input for receiving V PHY-A a first terminal for receiving a V REFA and a second terminal connected to the second terminal of integrated circuit 510. Circuit element 522 has a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. As in voltage divider 220, in some embodiments circuit element 522 is implemented by an adjustable current source having a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. In other embodiments circuit element 522 is implemented by an adjustable resistor having a first terminal connected to the second terminal of resistor 521 and a second terminal connected to ground. In still other embodiments circuit element 522 is implemented by a combination of an adjustable current source and an adjustable resistor.

[0029] The integrated circuit 530 includes a PAM4 transmitter 531 and a driver 535. The PAM4 transmitter 531 is OUTB an input for receiving a 2-bit output signal labeled "V[1:0]"; PHY-B A power input for receiving V REFB A driver 535 has an input for receiving a logic high voltage level labeled "1", an output connected to the first terminal of integrated circuit 230, and a reference input for receiving VPHY-B and a power input for receiving the power.

[0030] Transmission medium 550 includes a conductor 551 and a conductor 552. Conductor 551 has a first end connected to a first terminal of integrated circuit 530 and a second end connected to a first terminal of integrated circuit 510. Conductor 552 has a first end connected to a second terminal of integrated circuit 530 and a second end connected to a second terminal of integrated circuit 510. Driver 535 and voltage divider 520 are connected together by conductor 552 to form reference voltage generating circuit 560.

[0031] The data transmission system 500 operates in much the same way as the data transmission system 200 of Fig. 2, but implements PAM4 encoding and decoding. PAM4 allows for an effective doubling of data transmission throughput for a given clock frequency by encoding two bits of data as one of four voltage levels transmitted on each clock edge. According to PAM4, the voltage levels are encoded into four levels, as shown in Table 1 below.

[0032] [Table 1]

[0033] To decode the voltages into the appropriate symbols and corresponding data, the slice level generator 512 generates a 1 / 4V PHY-A , 1 / 2V PHY-A , and 3 / 4V PHY-A The slice level generator 512 generates three slice levels with values ​​equal to V REFA Based on V, three slice levels may be generated while injecting mixed power supply noise from integrated circuit 510 and integrated circuit 530. In one example, integrated circuit 510 and integrated circuit 530 may PHY-A and V PHY-B At half the voltage, V REFA and V REFB In this case, the slice level generator 512 generates VPHY-A A string of four equal value resistors is incorporated between the power supply and ground, and at the junction between the upper resistor and the upper middle resistor, a 3 / 4V PHY-A At the junction between the lower middle resistor and the lower resistor, PHY-A In this example, the buffer generates a value of V REFA and an output for driving a junction between the upper and lower middle resistors. REFA Since the PDNs of both integrated circuit 510 and integrated circuit 530 are mixed, slice level generator 512 outputs a slice level that has both of these noise components. By using a reference voltage that has power supply noise mixed from both ends of the communication link, the data eye exhibits improved eye opening as described above for binary signal transmission.

[0034] In some embodiments, resistors in a resistor string may be made programmable and trained to set slice levels at crossover points of levels in the data eye. For example, the data eye may exhibit asymmetries that skew the center of the data eye higher or lower. A calibration process may be used to make these adjustments for even more robust data transmission and reception.

[0035] Thus, the techniques disclosed herein may be used to improve data transmission bandwidth by transmitting non-binary symbols, i.e., symbols having more than two states per clock edge. It is believed that noise mitigation techniques may enable reception of PAM4 in systems that are otherwise not robust enough to decode the four voltage levels used in PAM4 symbols at existing clock rates.

[0036] An integrated circuit or integrated circuits including the reference voltage generating circuit or any portion thereof described herein may be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that includes the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0037] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, while this application details a binary (i.e., two-level) data transmission and reception system, in some embodiments, noise mitigation may be used in data transmission systems that transmit more than one bit per clock edge, such as PAM4. Furthermore, different portions of the reference voltage generation circuit may be implemented in different portions of an integrated circuit. Also, the reference voltage generation circuit may have voltage dividers and / or drivers at both ends of the transmission medium or only at one end. The disclosed techniques are applicable to a wide variety of integrated circuits that use high speed data transmission. In one particular example, one integrated circuit may be a data processor, a system on a chip (SOC) or a graphics processing unit (GPU) and the other integrated circuit is a DDR or gDDR SDRAM, although the techniques described herein may be used with many other types of integrated circuits. Also, the transmission medium may vary between embodiments and may include printed circuit board traces, bond wires, through silicon vias (TSVs), etc.

[0038] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. 1. A data transmission system, comprising: a first circuit comprising a transmitter powered by a first supply voltage, the transmitter having an input for receiving a data output signal and an output; a second circuit comprising a receiver powered by a second supply voltage, the receiver having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal; a reference voltage generating circuit that forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage. Data transmission system.

2. The reference voltage generating circuit includes: a driver having an input for receiving a predetermined signal and an output for providing the first signal referenced to the first power supply voltage; a voltage divider powered from a second supply voltage terminal, the voltage divider being coupled to the output of the driver and to the second input of the receiver, the voltage divider providing the reference voltage to the receiver; 2. The data transmission system of claim 1.

3. the transmitter and the driver are on a first integrated circuit; the receiver and the voltage divider are on a second integrated circuit.

3. The data transmission system according to claim 2.

4. The voltage divider comprises: a resistor having a first terminal for receiving the second power supply voltage and a second terminal coupled to the output of the driver for forming the reference voltage; a second circuit element having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 3. The data transmission system according to claim 2.

5. The second circuit element includes: a variable current source having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 5. The data transmission system according to claim 4.

6. The second circuit element includes: a variable resistor having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 5. The data transmission system according to claim 4.

7. 1. A data transmission system, comprising: a transmitter powered by a first supply voltage, the transmitter having an input for receiving a data output signal, and an output; a receiver powered by a second supply voltage, the receiver having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal; A reference voltage generating circuit, The reference voltage generating circuit includes: a driver powered by the first power supply voltage, the driver having an input for receiving a predetermined signal and an output; a voltage divider powered by the second power supply voltage, the voltage divider coupled to the output of the driver and the second input of the receiver, the voltage divider providing the reference voltage to the receiver; Data transmission system.

8. the transmitter is on a first integrated circuit; the receiver is on a second integrated circuit; the output of the transmitter is coupled to the first input of the receiver via a conductor; 8. The data transmission system according to claim 7.

9. The voltage divider comprises: a resistor having a first terminal for receiving the second power supply voltage and a second terminal coupled to the output of the driver for forming the reference voltage; a second circuit element having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 8. The data transmission system according to claim 7.

10. The second circuit element includes: a variable current source having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 10. The data transmission system according to claim 9.

11. The second circuit element includes: a variable resistor having a first terminal coupled to the second terminal of the resistor and a second terminal coupled to ground; 10. The data transmission system according to claim 9.

12. a data strobe driver powered by the first power supply voltage, the data strobe driver having an output for providing a data strobe signal; a data strobe receiver powered by the second power supply voltage, the data strobe receiver having a first input coupled to the output of the data strobe driver, a second input for receiving the reference voltage, and an output; a latch having a data input coupled to the output of the receiver, a clock input coupled to the output of the data strobe receiver, and an output for providing a latched data signal.

8. The data transmission system according to claim 7.

13. the receiver has an input for receiving at least one additional voltage level, an output of the receiver being a multi-bit digital signal, the receiving comprising: using the at least one additional voltage level to decode the multi-bit digital signal; the data transmission system further comprising a slice level generator having an input for receiving the reference voltage and an output coupled to the second input of the receiver for providing the at least one additional voltage level as a plurality of slice levels.

8. The data transmission system according to claim 7.

14. 1. A method comprising: transmitting a data signal from a transmitter of a first integrated circuit operating at a first power supply voltage, the first integrated circuit having a first voltage reference terminal; receiving the data signal at a receiver of a second integrated circuit operating at a second power supply voltage, the second integrated circuit having a second voltage reference terminal, the receiving including comparing the data signal with a voltage on the second voltage reference terminal to provide a received data signal; generating a shared reference voltage on the first voltage reference terminal and the second voltage reference terminal based on noise on both the first power supply voltage and the second power supply voltage. method.

15. Generating the shared reference voltage comprises: coupling the first voltage reference terminal to the second voltage reference terminal; driving the first voltage reference terminal and the second voltage reference terminal from one of the first integrated circuit and the second integrated circuit in response to a predetermined logic level; and dividing a voltage on the second voltage reference terminal using a reference circuit and forming the shared reference voltage in the other of the first integrated circuit and the second integrated circuit in response to said dividing.

15. The method of claim 14.

16. The pressure division includes: dividing the voltage on the second voltage reference terminal using a resistor having a first terminal for receiving the second power supply voltage and a second terminal coupled to the second voltage reference terminal, and a second circuit element having a first terminal coupled to the second voltage reference terminal and a second terminal coupled to ground.

16. The method of claim 15.

17. The pressure division includes: and performing voltage division using a variable current source as the second circuit element.

17. The method of claim 16.

18. The pressure division includes: and dividing the voltage using a variable resistor as the second circuit element.

17. The method of claim 16.

19. The transmitting step includes: transmitting a strobe signal from the first integrated circuit to the second integrated circuit using the first power supply voltage; The receiving includes: receiving the strobe signal at the second integrated circuit using the second power supply voltage and the shared reference voltage to form a received strobe signal; and latching the received data signal using the receive strobe signal.

15. The method of claim 14.

20. The transmitting step includes: transmitting a second data signal from a transmitter of the second integrated circuit; receiving the second data signal at a receiver of the first integrated circuit, the receiving including comparing the second data signal with a voltage on the second voltage reference terminal to provide a received second data signal.

15. The method of claim 14.

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