Driving capability adjustment method and information processing device

Abstract

To provide a drive capability adjustment method and an information processing device for optimizing transmission characteristics between a processor and a memory.SOLUTION: A drive capability adjustment method includes: performing signal transmission according to multiple types of training patterns representing combinations of read and write for each of a plurality of transmission paths connecting a processor and a plurality of memories; acquiring a plurality of eye patterns for each of the memories for each training pattern; determining a strobe point for each of the acquired eye patterns; generating a common eye pattern by superimposing the eye patterns around the determined strobe point for each memory; and adjusting drive capability in communication between the processor and the plurality of memories based on the generated common eye pattern.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a driving capability adjustment method and an information processing device. [Background technology]

[0002] In recent years, the data communication environment between CPU (Central Processing Unit) and memory has become severe due to various factors, such as faster transmission speeds and lower voltages. The data valid window shrinks due to faster speeds and lower voltages, and data communication is required to be performed using the narrowed data valid window, which makes the data communication environment more severe.

[0003] For example, in the case of DDR (Double Data Rate) 4 memory, the transmission speed per channel on a single-ended parallel bus exceeds 2400MT / s. Furthermore, in large-scale systems, the multi-layering of the board makes it more susceptible to noise, and the need to accommodate various memory mounting conditions makes the data communication environment more severe.

[0004] Conventionally, the drive capability of signals required for system operation between the CPU and memory was determined by operating only one memory controller, evaluating the transmission characteristics of read and write operations separately, and pre-evaluating a fixed drive capability.

[0005] For example, a configuration having a CPU and a memory system control unit will be described. The CPU has multiple memory controllers and I / O (Input / Output) circuits. The memory controller controls the transmission and reception of signals between the I / O circuits and the memory. The system control unit monitors and controls the entire device. The system control unit is also connected to the CPU and controls the memory controllers.

[0006] When communicating between the CPU and memory, the following two elements are determined. The first is the drive capacity, which is the signal strength of the memory bus that connects the CPU and memory. Drive capacity is expressed by the resistance value of the circuit that drives the signal, and the lower the value, the higher the drive capacity. The other is the "strobe point," which is the judgment value used when determining whether the transmitted signal is 0 / 1 on the receiving side. The strobe point is setting information that indicates the voltage and time position of the signal waveform when judging the signal. The drive capacity and strobe point are determined through processing by the system control unit.

[0007] Conventionally, these "driving capability" and "strobe point" have been determined as follows. Regarding the driving capability, a pre-evaluation is performed before the shipment of the information processing device, and an eye pattern that indicates the size of the area in which a signal can be judged as 0 / 1 in the communication between the CPU and the memory is measured. Then, the driving capability under the condition that the area of ​​the eye pattern is the largest is determined as the standard fixed setting value for the information processing device. Generally, the more memories connected to one memory bus, the greater the load on the memory bus and the narrower the eye pattern. Therefore, in order to be able to accommodate various memory configurations, the driving capability is set to a strong setting value that can also accommodate the maximum number of memories that will be the maximum load. Therefore, the driving capability determined by the conventional method is actually the optimal setting for the maximum load configuration.

[0008] Next, the strobe point will be explained. The strobe point is determined by automatic adjustment during training between the CPU and memory, which is performed by the system control unit when the device is started. First, the system control unit measures the eye pattern. After that, the system control unit sets the strobe point to a value that is in the middle of both the voltage direction and the time direction of the eye pattern so that 0 / 1 discrimination can be more stable. For this reason, the strobe point is set appropriately for various memory configurations. In cases where the CPU has multiple memory controllers and memory buses, these setting values ​​are determined based on the eye pattern measured by operating only a single memory controller and memory to be evaluated and adjusted.

[0009] However, in the conventional method of setting the driving capacity and strobe point, the determined driving capacity corresponds to the ideal transmission characteristics in a state where various noises are small, so the setting value of the driving capacity is set so as to be compatible with any memory mounting conditions.

[0010] As a technology related to transmission characteristics, there is a technology to evaluate the eye pattern according to the combination of parallel transmission lines running side by side, widen the eye pattern according to the propagation delay, and design it so that the strobe cross point is near the center of the eye pattern. There is also a technology to open the eye by making the output impedance high during the operating state of the reset period or the training period of the bus system, and inserting a resistive element or equalizer. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] JP 2011-010118 A [Patent Document 2] International Publication No. 2017 / 061247 Summary of the Invention [Problem to be solved by the invention]

[0012] However, in system operation after the OS (Operating System) is started, multiple memory controllers may perform read and write operations at the same timing, and it is considered that the transmission characteristics may deteriorate due to the influence of various noises. Therefore, in the conventional method of determining the driving capacity, the driving capacity that optimizes the transmission characteristics in the system operation was different from that at the time of evaluation. In addition to the driving capacity, the adjustment of the strobe point, which is the timing of data acquisition that is automatically adjusted to the optimal value before the system operation starts, may not be optimal because it is performed under conditions with few noises, just like when the driving capacity is determined, and this may cause errors. Therefore, it was difficult to optimize the transmission characteristics with the conventional method of determining the driving capacity and the strobe point.

[0013] In addition, the technology of widening the eye pattern according to the combination of parallel transmission lines according to the propagation delay and setting the strobe point near the center can guarantee the transmission delay, but does not consider the adjustment of the transmission characteristics between the CPU and memory. Therefore, it is difficult to apply this technology to training between the CPU and memory, and it is difficult to optimize the transmission characteristics between the CPU and memory. In addition, the technology of measuring the eye pattern by matching the operating state during the training period to the operating state during the reset period and opening the eye by inserting a resistive element or an equalizer does not provide eye patterns for various access patterns. Therefore, it is difficult to optimize the transmission characteristics between the CPU and memory during actual operation.

[0014] The disclosed technology has been made in consideration of the above, and has an object to provide a driving capability adjustment method and an information processing device that optimize the transmission characteristics between a processor and a memory. [Means for solving the problem]

[0015] In one aspect of the method for adjusting the driving capacity of a memory disclosed in the present application, signal transmission is performed according to multiple types of training patterns that represent combinations of read and write for each of multiple transmission paths connecting a processor and multiple memories, multiple eye patterns are obtained for each of the memories for each training pattern, a strobe point is determined for each of the obtained eye patterns, the eye patterns are superimposed around the strobe point determined for each of the memories to generate a common eye pattern, and the driving capacity in communication between the processor and the multiple memories is adjusted based on the generated common eye pattern. Effect of the Invention

[0016] In one aspect, the present invention can optimize the transmission characteristics between a processor and a memory. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram illustrating an example of a hardware configuration of an information processing system according to an embodiment. [Diagram 2] FIG. 2 is a schematic diagram illustrating a connection between a CPU and a memory according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing an eye pattern of a specific data signal during a read operation. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of the CPU and memory on the transmitting side during a write operation. [Diagram 5] FIG. 5 is a diagram showing an example of eye patterns measured during training with different driving capability settings in a pre-evaluation. [Figure 6] FIG. 6 is a block diagram of a system control unit according to the embodiment. [Figure 7] FIG. 7 is a diagram showing a case where both of the two memory controllers are performing a read operation. [Figure 8] FIG. 8 is a diagram showing a case where both of the two memory controllers are in write operation. [Figure 9]FIG. 9 is a diagram showing a case where one memory controller performs a read operation and the other memory controller performs a write operation. [Figure 10] FIG. 10 is a diagram showing a case where one memory controller performs a write operation and the other memory controller performs a read operation. [Figure 11] FIG. 11 is a diagram for explaining the generation of a common eye pattern during a write operation. [Figure 12] FIG. 12 is a diagram showing an example of a common eye pattern obtained by overlapping eye patterns of a plurality of data signals. [Figure 13] FIG. 13 is a diagram for explaining an example of the adjustment process of the driving capability. [Figure 14] FIG. 14 is a flowchart of a driving capability adjustment process according to the driving capability adjustment method according to the embodiment. [Figure 15] FIG. 15 is a flowchart of the process of measuring an eye pattern using four types of training patterns. [Figure 16] FIG. 16 is a flowchart of the process of weakening the driving capability. [Figure 17] FIG. 17 is a flowchart of a process for strengthening the driving capability. [Figure 18] FIG. 18 is a diagram showing an example of the result when the driving capability is adjusted by training in which each memory is operated independently. [Figure 19] FIG. 19 is a diagram showing an example of a result when the driving capability adjustment method according to the embodiment is used. [Figure 20] FIG. 20 is a diagram showing another example of the result when the driving capability is adjusted by training in which each memory is operated independently. [Figure 21] FIG. 21 is a diagram showing another example of the result when the driving capability adjustment method according to the embodiment is used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, embodiments of the driving capability adjustment method and the information processing device disclosed in the present application will be described in detail with reference to the drawings. Note that the driving capability adjustment method and the information processing device disclosed in the present application are not limited to the following embodiments. EXAMPLES

[0019] 1 is a diagram illustrating an example of a hardware configuration of an information processing system according to an embodiment. The information processing system 1 includes an information processing device 10, a storage device 20, an input device 30, and an output device 40.

[0020] In the conventional method of adjusting the transmission characteristics between the CPU 100 and the memory 200, the drive capacity is often set to a fixed value and a strong setting that increases the amplitude of the signal. Therefore, when the memory 200 is configured other than at maximum load, the size of the eye pattern during the write operation and the read operation becomes asymmetric, and there is a risk of the stability during communication decreasing. This asymmetry also occurs due to the mounting location of the memory 200 and individual variations that occur during manufacturing. Thus, it is difficult to obtain optimal settings for various memory configurations with the conventional method of adjusting the memory drive capacity. In addition, since the conventional adjustment method operates only the memory controller to be adjusted, during system operation in which multiple memory controllers operate simultaneously, the eye pattern shrinks due to the influence of various noises, and the optimal setting value during system operation is not obtained. Thus, it is difficult to obtain optimal setting values ​​during system operation after the OS is started in advance evaluation or training after the device is started.

[0021] Fig. 2 is a schematic diagram showing the connection between a CPU and a memory according to the embodiment. Fig. 2 shows a configuration in which memories 201-203 connected to a memory bus 301 and memories 211-213 connected to a memory bus 302 exist as memory 200. Here, when memories 201-203 and 211-213 are not distinguished from each other, they are called memory 200. Next, three main noises among various noises that affect the transmission characteristics of signals between CPU 100 and memory 200 will be described. Memory buses 301 and 302 are an example of "multiple transmission paths connecting a processor and multiple memories".

[0022] The first type of noise is crosstalk noise that occurs between adjacent signals. Crosstalk noise occurs because data signals run in parallel within the same memory bus, such as memory bus 301 or 302. Furthermore, in the case of a configuration with multiple memory buses, crosstalk noise occurs when a read operation or a write operation occurs at the same timing between memory bus 301 and memory bus 302. The amplitude of the write waveform is large at I / O control unit 113, which is the transmitting end of CPU 100, and has a large effect on the read waveform of I / O control unit 114, which is the other receiving end of CPU 100, and these cause the waveform to be distorted. In addition, the amplitude of the read waveform transmitted from memory 200 at the receiving end of memory 200 is large, and has a large effect on the write waveform received by the other memory 200, which also causes the waveform to be distorted. Large distortion of the waveform causes a transmission error.

[0023] The second type of noise is reflected noise that occurs when multiple memories 201-203 and 211-213 are mounted on each of the memory controllers 111 and 112, as shown in Fig. 2, or when the mounted memories 200 are of different ranks. This is caused by a lack of impedance matching in the transmission path. This type of reflected noise also causes waveform distortion.

[0024] The third type of noise is simultaneous switching noise, which occurs due to the fact that the memory 200 uses a parallel bus and a single-ended transmission method. Simultaneous switching noise occurs when transistors in the same power supply and ground are turned on and off at the same time. When simultaneous switching noise occurs, the power supply voltage and ground voltage fluctuate, increasing jitter in the circuit and reducing the timing margin.

[0025] These noises are correlated with the driving power of the signal, and can be improved by weakening the driving power. However, if the driving power is weakened too much, the original communication cannot be performed, so determining the optimal driving power is important for stable communication.

[0026] Next, an eye pattern measured when performing training for read and write between the CPU 100 and the memory 200 will be described. An eye pattern, which is a waveform indicating whether each data signal can be received in the I / O control units 113 and 114 of the CPU 100 during read training, will be used for the explanation. FIG. 3 is a diagram showing an eye pattern of a specific data signal during a read operation. In FIG. 3, the horizontal axis represents time and the vertical axis represents voltage. Here, one unit on the time axis is called a tap, and the time axis represents the tap value in the I / O control units 113 and 114 of the CPU 100. Here, one unit on the voltage axis is called a code, and the voltage axis represents the code value of the threshold voltage for determining the signal in the I / O control units 113 and 114. In the following, the directions relative to the eye pattern are expressed using up, down, left, and right as viewed from the paper surface in the diagram showing the eye pattern. The eye pattern 310 in FIG. 3 has a margin of 7 codes above the strobe point 311, a margin of 6 codes below, a margin of 7 taps to the left, and a margin of 8 taps to the right. The margin is a transmission allowance for preventing errors from occurring during signal transmission.

[0027] Conventionally, the system control unit 12 changes the settings of two parameters, namely delay tap and code, which are represented on the time axis and voltage axis, by instructing the memory controller 111 to change the settings. The system control unit 12 then compares a PRBS (Pseudo Random Binary Sequence) data pattern, which is a pseudorandom binary signal sequence received by the I / O control unit 113, with a PRBS pattern generated internally by the memory controller 111. Using the comparison result, the system control unit 12 judges whether the PRBS data pattern received by the I / O control unit 113 is correct. If the received data pattern matches the expected pattern, the system control unit 12 judges that there is no error. The system control unit 12 holds the judgment result, and obtains an eye pattern by changing the two parameters over a wide range and checking the presence or absence of errors at each point. The value 0 in FIG. 3 indicates that transmission is possible without errors, and the value 1 indicates that transmission is impossible due to the presence of errors. In the following, the region in the eye pattern where transmission is possible without errors may be referred to as the "eye pattern opening."

[0028] Conventionally, the strobe point was determined at the center of the eye pattern by this training adjustment performed by the system control unit 12. For example, in this case of Fig. 3, the opening of eye pattern 310 is 7 codes and 6 codes above and below the center of strobe point 311, respectively, and 7 taps and 8 taps to the left and right, respectively. From this, it can be seen that the lower margin of eye pattern 310 is relatively small. The calculation of the number of taps and the number of codes is also performed by the system control unit 12.

[0029] Here, consider an eye pattern that indicates whether or not a signal can be received in memory 200 during write training. The time axis of the eye pattern of memory 200 can be set by changing the delay at the time of transmission of I / O control units 113 and 114 of CPU 100. The setting of the threshold voltage of the voltage axis of the eye pattern of memory 200 is changed according to the control of memory 200 by memory controller 112. Whether or not a signal can be transmitted during this training is determined by looping back the signal received by memory 200 and having CPU 100 receive it. However, an eye pattern is acquired for each data bit of memory 200. For example, when the bus width of memory buses 301 and 302 is 72 bits, eye patterns for the number of data bits according to the bus width of memory buses 301 and 302 (for example, 72) are acquired for each memory 200.

[0030] Next, a conventional method of determining driving capability by prior evaluation will be described. FIG. 4 is a circuit diagram showing the configuration of a CPU and memory on the sending side during a write operation. Here, the CPU 100 has an I / O interface 150, and the memory 200 has an I / O interface 220. In the I / O interface 150 of the CPU 100 on the sending side, a variable resistor is connected to the power supply side and the ground side of the signal line, and when a signal is driven at H level, the ground side is disconnected and connected to the power supply side. On the other hand, in the I / O interface 220 of the memory 200 on the receiving side, a variable resistor is connected to the power supply side. The variable resistor can be set to either 34Ω or 48Ω. The relationship between driving capability and amplitude according to the set value, which is a resistance value, is such that the smaller the set value, the stronger the driving capability and the larger the amplitude. On the other hand, the larger the set value, the weaker the driving capability and the smaller the amplitude. The value of this variable resistor indicates the driving capability of the CPU 100.

[0031] Traditionally, the drive capacity setting was determined by changing the setting value for various memory configurations in advance evaluation and observing the write eye pattern during training. The wider the eye pattern, the better the transmission quality and the lower the probability of errors occurring. If the drive capacity is too strong, the write amplitude will become larger and the eye pattern will widen, but when the system is running after the OS starts up, the drive capacity will be too strong, increasing various noises and causing errors during read operations. In that case, even if the write eye pattern during training is open, it is difficult to use that setting value.

[0032] For example, Figure 5 shows an example of eye patterns measured during training with different drive capacity settings in a pre-evaluation. From the left on the page, the eye patterns are shown when the drive capacity is set to 40Ω, 34Ω, and 30Ω. When the drive capacity is set to 40Ω, the eye pattern opening during write operation is small. When the drive capacity is set to 30Ω, the eye pattern opening for write is large, but with this setting, an error occurred in the read operation when the system was running after the OS started up. Therefore, the setting in this case is set to 34Ω, which does not cause errors even in read operation.

[0033] Next, a measurement process of the strobe points of the read and write waveforms by conventional training will be described. First, the driving capability determined by a prior evaluation is set. Next, the memory bus 301 to be trained is set to a read operation by the memory controller 111, the eye patterns of the memories 201 to 203 are measured, and the strobe point is determined. At this time, the memory bus 302 is stopped. After that, the eye pattern of the memory bus 302 is measured, and the strobe point is determined. Next, the memory bus 301 is set to a write operation by the memory controller 111, the eye patterns of the memories 201 to 203 are measured, and the strobe point is determined. After that, the eye pattern during the write operation of the memory bus 302 is measured, and the strobe point is determined. After the training is completed, during the system operation after the OS is started, the multiple memory controllers 111 and 112 operate simultaneously, and the read operation and the write operation occur at the same timing. Due to various noises generated at this time, the eye pattern shrinks during both the read operation and the write operation.

[0034] Next, a method for determining the strobe point from the measured eye pattern will be described. The system control unit 12 determines the strobe point based on the measurement data. First, the eye pattern is measured. Next, the margins, which are the number of code margins to the upper and lower boundaries that can be transmitted at each point in the eye pattern, which is the transmission possible area, are respectively determined. Next, the margins, which are the number of delay tap margins to the left and right boundaries that can be transmitted, are determined. Next, the delay represented on the time axis is changed, and the calculation of the margins to the upper, lower, left and right boundaries is repeated. Next, the code of the threshold voltage is changed, and the calculation of the margins is repeated in the same manner. In this way, the upper and lower code margins and the left and right tap margins at each point in the eye pattern are determined. Next, the minimum number of taps or the number of codes at each point in the transmission possible area is determined. The above processing is performed for all points in the transmission possible area. Next, the point at which the margin, which is the number of margins in the obtained transmission possible area, is maximum is determined, and this point is determined as the strobe point, and the processing ends. The strobe point is also determined for each data bit of the memory 200. For example, if the bus width of the memory buses 301 and 302 is 72 bits including an error correction code, a strobe point is determined for every 72 data bits.

[0035] Here, the shift of the strobe point that causes an error during system operation will be explained. As an example, consider two eye patterns, one in which the eye pattern of the read is reduced and the other in which it becomes distorted. In order to widen the eye pattern during write operation, the driving power is increased, but this increases noise and causes the eye pattern of the read to be reduced. For example, if the driving power of the CPU 100 is too strong, the eye pattern of the write during system operation will be expanded, but the eye pattern of the read will be reduced due to noise. In this case, the eye pattern of the read will be reduced, but the strobe point will not be shifted from the center of the eye pattern. Also, there are cases where the eye pattern of the read will be reduced due to excessive driving power, and the eye pattern of the read during system operation will be distorted due to noise. The eye pattern during training is a normal circle or ellipse, and the strobe point is set at the center of the eye pattern, but the shape of the eye pattern will change during subsequent system operation, and the strobe point may be shifted from the center of the eye pattern.

[0036] From the above, there are two problems with the conventional method of adjusting transmission characteristics. One is that there is a difference in noise between training after the device is started and system operation after the OS is started, and the opening of the eye pattern is different. In a case where multiple memory buses are installed, such as in a large-scale system, read operations and write operations may occur simultaneously in multiple memory controllers 111 and 112 during system operation. Therefore, there is a difference in the opening of the eye pattern during training, which is adjusted individually for each memory controller 111 and 112, and during system operation. The other is that the eye patterns during read operation and write operation become unbalanced due to the set driving capacity being too strong. In other words, one of the eye patterns shrinks. For example, if the CPU driving capacity is too strong, the eye pattern during write operation opens, but the noise becomes large and the eye pattern during read operation shrinks. Since the strobe point is determined from the shape of the eye pattern during training, if the shape becomes distorted due to various noises during system operation as explained above, the strobe point may not be optimal. In the case of a normal circular eye pattern, the strobe point is at the center of the eye pattern, but in the case of an eye pattern with a distorted shape, for example, there is a risk of problems such as a reduction in the transmission margin on the lower side. For example, if the strobe point is on the boundary of the transmission area, it may cause errors.

[0037] Therefore, the driving capability adjustment method according to this embodiment improves the transmission characteristics by setting an optimal driving capability for each memory 200, and further enables adjustment of the strobe point with higher accuracy than before by performing training under a condition equivalent to the system operation. The procedure for determining the eye pattern and the strobe point by the driving capability adjustment method according to this embodiment will be described below.

[0038] 1, the information processing device 10 includes a main board 11 and a system control unit 12. The information processing device 10 also includes a PCI (Peripheral Component Interconnect) interface 13, a LAN (Local Area Network) interface 14, and a SATA (Serial Advanced Technology Attachment) interface 15. The information processing device 10 also includes a power supply unit 16 and a cooling fan 17.

[0039] A CPU 100 and a memory 200 are mounted on the main board 11. In this embodiment, the CPU 100 and the memory 200 are connected as shown in FIG.

[0040] The system control unit 12 has a Synchronous Dynamic Random Access Memory (SDRAM) 121, a Micro Processor Unit (MPU) 122, and an SD (registered trademark) card 123. The MPU 122 performs arithmetic processing and controls the CPU 100 by outputting commands to the CPU 100 and transmitting and receiving data. The SDRAM 121 is a main storage device used by the MPU 122. The SD card 123 is a main storage device used by the MPU 122. Although the processing by the system control unit 120 is actually executed by the MPU 122, the following description will be given assuming that it is executed by the system control unit 12.

[0041] The PCI interface 13 is connected to a PCI device and relays data transmission and reception between the connected PCI device and the CPU 100. The LAN interface 14 is connected to a network and relays communications between other information processing devices and the CPU 100. The SATA interface 15 is connected to a device conforming to the SATA standard and relays data transmission and reception between the connected device and the CPU 100.

[0042] The power supply unit 16 supplies power for driving the main board 11, the system control unit 12, the PCI interface 13, the LAN interface 14, the SATA interface 15, and the cooling fan 17. The cooling fan 17 blows air to the main board 11, the system control unit 12, etc. to cool them.

[0043] Further, the CPU 100 is connected to a storage device 20, an input device 30, and an output device 40 via a bus. The storage device 20 has a HDD (Hard Disk Drive) 21, which is an auxiliary storage device. Various programs, data, etc. are stored in the HDD 21. The various programs stored in the HDD 21 are read by the CPU 100 and executed using the data stored in the HDD 21, etc. The input device 30 includes, for example, a keyboard 31. The input device 30 may also include a mouse, etc. An operator inputs commands and data to the CPU 100 using the input device 30. The output device 40 includes a display 41. The operator checks images, messages, etc. displayed on the display 41 and performs input using the input device 30.

[0044] A CPU 100 and a memory 200 are mounted on the main board 11. In this embodiment, the CPU 100 and the memory 200 are connected as shown in FIG.

[0045] The CPU 100 according to this embodiment includes memory controllers 111 and 112, and I / O control units 113 and 114. The memory controller 111 is connected to a memory bus 301 via the I / O control unit 113. Memories 201 to 203 are connected to the memory bus 301. The memory controller 111 transmits and receives data to and from the memories 201 to 203 via the memory bus 301.

[0046] The CPU 100 operates according to the driving capability determined by the system control unit 12. The CPU 100 reads out various programs stored in the HDD 21, loads them into the memories 201 to 203, and executes them.

[0047] The system control unit 12 executes the following process when training the communication between the CPU 100 and the memory 200 at the start of the information processing device 10, and determines the strobe point and the driving capability of the CPU 100. Fig. 6 is a block diagram of a system control unit according to an embodiment. The system control unit 12 includes an eye pattern measuring section 401, a strobe point determining section 402, a common eye pattern generating section 403, and a driving capability adjusting section 404.

[0048] The eye pattern measurement unit 401 causes communication between the CPU 100 and the memories 201-203 and 211-213 using the memory buses 301 and 302, and acquires the respective eye patterns for each data bit of the memory 200. For example, when the bus width of the memory buses 301 and 302 is 72 bits including error correction codes and the number of data bits is 72, the eye pattern measurement unit 401 acquires 72 eye patterns for each memory 200 during each of the read operation and the write operation. The following description will be given assuming that the number of data bits of the memory 200 is 72.

[0049] The eye pattern measuring unit 401 operates the memory controllers 111 and 112 in four patterns described below. FIG. 7 is a diagram showing a case where both of the two memory controllers are operated in a read operation. FIG. 8 is a diagram showing a case where both of the two memory controllers are operated in a write operation. FIG. 9 is a diagram showing a case where one memory controller is operated in a read operation and the other memory controller is operated in a write operation. FIG. 10 is a diagram showing a case where one memory controller is operated in a write operation and the other memory controller is operated in a read operation. The eye pattern measuring unit 401 performs training in each of the training patterns shown in FIGS. 7 to 10. This makes it possible to create an operating environment equivalent to the system operation, and by adjusting the strobe point in this operating environment, it becomes possible to adjust the transmission characteristics suitable for the system operation.

[0050] Eye pattern measuring unit 401 acquires eye patterns of each of the data signals for each of the 72 data bits of memory 200 measured using each of the training patterns in Figures 7 to 10. In order to acquire eye patterns for each data bit, eye pattern measuring unit 401 acquires multiple eye patterns for each of memories 201 to 203 and 211 to 213 using multiple data signals. Since the number of data bits is 72 in this example, eye pattern measuring unit 401 acquires 72 eye patterns for each of the four training patterns for each of memories 201 to 203 and 211 to 213 using data signals #0 to #71.

[0051] Specifically, the eye pattern is measured with the following combinations: Measurement of the eye pattern with a combination of read and write from memory controller 111 and memory controller 112 will be described.

[0052] In the case of reads, the memory controllers 111 and 112 measure the eye pattern on the CPU 100 side, and therefore do not measure the eye patterns on the memories 201-203 and 211-213 side. There are four training patterns for combinations of reads and writes between the memory controllers 111 and 112: "read, read", "read, write", "write, read", and "write, write". For the read eye patterns on the CPU 100 side, the memory controller 111 measures two combinations of "read, read" and "read, write". Furthermore, the memory controller 112 measures two combinations of "read, read" and "write, read".

[0053] On the other hand, in the case of writing, eye patterns on the memories 201-203 and 211-213 sides are measured. Therefore, for the above four training patterns, two combinations of "write, read" and "write, write" are measured in the memories 201-203. Also, two combinations of "write, read" and "write, write" are measured in the memories 211-213.

[0054] Thereafter, the eye pattern measuring section 401 outputs the measured eye pattern for each data bit to the strobe point determining section 402 .

[0055] The strobe point determination section 402 receives an input of the eye pattern for each data bit for each of the four training patterns from the eye pattern measurement section 401. Next, the system control unit 12 determines the strobe point for each eye pattern.

[0056] Specifically, taking a specific eye pattern as an example, the strobe point determination unit 402 obtains a margin, which is the number of code margins to the upper and lower boundaries that can be transmitted at each point in the eye pattern. Next, the strobe point determination unit 402 obtains a margin, which is the number of delay tap margins to the left and right boundaries that can be transmitted. Next, the strobe point determination unit 402 changes the delay represented on the time axis and repeats the calculation of the margins to the upper, lower, left and right boundaries. Next, the strobe point determination unit 402 changes the code of the threshold voltage and similarly repeats the calculation of the margin. In this way, the strobe point determination unit 402 obtains the number of code margins above and below and the number of tap margins to the left and right at each point in the eye pattern. Next, the strobe point determination unit 402 obtains the minimum number of taps or the number of codes at each point in the transmission possible area for all points in the transmission possible area. Next, the strobe point determination unit 402 determines the point where the minimum margin in the obtained transmittable area is the largest as the strobe point in that eye pattern. After that, the strobe point determination unit 402 outputs information on the eye patterns for each data bit in the memory 200 corresponding to the four training patterns and information on the strobe points in each eye pattern to the common eye pattern generation unit 403.

[0057] Furthermore, the strobe point determination unit 402 notifies the CPU 100 of information on the strobe points for each data bit of the memory 200. Here, four strobe points are determined for each data bit for each training pattern. The strobe point determination unit 402 then uses the four strobe points to determine the strobe point for each data bit. For example, the strobe point determination unit 402 determines, for each data bit, the strobe point that has the largest minimum margin among the four strobe points in the four eye patterns as the strobe point for that data bit. Then, the strobe point determination unit 402 notifies the CPU 100 of information on the determined strobe points for each data bit.

[0058] As described below, the system control unit 12 generates a common eye pattern based on the strobe points and determines the driving capability, but the strobe points of this common eye pattern are not used as the strobe points used during actual system operation. The strobe points determined for each data bit by the strobe point determination unit 402 and notified to the CPU 100 are used as the strobe points during actual system operation.

[0059] The common eye pattern generating unit 403 receives information on eye patterns for each data bit of the memory 200 corresponding to the four training patterns and information on strobe points in each eye pattern from the strobe point determining unit 402. Next, the common eye pattern generating unit 403 generates a common eye pattern used to determine the drive capability of the CPU 100 for each memory 200 and for each read and write from the acquired eye pattern for each data bit. The generation of the common eye pattern used to determine the drive capability of the CPU 100 will be described in detail below. Conventionally, the strobe point has been used for binary judgment of each data signal, but in the drive capability adjustment method according to this embodiment, the strobe point is also used to adjust the drive capability.

[0060] The common eye pattern generating unit 403 overlaps the eye patterns during read operation corresponding to each training pattern for each memory 200, centering on the strobe point. The common eye pattern generating unit 403 also overlaps the eye patterns during write operation corresponding to each training pattern for each memory 200, centering on the strobe point. That is, the common eye pattern generating unit 403 uses the strobe point to align the centers of the eye patterns. The reason for overlapping the eye patterns is that it takes time to adjust the driving capability for each data signal, and in addition, the characteristics of the data signals are almost the same in the memory 200, so that the characteristics of the acquired data signals can be used without being impaired even when overlapped.

[0061] Fig. 11 is a diagram for explaining generation of a common eye pattern during a write operation. For example, as shown in Fig. 11, the common eye pattern generating unit 403 acquires an eye pattern for each data bit during a write operation using data signals #0 to #71 in the memory 213, as exemplified by eye patterns 501 to 508. Next, the common eye pattern generating unit 403 generates a common eye pattern 510 in the memory 213 by overlapping all the acquired eye patterns during the write operation, including the eye patterns 501 to 508, with the strobe point as the center.

[0062] Fig. 12 is a diagram showing an example of a common eye pattern obtained by superimposing eye patterns of a plurality of data signals. For example, when generating a common eye pattern during a write operation, the common eye pattern generating unit 403 superimposes all eye patterns for each data bit during a write operation, including eye patterns 521 and 522, for a specific memory 200, as shown in Fig. 12. Then, the common eye pattern generating unit 403 generates a common eye pattern 523, which has an eye pattern that is a common region of all eye patterns for each data bit during a write operation, including eye patterns 521 and 522.

[0063] 11, the common eye pattern generating unit 403 generates a common eye pattern 511 during a write operation for the memory 211, and generates a common eye pattern 512 during a write operation for the memory 212, in the same manner as the memory 213. The common eye pattern generating unit 403 also generates a common eye pattern during a read operation for the memories 211 to 213. Furthermore, the common eye pattern generating unit 403 generates a common eye pattern during a write operation and a common eye pattern during a read operation for the memories 201 to 203. That is, the common eye pattern generating unit 403 generates a common eye pattern during a write operation and a common eye pattern during a read operation for each memory 200. Thereafter, the common eye pattern generating unit 403 outputs the generated common eye pattern during a write operation and a common eye pattern during a read operation for each memory 200 to the drive capability adjusting unit 404.

[0064] At the time of startup, the driving capability adjustment unit 404 notifies an initial setting value of the driving capability and sets the driving capability of the CPU 100. For example, the initial setting value of the driving capability can be 40Ω.

[0065] Thereafter, the drive capability adjustment unit 404 receives inputs of the common eye pattern during write operation and the common eye pattern during read operation for each memory 200 from the common eye pattern generation unit 403. Next, the drive capability adjustment unit 404 compares the size of the common eye pattern during read operation and the common eye pattern during write operation for each memory 200, and changes the drive capability of the CPU 100 so as to achieve a balance. Here, the common eye pattern during write operation becomes larger in proportion to the drive capability of the CPU 100. On the other hand, since the common eye pattern during read operation becomes smaller due to the influence of the drive capability of the CPU 100, the common eye pattern during read operation can be made larger by reducing the drive capability of the CPU 100.

[0066] Specifically, the drive capacity adjustment unit 404 holds in advance the amount of change for each stage of drive capacity. Then, the drive capacity adjustment unit 404 compares the common eye pattern during the read operation of each memory 200 with the common eye pattern during the write operation, and performs the following process for each memory 200. For example, if the common eye pattern during the write operation is more open, the drive capacity adjustment unit 404 weakens the setting of the drive capacity of the CPU 100 by one step. Conversely, if the common eye pattern during the write operation is more closed, the drive capacity adjustment unit 404 strengthens the setting of the drive capacity of the CPU 100 by one step. The drive capacity adjustment unit 404 adjusts the drive capacity of the CPU 100 for all the memories 200 mounted.

[0067] After changing the driving capability of CPU100 for each memory 200, driving capability adjustment unit 404 sets the changed driving capability in CPU100. Furthermore, driving capability adjustment unit 404 notifies eye pattern measurement unit 401 of the change in driving capability and instructs readjustment of the driving capability. As a result, eye pattern measurement unit 401, strobe point determination unit 402, and common eye pattern generation unit 403 generate a common eye pattern during a write operation and a common eye pattern during a read operation for each memory 200 when CPU100 is operated with the changed driving capability. Driving capability adjustment unit 404 changes the driving capability of CPU100 again so as to achieve balance using the common eye pattern during a write operation and the common eye pattern during a read operation for each memory 200 when CPU100 is operated with the changed driving capability.

[0068] The drive capability adjustment unit 404 repeats changing the drive capability of the CPU 100 until the common eye pattern magnitudes during write and read operations of all memories 200 are balanced. When the common eye pattern magnitudes during write and read operations of all memories 200 are balanced, the drive capability adjustment unit 404 determines the drive capability at that time as the drive capability of the CPU 100. The drive capability adjustment unit 404 then sets the determined drive capability in the CPU 100, and causes the CPU 100 to operate at the determined drive capability during actual operation.

[0069] 13 is a diagram for explaining an example of the adjustment process of the driving capability. Table 601 shows the common eye pattern during read operation and write operation when a plurality of memory controllers 111 and 112 and a plurality of memories 201-203 and 211-213 are mounted and the driving capability is set to an initial setting value of 40Ω. Here, for convenience of explanation, the opening of the common eye pattern is simply divided into three stages, large, medium and small, but in reality, the opening of the common eye pattern can be expressed by the number of timing taps and the number of threshold voltage codes.

[0070] In table 601, it can be seen that the common eye pattern during read operation and write operation is not balanced in some memories 200. For example, when the driving capability of memory 201 of memory controller 111 is 40Ω, the common eye pattern during write operation is sufficiently open, but the common eye pattern during read operation is somewhat small. Therefore, drive capability adjustment unit 404 determines that the driving capability of memory 201 is somewhat too strong, and changes the driving capability to 48Ω by lowering it by one step. On the other hand, the common eye pattern during write operation of memory 202 of memory controller 111 is small, and the common eye pattern during read operation is large. Therefore, drive capability adjustment unit 404 determines that the driving capability of memory 202 is too weak, and increases the driving capability by one step to 34Ω. Drive capability adjustment unit 404 performs the same adjustment for memories 203 and 211 to 213.

[0071] After that, the common eye pattern is measured again with the changed settings. Table 602 shows the common eye pattern obtained again with the changed settings. From this, it can be seen that the common balance between the read operation and the write operation is better in each memory 200 than in the case of the initial setting value. However, since the balance is not yet achieved in some memories 200, the drive capacity adjustment unit 404 performs the adjustment again. For example, in table 602, in the memory 202 of the memory controller 111, the common eye pattern in the write operation is still small, and the common eye pattern in the read operation is still large. Therefore, the drive capacity adjustment unit 404 determines that the drive capacity of the memory 202 is too weak, and increases the drive capacity setting by one step to 30Ω. The setting value of the memory 200 that is balanced is maintained without being changed. After the readjustment, the drive capacity adjustment unit 404 obtains the common eye pattern again. At this time, the drive capacity adjustment unit 404 measures the common eye pattern again for the memory 200 that was balanced. This is because a change in the setting of the driving capability of another memory 200 may affect and change the opening of the common eye pattern.

[0072] Table 603 shows the common eye pattern after the second readjustment. It can be seen from table 603 that the read and write are balanced in all memories 200. Therefore, the driving capability adjustment unit 404 finishes adjusting the driving capability. As a result, the common eye pattern in all mounted memories 200 becomes large or medium, and can clear the reference value set as medium or above here.

[0073] 14 is a flowchart of the driving capability adjustment process by the driving capability adjustment method according to the embodiment. Next, the flow of the driving capability adjustment process by the driving capability adjustment method according to the embodiment will be described with reference to FIG.

[0074] The driving capability adjusting unit 404 sets the driving capability of the CPU 100 to an initial setting value (step S1).

[0075] The eye pattern measuring section 401 selects one training pattern from the unselected training patterns, and acquires the operating conditions according to the selected training pattern (step S2).

[0076] Next, the eye pattern measuring section 401 sets the acquired operating conditions in the memory buses 301 and 302 via the memory controllers 111 and 112 (step S3).

[0077] Next, the eye pattern measuring unit 401 measures the eye pattern for each data bit of each memory 200 when communication is performed between the CPU 100 and the memory 200 under the set operating conditions (step S4). Then, the eye pattern measuring unit 401 outputs the acquired eye pattern for each data bit of each memory 200 to the strobe point determining unit 402.

[0078] The strobe point determination unit 402 receives an input of an eye pattern for each data bit of each memory 200 from the eye pattern measurement unit 401. Then, the strobe point determination unit 402 determines a strobe point in each eye pattern (step S5). After that, the strobe point determination unit 402 outputs information on each eye pattern and information on the strobe points of each eye pattern to the common eye pattern generation unit 403.

[0079] After that, the eye pattern measuring unit 401 judges whether or not the measurement of the eye pattern has been completed for all the training patterns (step S6). If the training patterns remain (step S6: No), the eye pattern measuring unit 401 returns to step S2.

[0080] On the other hand, if all the training patterns have been completed (step S6: Yes), the common eye pattern generation unit 403 overlaps eye patterns for each data bit, centering on the strobe point for each read operation and write operation. Then, the common eye pattern generation unit 403 generates common eye patterns for each read operation and write operation for each memory 2000, taking the common part of the overlapped eye patterns as a common eye pattern (step S7). Thereafter, the common eye pattern generation unit 303 outputs each generated common eye pattern to the drive capability adjustment unit 404.

[0081] The driving capability adjustment unit 404 acquires the common eye patterns during the read operation and the write operation for each memory 200 from the common eye pattern generation unit 403. Next, the driving capability adjustment unit 404 obtains the center of each common eye pattern (step S8).

[0082] Next, the driving capability adjusting section 404 obtains the margins above, below, left and right from the center of each common eye pattern (step S9).

[0083] Then, based on the margins above, below, left, and right from the center of each common eye pattern, the drive capability adjustment unit 404 determines whether the common eye pattern during read and write operations of each memory 200 is equal to or greater than a predetermined reference value (step S10).

[0084] If there is a common eye pattern less than the reference value (step S10: No), the drive capability adjustment unit 404 determines whether there is a memory 200 having a small common eye pattern during a read operation and a large common eye pattern during a write operation (step S11). If there is no memory 200 having a small common eye pattern during a read operation and a large common eye pattern during a write operation (step S11: No), the drive capability adjustment unit 404 proceeds to step S13.

[0085] On the other hand, if there is a memory 200 with a small common eye pattern during a read operation and a large common eye pattern during a write operation (step S11: Yes), the driving capability adjustment unit 404 weakens the driving capability of the CPU 100 for that memory 200 (step S12).

[0086] Next, the drive capability adjustment unit 404 determines whether or not there is a memory 200 having a large common eye pattern during a read operation and a small common eye pattern during a write operation (step S13). If there is no memory 200 having a large common eye pattern during a read operation and a small common eye pattern during a write operation (step S13: No), the drive capability adjustment unit 404 proceeds to step S15.

[0087] On the other hand, if there is a memory 200 with a large common eye pattern during read operation and a small common eye pattern during write operation (step S13: Yes), the driving capability adjustment unit 404 strengthens the driving capability of the CPU 100 for that memory 200 (step S14).

[0088] Thereafter, the driving capability adjustment unit 404 notifies the memory controllers 111 and 112 of the determined driving capabilities of the CPU 100 for each memory 200, and sets the driving capabilities of the CPU 100 (step S15). Then, the driving capability adjustment process returns to step S2.

[0089] On the other hand, if the common eye patterns during read and write operations of each memory 200 are all equal to or greater than the reference value (step S10: Yes), the driving capacity adjustment unit 404 sets the driving capacity at that time as the driving capacity of the CPU 100 during actual operation, and ends the adjustment of the driving capacity.

[0090] Fig. 15 is a flowchart of the process of measuring eye patterns using four types of training patterns. Each process in the flow of Fig. 15 corresponds to an example of the process executed in steps S1 to S6 in the flow of Fig. 14. Next, the flow of the process of measuring eye patterns using four types of training patterns will be described with reference to Fig. 15.

[0091] The eye pattern measurement unit 401 sets both of the memory buses 301 and 302 for read operation. Then, the eye pattern measurement unit 401 acquires the communication results during the read operation using the memory buses 301 and 302 between the CPU 100 and the memory 200 from the I / O control units 113 and 114. Next, the eye pattern measurement unit 401 acquires the eye pattern for each data bit of the memory 200 from the acquired communication results. The strobe point determination unit 402 determines the strobe point in the eye pattern for each data bit of the memory 200 (step S101).

[0092] Next, eye pattern measurement unit 401 sets memory bus 301 for a read operation and sets memory bus 302 for a write operation. Then, eye pattern measurement unit 401 acquires the results of communication between CPU 100 and memory 200 during a read operation using memory bus 301 and the results of communication during a write operation using memory bus 302 from I / O control units 113 and 114. Next, eye pattern measurement unit 401 acquires an eye pattern for each data bit of memory 200 from the acquired communication results. Strobe point determination unit 402 determines a strobe point in the eye pattern for each data bit of memory 200 (step S102).

[0093] Next, eye pattern measurement unit 401 sets memory bus 301 for write operation and sets memory bus 302 for read operation. Then, eye pattern measurement unit 401 acquires the communication results of the write operation using memory bus 301 and the read operation using memory bus 302 between CPU 100 and memory 200 from I / O control units 113 and 114. Next, eye pattern measurement unit 401 acquires the eye pattern for each data bit of memory 200 from the acquired communication results. Strobe point determination unit 402 determines the strobe point in the eye pattern for each data bit of memory 200 (step S103).

[0094] Next, the eye pattern measurement unit 401 sets both of the memory buses 301 and 302 for write operation. Then, the eye pattern measurement unit 401 acquires the communication results during the write operation using the memory buses 301 and 302 between the CPU 100 and the memory 200 from the I / O control units 113 and 114. Next, the eye pattern measurement unit 401 acquires the eye pattern for each data bit of the memory 200 from the acquired communication results. The strobe point determination unit 402 determines the strobe point in the eye pattern for each data bit of the memory 200 (step S104).

[0095] Fig. 16 is a flow chart of the process of weakening the driving capability. Each process in the flow of Fig. 16 corresponds to an example of the process executed in step S12 in the flow of Fig. 14. Next, the flow of the process of weakening the driving capability will be described with reference to Fig. 16. Here, the case where the driving capability of the CPU 100 can be set to seven levels, namely, 80Ω, 60Ω, 48Ω, 40Ω, 34Ω, 30Ω, and 27Ω, will be described.

[0096] The drive capacity adjustment unit 404 judges whether the setting value of the drive capacity of the CPU 100 for the memory 200 to be adjusted is 80Ω or not (step S201). If the setting value of the drive capacity is 80Ω (step S201: Yes), the drive capacity is the minimum value, so the drive capacity adjustment unit 404 maintains the setting value of the drive capacity of the CPU 100 for the memory 200 to be adjusted at 80Ω (step S202). Then, the drive capacity adjustment unit 404 ends the process of weakening the drive capacity.

[0097] On the other hand, if the set value of the driving capability is not 80Ω (step S201: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 60Ω or not (step S203). If the set value of the driving capability is 60Ω (step S203: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 80Ω (step S204). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0098] On the other hand, if the set value of the driving capability is not 60Ω (step S203: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 48Ω or not (step S205). If the set value of the driving capability is 48Ω (step S205: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 60Ω (step S206). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0099] On the other hand, if the set value of the driving capability is not 48Ω (step S205: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 40Ω or not (step S207). If the set value of the driving capability is 40Ω (step S207: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 48Ω (step S208). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0100] On the other hand, if the set value of the driving capability is not 40Ω (step S207: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 34Ω or not (step S209). If the set value of the driving capability is 34Ω (step S209: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 40Ω (step S210). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0101] On the other hand, if the set value of the driving capability is not 34Ω (step S209: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 30Ω or not (step S211). If the set value of the driving capability is 30Ω (step S211: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 34Ω (step S212). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0102] On the other hand, if the setting value of the driving capability is not 30Ω (step S211: No), since the setting value is 27Ω, the driving capability adjustment unit 404 changes the setting value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 30Ω (step S213). Then, the driving capability adjustment unit 404 ends the process of weakening the driving capability.

[0103] Fig. 17 is a flow chart of the process of strengthening the driving capability. Each process in the flow of Fig. 17 corresponds to an example of the process executed in step S14 in the flow of Fig. 14. Next, the flow of the process of strengthening the driving capability will be described with reference to Fig. 17. Here, too, the case will be described where the driving capability of the CPU 100 can be set to seven levels: 80Ω, 60Ω, 48Ω, 40Ω, 34Ω, 30Ω, and 27Ω.

[0104] The drive capacity adjustment unit 404 judges whether the setting value of the drive capacity of the CPU 100 for the memory 200 to be adjusted is 27Ω or not (step S301). If the setting value of the drive capacity is 27Ω (step S301: Yes), the drive capacity is the maximum value, so the drive capacity adjustment unit 404 maintains the setting value of the drive capacity of the CPU 100 for the memory 200 to be adjusted at 27Ω (step S302). Then, the drive capacity adjustment unit 404 ends the process of strengthening the drive capacity.

[0105] On the other hand, if the set value of the driving capability is not 27Ω (step S301: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 30Ω or not (step S303). If the set value of the driving capability is 30Ω (step S303: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 27Ω (step S304). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0106] On the other hand, if the set value of the driving capability is not 30Ω (step S303: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 34Ω or not (step S305). If the set value of the driving capability is 34Ω (step S305: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 30Ω (step S306). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0107] On the other hand, if the set value of the driving capability is not 34Ω (step S305: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 40Ω or not (step S307). If the set value of the driving capability is 40Ω (step 307: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 34Ω (step S308). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0108] On the other hand, if the set value of the driving capability is not 40Ω (step S307: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 48Ω or not (step S309). If the set value of the driving capability is 48Ω (step S309: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 40Ω (step S310). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0109] On the other hand, if the set value of the driving capability is not 48Ω (step S309: No), the driving capability adjustment unit 404 judges whether the set value of the driving capability is 60Ω or not (step S311). If the set value of the driving capability is 60Ω (step S311: Yes), the driving capability adjustment unit 404 changes the set value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 48Ω (step S312). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0110] On the other hand, if the setting value of the driving capability is not 60Ω (step S311: No), since the setting value is 80Ω, the driving capability adjustment unit 404 changes the setting value of the driving capability of the CPU 100 for the memory 200 to be adjusted to 60Ω (step S313). Then, the driving capability adjustment unit 404 ends the process of strengthening the driving capability.

[0111] Next, the effect on transmission characteristics when using the driving ability adjustment method according to this embodiment will be described. Fig. 18 is a diagram showing an example of the result when the driving ability is adjusted by training in which each memory is operated independently. In this case, eye patterns during read and write operations are obtained for each memory 200 during training, and the strobe point is determined from the results.

[0112] Eye pattern 701 is an eye pattern during a read operation in training. Eye pattern 702 is an eye pattern during a write operation in training. Eye pattern 703 is an eye pattern during a read operation while the system is operating after the OS is started. Eye pattern 704 is an eye pattern during a write operation while the system is operating after the OS is started.

[0113] In this case, eye pattern 701 during read operation in training has a margin of 5 codes above and below the center, and a margin of 5 taps on each side. Also, eye pattern 702 during write operation in training has a margin of 9 codes above and below the center, and a margin of 9 taps on each side. Thus, in training in this case, the size of the eye pattern during read operation and the size of the eye pattern during write operation are significantly different.

[0114] In this case, eye pattern 703 during read operation while the system is operating has a margin above and below the center of 3 codes each, and a margin to the left and right of 3 taps each. Also, eye pattern 704 during write operation while the system is operating has a margin above and below the center of 7 codes each, and a margin to the left and right of 7 taps each. In this case, the eye pattern during both read and write operations is smaller during system operation compared to the case of training. In particular, the size of the eye pattern during read operation while the system is operating is smaller, increasing the possibility of an error occurring.

[0115] Fig. 19 is a diagram showing an example of the result when the driving capability adjustment method according to the embodiment is used. In this case, training is performed by operating all the mounted memories 200, and eye patterns during read and write operations are obtained, and the strobe point is determined from the results. Fig. 19 shows the result of measurement performed using the same system as in Fig. 18.

[0116] Eye pattern 711 is an eye pattern during a read operation in training when the drive capacity adjustment method according to this embodiment is used. Eye pattern 712 is an eye pattern during a write operation in training when the drive capacity adjustment method according to this embodiment is used. Eye pattern 713 is an eye pattern during a read operation during system operation after OS startup when the drive capacity adjustment method according to this embodiment is used. Eye pattern 714 is an eye pattern during a write operation during system operation after OS startup when the drive capacity adjustment method according to this embodiment is used.

[0117] In this case, eye pattern 711 during read operation in training has a margin of 5 codes above and below the center, and a margin of 5 taps on both the left and right sides. Also, eye pattern 712 during write operation in training has a margin of 5 codes above and below the center, and a margin of 5 taps on both the left and right sides. Thus, it can be seen that in training using the driving capability adjustment method according to this embodiment, the size of the eye pattern during read operation is balanced with the size of the eye pattern during write operation.

[0118] In addition, in the eye pattern 713 during a read operation during the system operation in this case, the margins above and below from the center are 5 codes, and the margins to the left and right are 5 taps. In addition, in the eye pattern 714 during a write operation during the system operation, the margins above and below from the center are 5 codes, and the margins to the left and right are 5 taps. In this case, it can be seen that the eye pattern during the system operation after the OS is started is equivalent to the eye pattern during training. In addition, it can be seen that the margins during the read operation in this case are expanded by 2 codes above and below and 2 taps to the left and right, compared to the eye pattern in the case where the driving capacity is adjusted by training in which each memory 200 is operated independently as shown in FIG. 18. That is, when the driving capacity adjustment method according to this embodiment is used, the occurrence of errors can be suppressed.

[0119] Further, the effect on the transmission characteristics when the driving capability adjustment method according to the present embodiment is used will be described using another example. Fig. 20 is a diagram showing another example of the result when the driving capability is adjusted by training in which each memory is operated independently.

[0120] Eye pattern 721 is an eye pattern during a read operation in training. Eye pattern 722 is an eye pattern during a write operation in training. Eye pattern 723 is an eye pattern during a read operation while the system is operating after the OS is started. Eye pattern 724 is an eye pattern during a write operation while the system is operating after the OS is started.

[0121] In this case, eye pattern 721 during read operation in training has a margin of 5 codes above and below the center, and a margin of 5 taps on each side. Also, eye pattern 722 during write operation in training has a margin of 9 codes above and below the center, and a margin of 9 taps on each side. Thus, in training in this case, the size of the eye pattern during read operation and the size of the eye pattern during write operation are significantly different.

[0122] In addition, in this case, the eye pattern 723 during a read operation during system operation has upper and lower margins of 3 codes and 0 codes from the center, and the left and right margins are 3 taps each. In addition, the eye pattern 704 during a write operation during system operation has upper and lower margins of 7 codes and left and right margins of 7 taps each. In this case, the eye pattern during the system operation is smaller than that during training in both read and write operations. In particular, errors frequently occur in the eye pattern during a read operation during system operation because there is no margin below the center. In this way, when training is performed to operate each memory 200 independently, even if the eye pattern is a normal circle during training, the eye pattern may become distorted due to the influence of noise or the like during system operation. In that case, the strobe point adjusted during training may not be the optimal position during system operation.

[0123] 21 is a diagram showing another example of the result when the driving capability adjustment method according to the embodiment is used, and shows the result of measurement performed using the same system as in FIG.

[0124] Eye pattern 731 is an eye pattern during a read operation in training when the drive capacity adjustment method according to this embodiment is used. Eye pattern 732 is an eye pattern during a write operation in training when the drive capacity adjustment method according to this embodiment is used. Eye pattern 733 is an eye pattern during a read operation during system operation after OS startup when the drive capacity adjustment method according to this embodiment is used. Eye pattern 734 is an eye pattern during a write operation during system operation after OS startup when the drive capacity adjustment method according to this embodiment is used.

[0125] In this case, eye pattern 731 during read operation in training has a margin of 4 codes above and below the center, and a margin of 5 taps on each side. Also, eye pattern 732 during write operation in training has a margin of 4 codes above and below the center, and a margin of 4 taps on each side. Thus, it can be seen that in training using the driving capability adjustment method according to this embodiment, the size of the eye pattern during read operation is balanced with the size of the eye pattern during write operation.

[0126] In addition, in this case, the eye pattern 733 during the read operation during the system operation has a margin of 4 codes above and below the center, and a margin of 5 taps on the left and right. In addition, the eye pattern 734 during the write operation during the system operation has a margin of 4 codes above and below the center, and a margin of 4 taps on the left and right. In this case, it can be seen that the eye pattern during the system operation after the OS is started is equivalent to the eye pattern during training. In this way, when the driving capacity adjustment method according to this embodiment is used, the driving capacity is determined in the same environment as during the system operation during training, so that the eye pattern during the system startup after the OS is started is almost equivalent to the eye pattern during training. Therefore, even during the system operation after the OS is started, it is possible to position the strobe point at the center of the eye pattern. In addition, the eye pattern during the system operation in this case has a margin expanded above, below, left and right during the read operation compared to the eye pattern when the driving capacity is adjusted by training in which each memory 200 shown in FIG. 20 is operated independently, and the transmission line margin can be sufficiently secured. In other words, when the driving capacity adjustment method according to this embodiment is used, the occurrence of errors can be suppressed.

[0127] As described above, the driving capability adjustment method according to this embodiment operates multiple memories simultaneously and measures eye patterns using multiple training patterns that are combinations of predetermined read and write operations. Next, the driving capability adjustment method according to this embodiment overlaps each eye pattern with the strobe point at the center to generate a common eye pattern whose overlapping area is the communication range. Then, the driving capability adjustment method according to this embodiment adjusts the driving capability of the CPU so that the common eye pattern during read operation and the common eye pattern during write operation are equal in size and both are sufficiently large.

[0128] This makes it possible to prevent the eye pattern during read and write operations from becoming smaller and to make the sizes equal. Furthermore, the eye pattern size during training and during system operation can be approximated so that the strobe point is positioned in the center of the eye pattern even during system operation. Therefore, it is possible to reduce the occurrence of transmission errors during system operation and to optimize the transmission characteristics between the CPU and memory.

[0129] Here, in this embodiment, the drive capacity of the CPU is adjusted to balance the eye pattern during read operation and the eye pattern during write operation, but if the system control unit is configured to be able to adjust the drive capacity of the memory, the drive capacity of the memory may be adjusted to balance the eye pattern during read operation and the eye pattern during write operation. [Explanation of symbols]

[0130] 1. Information Processing Systems 10. Information processing device 11 Mainboard 12 System Control Unit 13 PCI Interface 14 LAN Interface 15 SATA interface 16 Power supply unit 17 Cooling fan 20 Storage device 21 HDD 30 Input Devices 31 Keyboard 40 Output Device 41 Display 100 CPU 111,112 Memory Controller 113,114 I / O control unit 121 SDRAM 122 MPU 123 SD card 200~203,211~213 Memory 301,302 memory bus 401 Eye pattern measurement section 402 Strobe point determination section 403 Common eye pattern generator 404 Driving capacity adjustment unit

Claims

1. performing signal transmission according to a plurality of types of training patterns that represent combinations of reads and writes for each of a plurality of transmission paths that connect a processor and a plurality of memories, and acquiring a plurality of eye patterns for each of the memories for each of the training patterns; determining a strobe point for each of the acquired eye patterns; generating a common eye pattern by superimposing the eye patterns around a strobe point determined for each memory; Based on the generated common eye pattern, the driving capability in communication between the processor and a plurality of memories is adjusted. A driving capability adjustment method comprising the steps of: causing a computer to execute a process.

2. acquiring the eye patterns in a number corresponding to a bus width of the transmission path connected to each of the memories; A common eye pattern is generated by overlapping the eye patterns, the number of which corresponds to the bus width of the transmission path connected to each memory.

2. The method for adjusting driving capability according to claim 1.

3. generating a common eye pattern during the read operation by superimposing the eye patterns during the read operation for each of the memories; generating a common eye pattern during the write operation by superimposing the eye patterns during the write operation for each of the memories; The driving capability is adjusted based on a result of comparing the size of the common eye pattern during the read operation with the size of the common eye pattern during the write operation.

3. The method for adjusting driving capability according to claim 1 or 2.

4. 4. The driving capability adjustment method according to claim 3, further comprising adjusting the driving capability so that the common eye pattern during the read operation and the common eye pattern during the write operation are approximately the same in size, and the common eye pattern during the read operation and the common eye pattern during the write operation are equal to or greater than a reference value.

5. When the size of the common eye pattern during the write operation is increased, the driving capability of the processor is increased; When the size of the common eye pattern during the read operation is increased, the driving capability of the processor is reduced.

5. The driving capability adjusting method according to claim 3 or 4.

6. A plurality of transmission paths connecting the processor and a plurality of memories; an eye pattern measurement unit that performs signal transmission according to a plurality of types of training patterns that represent combinations of read and write for each of the transmission paths, and acquires an eye pattern for each data bit of the memory; a strobe point determination unit that determines a strobe point for each eye pattern acquired by the eye pattern measurement unit; a common eye pattern generating unit that generates a common eye pattern by superimposing eye patterns during a read operation and a write operation for each of the memories, with the strobe point determined by the strobe point determining unit as a center; a drive capability adjustment unit that adjusts drive capabilities in communication between a processor and a plurality of memories based on the common eye pattern generated by the common eye pattern generation unit; An information processing device comprising:

Images