Pachinko machine

Abstract

To provide a game machine capable of efficiently performing control pertaining to a performance image.SOLUTION: A game machine can execute processing for switching mutual functions between a drawing output destination buffer and a frame buffer, and includes registration means capable of registering image information in the drawing output destination buffer and performance image display control means for controlling a performance image on the basis of the registered image information. When image information stored in the frame buffer switched from the drawing output destination buffer is temporary stop image information, temporary stop image information is registered in the drawing output destination buffer switched from the frame buffer. Image information can be controlled by display control corresponding to priority, determination regarding a reproduction mode can be performed when image information is not registered in the drawing output destination buffer, and control can be performed so as to reproduce from the beginning regarding loop reproduction when image information is not registered in the drawing output destination buffer.SELECTED DRAWING: Figure 52

Description

Technical Field

[0001] The present invention relates to a gaming machine such as a pachinko machine.

Background Art

[0002] Conventionally, in a gaming machine such as a pachinko machine, when a game ball wins a prize at a start port, a lottery is conducted, and based on the result of this lottery, a production image is displayed on a display device or the like. If the result of the lottery is a big win, a big win game is started.

[0003] As this type of gaming machine, there is known a gaming machine that decodes compressed image data, appropriately converts the decoded image data, stores it in a frame buffer, and outputs it to a display device (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, the variations of the production images displayed on the display device have increased, and the control over the production images has tended to become complicated. In such a case, it is desired to efficiently perform the control over the production images.

[0006] The present invention has been made in view of such points, and an object thereof is to provide a gaming machine capable of efficiently performing control over production images.

Means for Solving the Problems

[0007] The gaming machine according to the present invention is A gaming machine capable of executing a process (e.g., bank flip) for switching the functions of each other between a drawing output destination buffer in which a drawing result is stored and a frame buffer used for display. Registration means (e.g., a display control circuit 230 capable of executing step S448 and step S457) capable of registering image information (e.g., composition) related to a production image displayed on a predetermined display means in the drawing output destination buffer, After being switched from the drawing output destination buffer to the frame buffer (e.g., after the process of step S446 is performed), production image display control means (e.g., the display control circuit 230) for controlling the production image to be displayed on the predetermined display means based on the image information registered by the registration means. Comprising When the image information stored in the frame buffer switched from the drawing output destination buffer is pause image information for pausing an image (e.g., when step S447 is a YES determination), it is possible to register the pause image information in the drawing output destination buffer switched from the frame buffer. The image information can be controlled by display control according to priority. When the image information is not registered in the drawing output destination buffer by the registration means (e.g., when step S444 is a NO determination), it is possible to make a determination regarding the playback mode. When the image information is not registered in the drawing output destination buffer by the registration means (e.g., when step S444 is a NO determination), it is possible to control to play from the beginning regarding loop playback. Characterized by this.

Effect of the Invention

[0008] According to the present invention, it is possible to provide a gaming machine capable of efficiently controlling a production image.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] Hereinafter, the configuration and various operations of a pachinko gaming machine (gaming machine) according to an embodiment of the present invention will be described with reference to the drawings.

[0011] <Function Flow> First, with reference to FIG. 1, the functions of the pachinko gaming machine according to the present embodiment will be described. FIG. 1 is a diagram showing the function flow of the pachinko gaming machine according to the present embodiment.

[0012] As shown in FIG. 1, the pachinko game is a game in which a game ball is launched by a user's operation, and a game ball payout control process is performed when the game ball wins various prizes. The pachinko game includes a special symbol game using special symbols and a normal symbol game using normal symbols. When a "big win" occurs in the special symbol game or a "win" occurs in the normal symbol game, relatively, the possibility of the game ball winning increases, and the game ball payout control process is likely to be performed.

[0013] In addition, various winning awards include a special symbol start winning award which is a condition for variable display of special symbols in the special symbol game, and a normal symbol start winning award which is a condition for variable display of normal symbols in the normal symbol game.

[0014] Note that the "variable display" as used in this specification is a concept of being able to be variably displayed. For example, it enables "fluctuating display" that actually fluctuates and is displayed, "stopped display" that actually stops and is displayed, etc. Also, in the "variable display", for example, "derived display" in which special symbols (identification information) are displayed as a result of the special symbol game can be performed. That is, in this specification, the operation from the start of the "fluctuating display" to the "derived display" is referred to as one "variable display". Furthermore, in this specification, the "identification information" means symbols such as special symbols, normal symbols, decorative symbols, and identification symbols used in pachinko games, identification symbols and decorative symbols used in pachislot or slot games, etc., which may include symbols used when a player plays a game to display or suggest the result of the game, and also various symbols in the embodiments and various modified examples described below.

[0015] Hereinafter, an overview of the processing flows of the special symbol game and the normal symbol game will be described.

[0016] (1) Special symbol game In the special symbol game, when there is a special symbol start winning award, random values (big win determination random value and symbol determination random value) are respectively extracted from the big win determination counter and the symbol determination counter, and each of the extracted random values is stored (refer to the flow of the special symbol start winning award process in the special symbol game shown in FIG. 1).

[0017] Also, as shown in FIG. 1, in the special symbol control process in the special symbol game, first, it is determined whether the condition for starting the variable display of the special symbol is satisfied. In this determination process, it is referred to whether a random value is stored due to the special symbol start winning award, and with the fact that a random value is stored as one condition, it is determined that the condition for starting the variable display of the special symbol is satisfied.

[0018] Next, when starting the variable display of the special symbol, the random number value for jackpot determination extracted from the jackpot determination counter is referred to, and a jackpot determination is made as to whether it is a "jackpot" or not. Thereafter, a stop symbol determination process is performed. In this process, the random number value for symbol determination extracted from the symbol determination counter and the result of the above-described jackpot determination are referred to, and the special symbol to be stopped and displayed is determined.

[0019] Next, a variation pattern determination process is performed. In this process, a random number value is extracted from the variation pattern determination counter, and the random number value, the result of the above-described jackpot determination, and the special symbol to be stopped and displayed described above are referred to, and the variation pattern of the special symbol is determined.

[0020] Next, an effect pattern determination process is performed. In this process, a random number value is extracted from the effect pattern determination counter, and the random number value, the result of the above-described jackpot determination, the special symbol to be stopped and displayed described above, and the variation pattern of the special symbol described above are referred to, and the effect pattern to be executed along with the variable display of the special symbol is determined.

[0021] Next, the result of the determined jackpot determination, the special symbol to be stopped and displayed, the variation pattern of the special symbol, and the effect pattern associated with the variable display of the special symbol are referred to, and a variable display control process for controlling the variable display of the special symbol and an effect control process for performing a predetermined effect are executed.

[0022] Then, when the variable display control process and the effect display control process are completed, it is determined whether it is a "jackpot" or not. In this determination process, if it is determined that it is a "jackpot", a jackpot game control process for performing a jackpot game is executed. In the jackpot game, the possibilities of the various winnings described above increase. On the other hand, if it is determined that it is not a "jackpot", the jackpot game control process is not executed.

[0023] When it is determined that a "big win" has not occurred, or when the big win game control process has ended, a game state transition control process for shifting the game state is performed. In this game state transition control process, the management of the normal game state different from the big win game state is carried out. As the normal game state, for example, in the above-described big win determination, a game state in which the probability of determining a "big win" increases (hereinafter referred to as a "probability variable game state"), a game state in which it is easier to obtain a special symbol start winning (hereinafter referred to as a "time shortening game state"), etc. are exemplified. Thereafter, again, a determination process is performed as to whether or not to start the variable display of the special symbol, and then, various processes of the above-described special symbol control process are repeated.

[0024] In addition, in the pachinko game machine of the present embodiment, when a game ball starts winning during the variable display of the special symbol, various data (big win determination random number value, symbol determination random number value, etc.) acquired at the time of the start winning are held. That is, when a game ball starts winning during the variable display of the special symbol, the variable display (variable display) of the special symbol corresponding to the start winning is held, and the variable display of the special symbol held after the end of the variable display of the special symbol currently being executed is started. Hereinafter, the variable display of the special symbol held is also referred to as a "held ball".

[0025] Also, in the pachinko game machine of the present embodiment, as will be described later, two types of special symbol start winnings (the first start port winning and the second start port winning) are provided, and a maximum of 4 held balls can be acquired for each special symbol start winning. That is, in the present embodiment, a maximum of 8 held balls can be acquired.

[0026] Furthermore, although not shown in FIG. 1, the pachinko game machine of the present embodiment also has a function of determining the winning or losing of the held ball (the presence or absence of a "big win" winning) based on the information of the above-described held ball, and further performing a predetermined effect based on the determination result, that is, a predictive effect function.

[0027] (2) Normal symbol game In the case of a normal symbol winning start in a normal symbol game, a random number value is extracted from the hit determination counter and stored (refer to the flow of the normal symbol winning start process during the normal symbol game shown in FIG. 1).

[0028] Also, as shown in FIG. 1, in the normal symbol control process during the normal symbol game, first, it is determined whether the condition for starting the variable display of the normal symbol is satisfied. In this determination process, it is checked whether a random number value is stored due to a normal symbol winning start. If a random number value is stored, it is determined that the condition for starting the variable display of the normal symbol is satisfied.

[0029] Next, when starting the variable display of the normal symbol, the random number value extracted from the hit determination counter is referred to, and a hit determination is made as to whether it is a "win". Then, a variation pattern determination process is performed. In this process, the result of the hit determination is referred to, and the variation pattern of the normal symbol is determined.

[0030] Next, the determined result of the hit determination and the variation pattern of the normal symbol are referred to, and a variable display control process for controlling the variable display of the normal symbol and an effect control process for performing a predetermined effect are executed.

[0031] When the variable display control process and the effect display control process are completed, it is determined whether it is a "win". In this determination process, if it is determined that it is a "win", a winning game control process for performing a winning game is executed. In the winning game control process, the possibilities of the above-mentioned various winnings are increased, particularly the possibility of a special symbol winning start of the game ball in the special symbol game. On the other hand, if it is determined that it is not a "win", the winning game control process is not executed. Then, again, a determination process is performed as to whether to start the variable display of the normal symbol, and thereafter, the various processes of the above-mentioned normal symbol control process are repeated.

[0032] As described above, in a pachinko game, depending on conditions such as whether a "big win" occurs in a special symbol game, the transition status of the game state, and whether a "win" occurs in a normal symbol game, the ease of performing the payout control process of the game balls changes.

[0033] In this embodiment, as a method for extracting various random values, a software random number method that generates random values by executing a program is used. However, the present invention is not limited to this. For example, when a pachinko gaming machine includes a random number generator in which random numbers are updated at a predetermined cycle, a hardware random number method of extracting random values from a counter (so-called ring counter) in the random number generator may be adopted as the method for extracting various random values described above. When using the hardware random number method, it is possible to prevent the same random value from being extracted at a predetermined cycle by determining the initial value of the random value at a timing different from the predetermined cycle.

[0034] <Structure of Pachinko Gaming Machine> Next, with reference to FIGS. 2 and 3, the structure of the pachinko gaming machine in this embodiment will be described. Note that FIG. 2 is a perspective view showing the appearance of the pachinko gaming machine. FIG. 3 is an exploded perspective view of the pachinko gaming machine.

[0035] As shown in FIGS. 2 and 3, the pachinko gaming machine 1 includes a main body 2, a base door 3 that is attached to the main body 2 so as to be openable and closable, and a glass door 4 that is attached to the base door 3 so as to be openable and closable.

[0036] [Main Body] The main body 2 is composed of a frame-shaped member having a rectangular opening 2a (see FIG. 3). This main body 2 is formed of a material such as wood, for example.

[0037] [Base Door] The base door 3 is composed of a plate-shaped member having a rectangular outer shape that is substantially equal to the outer shape of the main body 2. The base door 3 is disposed in front of the main body 2 (the front side of the pachinko machine 1), and by rotating the base door 3 about one side edge end of the main body 2, the opening 2a of the main body 2 is opened and closed. As shown in FIG. 3, a square opening 3a is provided in the base door 3. This opening 3a is formed from a substantially central portion of the base door 3 to an upper region and is formed to have a size that occupies most of the region.

[0038] In addition, a speaker 11, a game board 12, a display device 13, a dish unit 14, a launching device 15, a payout device 16, and a substrate unit 17 are attached to the base door 3.

[0039] The speaker 11 is disposed at the upper part (near the upper end) of the base door 3. The game board 12 is disposed in front of the base door 3 (the front side of the pachinko machine 1) and is disposed so as to cover the opening 3a of the base door 3.

[0040] The game board 12 is composed of a plate-shaped resin member having light transmissibility. As the resin having light transmissibility, for example, acrylic resin, polycarbonate resin, methacrylic resin, etc. can be used.

[0041] In addition, on the front surface of the game board 12 (the surface on the front side of the pachinko machine 1), a game area 12a where the game balls launched from the launching device 15 roll is formed. This game area 12a is an area surrounded by a guide rail 41 (specifically, an outer rail 41a shown in FIG. 4 described later), and its outer peripheral shape is substantially circular. Further, a plurality of game pins (see FIG. 4 described later) are driven into the game area 12a. The configuration of the game board 12 (game area 12a) will be described in detail later with reference to FIG. 4.

[0042] The display device 13 is attached to the back side of the game board 12 (the side opposite to the front side of the pachinko gaming machine 1). This display device 13 has a display area 13a for displaying images. The size of the display area 13a is set to a size that occupies all or a part of the surface area of the game board 12. Various images such as identification symbols for effects, effect images, and decorative images (decorative symbols) are displayed in the display area 13a of this display device 13 based on the result of a lottery process for special symbols described later. The player can visually recognize the various images displayed in the display area 13a of the display device 13 through the game board 12.

[0043] In this embodiment, a liquid crystal display device is used as the display device 13. However, the present invention is not limited to this, and as the display device 13, for example, display devices such as a plasma display, a rear projection display, and a CRT (Cathode Ray Tube) display may be applied.

[0044] Also, a spacer 19 is provided on the back side of the game board 12 (the side opposite to the front side of the pachinko gaming machine 1). This spacer 19 is provided between the back surface of the game board 12 (the surface on the back side of the pachinko gaming machine 1) and the front surface of the display device 13 (the surface on the front side of the pachinko gaming machine 1), and forms a space that serves as a flow path for game balls rolling in the game area 12a of the game board 12. The spacer 19 is formed of a material having light transmissivity. Note that the present invention is not limited to this, and the spacer 19 may be formed of a material having light transmissivity in part, or may be formed of a material having no light transmissivity.

[0045] The dish unit 14 is disposed below the game board 12. This dish unit 14 has an upper dish 21 and a lower dish 22 disposed below the upper dish 21. As shown in FIG. 2, payout ports 21a and 22a for lending out game balls and paying out (awarding balls) game balls are respectively formed in the upper dish 21 and the lower dish 22. When predetermined payout conditions are satisfied, game balls are discharged from the payout ports 21a and 22a and stored in the upper dish 21 and the lower dish 22 respectively. Further, the game balls stored in the upper dish 21 are launched into the game area 12a by the launching device 15.

[0046] In addition, an effect button 23 is provided on the dish unit 14. This effect button 23 is attached onto the upper dish 21. Further, a dial operation unit (jog dial) 24 is rotatably attached to the effect button 23 at the periphery of the effect button 23. The pachinko game machine 1 of the present embodiment has a predetermined effect function performed using the effect button 23 and / or the dial operation unit 24. When performing a predetermined effect, an image prompting the operation of the effect button 23 and / or the dial operation unit 24 is displayed in the display area 13a of the display device 13.

[0047] The launching device 15 is disposed in the lower right region (near the lower right corner) on the front surface of the base door 3. This launching device 15 includes a launch handle 25 operable by a player and a panel body 26 engaged with the lower right portion of the dish unit 14. The launch handle 25 is disposed on the front side of the panel body 26 and is rotatably supported by the panel body 26.

[0048] Although not shown in FIGS. 2 and 3, a solenoid actuator (drive device) for controlling the launching operation of the game ball is provided on the back side of the panel body 26. Although not shown in FIGS. 2 and 3, a touch sensor is provided at the peripheral portion of the launch handle 25, and a launch volume is provided inside the launch handle 25. The launch volume changes the resistance value according to the rotation amount of the launch handle 25 and changes the power supplied to the solenoid actuator.

[0049] In the pachinko gaming machine 1 of this embodiment, when the player's hand touches the touch sensor of the firing handle 25, the touch sensor outputs a detection signal. As a result, it is detected that the player has grasped the firing handle 25, and the solenoid actuator can fire the game balls. When the player holds the firing handle 25 and rotates it in the clockwise direction (rightward as viewed from the player's side), the resistance value of the firing volume changes according to the rotation angle of the firing handle 25, and the power corresponding to the resistance value is supplied to the solenoid actuator. As a result, the game balls stored in the upper tray 21 are sequentially fired, and the fired game balls are guided by the guide rail 41 (see FIG. 4 described later) and discharged into the game area 12a of the game board 12.

[0050] Also, although not shown in FIGS. 2 and 3, a firing stop button is provided on the side portion of the firing handle 25. The firing stop button is a button provided to stop the firing of the game balls by the solenoid actuator. When the player presses the firing stop button, the firing of the game balls is stopped even when the firing handle 25 is held and rotated.

[0051] The payout device 16 and the board unit 17 are arranged on the back side of the base door 3. The payout device 16 is supplied with game balls from a storage unit (not shown). The payout device 16 pays out a predetermined number of game balls to the upper tray 21 or the lower tray 22 based on the establishment of the payout conditions from the game balls supplied from the storage unit. The board unit 17 has various control boards. The various control boards are provided with a main control circuit 70, a sub-control circuit 200, etc. (see FIG. 5 described later).

[0052] [Glass door] The glass door 4 is composed of a plate-like member having a substantially rectangular surface. Further, the glass door 4 is arranged on the front side of the game board 12 and has a size to cover the game board 12. On the front surface of this glass door 4, a speaker cover 29 is provided in the upper region facing the speaker 11.

[0053] Also, in the central portion of the glass door 4, an opening 4a having a size that at least exposes the gaming area 12a of the game board 12 is formed in the area facing the gaming area 12a of the game board 12. A protective glass 28 having light transmissivity is attached to the opening 4a of the glass door 4, whereby the opening 4a is closed. Therefore, when the glass door 4 is closed with respect to the base door 3, the protective glass 28 is disposed so as to face at least the gaming area 12a of the game board 12.

[0054] [Game board] Next, the configuration of the game board 12 will be described with reference to FIG. 4. FIG. 4 is a front view showing the configuration of the game board 12.

[0055] On the front surface of the game board 12, as shown in FIG. 4, a guide rail 41, a ball passage detector 43, a first start port 44, a second start port 45 (start area), and a normal electric accessory 46 are provided. Also, on the front surface of the game board 12, general winning ports 51, 52, a first big winning port 53 (variable winning device), a second big winning port 54 (variable winning device), an out port 55, and a plurality of game pins 56 are provided. Further, on the front surface of the game board 12, above the display area 13a of the display device 13 disposed substantially at the center thereof, a special symbol display device 61, a normal symbol display device 62, a normal symbol hold display device 63, a first special symbol hold display device 64, and a second special symbol hold display device 65 are provided.

[0056] Although not shown in FIG. 4, an effect 7-segment counter is also provided on the front surface of the game board 12. The effect 7-segment counter is composed of a display counter capable of displaying two-digit numbers or two English characters. Also, in the present embodiment, a notification LED (Light Emitting Diode) that lights up when the result of the stop display of the special symbol is "big win", a round number display LED that displays the number of rounds during the big win game, etc. may be provided.

[0057] [Various components in the gaming area] The guide rail 41 is composed of an outer rail 41a extending in an arc shape that partitions the game area 12a, and an inner rail 41b extending in an arc shape and disposed inside (inner circumferential side) of this outer rail 41a. The game area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are arranged to face each other near the left end portion of the game area 12a as viewed from the player side. Thereby, a guide path 41c for guiding the game ball launched by the launching device 15 to the upper part of the game area 12a is formed between the outer rail 41a and the inner rail 41b.

[0058] Also, at the tip of the inner rail 41b located at the upper left of the game area 12a, a ball discharge port 41d is formed by the tip of the inner rail 41b and a part of the outer rail 41a facing it. And at the tip of the inner rail 41b, a ball return prevention piece 42 is provided so as to block the ball discharge port 41d. This ball return prevention piece 42 prevents the game ball discharged from the ball discharge port 41d into the game area 12a from passing through the ball discharge port 41d again and entering the guide path 41c.

[0059] The game ball discharged from the ball discharge port 41d flows down from the upper part to the lower part of the game area 12a. At this time, the game ball collides with various members provided in the game area 12a such as a plurality of game pins 56, a first starting port 44, and a second starting port 45, and flows down from the upper part to the lower part of the game area 12a while changing its traveling direction.

[0060] A display area 13a of the display device 13 is provided approximately at the center of the game area 12a. An obstacle 13b is provided at the upper end of this display area 13a. By providing the obstacle 13b, the game ball does not pass over the area overlapping the display area 13a in the game area 12a.

[0061] The ball passing detector 43 is arranged near the right end of the display area 13a as viewed from the player side. The ball passing detector 43 is provided with a passing ball sensor 43a (see FIG. 5 described later) for detecting the game balls passing through the ball passing detector 43. Also, when a game ball passes through the ball passing detector 43, a lottery for "winning" or not is conducted, and based on the result of the lottery, the variable display of the normal symbol is started.

[0062] The first start port 44 is arranged below the display area 13a, and the second start port 45 is arranged below the first start port 44. The first start port 44 and the second start port 45 are composed of members capable of receiving game balls. Hereinafter, the entry or passage of a game ball into the first start port 44 or the second start port 45 is referred to as "winning". And when a game ball wins in the first start port 44 or the second start port 45, a first predetermined number (3 in this embodiment) of game balls are paid out. Also, when a game ball enters the first start port 44, a lottery for whether it is either a "big win" or a "small win" is conducted, and based on the result of the lottery, the variable display of the special symbol is started. Further, when a game ball enters the second start port 45, a lottery for whether it is a "big win" or not is conducted, and based on the result of the lottery, the variable display of the special symbol is started.

[0063] The first start port 44 is provided with a first start port winning ball sensor 44a (see FIG. 5 described later) for detecting the game balls that have won in the first start port 44. Also, the second start port 45 is provided with a second start port winning ball sensor 45a (see FIG. 5 described later) for detecting the game balls that have won in the second start port 45. Note that the game balls that have won in the first start port 44 and the second start port 45 are conveyed to the game ball collection part (not shown) through a collection port (not shown) provided in the game board 12.

[0064] The normal electric component 46 is provided at the second starting port 45. The normal electric component 46 includes a pair of blade members rotatably attached to both sides of the second starting port 45, and a normal electric component solenoid 46a (see FIG. 5 described later) that drives the pair of blade members. This normal electric component 46 is driven by the normal electric component solenoid 46a to generate one of an open state in which the pair of blade members are expanded to facilitate winning of a game ball at the second starting port 45, and a closed state in which the pair of blade members are closed to make it impossible to win a game ball at the second starting port 45. In this embodiment, when the normal electric component 46 is in the closed state, the opening form of the pair of blade members may be a form that makes it difficult to win a game ball, rather than a form that makes it impossible to win.

[0065] The general winning port 51 is arranged near the lower left part of the game area 12a as viewed from the player side. The general winning port 52 is arranged below the ball passage detector 43 and near the lower right part of the game area 12a as viewed from the player side. The general winning port 51 and the general winning port 52 are composed of members capable of receiving game balls. Hereinafter, a game ball entering or passing through the general winning port 51 or the general winning port 52 is also referred to as "winning". When a game ball wins at the general winning port 51 or the general winning port 52, a second predetermined number (10 in this embodiment) of game balls are paid out.

[0066] A general winning ball sensor 51a (see FIG. 5 described later) for detecting a game ball that has won at the general winning port 51 is provided at the general winning port 51. A general winning ball sensor 52a (see FIG. 5 described later) for detecting a game ball that has won at the general winning port 52 is provided at the general winning port 52.

[0067] The first major winning opening 53 and the second major winning opening 54 are disposed below the ball passage detector 43 and between the first starting opening 44 and the general winning opening 52. The first major winning opening 53 and the second major winning opening 54 are arranged vertically along the flow path of the game balls, and the first major winning opening 53 is disposed above the second major winning opening 54. Both the first major winning opening 53 and the second major winning opening 54 are so-called attacker-type opening and closing devices, and include openable shutters 53a and 54a and solenoid actuators (the first major winning opening solenoid 53b and the second major winning opening solenoid 54b in FIG. 5 described later) for driving the shutters.

[0068] Each of the first major winning opening 53 and the second major winning opening 54 accepts game balls when the corresponding shutter is open (open state), and does not accept game balls when the shutter is closed (closed state). Hereinafter, a game ball entering or passing through the first major winning opening 53 or the second major winning opening 54 is also referred to as "winning". When a game ball wins in the first major winning opening 53, a predetermined number of 3 balls (10 balls in this embodiment) of game balls are paid out. On the other hand, when a game ball wins in the second major winning opening 54, a predetermined number of 4 balls (15 balls in this embodiment) of game balls are paid out.

[0069] In addition, a count sensor 53c (see FIG. 5 described later) for counting the game balls that have won in the first major winning opening 53 is provided in the first major winning opening 53. Further, a count sensor 54c (see FIG. 5 described later) for counting the game balls that have won in the second major winning opening 54 is provided in the second major winning opening 54.

[0070] The out opening 55 is provided at the lowermost part of the game area 12a. The out opening 55 accepts game balls that have not won in any of the first starting opening 44, the second starting opening 45, the general winning opening 51, the general winning opening 52, the first major winning opening 53, and the second major winning opening 54.

[0071] When the arrangement of various components in the game area 12a of this embodiment is set as shown in Fig. 4, when a game ball is hit into the right area of the game area 12a by a player (when it is hit right), the game ball is guided to the second start port 45 by the game nails 56 or the like. In this case, the possibility of winning the first start port 44 is almost eliminated. In this embodiment, as will be described later, winning the second start port 45 makes it easier for the player to receive a "big win" lottery that is more advantageous to the player than when winning the first start port 44. Therefore, in the "time-saving game state" described later in which winning the second start port 45 becomes relatively easy, by hitting right, the possibility of winning the first start port 44 (the possibility of a game state disadvantageous to the player) can be reduced.

[0072] [Special symbol display device] As shown in Fig. 4, the special symbol display device 61 is arranged approximately at the center of the upper part of the display area 13a of the display device 13.

[0073] The special symbol display device 61 is a display device that variably displays (fluctuates and stops displaying) special symbols in the special symbol game. In this embodiment, as shown in Fig. 4, the special symbol display device 61 is constituted by a device that displays special symbols with symbols such as numbers and symbols. Note that the present invention is not limited to this, and the special symbol display device 61 may be constituted by, for example, a plurality of LEDs. In this case, a display pattern constituted by the lighting and extinguishing of the plurality of LEDs is represented as a special symbol.

[0074] The special symbol display device 61 starts the variable display of special symbols (identification information) when a game ball wins the first start port 44 or the second start port 45 (special symbol start win). Then, after the special symbol display device 61 performs the variable display of the special symbol for a predetermined time, it performs the stop display of the special symbol. Hereinafter, when a game ball wins the first start port 44, the special symbol variably displayed on the special symbol display device 61 is referred to as the first special symbol. Also, when a game ball wins the second start port 45, the special symbol variably displayed on the special symbol display device 61 is referred to as the second special symbol.

[0075] In the special symbol display device 61, when the first special symbol or the second special symbol that is stopped and displayed is in a specific mode (the "big win" mode), the game state shifts from the normal game state to the big win game state, which is advantageous to the player. That is, in the special symbol display device 61, the fact that the first special symbol or the second special symbol is stopped and displayed in a mode that shifts to the big win game state is a "big win".

[0076] In the big win game state, the first big winning opening 53 or the second big winning opening 54 becomes the open state. Specifically, in this embodiment, when a game ball wins a prize at the first start opening 44 and the first special symbol is stopped and displayed in a specific mode on the special symbol display device 61, the first big winning opening 53 becomes the open state. On the other hand, when a game ball wins a prize at the second start opening 45 and the second special symbol is stopped and displayed in a specific mode on the special symbol display device 61, the second big winning opening 54 becomes the open state.

[0077] The open state of each big winning opening is maintained until a predetermined number of game balls win a prize or until a certain period (for example, 30 seconds) elapses. Then, when the elapsed period of the open state of each big winning opening satisfies any of these conditions, the big winning opening that was in the open state becomes the closed state.

[0078] Hereinafter, a game in which the first big winning opening 53 or the second big winning opening 54 is in a state (open state) where it is easy to accept game balls is called a round game. Between round games, the big winning opening is in the closed state. Also, round games are counted as the number of rounds such as the first round, the second round, etc. For example, the first round game is called the first round, and the second round game is called the second round.

[0079] Note that in the special symbol display device 61, when the special symbol that is stopped and displayed is in a mode other than the specific mode (the "losing" mode), the game state does not shift except when winning the fall lottery. That is, the special symbol game is a game in which the special symbol is variably displayed by the special symbol display device 61, then the special symbol is stopped and displayed, and the game state shifts or is maintained according to the result.

[0080] In the pachinko gaming machine 1 of the present embodiment, when a game ball wins the first start port 44 during the variable display of the first special symbol or the second special symbol, the variable display of the first special symbol corresponding to the winning is (reserved ball) is reserved. Then, when the first special symbol or the second special symbol that is currently being variably displayed stops being displayed, the variable display of the first special symbol that has been reserved is started. In the present embodiment, the number of variable displays of the first special symbol to be reserved (so-called "reservation number (number of reserved balls)") is defined to be a maximum of 4 times (pieces).

[0081] Furthermore, in the present embodiment, when a game ball wins the second start port 45 during the variable display of the first special symbol or the second special symbol, the variable display (reserved ball) of the second special symbol corresponding to the winning is reserved. Then, when the first special symbol or the second special symbol that is currently being variably displayed stops being displayed, the variable display of the second special symbol that has been reserved is started. In the present embodiment, the number of variable displays of the second special symbol to be reserved (reservation number) is defined to be a maximum of 4 times (pieces). Therefore, in the present embodiment, the maximum number of reserved variable displays of the special symbol is 8 in total.

[0082] Also, in the present embodiment, when the reserved balls of the first special symbol and the reserved balls of the second special symbol are mixed, the variable display of one special symbol is executed preferentially over the variable display of the other special symbol. Note that the present invention is not limited to this, and when the reserved balls of the first special symbol and the reserved balls of the second special symbol are mixed, the variable display of the special symbol may be executed in the order in which they are reserved.

[0083] [Normal symbol display device] As shown in FIG. 4, the normal symbol display device 62 is arranged substantially at the center of the upper part of the display area 13a of the display device 13. And in the present embodiment, the normal symbol display device 62 is arranged on the right side of the special symbol display device 61 when viewed from the player side.

[0084] The normal symbol display device 62 is a display device that variably displays (fluctuates and stops displaying) normal symbols in a normal symbol game. In the present embodiment, as shown in FIG. 4, the normal symbol display device 62 is configured by two LEDs (normal symbol display LEDs) arranged in the vertical direction. And in the normal symbol display device 62, a display pattern formed by lighting and extinguishing each normal symbol display LED represents a normal symbol.

[0085] When a game ball passes through the ball passage detector 43, the normal symbol display device 62 alternately lights and extinguishes the two normal symbol display LEDs to perform a variable display of the normal symbol. Then, after performing a variable display of the normal symbol for a predetermined time, the normal symbol display device 62 performs a stop display of the normal symbol.

[0086] In the normal symbol display device 62, when the stopped-displayed normal symbol is in a predetermined mode (the "win" mode), the normal electric accessory 46 changes from the closed state to the open state for a predetermined period. On the other hand, when the stopped-displayed normal symbol is in a mode other than the predetermined mode (the "loss" mode), the normal electric accessory 46 maintains the closed state. That is, the normal symbol game is a game in which the normal symbol display device 62 variably displays the normal symbol, then stops displaying the normal symbol, and the normal electric accessory 46 operates according to the result.

[0087] If a game ball passes through the ball passage detector 43 during the variable display of the normal symbol, the variable display of the normal symbol is suspended. And when the currently variably displayed normal symbol is stopped and displayed, the suspended variable display of the normal symbol is started. In the present embodiment, the number of variable displays of the suspended normal symbol (that is, the "suspension number") is defined as a maximum of 4 times (pieces).

[0088] [Normal Symbol Suspension Display Device] As shown in FIG. 4, the normal symbol suspension display device 63 is arranged substantially at the center of the upper part of the display area 13a of the display device 13. And in the present embodiment, the normal symbol suspension display device 63 is arranged below the special symbol display device 61 and the normal symbol display device 62.

[0089] The normal symbol hold display device 63 is a device that displays the number of holds for the variable display of normal symbols. In the present embodiment, as shown in FIG. 4, the normal symbol hold display device 63 is configured by four LEDs (normal symbol hold display LEDs) arranged in the left-right direction. Then, in the normal symbol hold display device 63, the number of holds for the variable display of normal symbols is displayed by lighting and extinguishing each normal symbol hold display LED.

[0090] Specifically, when the number of holds for the variable display of normal symbols is 1, as viewed from the player side, the normal symbol hold display LED located on the far left (the first normal symbol hold display LED from the left) lights up, and the other normal symbol hold display LEDs go out. When the number of holds for the variable display of normal symbols is 2, the first and second normal symbol hold display LEDs from the left light up, and the other normal symbol hold display LEDs go out. When the number of holds for the variable display of normal symbols is 3, the first to third normal symbol hold display LEDs from the left light up, and the other normal symbol hold display LEDs go out. And when the number of holds for the variable display of normal symbols is 4, all the normal symbol hold display LEDs light up.

[0091] [First Special Symbol Hold Display Device] As shown in FIG. 4, the first special symbol hold display device 64 is arranged on the upper part of the display area 13a of the display device 13, on the left side of the special symbol display device 61 as viewed from the player side.

[0092] The first special symbol hold display device 64 is a device that displays information regarding the variable display of the first special symbol held (the held balls of the first special symbol). In the present embodiment, as shown in FIG. 4, the first special symbol hold display device 64 is composed of a first special symbol hold number display section 64a and a first special symbol hold information display section 64b. And the first special symbol hold information display section 64b is arranged on the left side of the special symbol display device 61, and the first special symbol hold number display section 64a is arranged on the left side of the first special symbol hold information display section 64b.

[0093] The first special symbol hold number display unit 64a has four LEDs (first special symbol hold display LEDs) arranged in the left - right direction. Note that the display mode of the first special symbol hold number display unit 64a is the same as that of the normal symbol hold display device 63. That is, when the variable display of the first special symbol is on hold, as viewed from the player side, the first special symbol hold display LEDs from the first special symbol hold display LED located on the far left up to the number of holds light up.

[0094] Also, the first special symbol hold information display unit 64b displays information regarding the hold balls of the first special symbol. For example, the first special symbol hold information display unit 64b displays information (identification information) regarding the hold balls of the first special symbol to be variably displayed next in a symbol composed of numbers, symbols, etc. Note that the configuration of the first special symbol hold display device 64 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of holds of the variable display of the first special symbol.

[0095] [Second Special Symbol Hold Display Device] As shown in FIG. 4, the second special symbol hold display device 65 is arranged on the upper part of the display area 13a of the display device 13, on the right side of the normal symbol display device 62 as viewed from the player side.

[0096] The second special symbol hold display device 65 is a device that displays information regarding the variable display (hold balls of the second special symbol) of the second special symbol on hold. In the present embodiment, as shown in FIG. 4, the second special symbol hold display device 65 is composed of a second special symbol hold number display unit 65a and a second special symbol hold information display unit 65b. And the second special symbol hold information display unit 65b is arranged on the right side of the normal symbol display device 62, and the second special symbol hold number display unit 65a is arranged on the right side of the second special symbol hold information display unit 65b.

[0097] The second special symbol hold number display unit 65a has four LEDs (second special symbol hold display LEDs) arranged in the left - right direction. Note that the display mode of the second special symbol hold number display unit 65a is the same as that of the normal symbol hold display device 63. That is, when the variable display of the second special symbol is on hold, when viewed from the player side, the second special symbol hold display LEDs from the second special symbol hold display LED located on the far left up to the hold number light up.

[0098] Also, the second special symbol hold information display unit 65b displays information regarding the hold balls of the second special symbol. For example, the second special symbol hold information display unit 65b displays information (identification information) regarding the hold balls of the second special symbol to be variably displayed next in a symbol composed of numbers, symbols, etc. Note that the configuration of the second special symbol hold display device 65 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of holds of the variable display of the second special symbol.

[0099] [Display device] The display device 13 is configured as a liquid crystal display device as described above, and performs various image display effects in its display area 13a.

[0100] Specifically, in this embodiment, an effect image related to the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. At this time, for example, when the special symbol is in variable display on the special symbol display device 61, except for specific cases, a plurality of effect identification symbols (decoration symbols) composed of, for example, numbers from 1 to 8 and various characters are variably displayed in the display area 13a. Then, when the special symbol stops being displayed on the special symbol display device 61, a plurality of decoration symbols (big win symbols, etc., described later) corresponding to the special symbol also stop being displayed in the display area 13a.

[0101] When the special symbol stopped and displayed on the special symbol display device 61 is in a specific mode (the result of the stop display is "big win"), a production image for allowing the player to recognize that it is a "big win" is displayed in the display area 13a. As an effect for allowing the player to recognize that it is a "big win", for example, first, a plurality of decorative symbols that have stopped and are displayed become a specific mode (for example, a mode in which the same decorative symbols are arranged along a predetermined direction), and then, an effect such as displaying an image for notifying a "big win" can be mentioned.

[0102] Also, in the present embodiment, a production image related to the display contents of the first special symbol hold display device 64 and the second special symbol hold display device 65 is displayed in the display area 13a of the display device 13. For example, hold information (for example, hold symbols equal in number to the number of holds) for notifying the number of holds of the variable display of the special symbol is displayed in the display area 13a. Further, for example, in the pachinko gaming machine 1 of the present embodiment, a prediction effect is performed based on the information of the hold balls of the special symbol, and a notice of this prediction is also displayed in the display area 13a.

[0103] In the present embodiment, a function for displaying, in the display area 13a of the display device 13, a production image for allowing the player to recognize the information when the normal symbol stopped and displayed on the normal symbol display device 62 is in a predetermined mode may be further provided.

[0104] <Configuration of the circuit provided in the pachinko gaming machine> Next, with reference to FIG. 5, the configuration of various circuits provided in the pachinko gaming machine 1 of the present embodiment will be described. Note that FIG. 5 is a block diagram showing the circuit configuration of the pachinko gaming machine 1.

[0105] As shown in FIG. 5, the pachinko gaming machine 1 mainly includes a main control circuit 70 that controls the gaming operation, a payout / firing control circuit 123, and a sub-control circuit 200 that controls the production operation according to the progress of the game.

[0106] [Main control circuit] The main control circuit 70 includes a one-chip microcomputer 77, a clock generation circuit 74, and an initial reset circuit 75. As described above, in this embodiment, a special symbol lottery process is performed when a winning occurs at the first start port 44 or the second start port 45, and this process is controlled by the main control circuit 70. That is, the main control circuit 70 also serves as a means (lottery means) for performing a lottery process to determine whether to shift the game state to a state advantageous to the player.

[0107] The one-chip microcomputer 77 is composed of a main CPU (Central Processing Unit) 71, a main ROM (Read Only Memory) 72, a main RAM (Random Access Memory) 73, and a serial communication unit 76. Note that the main CPU 71, the main ROM 72, the main RAM 73, and the serial communication unit 76 may be provided separately.

[0108] In addition, in this embodiment, a configuration in which the main ROM 72 is built into the board of the main control circuit 70 is described, but the present invention is not limited to this. For example, a ROM board on which the main ROM 72 is mounted may be connected to the board of the main control circuit 70. Furthermore, in this embodiment, various circuits within the main control circuit 70 may be integrally formed or separately formed. Also, the main ROM 72 may not be configured to be installed in the gaming machine, and may be configured to be communicable with the gaming machine.

[0109] The clock generation circuit 74 and the initial reset circuit 75 are connected to the one-chip microcomputer 77. The main ROM 72 stores various programs (see FIGS. 28 to 35 described later) for controlling the operation of the pachinko game machine 1 by the main CPU 71, various data tables (see FIGS. 16 to 26 described later), and the like.

[0110] The main CPU 71 executes various processes according to the programs stored in the main ROM 72. The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and stores various flags and variable values required for the main CPU 71 to perform various processes. In this embodiment, the main RAM 73 is used as the temporary storage area of the main CPU 71, but the present invention is not limited thereto, and any writable and readable storage medium can be used as the temporary storage area.

[0111] The clock generation circuit 74 generates clock pulses at a predetermined period (for example, 2 msec) to execute the system timer interrupt process described later. The initial reset circuit 75 generates a reset signal when the power is turned on. Then, the serial communication unit 76 supplies commands to the sub-control circuit 200.

[0112] Also, as shown in FIG. 5, various devices that operate according to the output signals sent from the main control circuit 70 are connected to the main control circuit 70.

[0113] Specifically, a special symbol display device 61, a normal symbol display device 62, a normal symbol hold display device 63, a first special symbol hold display device 64, and a second special symbol hold display device 65 are connected to the main control circuit 70. These devices perform predetermined operations based on the output signals sent from the main control circuit 70. For example, when a predetermined output signal is sent from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 controls the variable display operation of the special symbol in the special symbol game based on the output signal.

[0114] In addition, an ordinary electric accessory solenoid 46a, a first big winning opening solenoid 53b, and a second big winning opening solenoid 54b are connected to the main control circuit 70. Then, the main control circuit 70 drives and controls the ordinary electric accessory solenoid 46a to set a pair of blade members of the ordinary electric accessory 46 in an open state or a closed state. Further, the main control circuit 70 drives and controls the first big winning opening solenoid 53b and the second big winning opening solenoid 54b respectively to set the first big winning opening 53 and the second big winning opening 54 in an open state or a closed state.

[0115] Furthermore, as shown in FIG. 5, various sensors are connected to the main control circuit 70 to receive output signals of the various sensors. Specifically, a count sensor 53c, 54c, general winning ball sensors 51a, 52a, a passing ball sensor 43a, a first start opening winning ball sensor 44a, a second start opening winning ball sensor 45a, a backup clear switch 121, etc. are connected to the main control circuit 70.

[0116] The count sensor 53c counts the game balls that have won in the first big winning opening 53 and outputs a predetermined output signal indicating the result to the main control circuit 70. The count sensor 54c counts the game balls that have won in the second big winning opening 54 and outputs a predetermined output signal indicating the result to the main control circuit 70. The general winning ball sensor 51a outputs a predetermined detection signal to the main control circuit 70 when a game ball wins in the general winning opening 51, and the general winning ball sensor 52a outputs a predetermined detection signal to the main control circuit 70 when a game ball wins in the general winning opening 52.

[0117] In addition, the passing ball sensor 43a outputs a predetermined detection signal to the main control circuit 70 when a game ball passes through the ball passing detector 43. The first start opening winning ball sensor 44a outputs a predetermined detection signal to the main control circuit 70 when a game ball wins in the first start opening 44. The second start opening winning ball sensor 45a outputs a predetermined detection signal to the main control circuit 70 when a game ball wins in the second start opening 45. Further, the backup clear switch 121 outputs a predetermined detection signal to the main control circuit 70 and the payout / firing control circuit 123 when backup data is cleared according to the operation of a game store manager or the like during a power failure or the like.

[0118] Furthermore, a payout / firing control circuit 123 is connected to the main control circuit 70. The details of the payout / firing control circuit 123 and various peripheral devices connected thereto will be described in detail later.

[0119] [Payout / Firing Control Circuit and Its Peripheral Devices] The payout / firing control circuit 123 is connected to a prize ball case unit 170, a payout state notification display device 178, a lower tray full switch 179, a firing device 15, an external terminal board 140, and a card unit 150. The external terminal board 140 is connected to a data display 141, and the card unit 150 is connected to a lending operation unit 151.

[0120] Based on various commands and the like transmitted from the main control circuit 70, the payout / firing control circuit 123 inputs and outputs signals and the like to these peripheral devices to control the operation of each peripheral device. For example, the payout / firing control circuit 123 receives a prize ball control command transmitted from the main control circuit 70 and a lending ball control signal (to be described later) transmitted from the card unit 150, and transmits a predetermined signal to the prize ball case unit 170. Thereby, the prize ball case unit 170 pays out game balls.

[0121] The prize ball case unit 170 is a device that pays out game balls, and includes a first 15-ball guarantee switch 172a, a second 15-ball guarantee switch 172b, a first counting switch 181a, a second counting switch 181b, and a payout motor 174. These components included in the prize ball case unit 170 are each connected to the payout / firing control circuit 123.

[0122] Also, although not shown here, two ball supply passages are provided inside the prize ball case unit 170. The first 15 - ball guarantee switch 172a detects the game balls replenished in one of the ball supply passages and outputs a predetermined output signal indicating the detection result to the payout - and - launch control circuit 123. The second 15 - ball guarantee switch 172b detects the game balls replenished in the other ball supply passage and outputs a predetermined output signal indicating the detection result to the payout - and - launch control circuit 123.

[0123] Furthermore, although not shown here, two payout passages are provided inside the prize ball case unit 170. The first counting switch 181a detects the game balls paid out through one of the payout passages and outputs a predetermined output signal indicating the detection result to the payout - and - launch control circuit 123. The second counting switch 181b detects the game balls paid out through the other payout passage and outputs a predetermined output signal indicating the detection result to the payout - and - launch control circuit 123.

[0124] The payout motor 174 is composed of a stepping motor and is driven according to the control signal input from the payout - and - launch control circuit 123. The payout motor 174 rotationally drives a sprocket (rotating member), not shown, provided inside the prize ball case unit 170. Then, by the rotational movement of this sprocket, the game balls accumulated in each ball supply path move one by one to the corresponding payout passage.

[0125] The payout - state notification display device 178 is a device for notifying the type of abnormality when an abnormality occurs regarding the payout of game balls, and is composed of a 7 - segment display. The payout - state notification display device 178 is installed at a position where only the manager of the game parlor (game arcade) can view it, for example, at a predetermined location on the back surface of the pachinko game machine 1.

[0126] The lower - tray full - tank switch 179 detects when the game balls stored in the lower tray 22 are full and outputs the detection result to the payout - and - launch control circuit 123.

[0127] In addition, when a signal indicating that the lower tray is full is input from the lower tray full switch 179 to the payout / firing control circuit 123, the payout / firing control circuit 123 notifies that the lower tray is full using the payout state notification display device 178, and outputs a signal indicating that the lower tray is full to the main control circuit 70. After that, when an effect control command is transmitted from the main control circuit 70 to the sub-control circuit 200, the sub-control circuit 200 notifies that the lower tray 22 is full using, for example, the speaker 11, the lamp group 18, the display device 13, etc.

[0128] The launching device 15 has a launch handle 25 that can be rotated by the player when launching the game balls stored in the upper tray 21 into the game area 12a. When the launch handle 25 is gripped by the player and rotated in the clockwise direction, the payout / firing control circuit 123 supplies power to a solenoid actuator (not shown) of the launching device 15 according to the rotation angle. Thereby, the launching device 15 launches the game balls. Note that as the driving means of the launching device 15, a motor may be used instead of the solenoid actuator.

[0129] The external terminal board 140 is used to transmit data to a hall computer that manages all pachinko gaming machines in the game parlor. The data display 141 is installed, for example, at the upper part of the pachinko gaming machine 1 as an accessory facility in the game parlor, and has functions such as calling a hall staff member and displaying the number of winning times.

[0130] When the lending operation unit 151 is operated by the player, it outputs a signal requesting the lending of game balls to the card unit 150. The card unit 150 determines the number of game balls (lent ball number) paid out via the prize ball case unit 170 based on the signal requesting the lending of game balls output from the lending operation unit 151. Then, when the card unit 150 receives a signal requesting the lending of game balls from the lending operation unit 151, it transmits a lent ball control signal including information on the determined lent ball number to the payout / firing control circuit 123.

[0131] [Sub-control circuit] The sub-control circuit 200 is connected to the serial communication unit 76 of the main control circuit 70. Then, the sub-control circuit 200 (the host control circuit 210 described later) controls the entire sub-control circuit 200 according to various commands (information related to the progress of the game) transmitted from the main control circuit 70. And the sub-control circuit 200 controls the voice reproduction operation by the speaker 11, the image display operation by the display device 13, the lamp lighting / extinguishing operation by the lamp group 18 including LEDs, the effect operation by the accessory 20 (decoration member), etc. based on various commands transmitted from the main control circuit 70. That is, the sub-control circuit 200 controls various effect devices based on the commands from the main control circuit 70 and executes various effects according to the progress of the game. In this embodiment, the configuration is such that a signal cannot be supplied from the sub-control circuit 200 to the main control circuit 70, but the present invention is not limited to this, and it may be provided with a configuration capable of transmitting a signal from the sub-control circuit 200 to the main control circuit 70.

[0132] Next, with reference to FIG. 6, the internal configuration of the sub-control circuit 200 will be described in more detail. Note that FIG. 6 is a block diagram showing the circuit configuration inside the sub-control circuit 200 and the connection relationship between the sub-control circuit 200 and its various peripheral devices.

[0133] As shown in FIG. 6, the sub-control circuit 200 includes a relay board 201, a sub-board 202 (first board), a control ROM board 203, and a CGROM (Character Generator ROM) board 204 (second board). And the sub-board 202 is connected to the relay board 201, the control ROM board 203, and the CGROM board 204. In the sub-control circuit 200, the sub-board 202 and various ROM boards (control ROM board 203 and CGROM board 204) are connected via a board-to-board connector (not shown).

[0134] The relay board 201 is a relay board that receives the commands transmitted from the main control circuit 70 and transmits the received commands to the sub-board 202.

[0135] The sub-board 202 is provided with a host control circuit 210, an audio / LED control circuit 220, a display control circuit 230, an SDRAM (Synchronous Dynamic RAM) 250, and a built-in relay board 260. Among these, at least the host control circuit 210, the audio / LED control circuit 220, and the display control circuit 230 are configured as one board substrate.

[0136] The host control circuit 210 is a circuit that controls the operation of the entire sub-control circuit 200 based on various commands transmitted from the main control circuit 70, and is composed of a CPU processor, a sub-work RAM 210a, an SRAM 210b, an RTC (Real Time Clock), and a watchdog timer. The host control circuit 210 is connected to the audio / LED control circuit 220, the display control circuit 230, and the built-in relay board 260 within the sub-board 202. Also, the host control circuit 210 is connected to the control ROM board 203.

[0137] In addition, the host control circuit 210 has a sub-work RAM 210a and an SRAM (Static RAM) 210b. The sub-work RAM 210a is a storage device that acts as a working temporary storage area when the host control circuit 210 executes various processes, and stores various flags and variable values required when the host control circuit 210 executes various processes. The SRAM 210b is a storage device that backs up predetermined data in the sub-work RAM 210a. In this embodiment, RAM is used as the temporary storage area of the host control circuit 210, but the present invention is not limited to this, and any recordable medium that is a readable and writable storage medium may be used as the temporary storage area.

[0138] The audio / LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and based on the control signals (sound requests and lamp requests described later) input from the host control circuit 210, it controls the audio playback operation by the speaker 11 and the light emission operation by the lamp group 18. Therefore, functionally, the audio / LED control circuit 220 has an audio controller 220a and a lamp controller 220b. The audio controller 220a and the lamp controller 220b are substantially included in the sound / lamp control module 226 described later. The internal configuration of the audio / LED control circuit 220 will be described in detail later with reference to the drawings.

[0139] Note that in this embodiment, when the control signals and data (for example, LED data described later) output from the audio / LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, the communication between the audio / LED control circuit 220 and the lamp group 18 is performed in the communication method of SPI (Serial Periperal Interface) (a kind of serial communication method). Also, in this embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling each LED.

[0140] The display control circuit 230 is connected to the display device 13, and is a circuit for controlling various processing operations when displaying an image related to the effect (decoration pattern image, background image, effect image, etc.) on the display device 13 based on the control signal (drawing request) input from the host control circuit 210. Note that the display control circuit 230 has a display controller (the first display controller 238 and the second display controller 239 described later) and a built-in VRAM (Video RAM) 237.

[0141] In addition, the display control circuit 230 is connected to the SDRAM 250 within the sub-board 202. Further, the display control circuit 230 is connected to the CGROM board 204. Also, the display controller within the display control circuit 230 is directly connected to the display device 13 without going through the relay board. Note that the internal configuration of the display control circuit 230 will be described in detail later with reference to the drawings.

[0142] The SDRAM 250 is composed of a DDR2 (Double-Date Rate2) SDRAM. Also, various buffers for temporarily storing various image data are provided in the SDRAM 250 in the drawing process of images (videos and still images) displayed by the display device 13. Specifically, for example, a texture buffer, a movie buffer, a blend buffer, two frame buffers (a first frame buffer and a second frame buffer), a motion buffer, etc. are provided in the SDRAM 250.

[0143] The built-in relay board 260 is a relay board that receives various signals and various data output from the host control circuit 210 and the audio / LED control circuit 220, and transmits the received various signals and various data to the speaker 11, the lamp group 18, and the accessory 20.

[0144] Also, the built-in relay board 260 has an I2C (Inter-Integrated Circuit) controller 261 and a digital audio power amplifier 262 (amplifying means). In this embodiment, an example where the I2C controller 261 and the digital audio power amplifier 262 are mounted on the same relay board is shown, but the present invention is not limited to this, and the relay board on which the I2C controller 261 is mounted may be provided separately from the relay board on which the digital audio power amplifier 262 is mounted.

[0145] The I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20. That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270. Then, the control signals and data output from the host control circuit 210 (such as the excitation data described later) are input to the accessory 20 via the I2C controller 261 and the motor controller 270.

[0146] In this embodiment, the communication between the I2C controller 261 and the motor controller 270 is performed in the I2C communication method (a type of serial communication method). Also, in this embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving each motor. Note that FIG. 6 shows an example in which only one accessory 20 is provided, but the present invention is not limited to this, and a plurality of accessories 20 may be provided.

[0147] Also, in the configuration of this embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a control circuit for motor control may be provided separately. Furthermore, in this embodiment, one control circuit controls a plurality of motor drivers (motors), but the present invention is not limited to this. In this embodiment, one or more (one or a plurality of) control circuits may control one or more (one or a plurality of) motors (motor drivers), or one or more (one or a plurality of) control circuits may control one motor (motor driver), or one control circuit may control one motor (motor driver).

[0148] Also, the digital audio power amplifier 262 is connected to the audio / LED control circuit 220 and the speaker 11. That is, the audio / LED control circuit 220 is connected to the speaker 11 via the digital audio power amplifier 262. Therefore, the audio signal etc. output from the audio / LED control circuit 220 is input to the speaker 11 via the digital audio power amplifier 262.

[0149] A sub-main ROM 205 is provided on the control ROM board 203. The sub-main ROM 205 stores various programs for controlling the effect operation of the pachinko gaming machine 1 by the host control circuit 210 and various data tables (see, for example, FIG. 26 described later). Then, the host control circuit 210 executes various processes according to the programs stored in the sub-main ROM 205.

[0150] In this embodiment, the sub-main ROM 205 is applied as the storage means for storing the programs and various tables used by the host control circuit 210, but the present invention is not limited to this. As such storage means, another type of storage medium may be used as long as it is a storage medium readable by a computer equipped with control means. For example, storage media such as a hard disk device, a CD-ROM, a DVD-ROM, and a ROM cartridge may be applied. Also, each of the programs may be recorded on separate storage media. Further, the program may be recorded on a recording medium in advance, or may be downloaded from the outside etc. after power-on and recorded in the sub-main ROM 205.

[0151] A CGROM substrate 204 is provided with a CGROM 206. The CGROM 206 is composed of a NOR type or NAND type flash memory. Further, the CGROM 206 stores, for example, image data displayed on the display device 13, audio data (which may also be referred to as sound data in this specification) reproduced by the speaker 11, and the like. At this time, various data are compressed (encoded) and stored in the CGROM 206, but the present invention is not limited thereto, and various data may be stored in the CGROM 206 without being compressed.

[0152] In the present embodiment, the configuration in which various ROM substrates (control ROM substrate 203 and CGROM substrate 204) and the sub-substrate 202 are connected by a board-to-board connector in the sub-control circuit 200 has been described, but the present invention is not limited thereto. For example, various ROMs may be directly inserted into ports such as sockets provided on the sub-substrate 202, and the sub-substrate 202 may be configured by a single substrate having a ROM function or the ROM itself. That is, the sub-substrate 202 and various ROMs may be integrally configured. Further, when the sub-substrate 202 is configured by a single substrate having a ROM function or the ROM itself, the sub-control circuit 200 may include switching means for physically or electrically switching the circuit on the sub-substrate to be used according to the type of memory used as the CGROM, or switching means for switching the information of the circuit on the sub-substrate to be used according to the type of memory.

[0153] Also, in this embodiment, the magnitude relationship of the data communication speeds between each of the various storage means (sub-main ROM 205, CG ROM 206, built-in VRAM 237, SDRAM 250) and the corresponding control circuit is such that built-in VRAM 237 > SDRAM 250 > sub-main ROM 205 ≈ CG ROM 206. That is, in this embodiment, the communication speed between the built-in VRAM 237 and the various circuits in the display control circuit 230 is the fastest, and then the communication speed between the SDRAM 250 and the display control circuit 230 is fast. And the communication speeds between the sub-main ROM 205 and the host control circuit 210, and between the CG ROM 206 and the display control circuit 230 are the slowest. However, the present invention is not limited to this, and the magnitude relationship of the communication speeds between each of the various storage means and the corresponding control circuit can be set arbitrarily. For example, the magnitude relationship of the communication speeds between each of the various storage means and the corresponding control circuit may be different from that of this embodiment, or the communication speeds between each storage means and the corresponding control circuit may all be the same.

[0154] Here, the possible configurations of the above-described various storage means will be described. In this embodiment, a configuration example is described in which the storage means for information on image data (compressed (encoded) image data) is the same (CG ROM 206) as the storage means for information on transparency data (alpha table described later) that can be used when setting transparency for the image data. That is, a configuration example in which the "first information storage means" is physically the same as the "second information storage means" is described. However, the present invention is not limited to this. For example, the "first information storage means" may be composed of a storage means (storage medium) that is physically different from the "second information storage means".

[0155] In addition, the "information storage means" as referred to in this specification may mean not only storage means such as the CGROM 206, but also tables stored in the storage means, data storage areas in the storage means, and the like. Therefore, for example, the "first information storage means" and the "second information storage means" may be different data storage areas within the same storage means, may be different tables from each other, or may be stored at different register addresses. That is, the "information storage means" being different as referred to in this specification includes not only the case where the physical storage means (storage medium) is different, but also the case where the physical storage means is the same (for example, ROM, RAM, etc.), but the data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) within the storage means are different.

[0156] Note that the meaning regarding the "information storage means" in the above-described specification is also applicable to the above-described "third information storage means" (SDRAM 250) and "fourth information storage means" (built-in VRAM 237). Therefore, for example, the "first information storage means" to the "fourth information storage means" may be physically constituted by different storage means (storage media), or the "first information storage means" to the "fourth information storage means" may be constituted by different data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) within one storage means.

[0157] Also, in the present embodiment, an example has been described in which the "first information storage means" and the "second information storage means" are configured as different data areas within one storage means (CGROM206), the "third information storage means" is configured as a storage means (SDRAM250) physically different from the storage means (CGROM206) including the "first information storage means" and the "second information storage means", and the "fourth information storage means" is configured as a storage means (built-in VRAM237) physically different from the storage means (CGROM206) including the "first information storage means" and the "second information storage means", and the "third information storage means" (SDRAM250). However, the present invention is not limited to this. How to configure the "information storage means" with either a data area or a storage means, and what combination of the "information storage means" defined as a data area and the "information storage means" defined as a storage means should be adopted can be appropriately set according to, for example, the configuration (such as the number and type) of the storage means provided in the gaming machine. For example, in the present embodiment, the "first information storage means" to the "third information storage means" may be configured as different data areas within one storage means, and the "fourth information storage means" may be configured as a storage means physically different from the storage means including the "first information storage means" to the "third information storage means".

[0158] [Audio / LED Control Circuit] Next, with reference to FIG. 7, the internal configuration of the audio / LED control circuit 220 will be described. FIG. 7 is a block diagram showing the internal circuit configuration of the audio / LED control circuit 220 and the connection relationship between the audio / LED control circuit 220 and its various peripheral devices and peripheral circuit parts. In FIG. 7, for the sake of simplicity of explanation, the illustration of relay substrates and the like provided between the audio / LED control circuit 220 and various peripheral devices and circuit parts is omitted.

[0159] As shown in FIG. 7, the audio-LED control circuit 220 includes a large-scale integration (LSI) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, a sound-lamp control module 226, a main generator 227, and a multi-effecter 228. The connection relationships among the respective parts within the audio-LED control circuit 220 are as follows.

[0160] Within the audio-LED control circuit 220, the sound-lamp control module 226 is connected to the memory interface 222, the peripheral interface 224, the command register 225, the main generator 227, and the multi-effecter 228. Also, the command register 225 is connected to the LSI interface 221 in addition to the sound-lamp control module 226. Further, the main generator 227 is connected to the memory interface 222 and the multi-effecter 228 in addition to the sound-lamp control module 226. Furthermore, the multi-effecter 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound-lamp control module 226 and the main generator 227.

[0161] Next, the configurations of the respective parts within the audio-LED control circuit 220 will be described.

[0162] The LSI interface 221 is an interface circuit used when performing input / output operations of control signals etc. (such as a sound request, a lamp request, etc.) between the host control circuit 210 and the command register 225. That is, the command register 225 is connected to the host control circuit 210 via the LSI interface 221.

[0163] The memory interface 222 is an interface circuit used when performing input / output operations of audio data and the like between the sub-main ROM 205 and each of the sound lamp control module 226, the main generator 227, and the multi-effecter 228.

[0164] The digital audio interface 223 is an interface circuit used when outputting an audio signal or the like from the multi-effecter 228 to the speaker 11. Also, the digital audio interface 223 outputs an audio input signal to the multi-effecter 228.

[0165] The peripheral interface 224 is an interface circuit used when performing input / output operations of lamp signals and the like (such as LED data described later) between the lamp group 18 and the sound lamp control module 226. Also, three physical systems are provided in the peripheral interface 224 as physical systems (SPI channels) when performing data output to the LED driver included in the lamp group 18. In this embodiment, as described later, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used.

[0166] The command register 225 is composed of a number of register groups (for example, a number of audio control registers) accessed from the host control circuit 210. The command register 225 performs function control settings for the sound lamp control module 226, the main generator 227, and the multi-effecter 228. Also, the command register 225 performs operation condition settings for each interface (LSI interface 221, memory interface 222, digital audio interface 223, peripheral interface 224).

[0167] Each register that constitutes the command register 225 is equipped with an IC (Integrated Circuit), and each register is constituted by a memory chip whose operation is stabilized by memory access control. When registers with such a configuration are used, the burden on the signal bus to which each register is connected is reduced. Therefore, by increasing the memory chips (registers), it is possible to easily increase the capacity per memory module (the capacity of the command register 225).

[0168] The sound lamp control module 226 comprehensively controls operations such as voice playback operations, and controls the operations of each component (each block) in the voice / LED control circuit 220 according to the set contents of the command register 225. As shown in FIG. 7, the sound lamp control module 226 includes a simple access controller 226a, a sequencer 226b, a lamp control unit 226c, and a peripheral control unit 226d.

[0169] The simple access controller 226a is a circuit unit that processes commands in a batch. The sequencer 226b has various sequencers (automatic playback function units) for controlling automatic playback operations such as lamp lighting and voice. Each sequencer controls various operations according to a timer and step conditions (for example, conditions set for each step process during sequence playback such as LED animation and voice described later).

[0170] The lamp control unit 226c calculates the luminance values to be set in all channels (eight channels) where the LED data described later can be set, and transmits the calculation results to the outside (LED driver). In addition, the peripheral control unit 226d performs physical transmission control when transmitting the data of the calculation results output from the lamp control unit 226c to the LED driver.

[0171] The main generator 227 is a circuit unit that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on a control signal input from the sound lamp control module 226, and converts the acquired audio data into a predetermined audio signal. This main generator 227 includes a decoder 227a that reproduces compressed data divided into playback channels CH1 to CH32, channel volumes 227b (V1 to V4) for adjusting the volume, a channel mixing unit 227c that mixes the reproduced sounds of the decoder 227a, and a remixing unit 227d that performs a final mixing operation.

[0172] The multi - effect 228 has a mixer that synthesizes an audio signal input from the main generator 227 and an audio input signal input from the digital audio interface 223, and various effectors for applying various acoustic effects to the audio. Then, the multi - effect 228 outputs the audio signal synthesized by the mixer, the output signal from the effector, etc. to the speaker 11 via the digital audio interface 223.

[0173] FIG. 8 is a drawing for explaining the output signal of the audio - LED control circuit. In the CGROM 206, a maximum of 8192 types of sequence code groups and a maximum of 8192 types of SAC data groups are stored. The sequence code and SAC data are each specified by a 13 - bit - long sequence code number and SAC number, and 8192 = 2 13 is in the relationship of.

[0174] In the case of this embodiment, as the sequencer 226b, 16 series (SQ0 to SQ15) operating in parallel are provided, and as the simple access controller 226a, 4 series (SAC0 to SAC3) operating in parallel are provided. Corresponding to this configuration, the command register 225 is provided with an audio control register RGj2 for controlling the sequencer (SQ0 to SQ15) and an audio control register RGj1 for controlling the SAC (SAC0 to SAC3).

[0175] Then, when the host control circuit 210 composed of a CPU processor writes the SAC number and its attached information to a predetermined voice control register RGj1 for SAC control based on the transmission operation of a voice command, the corresponding simple access controller 226a starts to function, and the simple access controller 226a writes a group of setting data specified by the SAC number to a group of voice control registers indicated by the SAC data. In this embodiment, a complicated setting operation can be completed by transmitting one SAC number and its attached information.

[0176] On the other hand, when the host control circuit 210 composed of a CPU processor writes the sequence code number and its attached information to a predetermined voice control register RGj2 for sequencer 226b (SQ0 to SQ7) control based on the transmission operation of a voice command, the corresponding sequencer SQi starts to function, and writes a group of setting data specified by the sequence code to a group of voice control registers indicated by the sequence code.

[0177] Here, in the predetermined voice control register RGj2 for sequencer (SQ0 to SQ7) control, for any sequencer SQi, a plurality (up to 8) of sequence code numbers and loop information for the production of each sequence code number can be entered. Therefore, for example, when n + 1 sequence code numbers (X0, X1, ···, Xn) are specified for the sequencer SQi, the setting operation of the sequence code number X0 → the setting operation of the sequence code number X1 → ··· the setting operation of the sequence code number Xn are executed in order, and the voice production corresponding to the setting operation is executed.

[0178] Also, since loop information such as the number of repetitions can be specified for each sequence code number, after the voice production specified by the sequence code number is repeated a predetermined number of times, it is possible to shift to the voice production specified by the next sequence code number.

[0179] Thus, the data to be set in the sequencer SQi is diverse, and it is necessary to appropriately set these sequence code numbers and associated data in the voice control register RGj2 for sequencer control. Therefore, in this embodiment, the entire sequence code number and associated data are divided in 1-byte units, and a group of SAC data is secured in the CGROM206, where each group consists of the divided 1-byte data and the register address of the sequencer control register RGj2 to which this 1-byte data is to be set (hereinafter, this is referred to as sequencer startup SAC data).

[0180] Then, the host control circuit 210 activates the simple access controller 226a by specifying a predetermined SAC number in the voice control register RGj1 for SAC control. Here, the SAC number, of course, specifies the sequencer startup SAC data. And based on the operation of the SAC (Simple Access Controller), the necessary data is expanded in the sequencer control register RGj2. Therefore, the setting operation of the startup data for the sequencers SQ0 to SQ15 is easy.

[0181] By the way, as described above with respect to FIG. 8, a group of sequence codes specified by one sequence code number includes a plurality of operation units (sequence steps) delimited by the step end code (FFFEH). Eventually, after all the sequence steps specified by one sequence code number are executed, the sequence steps specified by the next sequence code number are executed.

[0182] And since a waiting time can be set for each sequencer, the first sequence step (writing operation of a group of setting data) is started after the waiting time indicated by the host control circuit 210 composed of the CPU processor. When it is executed until the step end code (FFFEH), further, after the waiting time, the next group of setting data is written into the group of voice control registers. Note that the waiting time can be set with a single time information for each sequencer (SQ0 to SQ7). For example, in the preceding sequence step, by setting the waiting time applied to the subsequent sequence step following this, the waiting time for each sequence step can be arbitrarily set.

[0183] Furthermore, continuing the description of the internal configuration of the voice / LED control circuit 220, as shown in FIG. 7, the output signals of the 6 channels of the channel mixer section 227c (mixed L0, mixed R0, mixed L1, mixed R1, mixed SUB0, mixed SUB1) are digitally filtered in the multi-effect 228 based on the operation parameters defined in the predetermined voice control register of the command register 225, and then supplied to the total volume 229 (TV0 to TV3), and amplified based on the total volume value TV.

[0184] The total volume value TV is defined by the operation parameters written into the corresponding voice control register. As described above, in this embodiment, in principle, it is defined based on the setting switch (hardware switch) operated by the staff member. However, when the player operates the volume switch (screen operation) during the game operation (however, during the voice effect waiting), the total volume TV is defined (changed) based on the set value. Note that instead of or in addition to the total volume TV being defined based on the set value when the player operates the volume switch, the channel volume 227b (V1 to V4) may be defined (changed).

[0185] [Volume Control of Speaker] Next, the volume control of each speaker 11 executed by the host control circuit 210 will be described with reference to FIG. 9. FIG. 9 is a control block diagram for explaining an example of volume control by the host control circuit.

[0186] Sounds such as game sounds output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) are volume-controlled by a volume transition operation that gradually transitions the volume value of the audio signal by multiplying the audio signals of the total volumes TV0 to 3 output to all channels by the audio signals for each playback channel output to each individual channel among all channels.

[0187] Note that the "audio signal" has volume information (such as information on wattage, etc.) and can also be simply referred to as "volume". For example, in this specification, the "audio signal for each playback channel" may sometimes be referred to as the "volume for each playback channel".

[0188] The audio signals of the total volumes TV0 to 3 are defined by multiplying the combined value of the audio signal by the volume control 281 by the hardware switch and the audio signal by the user volume control 282 by the volume setting screen and the audio signal by the debug volume control 283 during debugging. The host control circuit 210 that executes the volume control 281 by the hardware switch, the user volume control 282 by the volume setting screen, and the debug volume control 283 during debugging corresponds to the "first volume control means" of the present invention.

[0189] Also, the volume for each playback channel is determined by multiplying the audio signal of the primary volume and the audio signal of the secondary volume. The audio signal of the primary volume is defined by the combined value of the audio signal output by the first playback channel primary control 284 that is affected by volume adjustment and the audio signal output by the second playback channel primary control 285 that is not affected by volume adjustment. In the first playback channel primary control 284, for example, based on an operation to change the volume by a player or the like, control is performed to change the volume of normal game sounds (i.e., audio signals (the same hereinafter)). In the second playback channel primary control 285, regardless of whether an operation to change the volume is performed, control is performed to output a specific game sound (e.g., an error sound or an alarm sound during illegal behavior) at a constant volume. This constant volume may always be the maximum volume. In this way, in the second playback channel primary control 285 that is not affected by volume adjustment, by controlling so that a specific game sound is output at a constant volume, it becomes possible to execute control to keep the volume of a specific game sound constant only in a specific playback channel, not overall. Also, the audio signal of the secondary volume is the volume incorporated in the audio data specified by the SAC number and is output by volume controls 286, 287, 288. The host control circuit 210 that executes the first playback channel primary control 284, the second playback channel primary control 285, and the volume controls 286, 287, 288 incorporated in the audio data corresponds to the "second volume control means" of the present invention.

[0190] In this way, since the sound output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) is defined by multiplying the volume of the total volume TV0 to 3 and the volume of the primary volume and the secondary volume which are the volume for each playback channel, it becomes possible to give diversity to the volume of the game sound. In particular, since the volume of the total volume TV0 to 3 is also defined by the volume output by the debug volume control 283 during debugging, during debugging, the game sound data used in the game can be used as it is, and it becomes possible to improve the work efficiency during debugging.

[0191] Also, regarding the volume of normal game sounds, the volume can be changed based on an operation by a player or the like to change the volume. However, regarding specific game sounds such as error sounds and warning sounds during illegal acts, a constant volume is output by the second playback channel primary control 285 regardless of whether an operation to change the volume has been performed. Therefore, it is impossible to hide the occurrence of an error or an illegal act, and it becomes possible to enhance security.

[0192] In the pachinko gaming machine 1 of the present embodiment, the volume control 281 by the hardware switch has, for example, three levels: large, medium, and small. Also, the user volume control 282 by the volume setting screen has seven levels, and in conjunction with the hardware switch, [small] = [1], [medium] = "4", and [large] = "7".

[0193] As described above, in the pachinko gaming machine 1 of the present embodiment, for specific sounds such as error sounds, the volume can be maintained only by the control by the second playback channel primary control 285. Therefore, it becomes possible to easily perform volume control such that the volume of specific sounds is maintained while the volume of other normal sounds is changed according to the volume adjustment. Note that the processing by the host control circuit 210 when the volume adjustment is performed will be described later with reference to FIGS. 61 to 65.

[0194] [Connection Configuration between Digital Audio Power Amplifier and Speaker] Next, with reference to FIG. 10, the connection configuration between the digital audio power amplifier 262 provided in the built-in relay board 260, its peripheral circuit, and the speaker 11 will be described. FIG. 10 is a connection configuration diagram between the built-in relay board 260 and the speaker 11. Note that in FIG. 10, to more clearly show the configuration of the connection portion, a state where the speaker 11 is not connected to the built-in relay board 260 is shown.

[0195] In the pachinko gaming machine 1 of the present embodiment, as shown in FIG. 10, a speaker box 11a provided with a speaker 11 is connected to a built-in relay board 260 via a harness 300.

[0196] The built-in relay board 260 includes a digital audio power amplifier 262, an LC circuit 263, a connection terminal group 264 including four connection terminals (a first connection terminal to a fourth connection terminal), two resistors 265 and 266, a capacitor 267, and a NOT circuit (logic circuit) 268.

[0197] The digital audio power amplifier 262 amplifies an input audio signal (audio data), outputs the amplified audio signal to the speaker 11, and drives the speaker 11. The LC circuit 263 is composed of a resonance circuit including a coil and a capacitor. The NOT circuit 268 is a logic circuit that inverts the level of an input signal and outputs it.

[0198] The clock input terminal (MCK) and the data input terminal (SDATA) of the digital audio power amplifier 262 are connected to the audio / LED control circuit 220. A clock signal (master clock signal) output from the audio / LED control circuit 220 is input to the clock input terminal (MCK) of the digital audio power amplifier 262, and an audio signal (audio data) output from the audio / LED control circuit 220 is input to the data input terminal (SDATA).

[0199] Also, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the first connection terminal and the second connection terminal in the connection terminal group 264 of the built-in relay board 260 via the LC circuit 263, respectively. In the present embodiment, an example in which two output terminals of the digital audio power amplifier 262 are provided is shown, but the present invention is not limited to this, and can be appropriately changed according to, for example, the functions and specifications of the speaker 11.

[0200] Furthermore, the digital audio power amplifier 262 has a mute terminal (MUTE: audio output control terminal). When the level (amplitude value) of the voltage signal applied to the mute terminal is at a LOW level, the digital audio power amplifier 262 has a function of stopping the output of the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2), or putting these output terminals in a state of being grounded via a high resistance (hereinafter referred to as the mute function). That is, when the level of the voltage signal applied to the mute terminal is at a LOW level, the digital audio power amplifier 262 has a function of generating a state in which the output of the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2) to the first connection terminal and the second connection terminal of the built-in relay board 260 is stopped.

[0201] On the other hand, when the level (amplitude value) of the voltage signal applied to the mute terminal (MUTE) is at a HIGH level, the digital audio power amplifier 262 outputs an audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2).

[0202] The third connection terminal in the connection terminal group 264 of the built-in relay board 260 is connected to the input terminal of the NOT circuit 268 via the resistor 266. Also, the output terminal of the NOT circuit 268 is connected to the mute terminal (MUTE) of the digital audio power amplifier 262. Note that the signal wiring between the third connection terminal of the built-in relay board 260 and the resistor 266 is connected to the power supply voltage (+5V) terminal provided in the built-in relay board 260 via the resistor 265. Also, the signal wiring between the input terminal of the NOT circuit 268 and the resistor 266 is connected to the ground (GND) terminal provided in the built-in relay board 260 via the capacitor 267 (grounded). Furthermore, the fourth connection terminal of the built-in relay board 260 is connected to the ground (GND) terminal.

[0203] As shown in FIG. 10, the speaker 11 is attached to a speaker box 11a composed of a wooden frame. The speaker box 11a is provided with a connection terminal group 11b including four connection terminals (a first connection terminal to a fourth connection terminal). The first connection terminal and the second connection terminal of the speaker box 11a are connected to the speaker 11 via signal wiring. The third connection terminal (a specific connection terminal) of the speaker box 11a is electrically connected to the fourth connection terminal by the signal wiring W1.

[0204] As shown in FIG. 10, the harness 300 is composed of bundling four signal wirings. One of the four connection terminals (a first connection terminal to a fourth connection terminal) of the four signal wirings is connected to the first connection terminal to the fourth connection terminal of the built-in relay board 260 respectively. On the other hand, the other four connection terminals (a fifth connection terminal to an eighth connection terminal) of the four signal wirings are connected to the first connection terminal to the fourth connection terminal of the speaker box 11a respectively. That is, between the first connection terminal of the built-in relay board 260 and the first connection terminal of the speaker box 11a is connected by the signal wiring between the first connection terminal and the fifth connection terminal in the harness 300, and between the second connection terminal of the built-in relay board 260 and the second connection terminal of the speaker box 11a is connected by the signal wiring between the second connection terminal and the sixth connection terminal in the harness 300. Also, between the third connection terminal of the built-in relay board 260 and the third connection terminal of the speaker box 11a is connected by the signal wiring between the third connection terminal and the seventh connection terminal in the harness 300, and between the fourth connection terminal of the built-in relay board 260 and the fourth connection terminal of the speaker box 11a is connected by the signal wiring between the fourth connection terminal and the eighth connection terminal in the harness 300. Thereby, the speaker 11 is connected to the built-in relay board 260 via the harness 300.

[0205] Note that the number of signal wirings included in the harness 300 is not limited to four, and is appropriately changed according to, for example, the specifications of the digital audio power amplifier 262 and the speaker 11, the connection configuration between both, and the like. The harness 300 only needs to include at least a signal wiring for connecting the output terminal of the digital audio power amplifier 262 and the speaker 11, and a signal wiring for grounding the mute terminal of the digital audio power amplifier 262 via the speaker box 11a.

[0206] As described above, when the built-in relay board 260 and the speaker 11 are connected via the harness 300, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the speaker 11 via the harness 300. Further, the mute terminal (MUTE) of the digital audio power amplifier 262 is grounded via the NOT circuit 268, the harness 300, and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a.

[0207] As a result, in a state where the speaker 11 is connected to the built-in relay board 260 (digital audio power amplifier 262) via the harness 300, a LOW-level voltage signal is input to the NOT circuit 268, so the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 becomes HIGH level. In this case, an audio signal is output from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 to the speaker 11.

[0208] On the other hand, when the speaker 11 is not connected to the built-in relay board 260 (digital audio power amplifier 262), the third connection terminal of the built-in relay board 260 is in an open state. In this case, since the power supply voltage (+5V) is input to the NOT circuit 268, the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 becomes LOW level, and the above-described mute function of the digital audio power amplifier 262 operates.

[0209] That is, when the speaker 11 is disconnected from the built-in relay board 260 (digital audio power amplifier 262), a state is generated in which the output of the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 to the first connection terminal and the second connection terminal of the built-in relay board 260 is stopped. As a result, the occurrence of a resonance phenomenon between the digital audio power amplifier 262 (output terminal) and the first and second connection terminals of the built-in relay board 260 can be suppressed, and malfunctions such as failures of the digital audio power amplifier 262 can be prevented.

[0210] As described above, in the present embodiment, the mute function of the digital audio power amplifier 262 can be activated regardless of the software control by the host control circuit 210 and the audio / LED control circuit 220. Therefore, for example, in a situation where the speaker 11 is disconnected from the built-in relay board 260, even if the host control circuit 210 and the audio / LED control circuit 220 recognize that they are performing output stop control of the audio signal, if an audio signal is erroneously output due to a bug (malfunction) in the program or the like, or in a pachinko gaming machine 1 having a structure in which the game board cannot be replaced unless the speaker 11 is removed from the harness 300, after the replacement of the game board is completed, if the door is closed without erroneously connecting the speaker 11 and the harness 300 and the audio output is started, etc., the mute function of the digital audio power amplifier 262 described above operates hard. In this case, the digital audio power amplifier 262 can be surely protected, and the safety of the pachinko gaming machine 1 can be improved.

[0211] Furthermore, in the present embodiment, as described above, the third connection terminal of the built-in relay board 260 is connected to a ground (GND) terminal provided in the built-in relay board 260 via the harness 300 and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a. In such a configuration, when the signal level of the third connection terminal of the built-in relay board 260 is LOW, it can be determined whether this factor is due to the fourth connection terminal of the built-in relay board 260 being grounded by measuring the signal level of the fourth connection terminal of the built-in relay board 260. Therefore, the digital output operation from the digital audio power amplifier 262 can be managed more accurately.

[0212] [Display control circuit] Next, with reference to FIG. 11, the internal configuration of the display control circuit 230 will be described. FIG. 11 is a block diagram showing the circuit configuration inside the display control circuit 230 and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuit sections.

[0213] As shown in FIG. 11, the display control circuit 230 includes a memory controller 231, a command memory 232, a command parser 233, a video decoder 234, a still image decoder 235, an SDRAM controller 236, a built-in VRAM 237, a first display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241. The connection relationship between the respective parts within the display control circuit 230 and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuits are as follows.

[0214] In the display control circuit 230, the memory controller 231 is connected to the command parser 233, the video decoder 234, and the still image decoder 235. In addition to the memory controller 231, the command parser 233 is connected to the command memory 232, the video decoder 234, the still image decoder 235, and the 3D geometry engine 240. In addition to the memory controller 231 and the command parser 233, the video decoder 234 is connected to the SDRAM controller 236. In addition to the memory controller 231 and the command parser 233, the still image decoder 235 is connected to the built-in VRAM 237.

[0215] Also, in the display control circuit 230, in addition to the video decoder 234, the SDRAM controller 236 is connected to the built-in VRAM 237, the first display controller 238, and the second display controller 239. In addition to the still image decoder 235 and the SDRAM controller 236, the built-in VRAM 237 is connected to the first display controller 238, the second display controller 239, and the rendering engine 241. Further, in addition to the command parser 233, the 3D geometry engine 240 is connected to the rendering engine 241.

[0216] Note that the SDRAM 250 is connected to the memory controller 231 and the SDRAM controller 236 in the display control circuit 230. Also, the CGROM board 204 is connected to the memory controller 231 in the display control circuit 230. Also, the host control circuit 210 is connected to the memory controller 231 and the command memory 232 in the display control circuit 230. Further, the display device 13 is connected to the first display controller 238 and the second display controller 239 in the display control circuit 230.

[0217] Next, the configuration of each part in the display control circuit 230 will be described.

[0218] The memory controller 231 mainly controls the communication between various external memories (the CGROM board 204 and the SDRAM 250) and the display control circuit 230. For example, the memory controller 231 performs processes such as transmitting and receiving address designation signals of external memories to be controlled, and managing the ready and busy states of the memories, and performs a process of acquiring data (such as rendering data and command data) stored at the designated address in various memories.

[0219] The command memory 232 is an internal memory that stores a command list. Note that the command list can also be stored in the SDRAM 250 and the CGROM board 204 (CGROM 206) in addition to the command memory 232.

[0220] The command parser 233 acquires a command list from the designated memory (the command memory 232, the SDRAM 250, or the CGROM 206). Specifically, in this embodiment, the type of memory (the command memory 232, the SDRAM 250, or the CGROM 206) in which the command list is arranged and its start address are set in a system control register (not shown) in the display control circuit 230 by the host control circuit 210. Then, the command parser 233 accesses the start address in the memory designated in the system control register (not shown) to acquire the command list.

[0221] In addition, the command parser 233 analyzes the acquired command list to generate a specific control code, and outputs the control code to the video decoder 234, the still image decoder 235, and the 3D geometry engine 240. In this embodiment, each image processing module in the display control circuit 230 operates based on the control code output by the command parser 233.

[0222] The video decoder 234 decodes (decodes) the video compression data acquired from the CGROM board 204 or the SDRAM 250. Then, the video decoder 234 outputs the decoded video data to the SDRAM 250 (external RAM). Note that the video data (decoding result) output from the video decoder 234 is stored in the movie buffer provided in the SDRAM 250.

[0223] The still image decoder 235 decodes the still image compression data acquired from the CGROM board 204 or the SDRAM 250. Then, the still image decoder 235 outputs the decoded still image data to the built-in VRAM 237. Note that the still image data (decoding result) output from the still image decoder 235 is temporarily stored in the sprite buffer, which will be described later, provided in the built-in VRAM 237.

[0224] The SDRAM controller 236 is a controller that controls operations such as storing the decoded video data and still image data in the RAM and transferring the image data between the built-in VRAM 237 and the CGROM board 204 or the SDRAM 250.

[0225] The built-in VRAM 237 operates as a work RAM when executing various processes such as decoding and rendering in the drawing process by the display control circuit 230. Also, in the transfer process of the image data between the built-in VRAM 237 and the CGROM board 204 or the SDRAM 250, which is performed in each process of the drawing process described later, various image data are temporarily stored in the built-in VRAM 237.

[0226] Each of the first display controller 238 and the second display controller 239 acquires the rendering result (drawing result) generated by the rendering engine 241 and outputs the rendering result to the display device 13. As a result, a predetermined image is displayed on the display screen of the display device 13. When two display controllers are provided as in the pachinko gaming machine 1 of the present embodiment, one display control circuit 230 (one chip) can provide two screens to the display device 13 and independently control each screen.

[0227] Based on the control code input from the command parser 233, the 3D geometry engine 240 performs processing for converting three-dimensional information into two-dimensional information (projection conversion processing) and affine conversion (graphic conversion) processing such as enlargement, reduction, rotation, and movement of graphics. Then, the 3D geometry engine 240 outputs the result of the conversion processing to the rendering engine 241.

[0228] The rendering engine 241 refers to a texture source (SDRAM 250 in this embodiment) in which the extended still image data and video data are stored, and performs rendering (drawing) processing on the image data. Then, the rendering engine 241 writes the rendering result to a rendering target (in this embodiment, the built-in VRAM 237 or SDRAM 250).

[0229] Note that "rendering (drawing)" as used in this specification means editing data decoded according to specified information such as enlargement, reduction, and rotation of a video (in this embodiment, information output from the 3D geometry engine 240). Also, the "rendering engine" as used here includes, for example, a "rasterizer", a "pixel shader", and the like. Therefore, in the rendering engine 241, similar to the pixel shader, arithmetic processing of ARGB values (A: alpha value indicating transparency (opacity), R: luminance value of the red component, G: luminance value of the green component, B: luminance value of the blue component) is also performed on a pixel-by-pixel basis for the image data.

[0230] [Connection configuration between the display control circuit and the CGROM] In the pachinko gaming machine 1 of this embodiment, it has a configuration that can handle different types (NOR type or NAND type) of CGROMs connected to the display control circuit 230. Here, with reference to FIGS. 12 and 13, the connection configuration between the display control circuit 230 provided in the sub-board 202 and its peripheral circuits, and the CGROM mounted on the CGROM board will be described.

[0231] FIG. 12 is a connection configuration diagram between the sub-board 202 and the CGROM board 204a when the CGROM is the NOR-type CGROM 206a (NOR-type flash memory). Further, FIG. 13 is a connection configuration diagram between the sub-board 202 and the CGROM board 204b when the CGROM is the NAND-type CGROM 206b (NAND-type flash memory). Note that in FIGS. 12 and 13, to more clearly show the configuration of the connection part, the state where the CGROM board is detached from the sub-board 202 is shown, but actually, both boards are connected via a board-to-board connector.

[0232] (1) Configuration of the sub-board First, the internal configuration of the sub-board 202 will be described. As is clear from the comparison between FIGS. 12 and 13, the configuration of the sub-board 202 when the NOR-type CGROM 206a is mounted on the CGROM board 204a is the same as that when the NAND-type CGROM 206b is mounted on the CGROM board 204b.

[0233] As shown in FIGS. 12 and 13, the sub-board 202 is provided with the display control circuit 230, and as its peripheral circuits, a bidirectional balun 301 and an AND circuit 302 (AND gate) are provided. Further, the sub-board 202 is provided with various signal wirings (buses) and a terminal group 303 including a plurality of connection terminals directly or indirectly connected to the display control circuit 230 via the various buses.

[0234] The bidirectional balun transceiver 301 has one set of four input / output terminals (terminals A0 to A3 in FIG. 12) and another set of four input / output terminals (terminals B0 to B3 in FIG. 12) respectively connected to the one set of four input / output terminals (terminals A0 to A3). The bidirectional balun transceiver 301 also has two control terminals (terminal OE and terminal DIR in FIG. 12) for switching and controlling the signal communication direction between input / output terminals A0 to A3 and input / output terminals B0 to B3.

[0235] The bidirectional balun transceiver 301 switches the signal communication direction between input / output terminals A0 to A3 and input / output terminals B0 to B3 according to the combination of the signal levels of the voltage signals respectively applied to control terminal OE and control terminal DIR. Thereby, even when an inconsistency occurs in the communication direction (communication operation) for some reason, the safety of the communication operation between the display control circuit 230 and the CGROM can be ensured. The switching control operation of the communication direction in the bidirectional balun transceiver 301 will be described in detail later. The bidirectional balun transceiver 301 used in this embodiment is also compatible with a system having two power supplies of 3.3V and 5V.

[0236] The display control circuit 230 is provided with four input / output dual-purpose terminals (terminals GMA31 / GRB3 to GMA28 / GRB0 in FIG. 12). When the CGROM is the NOR-type CGROM206a, these input / output dual-purpose terminals GMA31 / GRB3 to GMA28 / GRB0 act as the output terminals of the address bus, and when the CGROM is the NAND-type CGROM206b, they act as the input terminals of the ready / busy signal. The display control circuit 230 is also provided with 26 output terminals (terminals GMA27 to GMA2 in FIG. 12) that act as the output terminals for data (such as address designation data) related to the addresses in the data storage area of the CGROM.

[0237] In addition, the display control circuit 230 is provided with two CG memory chip enable output terminals (terminals GCE_0 and GCE_1 in FIG. 12). In this embodiment, the display control circuit 230 has two memory spaces corresponding to the two CG memory chip enable output terminals (GCE_0 and GCE_1: specific output terminals), and information such as the type of memory, bus width, and access timing is set in each memory space. However, in this embodiment, when the display control circuit 230 mixes a synchronous-mode ROM and an asynchronous-mode ROM, it cannot be configured to be used.

[0238] Furthermore, the display control circuit 230 is provided with a plurality of data bus input terminals for acquiring image data (compressed data of video / still images) from the CGROM via the data bus.

[0239] The electrical connection relationship of the above-described components provided on the sub-board 202 is as follows.

[0240] The input / output shared terminals GMA31 / GRB3 to GMA28 / GRB0 of the display control circuit 230 are respectively connected to the input / output terminals B0 to B3 of the bidirectional balun 301 as shown in FIGS. 12 and 13. The input / output terminals A0 to A3 of the bidirectional balun 301 are respectively connected to the first connection terminal to the fourth connection terminal of the terminal group 303. That is, the input / output shared terminals GMA31 / GRB3 to GMA28 / GRB0 of the display control circuit 230 are respectively connected to the first connection terminal to the fourth connection terminal of the terminal group 303 via the bidirectional balun 301.

[0241] Further, the output terminals GMA27 to GMA2 of the display control circuit 230 are respectively connected to the ninth connection terminal to the thirty-fourth connection terminal of the terminal group 303, and the CG memory chip enable output terminal GCE_0 and the CG memory chip enable output terminal GCE_1 are respectively connected to the thirty-fifth connection terminal and the thirty-sixth connection terminal of the terminal group 303. Further, the plurality of data bus input terminals of the display control circuit 230 are respectively connected to the corresponding connection terminals after the thirty-seventh connection terminal of the terminal group 303.

[0242] The control terminal DIR of the bidirectional balun 301 is connected to the fifth connection terminal of the terminal group 303, and the control terminal OE is connected to the output terminal of the AND circuit 302. One input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_0, and the other input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_1. Further, the sixth connection terminal and the seventh connection terminal of the terminal group 303 of the sub-board 202 are connected to the power supply voltage (+3.3V) terminal provided on the sub-board 202, and the eighth connection terminal is connected to the ground (GND) terminal provided on the sub-board 202.

[0243] (2) Configuration of the CGROM board (NOR type) Next, the internal configuration of the CGROM board 204a on which the NOR type CGROM 206a is mounted will be described with reference to FIG. 12.

[0244] When the NOR type CGROM 206a is mounted on the CGROM board 204a, the CGROM board 204a is provided with a terminal group 311 including various signal wirings (buses) and a plurality of connection terminals connected to the CGROM 206a via the various buses, together with the NOR type CGROM 206a.

[0245] The first connection terminal to the fourth connection terminal and the connection terminals after the ninth connection terminal in the terminal group 311 provided on the CGROM board 204a are connected to the CGROM 206a.

[0246] In the example shown in FIG. 12, since the CGROM 206a is a NOR type flash memory (random access type flash memory), the first to fourth connection terminals and the ninth to thirty-fourth connection terminals in the terminal group 311 are connected to the input terminals (not shown) of the address bus of the CGROM 206a. Also, the thirty-fifth and thirty-sixth connection terminals in the terminal group 311 are connected to the CG memory chip enable input terminals (not shown) of the CGROM 206a, and the connection terminals after the thirty-seventh connection terminal are connected to the data output terminals of the CGROM 206a used when the display control circuit 230 acquires image data (compressed data of moving images / still images) from the CGROM 206a.

[0247] In addition, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 provided on the CGROM substrate 204a is connected to the eighth connection terminal via the signal wiring W2, and the eighth connection terminal is connected to the ground (GND) terminal provided on the CGROM substrate 204a. That is, when the CGROM 206a is a NOR type flash memory, the fifth connection terminal is grounded via the signal wiring W2. Further, the sixth and seventh connection terminals in the terminal group 311 are connected to the power supply voltage (+3.3V) terminal provided on the CGROM substrate 204a.

[0248] The number of connection terminals included in the terminal group 311 is the same as the number of connection terminals of the terminal group 303 for connecting the CGROM substrate provided on the sub-substrate 202. When connecting (mounting) the CGROM substrate 204a to the sub-substrate 202, the two substrates are connected such that the connection terminals of the CGROM substrate 204a are connected to the connection terminals of the sub-substrate 202 with the same terminal numbers. That is, as shown in FIG. 12, the first connection terminal, the second connection terminal,..., the thirty-seventh connection terminal,... of the CGROM substrate 204a are respectively connected to the first connection terminal, the second connection terminal,..., the thirty-seventh connection terminal,... of the sub-substrate 202.

[0249] (3) Configuration of the CGROM Substrate (NAND Type) Next, the internal configuration of the CGROM substrate 204b equipped with the NAND-type CGROM 206b will be described with reference to FIG. 13. In the configuration of the CGROM substrate 204b shown in FIG. 13, the same components as those of the CGROM substrate 204a equipped with the NOR-type CGROM 206a shown in FIG. 12 are denoted by the same reference numerals.

[0250] When the NAND-type CGROM 206b is mounted on the CGROM substrate 204b, a transistor circuit 312 is provided as its peripheral circuit on the CGROM substrate 204b together with the NAND-type CGROM 206b. In addition, the CGROM substrate 204b is provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals directly or indirectly connected to the CGROM 206b via the various buses.

[0251] The first to fourth connection terminals in the terminal group 311 of the CGROM substrate 204b are connected to the drain terminals of the transistor circuit 312. Note that the gate terminal of the transistor circuit 312 is connected to the CGROM 206b, and the source terminal is connected to the ground (GND) terminal provided on the CGROM substrate 204b. That is, the first to fourth connection terminals are connected to the CGROM 206b via the transistor circuit 312.

[0252] In the example shown in FIG. 13, since the CGROM 206b is a NAND-type flash memory (a flash memory with a sequential access method), the gate terminal of the transistor circuit 312, that is, the first to fourth connection terminals in the terminal group 311, are connected to the ready / busy output terminals (not shown) provided on the CGROM 206b.

[0253] Further, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 of the CGROM substrate 204b is connected to the sixth and seventh connection terminals via the signal wiring W3, and the sixth and seventh connection terminals are connected to the power supply voltage (+3.3V) terminal provided on the CGROM substrate 204b. That is, when the CGROM 206b is a NAND type flash memory, the fifth connection terminal is connected to the power supply voltage (+3.3V) terminal via the signal wiring W3.

[0254] Also, the eighth connection terminal in the terminal group 311 of the CGROM substrate 204b is connected to the ground (GND) terminal provided on the CGROM substrate 204b.

[0255] Furthermore, the connection terminals after the ninth connection terminal in the terminal group 311 of the CGROM substrate 204b are connected to the CGROM 206b. At this time, the ninth to thirty-fourth connection terminals are connected to the input terminals (not shown) for data related to the address provided in the CGROM 206b, and the thirty-fifth and thirty-sixth connection terminals are connected to the CG memory chip enable input terminals provided in the CGROM 206b. Also, the connection terminals after the thirty-seventh connection terminal are connected to the data output terminals (not shown) of the CGROM 206b that are used when the display control circuit 230 acquires image data (compressed data of moving images / still images) from the CGROM 206b.

[0256] Note that even when a NAND type CGROM 206b is mounted on the CGROM substrate 204b, the number of connection terminals included in the terminal group 311 of the CGROM substrate 204b is the same as the number of connection terminals in the terminal group 303 for connecting the CGROM substrate provided on the sub-substrate 202. And when connecting (mounting) the CGROM substrate 204b to the sub-substrate 202, the two substrates are connected such that the connection terminals of the CGROM substrate 204b are connected to the connection terminals of the sub-substrate 202 with the same terminal numbers. That is, as shown in FIG. 13, the first connection terminal, the second connection terminal,..., the thirty-seventh connection terminal,... of the CGROM substrate 204b are respectively connected to the first connection terminal, the second connection terminal,..., the thirty-seventh connection terminal,... of the sub-substrate 202.

[0257] [Description of the communication operation between the display control circuit and the CGROM] Next, with reference to FIGS. 12 to 15, the operation when the display control circuit 230 acquires image data (compressed data of video / still image) from the CGROM will be described. Note that FIG. 14 is a truth table showing the correspondence between the input signals and the output signals in the AND circuit 302 provided on the sub-board 202, and FIG. 15 is a truth table showing the correspondence between the signal levels applied to the control terminal OE and the control terminal DIR and the communication direction in the bidirectional balun 301 provided on the sub-board 202.

[0258] (1) Operations of the AND circuit and the bidirectional balun As shown in FIG. 14, the AND circuit 302 outputs a HIGH-level signal to the control terminal OE of the bidirectional balun 301 only when HIGH-level signals (voltage signals) are input to both input terminals, and outputs a LOW-level signal to the control terminal OE under other input conditions.

[0259] As shown in FIG. 15, when a LOW-level signal (voltage signal) is input to the control terminal OE and a LOW-level signal is input to the control terminal DIR of the bidirectional balun 301, the input / output terminals A0 to A3 of the bidirectional balun 301 act as output terminals, and the input / output terminals B0 to B3 act as input terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is from the display control circuit 230 to the CGROM.

[0260] Also, when a LOW-level signal is input to the control terminal OE and a HIGH-level signal is input to the control terminal DIR of the bidirectional balun 301, the input / output terminals A0 to A3 of the bidirectional balun 301 act as input terminals, and the input / output terminals B0 to B3 act as output terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is from the CGROM to the display control circuit 230.

[0261] When the combination of the signal level input to the control terminal OE of the bidirectional balun transceiver 301 and the signal level input to the control terminal DIR is a combination other than the above (When a HIGH-level signal is input to the control terminal OE of the bidirectional balun transceiver 301), the input / output terminals A0 to A3 and the input / output terminals B0 to B3 of the bidirectional balun transceiver 301 are in a HIGH impedance state ("Z" in FIG. 15), that is, a state equivalent to an open state, and communication is not performed between the display control circuit 230 and the CGROM.

[0262] (2) Communication operation between the display control circuit and the CGROM (NOR type) Here, first, consider the case where a CGROM substrate 204a equipped with a NOR-type CGROM 206a is connected (mounted) to the sub-substrate 202.

[0263] In this case, in the present embodiment, since a LOW-level signal is output from at least one of the two CG memory chip enable output terminals GCE_0 and GCE_1 of the display control circuit 230, a LOW-level signal is input to the control terminal OE of the bidirectional balun transceiver 301. The signal levels of the CG memory chip enable output terminals GCE_0 and GCE_1 are set in the hardware initialization process (see FIG. 38 described later).

[0264] In this embodiment, since the amplitude values of the output signals from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals) preset by the sub-control circuit 200 vary according to the type of CGROM, the amplitude values of the signals output from the CG memory chip enable output terminals GCE_0 and GCE_1 provided in the display control circuit 230 change according to the type of storage means. However, the mode of "the amplitude value of the output signal changes according to the type of CGROM" is not limited to this mode. As described in Modification Example 7 below, the display control circuit 230 may detect the type of the connected storage means and set the amplitude value of the signal output from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals) based on the detection result.

[0265] Also, as shown in FIG. 12, the fifth connection terminal of the sub-board 202 to which the control terminal DIR of the bidirectional balun 301 is connected is grounded via the fifth connection terminal of the CGROM board 204a and the signal wiring W2, so that a LOW-level signal is input to the control terminal DIR.

[0266] Therefore, when the CGROM board 204a equipped with the NOR-type CGROM 206a is connected to the sub-board 202, as shown in FIG. 15, the input / output terminals A0 to A3 of the bidirectional balun 301 act as output terminals, and the input / output terminals B0 to B3 act as input terminals. That is, the communication direction between the display control circuit 230 and the CGROM 206a in the bidirectional balun 301 is from the display control circuit 230 to the CGROM 206a.

[0267] In this case, the signal wiring connected via the first to fourth connection terminals of the sub-board 202 and the first to fourth connection terminals of the CGROM board 204a can be used as an address bus, and the display control circuit 230 can normally execute the memory address specifying operation for the NOR-type CGROM 206a. As a result, the display control circuit 230 can directly specify an address via the address bus and perform a data read operation.

[0268] (3) indicates the communication operation between the control circuit and the CGROM (NAND type). Next, consider the case where a CGROM board 204b equipped with a NAND-type CGROM 206b is connected (mounted) to the sub-board 202.

[0269] Also in this case, in the present embodiment, since a signal of LOW level is output from at least one of the two CG memory chip enable output terminals CGE_0 and CGE_1 of the display control circuit 230, a signal of LOW level is input to the control terminal OE of the bidirectional balun 301. That is, in the present embodiment, regardless of whether the type of the CGROM is NOR type or NAND type, a signal of LOW level is input to the control terminal OE of the bidirectional balun 301. Further, as shown in FIG. 13, the fifth connection terminal of the sub-board 202 to which the control terminal DIR of the bidirectional balun 301 is connected is connected to the power supply voltage (+3.3V) terminal via the fifth connection terminal of the CGROM board 204b and the signal wiring W3, so a signal of HIGH level is input to the control terminal DIR.

[0270] Therefore, when the CGROM board 204b equipped with the NAND-type CGROM 206b is connected to the sub-board 202, as shown in FIG. 15, the input / output terminals A0 to A3 of the bidirectional balun 301 act as input terminals, and the input / output terminals B0 to B3 act as output terminals. That is, the communication direction between the display control circuit 230 and the CGROM 206b in the bidirectional balun 301 is in the direction from the CGROM 206b to the display control circuit 230.

[0271] In this case, the signal wiring connected via the first to fourth connection terminals of the sub-substrate 202 and the first to fourth connection terminals of the CGROM substrate 204b can be used as the communication wiring for the ready / busy signal. That is, in this case, when data is read from the NAND-type CGROM 206b in a sequential access method, the transmission process of the ready / busy signal from the CGROM 206 to the display control circuit 230 that the display control circuit 230 refers to can be executed. As a result, the display control circuit 230 can normally execute the operation of acquiring the state (ready / busy state) of the memory with respect to the NAND-type CGROM 206b.

[0272] As described above, in this embodiment, even if the type of the CGROM changes, the communication operation between the display control circuit 230 and the CGROM can be normally executed without changing the configuration of the sub-substrate 202. Therefore, in this embodiment, for example, an optimal CGROM can be selected in consideration of data capacity, communication speed, price, etc. Further, for example, when manufacturing a new pachinko game machine 1, even in the case of reusing the sub-substrate 202 used in the pachinko game machines manufactured in the past according to the conditions such as data capacity and communication speed and only changing the type of the CGROM, it can be easily dealt with. That is, in the pachinko game machine 1 of this embodiment, it becomes possible to select the CGROM according to the embodiment, and the expandability of the pachinko game machine 1 can be ensured.

[0273] Furthermore, in this embodiment, by using the bidirectional balun 301, the first to fourth connection terminals in the terminal group 303 of the sub-substrate 202 and the first to fourth connection terminals in the terminal group 311 of the CGROM substrate 204 can be used as terminals for both data input and output. In this case, it is not necessary to separately provide data input terminals and output terminals corresponding to the first to fourth connection terminals of the sub-substrate 202 and the CGROM substrate 204, and space saving of the sub-substrate 202 and the CGROM substrate 204 can be achieved.

[0274] Note that, as described above, in this embodiment, the bidirectional balun 301 can switch the "communication mode" between the display control circuit 230 and the CGROM according to the type of the CGROM. However, the "communication mode" between the display control circuit 230 and the CGROM as referred to in this specification means the overall transmission and reception modes of various information between the display control circuit 230 and the CGROM.

[0275] For example, the "communication mode" between the display control circuit 230 and the CGROM as referred to in this specification includes not only the transmission and reception mode between the display control circuit 230 and the CGROM of the data (image data (compressed data of video / still image)) necessary when displaying information related to the effect operation on the display device 13, but also the transmission and reception mode when communicating the information specifying the address of the data stored in the CGROM between the display control circuit 230 and the CGROM, and the transmission and reception mode when the display control circuit 230 receives the ready / busy signal from the CGROM. Note that the present invention is not limited to this, and the "communication mode" as referred to in this specification may mean only the communication mode in which the transmission and reception mode of information changes according to the type of the CGROM.

[0276] <Type of game state> Next, the types of game states controlled and managed by the main CPU 71 will be described.

[0277] In this embodiment, the types of game states controlled and managed by the main CPU 71 include a "big win game state" (special game state) and a "small win game state" (specific game state) in which the expectations of winning balls are different from each other. The "big win game state" is a game state in which a round game with a long opening period (i.e., a period of one round) (e.g., 30 sec, etc.) of the shutter of the first big winning port 53 or the second big winning port 54 occurs, and it is a game state in which a large number of winning balls can be expected by the player. That is, in the "big win game state", the repeating pattern of the opening state and the closing state of the shutter of the big winning port becomes an advantageous state for the player.

[0278] On the one hand, the "small win gaming state" is a gaming state in which a round game with a shorter period per round (e.g., 1.8 seconds, etc.) than the "big win gaming state" occurs, and it is a gaming state in which a large number of prize balls cannot be expected by the player. That is, in the "small win gaming state", the repeating pattern of the open state and the closed state of the shutter of the big winning opening becomes an unfavorable state for the player.

[0279] Also, in the present embodiment, as types of gaming states controlled and managed by the main CPU 71, there are a "probability-variable gaming state" (high-probability gaming state) and a "normal gaming state" (low-probability gaming state) in which the winning probabilities of "big wins" are different from each other.

[0280] The "probability-variable gaming state" is a gaming state with a high winning probability of "big win" (1 / 131 in the present embodiment). On the other hand, the "normal gaming state" is a gaming state with a lower winning probability of "big win" (1 / 392 in the present embodiment) compared to the "probability-variable gaming state".

[0281] Furthermore, in the present embodiment, as types of gaming states controlled and managed by the main CPU 71, there are a "time-saving gaming state" (high-winning gaming state) and a "non-time-saving gaming state" (low-winning gaming state) in which the winning probabilities of the normal symbols (the probabilities of the normal symbols being in the "winning" mode) are different from each other.

[0282] As used in this specification, the "time-saving game state" refers to a game state in which the winning probability of the normal symbol is high. That is, the "time-saving game state" is a game state in which the normal electric accessory 46 (blade member) provided at the second start port 45 is likely to be in an open state (a game state in which winning at the second start port is likely to occur), and is a game state advantageous to the player. Note that the "time-saving game state" ends when a "big win" is determined or when the variable display of special symbols for a predetermined number of time-saving times described later is executed. Also, in the time-saving game state, as the variable time, which is the time for executing the variable display of special symbols during the state, it may be controlled so that a variable time shorter than the variable time selected during the normal game state is more likely to be selected. By such control, the variable time may be shortened in the time-saving game state compared to during the normal game state, and a game state advantageous to the player may be provided by increasing the number of game times per unit time.

[0283] On the other hand, the "non-time-saving (no time-saving) game state" refers to a game state in which the winning probability of the normal symbol is lower than that in the "time-saving game state". Therefore, the "non-time-saving game state" is a game state in which the normal electric accessory 46 (blade member) is unlikely to be in an open state (a game state in which winning at the second start port is unlikely to occur), and is a game state disadvantageous to the player.

[0284] And in this embodiment, game states of various combinations of the above-described game states other than the "big win game state" and the "small win game state" are provided. Specifically, in this embodiment, a game state in which the "probability variable game state" and the "time-saving game state" occur simultaneously (hereinafter referred to as the state of "high probability variable with time-saving"), and a game state in which the "probability variable game state" and the "non-time-saving game state" occur simultaneously A state called "without high-probability time reduction" is provided. In the state of "without high-probability time reduction", it is difficult for the player to determine whether the game state is the "probability-variable game state". Therefore, here, such a game state is also referred to as the "latent probability-variable game state". Further, in the present embodiment, a game state in which the "normal game state" and the "non-time-reduction game state" occur simultaneously (hereinafter referred to as the state of "without low-probability time reduction"), and a game state in which the "normal game state" and the "time-reduction game state" occur simultaneously (hereinafter referred to as the state of "with low-probability time reduction") are also provided.

[0285] <Configuration of the data table stored in the main ROM> Next, with reference to FIGS. 16 to 25, the configuration of various data tables stored in the main ROM 72 of the main control circuit 70 will be described.

[0286] [Big-win random number determination table (when the first start port wins a prize)] First, with reference to FIG. 16, the big-win random number determination table (when the first start port wins a prize) will be described. The big-win random number determination table (when the first start port wins a prize) is a table referred to when determining any one of "big win", "small win" and "loss" by lottery based on the big-win determination random number value obtained when a game ball enters the first start port 44 (wins a prize). The big-win determination random number value is a random number value for determining the lottery result triggered by the start port winning a prize. More specifically, it is a random number value indicating the lottery result of the special symbols (the first special symbol and the second special symbol). Also, in the present embodiment, the big-win determination random number value (the random number value for lottery of special symbols) is selected from 0 to 65535 (65536 types).

[0287] Note that the big-win determination random number value is a random number value for determining the lottery result triggered by the start port winning a prize. More specifically, it is a random number value indicating the lottery result of the special symbols (the first special symbol and the second special symbol). Also, in the present embodiment, the big-win determination random number value (the random number value for lottery of special symbols) is selected from 0 to 65535 (65536 types).

[0288] In this embodiment, when a game ball wins a prize at the first start port 44, one of "big win", "small win", and "loss" is determined by lottery. Therefore, in the big win random number determination table (when winning a prize at the first start port), as shown in FIG. 16, for each value of the probability variation flag ("0 (= off)" or "1 (= on)"), the range of the big win determination random number value for which each of "big win", "small win", and "loss" is determined to win, and the relationship with the corresponding determination value data (any one of "big win determination value data", "small win determination value data", and "loss determination value data") are defined. The probability variation flag is one of the management flags stored in the main RAM 73, and is a flag for managing whether the game state is in a "probability variation game state". When the game state is in a "probability variation game state", the determination flag becomes "1".

[0289] In this embodiment, as shown in FIG. 16, when winning a prize at the first start port 44, if the probability variation flag is "0" and the big win determination random number value is any value from "777" to "943", "big win" is selected and "big win determination value data" is determined. That is, the winning probability of "big win" in this case (the "selection rate" in FIG. 16) is 167 / 65536.

[0290] Also, when winning a prize at the first start port 44, if the probability variation flag is "0" and the big win determination random number value is any value from "1" to "300", "small win" is selected and "small win determination value data" is determined. That is, the winning probability of "small win" in this case is 300 / 65536.

[0291] Furthermore, when winning a prize at the first start port 44, if the probability variation flag is "0" and the big win determination random number value is neither any value from "1" to "300" nor any value from "777" to "943", "loss" is selected and "loss determination value data" is determined.

[0292] On the other hand, when the first start port 44 wins a prize and the probability variation flag is "1" and the jackpot determination random value is any one of "777" to "1277", as shown in FIG. 16, "jackpot" is selected and "jackpot determination value data" is determined. That is, the winning probability of "jackpot" in this case (the "selection rate" in FIG. 16) is 500 / 65536, which is higher than that when the probability variation flag is "0".

[0293] Also, when the first start port 44 wins a prize and the probability variation flag is "1" and the jackpot determination random value is any one of "1" to "300", "small win" is selected and "small win determination value data" is determined. That is, the winning probability of "small win" in this case is 300 / 65536, which is the same as that when the probability variation flag is "0".

[0294] Furthermore, when the first start port 44 wins a prize and the probability variation flag is "1" and the jackpot determination random value is neither any one of "1" to "300" nor any one of "777" to "1277", "loss" is selected and "loss determination value data" is determined.

[0295] As described above, in this embodiment, when a game ball wins a prize at the first start port 44, the selection rate (jackpot probability) varies depending on whether the game state at the time of winning is a "probability variation game state". Specifically, the jackpot probability when a game ball wins a prize at the first start port 44 when the game state is a "probability variation game state" is approximately three times higher than that when the game state is not a "probability variation game state".

[0296] [Jackpot Random Determination Table (When the Second Start Port Wins a Prize)] Next, referring to FIG. 17, the jackpot random determination table (when the second start port wins a prize) will be described. The jackpot random determination table (when the second start port wins a prize) is a table referred to when performing a lottery on whether it is a "jackpot" based on the jackpot determination random value obtained when a game ball enters (wins a prize) the second start port 45. (Wins a prize)

[0297] In this embodiment, when a game ball wins a prize at the second start port 45, either "big win" or "loss" is determined by lottery. Note that when a game ball wins a prize at the second start port 45, "small win" is not selected. Therefore, in the big win random number determination table (when winning a prize at the second start port), as shown in FIG. 17, for each value of the probability variation flag ("0 (=off)" or "1 (=on)"), the range of the big win determination random number value for determining each of the "big win" and "loss" selections, and the relationship with the corresponding determination value data (either "big win determination value data" or "loss determination value data") are defined.

[0298] In this embodiment, as shown in FIG. 17, when winning a prize at the second start port 45, if the probability variation flag is "0" and the big win determination random number value is any value from "777" to "943", "big win" is selected and "big win determination value data" is determined. That is, the winning probability of "big win" in this case (the "selection rate" in FIG. 17) is 167 / 65536.

[0299] Also, when winning a prize at the second start port 45, if the probability variation flag is "0" and the big win determination random number value is not any value from "777" to "943", "loss" is selected and "loss determination value data" is determined.

[0300] On the other hand, when winning a prize at the second start port 45, if the probability variation flag is "1" and the big win determination random number value is any value from "777" to "1277", as shown in FIG. 17, "big win" is selected and "big win determination value data" is determined. That is, the winning probability of "big win" in this case (big win probability) is 500 / 65536, which is higher than that when the probability variation flag is "0".

[0301] Also, when winning a prize at the second start port 45, if the probability variation flag is "1" and the big win determination random number value is not any value from "777" to "1277", it is a "loss", and "loss determination value data" is determined.

[0302] As described above, in the present embodiment, even when a game ball wins a prize at the second start port 45, the selection rate (jackpot probability) varies depending on whether the game state at the time of winning is a "probability variation game state" or not. Specifically, similar to when a game ball wins a prize at the first start port 44, when a game ball wins a prize at the second start port 45, the jackpot probability when the game ball wins a prize at the second start port 45 when the game state is a "probability variation game state" is about three times higher than that when the game state is not a "probability variation game state".

[0303] [Symbol determination table (when the first start port wins a prize)] Next, with reference to FIG. 18, the symbol determination table (when the first start port wins a prize) will be described.

[0304] In the present embodiment, based on the winning type ("jackpot", "small win" or "loss") of the lottery based on the jackpot determination random value performed when a game ball wins a prize at the first start port 44 and the symbol random value (symbol determination random value) obtained when the first start port wins a prize, a special symbol is selected. The symbol determination table (when the first start port wins a prize) is a table referred to when selecting the special symbol. The symbol random value is a random value for determining the special symbol and is selected from 0 to 99 (100 types) regardless of the winning type of the lottery based on the jackpot determination random value.

[0305] As shown in FIG. 18, in the symbol determination table (when the first start port wins a prize), for each determination value data indicating the winning type of the lottery based on the jackpot determination random value, the relationship between the symbol designation command ("zA1" to "zA3") for designating the special symbol and the symbol random value when the symbol designation command is selected is defined.

[0306] When the winning type of the lottery based on the jackpot determination random value is "small win" (small win determination value data), the selected symbol designation command is one type (zA2), and that symbol designation command (zA2) is always determined. Also, when the winning type of the lottery based on the jackpot determination random value is "loss" (loss determination value data), the selected symbol designation command is one type (zA3), and that symbol designation command (zA3) is always determined.

[0307] On the other hand, when the winning category of the lottery based on the jackpot determination random value is "jackpot" (jackpot determination value data), as shown in FIG. 18, there are multiple types of special symbols to be selected, and multiple types ("z0" to "z4") of symbol designation commands (jackpot selection symbol commands in FIG. 18) are prepared for "jackpot". And when it is a "jackpot", the jackpot selection symbol command determined according to the symbol random value obtained also changes. For example, when the symbol random value obtained at the time of "jackpot" is any one of "40" to "59", the jackpot selection symbol command "z2" is selected, and its selection rate is 20 / 100.

[0308] [Symbol determination table (when winning at the second start port)] Next, with reference to FIG. 19, the symbol determination table (when winning at the second start port) will be described.

[0309] In this embodiment, based on the winning category ("jackpot" or "loss") of the lottery based on the jackpot determination random value performed when a game ball wins at the second start port 45, and the symbol random value (symbol determination random value) obtained when winning at the second start port, a special symbol is selected. The symbol determination table (when winning at the second start port) is a table referred to when selecting the special symbol.

[0310] In the symbol determination table (when winning at the second start port), as shown in FIG. 19, for each determination value data indicating the winning category of the lottery based on the jackpot determination random value, the relationship between the symbol designation command ("zA1" and "zA3") for designating the special symbol and the symbol random value for which the symbol designation command is selected is defined.

[0311] Note that even when the winning category of the lottery based on the jackpot determination random value is "loss" (loss determination value data), the selected symbol designation command is one type (zA3), and that symbol designation command (zA3) is always determined.

[0312] On the other hand, when the winning type of the lottery based on the jackpot determination random value is "jackpot" (jackpot determination value data), as shown in FIG. 19, there are multiple types of special symbols to be selected, and multiple types ("z0" and "z4") of symbol designation commands at the time of "jackpot" (jackpot selection symbol commands in FIG. 19) are prepared. And at the time of "jackpot", the jackpot selection symbol command determined according to the obtained symbol random value also changes. For example, when the symbol random value obtained at the time of "jackpot" is any one of "29" to "99", the jackpot selection symbol command "z4" is selected, and the selection rate is 80 / 100.

[0313] [Jackpot Type Determination Table] Next, with reference to FIGS. 20 to 23, the jackpot type determination table will be described. In the present embodiment, when the jackpot selection symbol command (any one of "z0" to "z4") is determined with reference to the symbol determination table (see FIGS. 18 and 19) at the time of jackpot, the type of "jackpot" (the content of the jackpot game) is determined based on the determined jackpot selection symbol command. The jackpot type determination table is a table referred to when determining the type of "jackpot" (the content of the jackpot game) based on the jackpot selection symbol command.

[0314] In addition, in the present embodiment, a jackpot type determination table is provided for each game state at the time of winning the "jackpot". FIG. 20 is the jackpot type determination table (No. 1) referred to when winning the "jackpot" when the game state is "low probability, no short time", and FIG. 21 is the jackpot type determination table (No. 2) referred to when winning the "jackpot" when the game state is "low probability, with short time". FIG. 22 is the jackpot type determination table (No. 3) referred to when winning the "jackpot" when the game state is "high probability, no short time", and FIG. 23 is the jackpot type determination table (No. 4) referred to when winning the "jackpot" when the game state is "high probability, with short time".

[0315] In the jackpot type determination table, the relationship between the jackpot selection symbol commands ("z0" to "z4") and various parameters for determining the type of "jackpot" is defined. The type of "jackpot" As various parameters for determining the content of the jackpot game, the value of the time-saving flag, the number of time-saving times, the value of the probability-variable flag, and the number of rounds in the jackpot game are defined.

[0316] For example, when winning the "jackpot" in the state of "high probability with time saving" and the jackpot selection symbol command "z1" is determined, as shown in FIG. 23, as various parameters for determining the type of "jackpot" (the content of the jackpot game), the time-saving flag "1", the number of time-saving times "100", the probability-variable flag "0", and the number of rounds "10" are set.

[0317] Note that the "number of rounds" defined in the jackpot type determination table is the number of rounds in the jackpot game during which the opening time of the big winning opening is relatively long. Also, the "time-saving flag" is one of the management flags stored in the main RAM 73 and is a flag for managing whether the game state is the "time-saving game state". When the game state is the "time-saving game state", the time-saving flag becomes "1 (on)". Also, the "number of time-saving times" is the number of times of the variable display of the special symbol given in the "time-saving game state".

[0318] [Prize-winning performance information determination table] Next, with reference to FIG. 24, the prize-winning performance information determination table will be described.

[0319] In this embodiment, the main control circuit 70 (main CPU 71) determines information used by the sub-control circuit 200 when determining the production content based on the winning type ("big win", "small win" or "loss") determined at the time of winning (starting port winning) and the symbol designation command or the big win selection symbol command. For example, in the sub-control circuit 200, information used when determining content related to the color change effect of the hold symbol indicating the hold ball of the special symbol, content related to the prediction effect, etc. is determined. The winning effect information determination table is a table referred to when determining the outline of the production content executed by the sub-control circuit 200 based on the information acquired by the main control circuit 70 at the time of winning (starting port winning).

[0320] In the winning effect information determination table, the relationship between the combination of various information determined at the time of winning (starting port winning) and the "winning effect information 1" and "winning effect information 2" indicating the outline of the production content executed by the sub-control circuit 200 is defined. In this embodiment, as various information determined at the time of winning (starting port winning), the type of the starting port, the type of the determination value data, the type of the big win selection symbol command, and the type of the symbol designation command are defined in the winning effect information determination table.

[0321] The winning effect information 1 ("1A" to "1D") defined in the winning effect information determination table is effect information mainly used by the sub-control circuit 200 when determining content related to the color change effect of the hold symbol indicating the hold ball of the special symbol. When the sub-control circuit 200 receives the winning effect information 1 determined based on the winning effect information determination table, the sub-control circuit 200 selects one effect pattern from a plurality of effect patterns related to the color change effect of the hold symbol included in the classification of the winning effect information 1.

[0322] In addition, the winning performance information 2 ("2A" to "2D") defined in the winning performance information determination table is performance information mainly used in the sub-control circuit 200 to determine the content related to the prediction performance (continuous prediction performance) based on the hold balls of the special symbols when determining. When the sub-control circuit 200 receives the winning performance information 2 determined based on the winning performance information determination table, the sub-control circuit 200 selects one performance pattern from a plurality of performance patterns of the prediction performance included in the classification of the winning performance information 2.

[0323] When referring to the winning performance information determination table of this embodiment, for example, when "big win" is won at the first start port winning, regardless of the type of the big win selection symbol command, "1A" is determined as the winning performance information 1, and "2A" is determined as the winning performance information 2.

[0324] [Variable performance pattern determination table] Next, with reference to FIG. 25, the variable performance pattern determination table will be described.

[0325] In this embodiment, the main control circuit 70 (main CPU 71) determines the variable performance pattern of the special symbol based on information such as the winning type ("big win", "small win" or "loss"), the symbol designation command, the big win selection symbol command, and the variable time when the variable display of the special symbol starts. The variable performance pattern determination table is a table referred to when determining this variable performance pattern of the special symbol.

[0326] Note that the variable performance pattern determined based on the variable performance pattern determination table (information included in the special symbol performance start command described later) is transmitted from the main control circuit 70 to the sub-control circuit 200 (host control circuit 210). Then, when the sub-control circuit 200 receives the information of the variable performance pattern, it determines the type of performance based on the received variable performance pattern and information such as the game state.

[0327] In the variable effect pattern determination table, as shown in FIG. 25, the relationship is defined between the combination of the symbol designation command, jackpot selection symbol command, and variable time of the special symbol determined at the time of winning (starting port winning), and the type of effect (variable effect pattern) executed by the sub-control circuit 200 during the variable display of the special symbol.

[0328] In this embodiment, the variable effect pattern is represented by a two-digit alphanumeric character, and is represented by the combination of the "upper" (first digit) parameter and the "lower" (second digit) parameter described in the variable effect pattern column in FIG. 25. For example, when the symbol designation command determined at the time of winning (starting port winning) is "zA1", the jackpot selection symbol command is "z0", and the variable time of the special symbol is "15000 msec", the variable effect parameter is "C1" (the combination of the upper "C" and the lower "1").

[0329] Note that in this embodiment, the information of the variable effect parameter is included in the special symbol effect start command described later. At this time, the "upper" parameter and the "lower" parameter defined in the variable effect pattern column are stored in different parameter areas. Therefore, in the variable effect pattern determination table, the "upper" parameter and the "lower" parameter of the variable effect pattern are defined separately.

[0330] <Configuration of the data table stored in the sub-main ROM> Next, the configuration of various data tables stored in the sub-main ROM 205 of the sub-control circuit 200 will be described with reference to FIG. 26.

[0331] [Variable effect table] First, the variable effect table will be described with reference to FIG. 26.

[0332] In the pachinko gaming machine 1 of the present embodiment, as described above, various effects are executed under the control of the sub-control circuit 200 (host control circuit 210) during the variable display of the special symbols. The content (effect pattern) of the effect performed at this time is determined based on information such as the variable effect pattern information of the special symbol included in the special symbol effect start command described later, which is transmitted from the main control circuit 70 to the sub-control circuit 200 at the start of the variable display of the special symbol. The variable effect table is used to determine this effect content (effect pattern) based on information such as the variable effect pattern and the game state.

[0333] As shown in FIG. 26, in the variable effect table, the correspondence between combinations of various information (including variable effect pattern information) determined at the time of winning (winning at the start port), the effect patterns ("EN00" to "EN44") and effect content determined by lottery, and the random number values and selection rates (winning probabilities) for selecting (determining) each effect pattern is defined. In the present embodiment, as various information determined at the time of winning (winning at the start port), the types of variable effect patterns of the special symbols ("A0" to "A4", "B1" to "B3", and "C1" to "CF"), the variable time of the special symbols, the winning type ("big win", "small win", or "loss"), the symbol designation command, and the big win selection symbol command are defined in the variable effect table.

[0334] In the present embodiment, it is assumed that the variable time of the special symbols defined in the variable effect table is approximately the same as the effect time of the corresponding effect pattern. Also, the random number values defined in the variable effect table are the random number values obtained in the sub-lottery process and are any of "0" to "999" (1000 types).

[0335] When determining the presentation pattern with reference to the variation presentation table of this embodiment, for example, when the variation pattern of the special symbol determined at the start of the variation display of the special symbol is "C1" and the random number value obtained when selecting the presentation pattern is any value from "0" to "499", "EN15" is selected as the presentation pattern. In this case, during the variation display period (15000 msec) of the special symbol, a presentation called "Normal Reach Presentation A" is performed. Then, upon the end of "Normal Reach Presentation A", a "big win" mode display is performed in the display area 13a of the display device 13, and the variation of the special symbol stops.

[0336] <Outline of the drawing control method> Next, the outline of the drawing process executed by the display control circuit 230 when a drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to FIG. 27. Note that FIG. 27 is a diagram showing the flow of image data (video data and still image data) during the drawing process.

[0337] In this embodiment, the data (compressed data) of the image (video and / or still image) to be displayed on the liquid crystal screen of the display device 13 is stored in the CGROM 206 in the CGROM substrate 204. When a drawing request is input to the display control circuit 230, the display control circuit 230 first reads out the image compressed data from the CGROM 206 and decodes (expands) it. At this time, when video compressed data is read out, the video compressed data is decoded by the video decoder 234 in the display control circuit 230, and when still image compressed data is read out, the still image compressed data is decoded by the still image decoder 235 in the display control circuit 230.

[0338] Next, the display control circuit 230 writes the decoding result (image expansion data) of the image data to a predetermined buffer specified as the texture source. In this embodiment, as the texture source, a movie buffer provided in the SDRAM 250 (external RAM), a texture buffer, or a sprite buffer in the built-in VRAM 237 is specified. For example, when displaying one video frame, the expanded video data (decoding result) is written to the movie buffer in the SDRAM 250. Also, for example, when displaying one still image, the expanded still image data is written to the sprite buffer in the built-in VRAM 237.

[0339] Next, the display control circuit 230 specifies a rendering target to which the rendering (drawing) result of the image data is written. As the rendering target, for example, a frame buffer provided in the SDRAM 250 (external RAM) or a frame buffer provided in the built-in VRAM 237 can be specified.

[0340] Next, the display control circuit 230 activates the rendering engine 241 to perform rendering processing on the decoding result of the image data written to the texture source, and writes the rendering result to the rendering target. In this process, the rendering processing is performed according to the specified information such as the enlargement / reduction and rotation of the video (various information input from the 3D geometry engine 240).

[0341] Next, the display control circuit 230 displays the rendering result (display output data) written to the rendering target on the display screen of the display device 13.

[0342] In this embodiment, two frame buffers are prepared as rendering targets. When writing the rendering result from the rendering engine 241 to the frame buffer, the frame buffer to which the rendering result is written is switched for each frame. For example, when the rendering result is written to one frame buffer in a predetermined frame, in the next frame, the rendering result is written to the other frame buffer, and in every other frame, the rendering result is written to one frame buffer. That is, in this embodiment, the process of writing the rendering result to one frame buffer and the process of writing the rendering result to the other frame buffer are alternately switched and executed for each frame.

[0343] Also, in the flow of the above-described process of writing the rendering result and the display process, the rendering result written to one frame buffer in a predetermined frame is displayed on the display screen of the display device 13 in the next frame (the function of one frame buffer is switched from the drawing function to the display function). Also, the rendering result written to the other frame buffer in the next frame is displayed on the display screen of the display device 13 in every other frame (the function of the other frame buffer is switched from the drawing function to the display function). That is, in this embodiment, the display process of the rendering result in one frame buffer and the display process of the rendering result in the other frame buffer are alternately switched and executed for each frame.

[0344] <Overview of the audio playback control method> Next, the outline of the audio playback process executed by the audio / LED control circuit 220 when a sound request is output from the host control circuit 210 to the audio / LED control circuit 220 will be described with reference back to FIG. 8.

[0345] In this embodiment, the audio data output to the speaker 11 is stored in the CGROM 206. The audio data stored in the CGROM 206 is phrase compressed data specified by a 13-bit long phrase number NUM (000H to 1FFFH), and up to 8,192 types (= 2^13) of a piece of a series of background music (BGM) or a set of production sounds (preview sounds), etc. are stored corresponding to the phrase number NUM respectively. And this phrase number NUM is specified by the set value (operation parameter) of the audio command transmitted from the host control circuit 210 to the command register 225 of the audio / LED control circuit 220.

[0346] The audio command is used for the Individual Write purpose of transmitting a 1-byte long set value to any one of a number of audio control registers built in the audio / LED control circuit 220, or for the Block Write purpose of transmitting a set of N set values to a series of consecutive N audio control register groups.

[0347] In any case, the audio control register to be accessed is specified by a 1-byte long register address, and the storage capacity of each audio control register is 1 byte. And in this embodiment, a number of audio control registers are secured by being divided into 7 register banks. That is, since the register bank is divided into 7 sections, the total number of audio control registers is theoretically up to 7 × 256.

[0348] In this embodiment, in all register banks, a specific register address serves as the audio control register for register bank setting. Therefore, to specify any one of the 7 × 256 audio control registers, after writing the register bank to the audio control register for bank setting by a preceding audio command, the audio control register belonging to that register bank is specified by a 1-byte long register address.

[0349] Incidentally, the operation of setting the set value to the voice control register does not necessarily require directly specifying the register address of the voice control register to be set. Instead, by specifying the SAC data (Simple Access Code Data) or the sequence code stored in the CGROM206, it is also possible to complete a series of setting operations for a group of voice control registers. To realize such an operation, the voice / LED control circuit 220 incorporates four simple access controllers 226a (simple Access Controller) and sixteen sequencers 226b shown in FIG. 8.

[0350] Explaining from the SAC (Simple Access Code) data for operating the simple access controller 226a, the SAC data is a data group of up to 512 pairs (= 1024 bytes) that corresponds the register address (1 byte) of the voice control register and the set value (1 byte) to the voice control register, and means an aggregate terminated with the SAC end code (FFFFH) (see FIG. 8).

[0351] In the case of this embodiment, up to 8192 types (= 2^13) of such SAC data can be provided. The host control circuit 210 can operate the simple access controller 226a by writing a 13-bit SAC number to the voice control register for SAC control (see FIG. 8). The simple access controller 226a that has started operating reads out a group of SAC data specified by the SAC number from the CGROM206 in order, and sets the set value indicated by the SAC data to the voice control register indicated by the SAC data.

[0352] Therefore, the host control circuit 210 only needs to write (register) the SAC number into the voice control register for SAC control, and can instruct a series of setting operations without individually specifying the register address of the voice control register. Note that it is also possible to set a standby time (standby information as attached data) that defines the start timing of a series of setting operations in the voice control register for SAC control, and it is also possible to delay the start timing of setting to the voice control register by the simple access controller 226a from the writing timing of the SAC number to the voice control register for SAC control.

[0353] Subsequently, the sequence code (Sequence Code) for operating the sequencer 226b will be described. Similar to the SAC data, the sequence code is also a plurality of sets of data that associate the register address (1 byte) of the voice control register with the set value (1 byte) to that voice control register (see FIG. 8). However, different from the SAC data, the sequence code can define a plurality of operation steps (a plurality of sequence steps) that can be intermittently executed after a predetermined standby time.

[0354] In addition, the voice control register for sequencer control can include, for each sequencer SQ0 to SQ15, a standby time (standby information) that defines the start timing of the setting operation, the presence or absence of a repetitive operation, and the number of repetitions (loop information). Therefore, the sequence code will specify a series of voice effects that require a predetermined time to execute.

[0355] As shown in FIG. 8, a plurality of operation steps are delimited by a step end code (FFFEH), and the end of the plurality of operation steps is terminated by a sequence end code (FFFFH). In the case of this embodiment, up to 8192 types (= 2^13) of sequence codes can also be provided. The host control circuit 210 can write a 13-bit sequence code number and associated data that defines the operation of the sequencer into the voice control register for sequencer control, thereby instructing the sequencer 226b to perform a series of setting operations.

[0356] In this embodiment, such SAC data and sequence codes are stored in advance in the CGROM 206 in the required combinations. A group of SAC data and a group of sequence codes are specified by SAC numbers and sequence code numbers. Therefore, in the case of this embodiment, the voice commands for Write purposes include not only cases where they define direct setting operations to the voice control register, but also cases where they define indirect setting operations via the simple access controller 226a and the sequencer 226b.

[0357] To implement the above operations, the host control circuit 210 and the voice / LED control circuit 220 are connected by a parallel signal line (data bus) capable of transmitting and receiving 1-byte data, a 2-bit operation management data line (address bus) capable of transmitting operation management data, a 2-bit control signal line capable of controlling read / write operations, and a chip select signal line for selecting the voice / LED control circuit 220.

[0358] The parallel signal line is realized by the data bus of the host control circuit 210, and the operation management data line is realized by the address bus of the host control circuit 210. The voice / LED control circuit 220 is assigned three port numbers PORT with the upper 6 bits being common and the lower 2 bits being 00, 01, 10. When the host control circuit 210 executes an I / OREAD instruction or an I / OWRITE instruction for these port numbers PORT, in any case, the circuit is configured such that the chip select signal CS becomes an active level.

[0359] Then, when an I / O READ command or an I / O WRITE command is executed, the data output to the lower 2 bits A0 to A1 of the address bus becomes operation management data A0 to A1 for the audio / LED control circuit 220. Based on these 2 bits A0 to A1, it is possible to specify whether the 1-byte data on the data bus at that time is a register address, or write data or read data.

[0360] That is, if the address data is

[00] , the data on the data bus at that timing is evaluated as a register address. On the other hand, if the address data is

[01] , the data on the data bus at that timing becomes write data or read data. Note that when an I / O READ command is executed, it is read data, and when an I / O WRITE command is executed, it is write data.

[0361] Therefore, the transmission operation of an audio command for writing a predetermined set value to a predetermined audio control register is realized by continuously executing an I / OWRITE command while shifting the lower 2 bits A0 and A1 of the port number PORT of the audio / LED control circuit 220. Specifically, while shifting the lower 2 bits A0 to A1 of the address data as

[00] →

[01] , the 1-byte data on the data bus is shifted as [register address of the audio control register] → [write data to the audio control register], thereby realizing the transmission operation of a predetermined audio command.

[0362] When writing data is multiple bytes long and the register addresses of the control registers are consecutive, as in the case of transmitting an SAC number (13 bits), a sequence code number (13 bits), and accompanying control data (such as standby information and loop information), the operation management data A0 to A1 of

[01] is repeated as

[00] →

[01] →

[01] →

[01] , and the multiple-byte write data is transmitted.

[0363] The voice command transmitted in this way is then validated inside the voice / LED control circuit 220 as long as there is no communication anomaly. However, if a communication anomaly is recognized, such as when the data of multiple byte lengths do not match each other, the voice command will not be validated. Then, the error flag of the voice control register is set, and this error flag (status information STS) can be received by executing an I / O READ command that transitions the operation management data A0 to A1 of the address bus from

[01] to

[10] .

[0364] In this way, in this embodiment, in the final cycle where the operation management data A0 to A1 transitions as

[00] →

[01] → ···

[01] →

[10] , error information (FFH in case of anomaly) of multiple bit lengths can be obtained. And by retransmitting the voice command that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of this embodiment, the unnaturalness such that the voice effect suddenly stops can be eliminated.

[0365] On the other hand, the data reading operation by the I / O READ operation is realized by continuously executing an I / O WRITE command and an I / O READ command while transitioning the lower 2 bits A0 and A1 of the port number PORT of the voice / LED control circuit 220. When the read data is of multiple byte lengths, the I / O READ command is continued for the required number of bytes.

[0366] Specifically, upon confirmation, first, as an I / O WRITE operation, [the register address (1 byte length) of the voice control register that stores operation status, etc.] is output to the port number PORT where the lower 2 bits A0 to A1 of the address data are

[00] . Next, by executing an I / O READ command for the port number PORT where the lower 2 bits A0 to A1 of the address data are

[01] , necessary data such as the operation status can be obtained from a predetermined voice control register.

[0367] The sound reproduced by the audio / LED control circuit 220 having the above configuration is transmitted to the digital audio power amplifier 262 in the form of a 5-bit signal (SCLK, LRO, SD0, SD1, SD2) as a digital audio signal of the audio / LED control circuit 220, amplified in class D by the digital audio power amplifier 262, and supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to the lower speaker for bass, and the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to four normal speakers (for example, see FIG. 9 (L0, R0, L1, R1)) and two subwoofers (for vibration) (for example, see FIG. 9 (SUB0, SUB1)) that are substantially aligned in the vertical and horizontal positions with respect to the player.

[0368] <Description of the operation of the main control circuit> Next, with reference to FIGS. 28 to 35, the contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described.

[0369] [Main control main process] First, with reference to FIG. 28, the main control main process under the control of the main CPU 71 will be described. Note that FIG. 28 is a flowchart showing the procedure of the main control main process in the present embodiment.

[0370] When the pachinko game machine 1 is powered on, first, the main CPU 71 performs an initial setting process (S1). In this process, the main CPU 71 performs processes such as permission to access the main RAM 73, backup restoration, and initialization of the work area. Next, the main CPU 71 performs an update process of the initial value random number (S2). In this process, the main CPU 71 updates the initial random number counter value.

[0371] Next, the main CPU 71 performs special symbol control processing (S3). In this processing, the main CPU 71 performs predetermined control processing regarding the progress of the special symbol game and the special symbols (the first special symbol and the second special symbol) displayed on the special symbol display device 61. Note that the details of the special symbol control processing will be described later with reference to FIG. 29.

[0372] Next, the main CPU 71 performs normal symbol control processing (S4). In this processing, the main CPU 71 performs predetermined control processing regarding the progress of the normal symbol game and the normal symbols displayed on the normal symbol display device 62.

[0373] Next, the main CPU 71 performs control processing of the symbol display device (S5). In this processing, the main CPU 71 performs display control of variable display of the special symbols (the first special symbol and the second special symbol) and the normal symbols based on the execution results of the special symbol control processing (S3) and the normal symbol control processing (S4).

[0374] Next, the main CPU 71 performs game information data generation processing (S6). In this processing, the main CPU 71 generates game information data to be transmitted to the payout / firing control circuit 123, the sub-control circuit 200, the hall computer of the game parlor, etc., and stores the game information data in the main RAM 73.

[0375] Next, the main CPU 71 performs storage / game state data generation processing (S7). In this processing, the main CPU 71 generates storage / game state data to be transmitted to the sub-control circuit 200 based on the values of the probability variation flag and the time shortening flag, and stores the storage / game state data in the main RAM 73.

[0376] Then, after the processing of S7, the main CPU 71 returns the processing to the processing of S2 and repeats the processing after S2 described above.

[0377] [Special Symbol Control Processing] Next, with reference to FIG. 29, the special symbol control process performed in S3 during the main control main process (see FIG. 28) will be described. FIG. 29 is a flowchart showing the procedure of the special symbol control process in the present embodiment. Note that the numerical values in parentheses ("00" to "08") shown beside the reference numerals of each processing step shown in FIG. 29 indicate the values of the control state flags, and these control state flags are stored in a predetermined storage area in the main RAM 73. The main CPU 71 advances the special symbol game by executing each processing step corresponding to the numerical value of the control state flag.

[0378] First, the main CPU 71 loads the control state flag (S11). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

[0379] Based on the value of the control state flag loaded in S11, the main CPU 71 determines whether to execute various processes of S12 to S20 described later. This control state flag indicates the state of the game of the special symbol game and enables the execution of any one of the processes of S12 to S20.

[0380] Also, the main CPU 71 executes the processing of each step at a predetermined timing determined according to the waiting time set for each processing of S12 to S20. Note that before reaching this predetermined timing, other subroutine processes are executed without executing the processing of each step. Also, the system timer interrupt process (see FIG. 33 described later) is executed at a predetermined cycle.

[0381] Then, when the process of S11 ends, the main CPU 71 performs a special symbol memory check process (S12).

[0382] In this process, when the control state flag has a value indicating the special symbol memory check process ("00"), the main CPU 71 checks the number of pending variable displays of the special symbol. If the number of pending displays is not "0" (when there are pending balls), the main CPU 71 performs processes such as a winning determination, a determination of the special symbol, and a determination of the variation pattern of the special symbol. Also, in this process, the main CPU 71 sets the control state flag to a value ("01") indicating the special symbol variation time management process (S13) described later, and sets the variation time of the special symbol corresponding to the variation pattern determined in this process to the waiting time timer. That is, by this process, after the variation time of the special symbol corresponding to the variation pattern determined in the process of S12 has elapsed, the special symbol variation time management process described later is set to be executed.

[0383] On the other hand, when the number of pending displays is "0" (when there are no pending balls), the main CPU 71 performs a demo display process for displaying a demo screen. Note that the details of the special symbol memory check process will be described later with reference to FIG. 30.

[0384] Next, the main CPU 71 performs the special symbol variation time management process (S13). In this process, when the control state flag has a value indicating the special symbol variation time management process ("01") and the variation time of the special symbol has elapsed, the main CPU 71 sets the control state flag to a value ("02") indicating the special symbol display time management process (S14) described later, and sets the waiting time after confirmation to the waiting time timer. That is, by this process, after the waiting time after confirmation set in the process of S13 has elapsed, the special symbol display time management process described later is set to be executed.

[0385] Next, the main CPU 71 performs special symbol display time management processing (S14). In this processing, when the control state flag has a value indicating special symbol display time management processing ("02") and the determined waiting time set in the processing of S13 has elapsed, the main CPU 71 determines whether the result of the hit determination is "big hit" or "small hit". And when the result of the hit determination is "big hit" or "small hit", the main CPU 71 sets a value ("03") indicating the big hit start interval management processing (S15) described later in the control state flag, and sets the time corresponding to the big hit start interval in the waiting time timer. That is, by this processing, after the time corresponding to the big hit start interval set in the processing of S14 has elapsed, the big hit start interval management processing described later is set to be executed.

[0386] On the other hand, when the result of the hit determination is not "big hit" or "small hit", the main CPU 71 sets a value ("08") indicating the special symbol game end processing (S20) described later in the control state flag. That is, in this case, the special symbol game end processing described later is set to be executed. Note that the details of the special symbol display time management processing will be described later with reference to FIG. 31.

[0387] Next, when it is determined in S14 that the result of the hit determination is "big hit" or "small hit", the main CPU 71 performs big hit start interval management processing (S15). In this processing, when the control state flag has a value indicating big hit start interval management processing ("03") and the time corresponding to the big hit start interval set in the processing of S14 has elapsed, in order to open the first big winning opening 53 or the second big winning opening 54, based on the data read from the main ROM 72, the main CPU 71 updates the variable located in the main RAM 73.

[0388] Also, in this process, the main CPU 71 sets a value ("04") indicating the jackpot opening process (S16) described later in the control status flag, and sets the upper limit time for opening the jackpot (e.g., 30 sec) in the jackpot opening time timer. That is, by this process, it is set so that the jackpot opening process described later is executed.

[0389] Next, the main CPU 71 performs the jackpot opening process (S16). In this process, first, when the control status flag is a value ("04") indicating the jackpot opening process, the main CPU 71 checks if either the condition that the jackpot winning counter is equal to or greater than a predetermined number, or the condition that the upper limit time has elapsed (the jackpot opening time timer is "0") (a predetermined closing condition is satisfied).

[0390] In S16, when one of the conditions is satisfied, the main CPU 71 updates the variable located in the main RAM 73 to close a predetermined jackpot (the first jackpot or the second jackpot). Then, the main CPU 71 sets a value ("05") indicating the residual ball monitoring process in the jackpot (S17) described later in the control status flag, and sets the residual ball monitoring time in the jackpot in the waiting time timer. That is, by this process, it is set so that the residual ball monitoring process in the jackpot set in S17 is executed after the residual ball monitoring time in the jackpot has elapsed.

[0391] Also, the main CPU 71 sends an inter-round display command to the sub-control circuit 200 immediately before the end of the jackpot opening process in S16.

[0392] Next, the main CPU 71 performs the residual ball monitoring process in the jackpot (S17). In this process, the main CPU 71 checks if the condition that the value of the jackpot opening count counter is equal to or greater than the maximum value of the jackpot opening counts (the final round) is satisfied when the control status flag is a value ("05") indicating the residual ball monitoring process in the jackpot and the residual ball monitoring time in the jackpot has elapsed.

[0393] In S17, when the main CPU 71 determines that the above conditions are not satisfied, the main CPU 71 sets a value indicating the jackpot opening reopening waiting time management process ("06") in the control status flag. Also, the main CPU 71 sets the time corresponding to the inter-round interval in the waiting time timer. That is, by this process, after the time corresponding to the inter-round interval has elapsed, the waiting time management process before the jackpot opening reopening described later is set to be executed.

[0394] On the other hand, in S17, when the main CPU 71 determines that the above conditions are satisfied, the main CPU 71 sets a value indicating the jackpot end interval process ("07") in the control status flag, and sets the time corresponding to the jackpot end interval (jackpot end interval time) in the waiting time timer. That is, by this process, after the time corresponding to the jackpot end interval set in S17 has elapsed, the jackpot end interval process described later is set to be executed.

[0395] Next, in S17, when the main CPU 71 determines that the value of the jackpot opening count counter is not greater than or equal to the maximum value of the jackpot opening count, the main CPU 71 performs the waiting time management process before the jackpot opening reopening (S18). In this process, when the control status flag is the value indicating the waiting time management process before the jackpot opening reopening ("06") and the time corresponding to the inter-round interval has elapsed, the main CPU 71 updates the memory to increase the value of the jackpot opening count counter by "1". Also, the main CPU 71 sets a value indicating the jackpot opening in-process process ("04") in the control status flag. Then, the main CPU 71 sets the opening upper limit time (for example, 30 sec) in the jackpot opening time timer. That is, by this process, after the process of S18, the jackpot opening in-process process (S16) described above is set to be executed again.

[0396] Furthermore, in S18, immediately before the end of the waiting time management process before the jackpot opening reopening, the main CPU 71 transmits a jackpot opening in-process display command to the sub-control circuit 200.

[0397] Also, in S17, when the main CPU 71 determines that the value of the big winning opening count counter is equal to or greater than the maximum value of the big winning opening count, it performs a big win end interval process (S19). In this process, when the control state flag is a value indicating the big win end interval process ("07") and the time corresponding to the big win end interval has elapsed, the main CPU 71 sets a value indicating the special symbol game end process ("08") in the control state flag. That is, by this process, it is set so that the special symbol game end process described later is executed after the process of S19. Note that the details of the big win end interval process will be described later with reference to FIG. 32.

[0398] Then, when the big win symbol is a probability-variable symbol, the main CPU 71 performs control to shift the game state to the probability-variable game state, and when the big win symbol is a non-probability-variable symbol, the main CPU 71 performs control to shift the game state to the normal game state. When the big win symbol is a symbol corresponding to a "small win", the main CPU 71 controls so that the game state after the "small win" game ends does not shift to a game state more advantageous than the game state controlled when the "small win" was won.

[0399] Next, when the big win game state or the small win game state ends, or when a "loss" is won, the main CPU 71 performs a special symbol game end process (S20).

[0400] In this process, when the control state flag is a value indicating the special symbol game end process ("08"), the main CPU 71 updates the memory so as to decrease the data (start memory information) indicating the number of held items by "1". Also, the main CPU 71 updates the special symbol storage area for the next variable display of the special symbol. Further, the main CPU 71 sets a value indicating the special symbol memory check process ("00") in the control state flag. That is, by this process, it is set so that the special symbol memory check process (S12) described above is executed after the process of S20.

[0401] After the process of S20, the main CPU 71 ends the special symbol control process and transfers the process to S4 of the main control main process (see FIG. 28).

[0402] As described above, in the pachinko gaming machine 1 of the present embodiment, the special symbol game is advanced by sequentially setting various values in the control state flag. Specifically, when the game state is neither the jackpot game state nor the small win game state and the result of the win determination is "loss", the main CPU 71 sets the control state flag in the order of "00", "01", "02", "08". Thereby, the main CPU 71 executes the above-described special symbol memory check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and special symbol game end process (S20) in this order at a predetermined timing.

[0403] Further, when the game state is neither the jackpot game state nor the small win game state and the result of the win determination is "jackpot" or "small win", the main CPU 71 sets the control state flag in the order of "00", "01", "02", "03". Thereby, the main CPU 71 executes the above-described special symbol memory check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and jackpot start interval management process (S15) in this order at a predetermined timing, and executes the transition control to the jackpot game state or the small win game state.

[0404] Furthermore, when the transition control to the jackpot game state or the small win game state is executed, the main CPU 71 sets the control state flag in the order of "04", "05", "06". Thereby, the main CPU 71 executes the above-described big winning opening in-process (S16), big winning opening remaining balls monitoring process (S17), and big winning opening reopening waiting time management process (S18) in this order at a predetermined timing, and executes the jackpot game or the small win game.

[0405] During a big win game, if the end condition of the big win game state is satisfied, the main CPU 71 sets the control state flag in the order of "04", "05", "07", and "08". As a result, the main CPU 71 executes the above-described big winning opening release process (S16), the remaining balls monitoring process in the big winning opening (S17), the big win end interval process (S19), and the special symbol game end process (S20) in this order at a predetermined timing, and ends the big win game state.

[0406] As described above, in the special symbol control process, the processing flow is branched according to the status. Also, the normal symbol control process of S4 in the main control main process shown in FIG. 28 also branches the processing flow according to the status in the same manner as the special symbol control process, as will be described later.

[0407] The processing program of the present embodiment is programmed with a call instruction when the processing is branched according to the status so that a pure return process from a small module to a parent module is possible. As a result, compared with the case of arranging a jump table to execute the above processing, the program capacity can be reduced in the present embodiment.

[0408] [Special Symbol Memory Check Process] Next, with reference to FIG. 30, the special symbol memory check process performed in S12 during the special symbol control process (see FIG. 29) will be described. FIG. 30 is a flowchart showing the procedure of the special symbol memory check process in the present embodiment.

[0409] First, the main CPU 71 loads the control state flag (S31). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

[0410] Next, the main CPU 71 determines whether or not the control state flag indicates a special symbol memory check process (value: "00") (S32). In S32, if the main CPU 71 determines that the control state flag is not "00" (when S32 is a NO determination), the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

[0411] On the other hand, in S32, if the main CPU 71 determines that the control state flag is "00" (when S32 is a YES determination), the main CPU 71 determines whether or not the number of holds (second start memory count) of the second start port winning (variable display of the second special symbol) is "0" (S33).

[0412] In S33, if the main CPU 71 determines that the number of holds of the second start port winning is not "0" (when S33 is a NO determination), the main CPU 71 subtracts "1" from the value of the second start memory count corresponding to the number of holds of the second start port winning (S34).

[0413] In the present embodiment, the main CPU 71 determines whether or not data is stored in the second special symbol start memory areas (0) to (4) provided in the main RAM 73, and determines whether or not there is start memory for the special symbol game corresponding to the variable display of the second special symbol during variation or on hold. In the second special symbol start memory area (0), data (information) of the special symbol game corresponding to the variable display of the second special symbol during variation is stored as start memory. Then, in the second special symbol start memory areas (1) to (4), data (information) of the special symbol game corresponding to the variable display (held balls) of the second special symbol on hold for four times is stored as start memory. Note that the data included in the start memory stored in each second special symbol start memory area is, for example, data such as a jackpot determination random number value and a jackpot symbol random number value obtained at the time of winning at the second start port 45.

[0414] After the process of S34, the main CPU 71 performs a special symbol memory transfer process based on the second start port winning (S35). In this process, the main CPU 71 transfers (stores) the data in the second special symbol start memory areas (1) to (4) to the second special symbol start memory areas (0) to (3), respectively. Then, after the process of S35, the main CPU 71 performs the process of S40 described later.

[0415] Here, returning to the process of S33 again, in S33, when the main CPU 71 determines that the number of holds of the second start port winning is "0" (when S33 is a YES determination), the main CPU 71 determines whether the number of holds (the first start memory number) of the first start port winning (variable display of the first special symbol) is "0" (S36).

[0416] In S36, when the main CPU 71 determines that the number of holds of the first start port winning is "0" (when S36 is a YES determination), the main CPU 71 performs a demo display process (S37). Then, after the process of S37, the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

[0417] In the demo display process of S37, the main CPU 71 sets a demo display permission value in the main RAM 73. That is, when the state where the number of holds of the first start port winning and the second start port winning becomes "0" (the start memory of the special symbol game becomes "0") is maintained for a predetermined time (for example, 30 sec), the main CPU 71 sets a predetermined value as the demo display permission value. Also, when the demo display permission value is a predetermined value in the demo display process of S37, the main CPU 71 sets demo display command data in the main RAM 73. Then, the demo display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 in the sub-control circuit 200. When receiving the demo display command data, the sub-control circuit 200 displays a demo screen in the display area 13a of the display device 13.

[0418] On the other hand, in S36, when the main CPU 71 determines that the number of reserved first start port wins is not "0" (when S36 is a NO determination), the main CPU 71 subtracts 1 from the value of the first start memory number corresponding to the number of reserved first start port wins (S38).

[0419] In this embodiment, the main CPU 71 determines whether data is stored in the first special symbol start memory areas (0) to (4) provided in the main RAM 73, and determines whether there is start memory for the special symbol game corresponding to the variable display of the first special symbol during variation or reservation. In the first special symbol start memory area (0), data (information) of the special symbol game corresponding to the variable display of the first special symbol during variation is stored as start memory. Then, in the first special symbol start memory areas (1) to (4), data (information) of the special symbol game corresponding to the variable display (reserved balls) of the first special symbol for four reserved times is stored as start memory. Note that the data included in the start memory stored in each first special symbol start memory area is, for example, data such as the jackpot determination random number value and the jackpot symbol random number value obtained at the time of winning at the first start port 44.

[0420] After the process of S38, the main CPU 71 performs a special symbol memory transfer process based on the first start port win (S39). In this process, the main CPU 71 transfers (stores) the data in the first special symbol start memory areas (1) to (4) to the first special symbol start memory areas (0) to (3), respectively. Then, after the process of S39, the main CPU 71 performs the process of S40 described later.

[0421] Next, after the process of S35 or S39, the main CPU 71 determines whether the value of the time-saving state variation count counter is "0" (S40).

[0422] In S40, when the main CPU 71 determines that the value of the short-time state change count counter is "0" (when S40 is a YES determination), the main CPU 71 performs the process of S44 described later. On the other hand, in S40, when the main CPU 71 determines that the value of the short-time state change count counter is not "0" (when S40 is a NO determination), the main CPU 71 subtracts "1" from the value of the short-time state change count counter (S41).

[0423] After the process of S41, the main CPU 71 determines whether the value of the short-time state change count counter is "0" (S42).

[0424] In S42, when the main CPU 71 determines that the value of the short-time state change count counter is not "0" (when S42 is a NO determination), the main CPU 71 performs the process of S44 described later. On the other hand, in S42, when the main CPU 71 determines that the value of the short-time state change count counter is "0" (when S42 is a YES determination), the main CPU 71 sets "0" in the short-time flag (S43).

[0425] After the process of S43, when S40 is a YES determination or when S42 is a NO determination, the main CPU 71 sets a value ("01") indicating the special symbol variation time management process in the control state flag (S44). Also, in this process, the main CPU 71 transmits a hold subtraction command and a special symbol effect start command to the sub-control circuit 200.

[0426] Next, the main CPU 71 performs a big win determination process (S45). In this process, the main CPU 71 determines (decides) which of "big win", "small win", and "loss" it has won by lottery based on the big win determination random number value obtained at the time of starting port winning.

[0427] Next, the main CPU 71 clears the information (data) in the storage area used for the previous variation display (S46). Next, the main CPU 71 sets the variation time corresponding to the determined variation pattern of the special symbol in the waiting time timer (S47). Then, after the process of S47, the main CPU 71 ends the special symbol storage check process and returns the process to the special symbol control process (see FIG. 29).

[0428] [Special Symbol Display Time Management Process] Next, with reference to FIG. 31, the special symbol display time management process performed in S14 during the special symbol control process (see FIG. 29) will be described. Note that FIG. 31 is a flowchart showing the procedure of the special symbol display time management process in the present embodiment.

[0429] First, the main CPU 71 determines whether the control state flag is a value indicating the special symbol display time management process ("02") (S51). In S51, when the main CPU 71 determines that the control state flag is not a value indicating the special symbol display time management process ("02") (when S51 is a NO determination), the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[0430] On the other hand, in S51, when the main CPU 71 determines that the control state flag is a value indicating the special symbol display time management process ("02") (when S51 is a YES determination), the main CPU 71 determines whether the value of the waiting time timer (waiting time) is "0" (S52). In this process, the main CPU 71 determines whether the waiting time (variation start waiting time) after the variation is set in the waiting time timer has elapsed.

[0431] In S52, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when S52 is a NO determination), the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29). On the other hand, in S52, when the main CPU 71 determines that the value of the waiting time timer is "0" (when S52 is a YES determination), the main CPU 71 determines whether the special symbol game is a "big win" (S53). Also, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub-control circuit 200.

[0432] In S53, when the main CPU 71 determines that the special symbol game is not a "big win" (when S53 is a NO determination), the main CPU 71 sets a value ("08") indicating the special symbol game end process in the control state flag (S54). After the process of S54, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[0433] On the other hand, in S53, when the main CPU 71 determines that the special symbol game is a "big win" (when S53 is a YES determination), the main CPU 71 sets the big win flag to the on state (S55). Note that the big win flag is a flag indicating whether to perform a big win game.

[0434] Next, the main CPU 71 clears the value of the time shortening state change number counter, the value of the time shortening flag, and the value of the probability variation flag (S56). Next, the main CPU 71 sets a value ("03") indicating the big win start interval management process in the control state flag (S57).

[0435] Next, the main CPU 71 sets the jackpot start interval time (e.g., 5000 msec) corresponding to the special symbol (the first special symbol or the second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets the jackpot start command (special symbol start display command) corresponding to the special symbol in the main RAM 73 (S59). Also, in this process, the main CPU 71 simultaneously transmits the special symbol start display command to the sub-control circuit 200.

[0436] Next, the main CPU 71 sets the round number display LED pattern flag to the ON state (S60). Note that the round number display LED pattern flag is a flag indicating whether to display the remaining round number in a predetermined pattern. After the process of S60, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[0437] [Jackpot End Interval Process] Next, referring to FIG. 32, the jackpot end interval process performed in S19 during the special symbol control process (see FIG. 29) will be described. Note that FIG. 32 is a flowchart showing the procedure of the jackpot end interval process in the present embodiment.

[0438] First, the main CPU 71 determines whether the control state flag is a value indicating the jackpot end interval process ("07") (S71).

[0439] In S71, when the main CPU 71 determines that the control status flag is not a value indicating the jackpot end interval process ("07") (when S71 makes a NO determination), the main CPU 71 ends the jackpot end interval process and returns the process to the special symbol control process (see FIG. 29). On the other hand, in S71, when the main CPU 71 determines that the control status flag is a value indicating the jackpot end interval process ("07") (when S71 makes a YES determination), the main CPU 71 determines whether the value of the waiting time timer is "0" (S72). In this process, the main CPU 71 determines whether the jackpot end interval time set in the waiting time timer has elapsed.

[0440] In S72, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when S72 makes a NO determination), the main CPU 71 ends the jackpot end interval process and returns the process to the special symbol control process (see FIG. 29). On the other hand, in S72, when the main CPU 71 determines that the value of the waiting time timer is "0" (when S72 makes a YES determination), the main CPU 71 clears the big winning opening return count display LED pattern flag (S73).

[0441] Next, the main CPU 71 clears the round number allocation flag (sets it to "0") (S74).

[0442] Next, the main CPU 71 sets a value indicating the special symbol game end process ("08") in the control status flag (S75). Also, in this process, the main CPU 71 simultaneously transmits a special symbol win end display command to the sub-control circuit 200. Next, the main CPU 71 clears the jackpot flag (S76).

[0443] Next, the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23) and sets the value of the probability variation flag based on the game state at the time of jackpot winning and the type of the selected symbol command at the time of jackpot. Next, the main CPU 71 refers to the jackpot type determination table With reference to (see FIGS. 20 to 23), the value of the time shortening flag is set based on the game state at the time of winning the big hit and the type of the big hit selection symbol command (S78).

[0444] Next, the main CPU 71 determines whether the value of the time shortening flag is "1" (whether the time shortening flag is in the on state) (S79). In S79, when the main CPU 71 determines that the value of the time shortening flag is not "1" (when S79 is a NO determination), the main CPU 71 ends the big hit end interval process and returns the process to the special symbol control process (see FIG. 29).

[0445] On the other hand, in S79, when the main CPU 71 determines that the value of the time shortening flag is "1" (when S79 is a YES determination), the main CPU 71 refers to the big hit type determination table (see FIGS. 20 to 23), and based on the game state at the time of winning the big hit and the type of the big hit selection symbol command, sets the value of the corresponding time shortening count to the time shortening state change count counter (S80). Then, after the process of S80, the main CPU 71 ends the big hit end interval process and returns the process to the special symbol control process (see FIG. 29).

[0446] [System timer interrupt process] In the pachinko gaming machine 1 of the present embodiment, the main CPU 71 interrupts the main process at a predetermined cycle even during the execution of the main process, and executes the system timer interrupt process. Specifically, the main CPU 71 executes the system timer interrupt process in response to the clock pulses generated from the clock generation circuit 74 at a predetermined cycle (for example, 2 msec). Here, with reference to FIG. 33, the system timer interrupt process executed by the main CPU 71 will be described. Note that FIG. 33 is a flowchart showing the procedure of the system timer interrupt process in the present embodiment.

[0447] First, the main CPU 71 saves the data (information) of each register (S121). Next, the main CPU 71 performs random number update processing (S122). In this processing, the main CPU 71 updates various random number values extracted from a jackpot determination counter, a symbol determination counter, a win determination counter, a fall determination counter, a variation pattern determination counter, an effect pattern determination counter, and the like. Note that if the update timing of the jackpot determination counter and the symbol determination counter is indefinite, it lacks fairness. Therefore, the jackpot determination counter and the symbol determination counter are updated at fixed timing in a 2 msec cycle to ensure fairness.

[0448] Next, the main CPU 71 performs switch input detection processing (S123). In this processing, the main CPU 71 detects winning or passing through various start ports, various winning ports, and the ball passage detector 43. Note that the details of the switch input detection processing will be described later with reference to FIG. 34.

[0449] Next, the main CPU 71 performs timer update processing (S124). Specifically, the main CPU 71 performs update processing of various timers such as a waiting time timer for synchronizing the main control circuit 70 and the sub-control circuit 200, and a big winning port opening time timer for measuring the opening time of the big winning port.

[0450] Next, the main CPU 71 performs command output processing (S125). In this processing, the main CPU 71 outputs various commands such as a winning command and a variation command to the host control circuit 210 of the sub-control circuit 200.

[0451] Next, the main CPU 71 performs game information output processing (S126). In this processing, the main CPU 71 outputs various game-related information processed by the main control circuit 70, the sub-control circuit 200, the payout / firing control circuit 123, etc. to the hall computer of the game parlor.

[0452] Next, the main CPU 71 restores the data of each register saved in S121. (S127). After the process of S127, the main CPU 71 ends the system timer interrupt process.

[0453] [Switch Input Detection Process] Next, with reference to FIG. 34, the switch input detection process performed in S123 during the system timer interrupt process (see FIG. 33) will be described. Note that FIG. 34 is a flowchart showing the procedure of the switch input detection process in the present embodiment.

[0454] First, the main CPU 71 performs a start port winning detection process (S131). In this process, the main CPU 71 determines whether a game ball has entered (passed through) the first start port 44 or the second start port 45. That is, the main CPU 71 detects whether a winning of the game ball is detected by the first start port winning ball sensor 44a or the second start port winning ball sensor 45a. The details of the start port winning detection process will be described later with reference to FIG. 35.

[0455] Next, the main CPU 71 performs a general winning port passing detection process (S132). In this process, the main CPU 71 determines whether a game ball has entered the general winning port 51 or 52. That is, the main CPU 71 detects whether a winning of the game ball is detected by the general winning ball sensor 51a or 52a. When a winning of the game ball into the general winning port 51 or 52 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

[0456] Next, the main CPU 71 performs a big winning port passing detection process (S133). In this process, the main CPU 71 determines whether a game ball has entered the first big winning port 53 or the second big winning port 54. That is, the main CPU 71 detects whether a winning of the game ball is detected by the first big winning port solenoid 53b or the second big winning port solenoid 54b. When a winning of the game ball into the first big winning port 53 or the second big winning port 54 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

[0457] Next, the main CPU 71 performs gate passage detection processing (S134). In this processing, the main CPU 71 determines whether or not a game ball has passed through the ball passage detector 43. That is, the main CPU 71 detects whether or not the passage of the game ball is detected by the passing ball sensor 43a. Next, when it is detected that the game ball has passed through the ball passage detector 43, the main CPU 71 performs various predetermined processes corresponding to the passage. Then, after the processing of S134, the main CPU 71 ends the switch input detection processing and transfers the processing to S124 of the system timer interrupt processing (see FIG. 33).

[0458] [Start port winning detection processing] Next, referring to FIG. 35, the start port winning detection processing performed in S131 during the switch input detection processing (see FIG. 34) will be described. Note that FIG. 34 is a flowchart showing the procedure of the start port winning detection processing in the present embodiment.

[0459] First, the main CPU 71 determines whether or not a winning of a game ball into the first start port 44 is detected based on the output signal of the first start port winning ball sensor 44a (S141).

[0460] In S141, when the main CPU 71 determines that a winning of a game ball into the first start port 44 has not been detected (when S141 is NO determination), the main CPU 71 performs the processing of S149 described later. On the other hand, in S141, when the main CPU 71 determines that a winning of a game ball into the first start port 44 has been detected (when S141 is YES determination), the main CPU 71 sets the payout information corresponding to the first start port winning in the main RAM 73 (S142). In the present embodiment, when a game ball wins in the first start port 44, a predetermined number of game balls are paid out. Therefore, in the processing of S142, the payout information of a predetermined number of game balls is set.

[0461] After the processing of S142, the main CPU 71 determines whether or not the reserved number (the number of reserved balls) of the first start port winning (variable display of the first special symbol) is less than "4" (S143).

[0462] In S143, when the main CPU 71 determines that the number of reserved first start port wins is not less than "4" (when S143 is NO), the main CPU 71 performs the process of S149 described later. On the other hand, in S143, when the main CPU 71 determines that the number of reserved first start port wins is less than "4" (when S143 is YES), the main CPU 71 performs a process of adding "1" to the number of reserved first start port wins (S144).

[0463] After the process of S144, the main CPU 71 acquires various random number values used for lottery and stores the acquired various random number values in a predetermined area of the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random number values such as a jackpot determination random number value, a symbol random number value, and a fall determination random number value.

[0464] Next, the main CPU 71 performs a first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16) and the symbol determination table (first start port) (see FIG. 18), and based on the jackpot determination random number value and the symbol random number value acquired in S145, determines whether it is a "jackpot", and in the case of a "jackpot", selects (determines) the jackpot symbol (production identification symbol) to be displayed on the display screen of the display device 13.

[0465] Next, the main CPU 71 performs a process of determining the presence or absence of a fall (S147). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S145 and determines the presence or absence of the occurrence of a fall. Thereby, the main CPU 71 acquires fall lottery information ("0": no fall, or "1": fall).

[0466] Next, the main CPU 71 sets the reserved addition command data at the time of the first start port win in the main RAM 73 (S148).

[0467] In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16), the symbol determination table (first start port) (see FIG. 18), the jackpot type determination table (see FIGS. 20 to 23), and the winning performance information determination table (see FIG. 24), and determines the information (transmission content) to be included in the hold addition command based on the game state ("normal", "probability change", "time shortening"), winning type ("jackpot", "minor win", "loss"), start memory number (the number of reserved first special symbols), symbol designation command, jackpot selection symbol command, winning performance information, jackpot determination result information, fall lottery information, etc.

[0468] At this time, the game state is obtained by referring to the values of the probability change flag and the time shortening flag, the winning type is obtained by referring to the jackpot random number determination table (first start port) (see FIG. 16), the symbol designation command and the jackpot selection symbol command are obtained by referring to the symbol determination table (first start port) (see FIG. 18), and the winning performance information is obtained by referring to the winning performance information determination table (see FIG. 24). Also, the jackpot determination result information is obtained in the process of S146, and the fall lottery information is obtained in the process of S147.

[0469] Also, in this embodiment, in the process of S148, the hold addition command at the time of winning at the first start port is transmitted from the main CPU 71 to the sub-control circuit 200 (host control circuit 210). Then, based on this hold addition command at the time of winning at the first start port, the sub-control circuit 200 selects the performance patterns of the hold performance and the pre-reading performance.

[0470] After the process of S148, or when S141 or S143 is NO determination, the main CPU 71 determines whether or not the winning of the game ball into the second start port 45 is detected based on the output signal of the second start port winning ball sensor 45a (S149).

[0471] In S149, when the main CPU 71 determines that the winning of a game ball at the second start port 45 has not been detected (when S149 is a NO determination), the main CPU 71 ends the start port winning detection process and transfers the process to S132 of the switch input detection process (see FIG. 34). On the other hand, in S149, when the main CPU 71 determines that the winning of a game ball at the second start port 45 has been detected (when S149 is a YES determination), the main CPU 71 sets the payout information corresponding to the winning at the second start port in the main RAM 73 (S150). In this embodiment, when a game ball wins at the second start port 45, a predetermined number of game balls are paid out. Therefore, in the process of S150, the payout information of a predetermined number of game balls is set.

[0472] After the process of S150, the main CPU 71 determines whether the number of holds (the number of held balls) for the winning at the second start port (variable display of the second special symbol) is less than "4" (S151).

[0473] In S151, when the main CPU 71 determines that the number of holds for the winning at the second start port is not less than "4" (when S151 is a NO determination), the main CPU 71 ends the start port winning detection process and transfers the process to S132 of the switch input detection process (see FIG. 34). On the other hand, in S151, when the main CPU 71 determines that the number of holds for the winning at the second start port is less than "4" (when S151 is a YES determination), the main CPU 71 performs a process of adding "1" to the number of holds for the winning at the second start port (S152). After the process of S152, the main CPU 71 acquires various random number values used for lottery and stores the acquired various random number values in a predetermined area of the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random number values such as a jackpot determination random number value, a symbol random number value, and a fall determination random number value.

[0474] Next, the main CPU 71 performs second special stop symbol determination processing (S154). In this processing, the main CPU 71 refers to the jackpot random number determination table (second start port) (see FIG. 17) and the symbol determination table (second start port) (see FIG. 19), and based on the jackpot determination random number value and the symbol random number value acquired in S153, determines whether it is a "jackpot", and in the case of a jackpot, selects (determines) the jackpot symbol (production identification symbol) to be displayed on the display screen of the display device 13.

[0475] Next, the main CPU 71 performs determination processing for the presence or absence of a fall (S155). In this processing, the main CPU 71 conducts a fall lottery based on the fall determination random number value acquired in S153, and determines the presence or absence of the occurrence of a fall. Thereby, the main CPU 71 acquires fall lottery information ("0": no fall, or "1": fall).

[0476] Next, the main CPU 71 sets the hold addition command data at the time of winning the second start port in the main RAM 73 (S156).

[0477] In this processing, the main CPU 71 refers to the jackpot random number determination table (second start port) (see FIG. 17), the symbol determination table (second start port) (see FIG. 19), the jackpot type determination table (see FIGS. 20 to 23), and the winning production information determination table (see FIG. 24), and based on information such as the game state ("normal", "probability variation", "time shortening"), winning type ("jackpot", "loss"), start memory number (number of holds of the second special symbol), symbol designation command, jackpot selection symbol command, winning production information, jackpot determination result information, fall lottery information, etc., determines the information (transmission content) to be included in the hold addition command.

[0478] Incidentally, at this time, the game state is acquired by referring to the values of the probability variation flag and the time shortening flag, the winning type is acquired by referring to the big win random number determination table (second start port) (see FIG. 17), the symbol designation command and the big win selection symbol command are acquired by referring to the symbol determination table (second start port) (see FIG. 19), and the winning performance information is acquired by referring to the winning performance information determination table (see FIG. 24). Further, the result information of the big win determination is acquired in the process of S154, and the fall lottery information is acquired in the process of S155.

[0479] Also, in the present embodiment, in the process of S156, the hold addition command at the time of winning at the second start port is transmitted from the main CPU 71 to the sub-control circuit 200 (host control circuit 210). The sub-control circuit 200 selects the performance patterns of the hold performance and the pre-reading performance based on this hold addition command at the time of winning at the second start port. Then, after the process of S156, the main CPU 71 ends the start port winning detection process and transfers the process to S132 of the switch input detection process (see FIG. 34).

[0480] <Explanation of the operation of the sub-control circuit> Next, with reference to FIGS. 36 to 74, the contents of various processes executed by various control circuits in the sub-board 202 of the sub-control circuit 200 (both, for example, see FIG. 6) will be described. The sub-control circuit 200 receives various commands transmitted from the main control circuit 70 (for example, see FIG. 6) and performs various processes based on these various commands.

[0481] [Sub-control main process] First, referring to FIG. 36, the sub-control main process executed by the host control circuit 210 (see, for example, FIG. 6; the same applies hereinafter) will be described. FIG. 36 is a flowchart showing an example of the sub-control main process in the present embodiment. The sub-control main process is a process that starts when the power is turned on. In the sub-control main process described with reference to FIG. 36 and the sub-control main process described later (see FIGS. 47, 48, and 49), even if the processes are the same, different reference numerals are given for convenience of explanation. For example, taking various initialization processes as an example, the various initialization processes in FIG. 36 (step S201), the various initialization processes in FIG. 47 (step S381), the various initialization processes in FIG. 48 (step S391), and the various initialization processes in FIG. 48 (step S401) are substantially the same processes but are given different reference numerals.

[0482] First, the host control circuit 210 performs various initialization processes (step S201). In this process, the host control circuit 210 performs various initialization processes such as hardware initialization processing, device initialization processing, various application initialization processing, backup data restoration initialization processing, and RTC acquisition processing. When game data is erased by RAM clear, random number initialization processing is also performed. Further, each time each initialization process ends, the host control circuit 210 clears the counter of the watchdog timer. At startup, the reset time of the watchdog timer is set, and thereafter, when the service pulse is not written (at timeout), a power-off process is performed. Also, the timing for clearing the watchdog timer is at the start of each process in the main loop within the sub-control main process, at the start of each initialization process, and at the transition to the power-off process.

[0483] Next, the host control circuit 210 enters the main loop and performs an RTC acquisition process, that is, a process of acquiring the current time, based on the RTC time (step S202).

[0484] The host control circuit 210 performs random number initialization processing in step S203. This random number initialization processing will be described later.

[0485] The host control circuit 210 acquires the control code of the accessory in step S204 and performs synchronization processing between the accessory and the solenoid (step S205). These processes will be described in the "Accessory Solenoid Control Process" described later.

[0486] The host control circuit 210 performs sub-device input processing in step S206. In this process, the host control circuit 210 performs information acquisition processing of the operation content and the like based on the input state of the operation means (such as whether an operation has been performed on the operation means such as a button by the player). This sub-device input processing (step S206) includes brightness adjustment of LEDs and the like by the operation of the player or the like.

[0487] The host control circuit 210 performs various request control processes in step S207. In this process, the host control circuit 210 performs various request control processes such as sound request control processing, LED request control processing, and accessory request control processing. Note that the sound request, LED request, accessory request, etc. are stored in the buffer and output to each device after the bank flip in step S213 described later. Thereby, synchronization with drawing can be achieved. Note that the bank flip is a process of switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function.

[0488] Next, the host control circuit 210 enters the packet reception loop in the main loop and performs main-sub command control processing (step S208). In this process, the host control circuit 210 performs the command data reading process (command reception process) when receiving command data from the main CPU 71 and the command data storage process (received data storage process) to the sub-work RAM 210a.

[0489] In step S209, the host control circuit 210 performs game data backup processing. In the pachinko gaming machine 1 of the present embodiment, as game data used for RAM clear determination, first data (magic code, program version, and SUM value) and second data (both magic code and SUM value, which are information set in the hall menu) are prepared. In the game data backup processing, after storing the first data in the game data, it is backed up to the SRAM 210b (see FIG. 6). Also, game data is backed up (mirrored) in another area of the SRAM 210b. After power-on, the game data is restored from the data backed up in the SRAM 210b. At this time, using the first data, it is checked whether the backed-up data is damaged. If the backed-up data is damaged, it is checked whether the second data is damaged. At this time, all the data stored in the SRAM 210b, such as hall menu information, is also initialized.

[0490] Next, the host control circuit 210 performs animation request construction processing (step S210). In this processing, the host control circuit 210 performs command analysis, state setting, and lottery processing, and in response to these, generates an animation request necessary for performing production control using the display device 13. Corresponding to the production control (display) in the display device 13 executed based on this animation request, various requests (sound request, lamp request, and accessory request) for operating various production devices are generated.

[0491] The host control circuit 210 executes the processing of steps S202 to S205 until the number of received commands is reached, and when the number of received commands is reached, it exits the packet reception loop. Thereafter, the host control circuit 210 repeats each process in the main loop through animation update processing (step S211), drawing processing (step S212), and bank flip / waiting for bank flip end (step S213).

[0492] The host control circuit 210 executes the processing of an example of the above-described steps S202 to S213 (main loop processing) at a predetermined FPS cycle. The FPS cycle is set to, for example, approximately 16.7 msec (60 FPS), approximately 33.3 msec (30 FPS), etc. The predetermined FPS cycle is adjusted in time at step S213.

[0493] Below, the timer interrupt processing, sub-device input processing, backlight control processing, brightness adjustment of the backlight and various LEDs, RTC acquisition processing, composition reproduction control, sound amplifier control processing, sound request control processing (when there are multiple sound requests for the same channel), sound request control processing (when volume adjustment is performed), LED brightness adjustment processing, accessory solenoid control processing, data load processing, and sub-random number processing will be described in this order. Note that the order of explanation of the above-described respective processes is different from the processing order for convenience of explanation.

[0494] [Timer Interrupt Processing] In the pachinko gaming machine 1 of the present embodiment, the host control circuit 210 performs interrupt processing at a 1 msec cycle. Although the interrupt processing will also be described in each of the processes described later, here, an example of a typical interrupt processing will be briefly described with reference to FIG. 37. FIG. 37 is a flowchart showing an example of the timer interrupt processing executed by the host control circuit (sub-control circuit). Note that in the timer interrupt processing briefly described with reference to FIG. 37 and the timer interrupt processing described later (see FIGS. 44 and 46), even if it is the same process, different reference numerals are attached for convenience of explanation. For example, taking the accessory motor control as an example, the accessory motor control in FIG. 37 (step S251), the accessory motor control in FIG. 44 (step S352), and the accessory motor control in FIG. 46 (step S371) are substantially the same process but are attached with different reference numerals.

[0495] Referring to FIG. 37, in the timer interrupt process, the host control circuit 210 first performs accessory motor control (step S251). Next, the host control circuit 210 performs input state determination processing based on the input information of the sub-device (step S252). Next, the host control circuit 210 performs control processing of, for example, the backlight of the liquid crystal display device used as the display device 13 based on the luminance value (step S253). Next, the host control circuit 210 performs a sound amplifier check process (step S254).

[0496] [Sub-device input processing] In the present embodiment, the host control circuit 210 creates sub-device input discrimination information in the main process every 33.3 msec based on the input state of the sub-device detected by the timer interrupt every 1 msec, and controls the sub-device based on the created sub-device input discrimination information.

[0497] When the host control circuit 210 detects the input state of the sub-device by the timer interrupt every 1 msec, based on the detection result, as the above-mentioned sub-device input discrimination information created in the main process, the host control circuit 210 creates sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information.

[0498] The sub-device input process shown in FIG. 36 will be described below with reference to FIGS. 38 to 41. The sub-device is controlled by the host control circuit 210 based on input (e.g., operation) information, such as a push button. Note that FIG. 38 is a diagram showing an example for explaining the sub-device input discrimination information to be created, (a) a diagram showing the input state of the sub-device detected by a timer interrupt, (b) a diagram showing the sub-device input information created in the main process, (c) a diagram showing the sub-device input ON edge information created in the main process, (c) a diagram showing the sub-device input ON edge information (with a repeat function) created in the main process, (d) a diagram showing the sub-device input OFF edge information created in the main process. FIG. 39 is a flowchart showing an example of the sub-device input process. FIG. 40 is a flowchart showing an example of the sub-device input ON edge information (with a repeat function) process. FIG. 41 is a flowchart showing an example of the sub-device input ON edge information (with a repeat function) process and is a flowchart continuing from FIG. 40.

[0499] As shown in FIG. 38(b), the sub-device input information created in the main process is created in accordance with the sub-device input state (see FIG. 38(a)) detected by a timer interrupt. That is, when the sub-device input state detected by the timer interrupt is ON, 1 is set. Also, when the sub-device input state detected by the timer interrupt is OFF, 0 is set.

[0500] As shown in FIG. 38(c), when it is detected that the sub-device input state detected by the timer interrupt has changed from OFF to ON, the sub-device input ON edge information is set to 1 only for one frame in the main process.

[0501] The sub-device input ON edge information (with repeat function) is information used for control during, for example, debugging or when an operation button is long-pressed. As shown in FIG. 38(d), when it is detected that the sub-device input state detected by a timer interrupt has changed from OFF to ON, 1 is set for one frame in the main process. And if the ON state of the sub-device input state continues thereafter, for example, 1 is set for one frame after 10 frames have elapsed in the main process as a fixed time until key repeat starts, and thereafter, for example, 1 is set every 4 frames in the main process. In this way, making the first frame 10 frames long is to enable discrimination of whether the sub-device has been long-pressed. If the first frame is short, it can be determined that it is not a long-press.

[0502] The sub-device input OFF edge information is, as shown in FIG. 38(e), when it is detected that the sub-device input state detected by a timer interrupt has changed from ON to OFF, 1 is set for only one frame in the main process.

[0503] In this embodiment, assuming there are multiple sub-devices, the host control circuit 210 manages sub-device input discrimination information in bit units. For example, bit0 is for the main button, bit1 is for the left button, bit2 is for the right button, and so on. It can manage sub-device input discrimination information for up to, for example, 32 devices.

[0504] Next, referring to FIG. 39, the sub-device input process (see, for example, step S206 in FIG. 36) will be described. This sub-device input process is a process of creating, for example, four types of information as sub-device input discrimination information, such as sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information.

[0505] First, based on the input state of the current sub-device, the host control circuit 210 creates input information for the current sub-device (step S301). Specifically, if the sub-device is in the ON state, 1 is set; if the sub-device is in the OFF state, 0 is set.

[0506] Next, the host control circuit 210 updates the input information of the sub-device to match the current sub-device input information, that is, the input information of the sub-device created in step S301. (step S302).

[0507] Next, the host control circuit 210 determines whether the previous sub-device input information was 0 and the current sub-device input information is 1 (step S303). If the previous sub-device input information was 0 and the current sub-device input information is 1 (YES in step S303), the host control circuit 210 sets the sub-device input ON edge information to 1 (step S304) and proceeds to step S306. On the other hand, if the previous sub-device input information was 0 and the current sub-device input information is not 1 (that is, if the previous sub-device input information was 1 or / and the current sub-device input information is 0), the host control circuit 210 sets the sub-device input ON edge information to 0 (step S305) and proceeds to step S306.

[0508] In step S306, the host control circuit 210 determines whether the previous sub-device input information was 1 and the current sub-device input information is 0. If the previous sub-device input information was 1 and the current sub-device input information is 0 (YES in step S306), the host control circuit 210 sets the sub-device input OFF edge information to 1 (step S307) and proceeds to step S309. On the other hand, if the previous sub-device input information was 1 and the current sub-device input information is not 0 (that is, if the previous sub-device input information was 0 or / and the current sub-device input information is 1), the host control circuit 210 sets the sub-device input OFF edge information to 0 (step S308) and proceeds to step S309.

[0509] In step S309, the host control circuit 210 performs sub-device input ON-edge information (with repeat function) processing. Details of this sub-device input ON-edge information (with repeat function) processing will be described later.

[0510] When the sub-device input ON-edge information (with repeat function) processing in step S309 is completed, the host control circuit 210 sets the current sub-device input information to the previous sub-device input information (step S310), and ends the sub-device input processing.

[0511] Next, with reference to FIGS. 40 and 41, the sub-device input ON-edge information (with repeat function) processing will be described.

[0512] As shown in FIG. 40, in the sub-device input ON-edge information (with repeat function) processing, the host control circuit 210 first determines whether the previous sub-device input information is 0 (step S321). If the previous sub-device input information is 0 (YES in step S321), the process proceeds to step S322.

[0513] In step S322, the host control circuit 210 determines whether the current sub-device input information is 1. If the current sub-device input information is 1 (YES in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 1, the process proceeds to step S323. On the other hand, if the current sub-device input information is not 1 (NO in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 0, the sub-device input ON-edge information (with repeat function) processing is ended.

[0514] Next, the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 1 (step S323), sets 10 frames as the elapsed frames (step S324), and ends the sub-device input ON edge information (with repeat function) process.

[0515] In step S321, if the previous sub-device input information is 1 (NO in step S321), the host control circuit 210 moves to step S325 in FIG. 41.

[0516] Referring to FIG. 41, in step S325, the host control circuit 210 determines whether the current sub-device input information is 1. If the current sub-device input information is 1 (YES in step S325), that is, if the previous sub-device input information is 1 and the current sub-device input information is 1, subtract 1 from the elapsed frames (step S326) and move to step S327.

[0517] In step S327, the host control circuit 210 determines whether the elapsed frames are 0. If the elapsed frames are 0 (YES in step S327), set the sub-device input ON edge information (with repeat function) to 1 (step S328), set the elapsed frames to 4 (step S329), and end the sub-device input ON edge information (with repeat function) process.

[0518] In step S325, if the current sub-device input information is not 1 (NO in step S325), that is, if the previous sub-device input information is 1 and the current sub-device input information is 0, the host control circuit 210 sets the elapsed frames to 0 (step S330) and moves to step S331.

[0519] When the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 0 in step S331, the sub-device input ON edge information (with repeat function) process ends.

[0520] In this way, based on the input state of the sub-device detected by the timer interrupt every 1 msec, the host control circuit 210 creates the above four types of sub-device input discrimination information in the main process every 33.3 msec, and controls the sub-device based on these four types of sub-device input discrimination information, making it possible to easily control the rapid-fire effect of the sub-device, the long-press effect, the control during time setting, and other operations.

[0521] [Backlight control process] Next, the backlight control process (for example, the backlight control process for controlling the backlight of a liquid crystal display or the like) will be described with reference to FIGS. 42 and 43. FIG. 42 is a diagram showing an example for conceptually explaining the backlight control process. FIG. 43 is a flowchart showing an example of the backlight control process.

[0522] The backlight control process of this embodiment uses the function of SPI asynchronous data write (SPI + DMA) to continuously and constantly output a signal equivalent to pulse width modulation (hereinafter referred to as "PWM") from the serial output terminal of, for example, a Serial Peripheral Interface (hereinafter referred to as "SPI") so that the duty (brightness) can be changed. Thereby, it becomes possible to perform backlight control without going through a driver for backlight control.

[0523] In this embodiment, for example, the frequency of the SPI clock is 100 kHz, the SPI1 clock is 0.01 msec, the time required for data transmission of 16 bits in SPI (one data of luminance data is 16 bits) is 0.16 msec, the timer interrupt of the host control circuit 210 is 1 msec, and the number of luminance data transmitted from SPI between timer interrupts of the host control circuit 210 is 100 bits. Therefore, the number of luminance data transmitted between timer interrupts of the host control circuit 210 is 6.25 (100 / 16) (see FIG. 42). Therefore, it is considered that the number of timer interrupts executed until 32 luminance data are replenished in the data area of a FIFO (First In First Out) that can set (store) 64 pieces of 16-bit luminance data is 5 to 6 times. Note that this number varies depending on the time of the timer interrupt of the host control circuit 210.

[0524] For example, when the number of luminance data stored in the data area of a FIFO (First In First Out) that can set (store) 64 pieces of 16-bit luminance data is less than 32, the callback function is called. Therefore, the data area of the FIFO is not always filled. Therefore, if the process of setting (storing) luminance data in the data area of the FIFO does not come around due to time required for other processes in the main process executed at a cycle of 33.3 msec, the data area of the FIFO may become empty (the backlight may go completely dark).

[0525] Therefore, in this embodiment, after power-on, first, 64 pieces of luminance data of 16 bits per data are first set to fill the data area of the FIFO. After that, when the number of luminance data set in the data area of the FIFO is less than 32, the callback function is called, and 32 pieces of data are set in the callback function so that the data area of the FIFO does not become empty.

[0526] As shown in FIG. 43, in the backlight control process, the host control circuit 210 first determines whether it is a process at the time of initial setting (step S341). When the host control circuit 210 determines that it is a process at the time of initial setting (i.e., one of the processes in step 201 of FIG. 36) (YES in step S341), it sets 64 pieces of luminance data with a luminance of 0 in the data area of the FIFO (step S342) and moves to step S343. On the other hand, when it determines that it is not a process at the time of initial setting (i.e., the process in step S253 of FIG. 37) (NO in step S341), it skips the process of step S342 and moves to step S343.

[0527] In step S343, the host control circuit 210 determines whether the luminance value has been changed. When the host control circuit 210 determines that the luminance value has been changed (YES in step S343), it changes the luminance data to be set in the data area of the FIFO (step S344) and moves to step S345. On the other hand, when it determines that the luminance value has not been changed (NO in step S343), it skips the process of step S344 and moves to step S345.

[0528] In step S345, the host control circuit 210 determines whether the number of luminance data set in the data area of the FIFO is less than 32. If the number of luminance data set in the data area of the FIFO is less than 32 (YES in step S345), it sets, that is, replenishes, 32 pieces of luminance data in the data area of the FIFO (step S346) and ends the backlight control process. On the other hand, if the number of luminance data set in the data area of the FIFO is more than 32 (NO in step S345), the host control circuit 210 ends the backlight process.

[0529] By processing the luminance data set in the FIFO data area in such a way that it does not become empty, a PWM-equivalent signal can be continuously and constantly output from the serial data output terminal of the SPI, and it becomes possible to perform backlight control without going through a driver for backlight control.

[0530] Note that the processing of steps S343 to S346 of the backlight control process of this embodiment can also be changed as follows. That is, after setting 64 pieces of data with a luminance of 0 (refer to step S342), a process of determining whether the number of luminance data set in the FIFO data area is less than 32 is performed. Thereafter, it is determined whether the luminance value has been changed. If it is determined that the luminance value has been changed, 32 pieces of luminance data corresponding to the setting are set in the FIFO data area. If it is determined that the luminance value has not been changed, 32 pieces of the same luminance data as the previous time are set in the FIFO data area. In this way, the luminance data may be set in the FIFO data area to end the backlight control process.

[0531] Also, in this embodiment, there are 32 pieces of luminance data set in the FIFO data area When it is less than half of the number of data that can be set in the FIFO (32 in this case), 32 luminance data are replenished. However, the timing of replenishing the luminance data and the number of luminance data to be replenished are not limited to this. When the luminance data set in the data area of the FIFO is less than a predetermined number, the luminance data of the predetermined number may be replenished. Also, the luminance data replenished in the data area of the FIFO does not have to be the above-mentioned predetermined number. For example, when the luminance data set in the data area of the FIFO is less than the first number, the luminance data of the second number may be replenished. However, from the viewpoint of preventing the frequency of setting luminance data in the data area of the FIFO from becoming too high and preventing the luminance data set in the data area of the FIFO from becoming empty, the above-mentioned predetermined number or the first number is preferably the number of luminance data about half of the number of data that can be set in the data area of the FIFO. However, as described above, it is not limited to this. The above-mentioned "about half" means that it is sufficient as long as the frequency of setting luminance data in the data area of the FIFO does not become too high and the luminance data set in the data area of the FIFO does not become empty. There are various judgment methods such as less than half or less than half depending on the consumption speed of the luminance data set in the data area of the FIFO. For example, since the data area of the FIFO in this embodiment can set up to 64 pieces of 16-bit luminance data, when the luminance data set in the data area of the FIFO is 1 to 64 pieces, one or more new luminance data may be set. However, from the viewpoint of preventing the backlight from becoming dark (the luminance data set in the data area of the FIFO becoming 0), it is preferable to set one or more new luminance data when the luminance data set in the data area of the FIFO is 2 or more. Also, the number of luminance data that can be set in the data area of the FIFO is not limited to 64, and at least two or more luminance data can be set. Thus, when the luminance data that can be set in the data area of the FIFO is, for example, 2 or more, when the luminance data set in the data area of the FIFO is less than the first number (for example, 2), the luminance data of the second number (for example, 1) may be replenished.

[0532] [Modification Example of Backlight Control Processing] Next, a modification example of the backlight control processing will be described with reference to FIGS. 44 and 45. FIG. 44 is a flowchart showing an example of the timer interrupt processing associated with the modification example of the backlight control processing. FIG. 45 is a flowchart showing the modification example of the backlight control processing.

[0533] In the modification example of the backlight control processing, when there is a possibility that the processing takes time in the 1 msec timer interrupt processing, it is determined whether or not a predetermined time has elapsed after setting data in the data area of the FIFO in the backlight control processing, and when the predetermined time has elapsed, data is set in the data area of the FIFO.

[0534] In the timer interrupt processing of FIG. 44, the host control circuit 210 first performs the backlight control processing (step S351). Hereinafter, for the sake of convenience of explanation, before explaining the processing after step S352, the backlight control processing of step S351 will be explained with reference to FIG. 45.

[0535] As shown in FIG. 45, in the backlight control processing, the host control circuit 210 first determines whether or not it is the processing at the initial setting (step S361). When the host control circuit 210 determines that it is the processing at the initial setting (that is, one of the processes in step 201 of FIG. 36) (YES in step S361), 64 pieces of luminance data with luminance 0 are set in the data area of the FIFO (step S362), and then the process proceeds to step S366. On the other hand, when it is determined that it is not the processing at the initial setting (that is, the processing of step S351) (NO in step S361), the process proceeds to step S363.

[0536] In step S363, the host control circuit 210 determines whether the number of luminance data set in the data area of the FIFO is less than 32. If the number of luminance data set in the data area of the FIFO is less than 32 (YES in step S363), 32 luminance data are set in the data area of the FIFO, that is, replenished (step S364), and the process proceeds to step S365. On the other hand, if the number of luminance data set in the data area of the FIFO is more than 32 (NO in step S363), the process proceeds to step S366. As described above, the above 32 is half of the number of data that can be set in the FIFO.

[0537] In step S365, the host control circuit 210 resets the elapsed time (step S365) and starts measuring the elapsed time (step S366). When starting to measure the elapsed time in step S366, the host control circuit 210 ends the backlight control process.

[0538] Returning to FIG. 44, after ending the backlight control process in step S351, the host control circuit 210 performs accessory motor control (step S352).

[0539] In this modification, after performing a process that may take time, such as accessory motor control, the host control circuit 210 determines whether the elapsed time started to be measured in step S366 has elapsed for a predetermined time or more (step S353). If it has elapsed for a predetermined time or more (YES in step S353), 32 luminance data are set in the data area of the FIFO (step S354). On the other hand, if it has not elapsed for a predetermined time or more (NO in step S353), since there is no need to replenish the luminance data in the data area of the FIFO, the process proceeds to step S357.

[0540] As described above, since the time required for 16-bit data transmission (one piece of luminance data is 16 bits) by SPI is 0.16 msec, it is considered that 5.12 msec is required to transmit 32 pieces of luminance data. Therefore, in this modification example, in step S353, it is determined whether or not a predetermined time of 5.12 msec or more has elapsed.

[0541] After the host control circuit 210 performs the process of step S354, it resets the elapsed time (step S355) and starts measuring the elapsed time again (step S356). Then, when starting to measure the elapsed time in step S356, the host control circuit 210 performs an input state determination process (step S357) and ends the timer interrupt process.

[0542] In this way, when starting to measure the time when luminance data is set in the data area of the FIFO, and if the measured time has elapsed for a predetermined time or more after a process that may take time, by replenishing the luminance data, it is possible to prevent the luminance data in the data area of the FIFO from becoming empty.

[0543] Note that in this modification example, the processes of steps S353 to S357 have been described as an example of being performed after the accessory motor control (step S352), but this is just an example. That is, from the viewpoint of preventing the luminance data set in the data area of the FIFO from becoming empty, the processes of steps S353 to S357 may be performed after a process that may take time for the process, and such a process is not limited to a specific process.

[0544] [Brightness Adjustment of Backlight and Various LEDs] Next, variations in the brightness adjustment of the backlight and various LEDs will be described. The various LEDs correspond to, for example, the board-side LEDs (such as the LEDs arranged on the game board 12) and the frame-side LEDs, etc. In this specification, the lamp group 18 etc. including LEDs (see, for example, FIG. 5) correspond to this. Further, in this specification, as variations in the brightness adjustment of the backlight and various LEDs, three variations of the first embodiment to the third embodiment will be described with reference to FIGS. 46 to 49 respectively. FIG. 46 is a flowchart showing an example of a timer interrupt process indicating the backlight control process. FIG. 47 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining the first embodiment of the process for adjusting the brightness of the backlight and various LEDs. FIG. 48 is the sub-control main process (overall flow) for explaining the second embodiment of the process for adjusting the brightness of the backlight and various LEDs. FIG. 49 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining the third embodiment of the process for adjusting the brightness of the backlight and various LEDs. However, in FIGS. 47 to 49, only the processes necessary for the explanation are shown, and other processes are omitted. In addition, also in the first embodiment to the third embodiment described below, as described above, when the luminance data set in the data area of the FIFO becomes about half, the host control circuit 210 replenishes the luminance data in the data area of the FIFO.

[0545] Note that the timing for replenishing the luminance data in the FIFO data area is not limited to when the luminance data set in the FIFO data area reaches about half. In the FIFO data area in this embodiment, for example, up to 64 pieces of 16-bit luminance data can be set. Therefore, when the number of luminance data set in the FIFO data area is 1 to 64, one or more pieces of new luminance data may be set. However, from the viewpoint of preventing the backlight from becoming dark (the luminance data set in the FIFO data area becoming 0), it is preferable to set one or more pieces of new luminance data when the number of luminance data set in the FIFO data area is 2 or more. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and at least 2 or more pieces of luminance data can be set. Thus, when the number of luminance data that can be set in the FIFO data area is, for example, 2 or more, when the luminance data set in the FIFO data area falls below the first number (for example, 2), the second number (for example, 1) of luminance data may be replenished.

[0546] (First Embodiment) For example, when the luminance of the backlight (such as the backlight of a liquid crystal display) is adjusted by the operation of a player or the like, the luminance of the backlight is changed. At this time, it may affect the control of the panel-side LED and the frame-side LED. In this embodiment, ...

Claims

[Claim 1] A gaming machine capable of switching between a drawing output buffer in which a drawing result is stored and a frame buffer used for displaying the result, comprising: A registration means for registering image information relating to a performance image to be displayed on a predetermined display means in the drawing output destination buffer; a performance image display control means for controlling the predetermined display means to display a performance image based on the image information registered by the registration means after switching from the drawing output buffer to the frame buffer; Equipped with When the image information stored in the frame buffer switched from the drawing output destination buffer is pause image information for temporarily stopping an image, pause image information can be registered in the drawing output destination buffer switched from the frame buffer, The image information can be controlled by display control according to a priority; When the image information is not registered in the drawing output destination buffer by the registration means, a determination regarding a playback mode can be made, When the image information is not registered in the drawing output destination buffer by the registration means, loop playback can be controlled to be performed from the beginning. A gaming machine characterized by:

Images