Symbol demapping circuit, receiving apparatus, and symbol demapping method

Abstract

To realize highly efficient symbol demappping processing.SOLUTION: A symbol demapping circuit 22a includes: a hard determination value derivation unit 220 for deriving a bit sequence which corresponds to an ideal signal point closest to a reception signal on the basis of a reception signal on which multi-value modulation was performed; and an LLR derivation unit 222 for deriving an LLR as likelihood information for each bit of the bit sequence. The LLR derivation unit 222 reduces the number of effective bits of the LLR calculated from reception symbol errors, with the reception signal on which the multi-value modulation was performed as an input.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a symbol demapping circuit of a receiving device used, for example, in a digital coherent optical transmission system.

Background Art

[0002] In recent years, there has been a need for a large-capacity information transmission method, and attempts have been made to increase the transmission capacity by increasing the number of values of modulation signals. In a multi-value modulation method, a large number of bits (information) can be transmitted with one symbol, which is suitable for increasing the capacity. On the other hand, since the number of signal points arranged on the IQ plane increases, the signal point interval becomes small, making it susceptible to noise and difficult to determine which signal point the received signal is. For this reason, the importance of powerful error correction codes has become even more prominent (see Patent Document 1).

[0003] When performing the process of decoding a code on the receiving side, LLR (Log-Likelihood Ratio) is used as soft decision information that is input to the error correction decoding circuit. This LLR is a value derived from the received signal by the symbol demapping process on the receiving side and is a prior probability that probabilistically represents whether the transmitted signal is 0 or 1.

[0004] Fig. 28 shows the configuration of a receiving device of a conventional communication system. The receiving device 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, and an error correction decoding circuit 23.

[0005] The AD conversion circuit 20 converts an analog received signal received from a transmitting device via a communication path into a digital signal. The demodulation circuit 21 performs a demodulation process corresponding to the modulation performed on the transmitting device side on the signal output from the AD conversion circuit 20 and outputs the demodulated received signal to the symbol demapping circuit 22. Here, as the modulation performed on the transmitting device side, for example, there is OFDM (Orthogonal Frequency Division Multiplexing) modulation.

[0006] The symbol demapping circuit 22 outputs a bit string corresponding to the ideal signal point closest to the received signal (received symbol) by hard decision from the received signal output from the demodulation circuit 21, and also outputs the LLR which is the likelihood information for each bit of the bit string. The error correction decoding circuit 23 performs error correction decoding processing on the bit string output from the symbol demapping circuit 22 based on the LLR.

[0007] In the conventional technology, symbols were demapped in a mid-tread type. The input / output characteristics of the mid-tread type are shown in FIG. 29. For the case where the multilevel modulation scheme is 16QAM (Quadrature Amplitude Modulation), examples of the results of demapping processing by the conventional symbol demapping circuit 22 are shown in FIGS. 30 and 31. Also, for the case where the multilevel modulation scheme is QPSK (Quadrature Phase Shift Keying), an example of the result of demapping processing by the symbol demapping circuit 22 is shown in FIG. 32.

[0008] Note that in FIGS. 30 to 32, only the coordinates (input amplitude) on the I-axis of the received symbol are shown. For example, the input amplitude of "31 (+31.0)" in FIGS. 30 and 31 means that 31 is the representative value for inputs in the range from +30.5 to +31.5. Similarly, for example, the input amplitude of "15 (+15.0)" in FIG. 32 means that 15 is the representative value for inputs in the range from +14.5 to +15.5.

[0009] As shown in FIG. 33(A), when the multilevel modulation scheme is 16QAM, the symbol demapping circuit 22 outputs the MSB (Most Significant Bit) and the LSB (Least Significant Bit) for the 64 levels of input amplitude represented by 6 bits, and the LLR for each of these bits. The LLR:MSB in FIGS. 30 to 32 indicates the LLR of the MSB, and the LLR:LSB indicates the LLR of the LSB.

[0010] Also, when the multi-value modulation method is QPSK as shown in FIG. 33(B), the symbol demapping circuit 22 outputs an output DT of 1 bit and the LLR of this bit for the 32-level input amplitude represented by 5 bits. In both cases of 16QAM and QPSK, the LLR represents 9 levels of values from 0 to 8 by 4 bits.

[0011] As shown in FIGS. 30 to 32, in the conventional technology, when the input amplitude is the minimum value (-32 (-32.0) in 16QAM and -16 (-16.0) in QPSK), it becomes unused, and there is a problem that the data usage efficiency is poor.

[0012] Also, in the conventional technology, as shown in FIGS. 30 to 32, at the boundary where the output bit of the symbol demapping circuit 22 changes from "1" to "0", the LLR of the output bit "1" immediately before changing to "0" is 1, while the LLR of the output bit "0" immediately after changing is 0, and there is a problem that the generated value of the LLR becomes unbalanced at the boundary where the value of the output bit changes.

[0013] Also, in the conventional technology, since the LLR is represented by 4 bits, there is a problem that the circuit scale of the symbol demapping circuit 22 and the subsequent error correction decoding circuit 23 increases and the power consumption increases. If the lower bits of the LLR are simply deleted to reduce the number of bits of the LLR value and the LLR is represented by 2 bits, as shown in FIG. 34, for the conventional 4-bit representation of the LLR, in the LLR with the lower 2 bits deleted, the ratio of 0 and 1 is not maintained, and it becomes impossible to correctly discriminate the superiority and inferiority between the correction candidates during error correction.

Prior Art Documents

Patent Documents

[0014]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0015] The present invention has been made to solve the above problems, and an object thereof is to provide a symbol demapping circuit, a receiving apparatus, and a symbol demapping method capable of realizing highly efficient symbol demapping processing.

Means for Solving the Problems

[0016] The symbol demapping circuit of the present invention includes a hard decision value derivation unit configured to derive a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multilevel modulation, a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string, and a weighting processing unit configured to perform weighting on the received signal subjected to multilevel modulation such that the number of the likelihood information of 0 or 1 at a boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4. The likelihood information derivation unit is characterized in that it expresses the likelihood information in 2 bits with the received signal subjected to the weighting process as an input. Further, the symbol demapping circuit of the present invention includes a hard decision value derivation unit configured to derive a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multilevel modulation, and a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string , a weighting processing unit configured to perform weighting on a received signal subjected to the multilevel modulation so that the number of pieces of the likelihood information of 0 or 1 at a boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4 and is characterized in that the likelihood information derivation unit the processing of the weighting derives the 2-bit likelihood information based on the input / output characteristics of a mid-rise type with the received signal subjected to the above processing as an input. Further, in the PCS reception process, the symbol demapping circuit of the present invention includes a reception amplitude adjustment unit configured to adjust the input amplitude value of a received signal subjected to multilevel modulation, a hard decision value derivation unit configured to derive a bit string corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted, and a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string. The likelihood information derivation unit is configured such that the likelihood information with respect to the input amplitude is set with the received signal whose input amplitude value has been adjusted as an input 32 / 33.5 times ​S The likelihood information is derived using a D table. Further, the receiving apparatus of the present invention includes the symbol demapping circuit and an error correction decoding circuit configured to perform error correction decoding processing of the bit string based on the likelihood information to decode received data.

[0017] Further, the symbol demapping method of the present invention includes: a first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multilevel modulation; a second step of weighting the received signal subjected to multilevel modulation so that the number of likelihood information of 0 or 1 at a boundary where the value of the output bit in the first step changes becomes 4; and a third step of deriving the likelihood information for each bit of the bit string, with the third step including a step of expressing the likelihood information in 2 bits. Further, the symbol demapping method of the present invention includes: a first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multilevel modulation; a second step of performing weighting on a received signal subjected to the multilevel modulation so that the number of pieces of the likelihood information of 0 or 1 at a boundary where the value of the output bit of the first step changes becomes 4; and a third step of deriving the likelihood information for each bit of the bit string by using, as an input, the received signal subjected to the weighting processing step; the first 3 step is , mi characterized by including a step of deriving the 2-bit likelihood information according to an input-output characteristic of a dead-lifter type. Further, the symbol demapping method of the present invention includes, in PCS reception processing, a first step of adjusting an input amplitude value of a received signal subjected to multilevel modulation; a second step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted; and a third step of deriving likelihood information for each bit of the bit string, with the third step including a step of deriving the likelihood information using a D table with the received signal whose input amplitude value has been adjusted as an input and the likelihood information with respect to the input amplitude being set. 32 / 33.5 times S characterized by including a step of deriving the likelihood information using a D table. ​

Advantages of the Invention

[0018] According to the present invention, likelihood information can be generated even when the input amplitude of the received signal is at its minimum value, and the data usage efficiency can be improved. Further, in the present invention, it is possible to solve the problem that the generated value of the likelihood information becomes unbalanced at the boundary where the value of the output bit of the hard decision value derivation unit changes.

[0019] Moreover, in the present invention, by providing a weighting processing unit, it is possible to maintain the number of low-likelihood assignments at the boundary where the value of the output bit of the hard decision value derivation unit changes. As a result, in the present invention, it is possible to solve the problem that correct discrimination between correction candidates becomes impossible during error correction due to reduction of the bit width of the likelihood information, and the output bits with high error probability can be correctly selected and corrected by the subsequent error correction decoding circuit. Also, in the present invention, since the circuit scale of the symbol demapping circuit and the subsequent error correction decoding circuit can be reduced compared to the prior art, the power consumption can be reduced.

Brief Description of the Drawings

[0020]

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DETAILED DESCRIPTION OF THE INVENTION

[0021] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmission device of a communication system according to a first embodiment of the present invention. The communication system is composed of a transmission device 1 and a reception device. The transmission device 1 encodes and modulates transmission data to generate a transmission signal. The transmission signal is received by the reception device via a wired or wireless communication path. The reception device demodulates and decodes the reception signal to generate reception data.

[0022] The transmission device 1 includes an error - correction encoding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a DA conversion circuit 13. The error - correction encoding circuit 10 generates encoded data by performing, for example, turbo encoding or LDPC (Low Density Parity Check) encoding on the transmission data.

[0023] The symbol mapping circuit 11 performs carrier modulation by assigning the encoded data output from the error - correction encoding circuit 10 to symbol points such as QPSK and 16QAM. The modulation circuit 12 generates a modulation signal by performing, for example, OFDM modulation or the like on the data carrier-modulated by the symbol mapping circuit 11. The DA conversion circuit 13 converts the modulation signal from a digital signal to an analog signal to generate a transmission signal.

[0024] Figure 2 is a block diagram showing the configuration of the receiving apparatus of the communication system according to the present embodiment. The receiving apparatus 2a includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22a, and an error correction decoding circuit 23.

[0025] The symbol demapping circuit 22a of the present embodiment outputs, from the received signal output from the demodulation circuit 21, a bit string corresponding to the ideal signal point closest to the received signal (received symbol) by hard decision, and outputs the LLR which is the likelihood information for each bit of the bit string.

[0026] Figure 3 is a block diagram showing the configuration of the symbol demapping circuit 22a. The symbol demapping circuit 22a includes a hard decision value derivation unit 220, a weighting processing unit 221, and an LLR derivation unit 222 (likelihood information derivation unit).

[0027] Figure 4 is a flowchart for explaining the operation of the symbol demapping circuit 22a. The hard decision value derivation unit 220 derives a bit string (hard decision value) based on the coordinates on the I axis and the coordinates on the Q axis of the received signal subjected to multilevel modulation. The hard decision value derivation unit 220 converts the coordinates (input amplitude) of the received signal (received symbol) into a bit string using, for example, an internal table (step S100 in FIG. 4).

[0028] The weighting processing unit 221 performs weighting on the received signal subjected to multilevel modulation (step S101 in FIG. 4). The LLR derivation unit 222 derives the LLR for each bit of the bit string output from the hard decision value derivation unit 220 based on the coordinates on the I axis and the coordinates on the Q axis of the weighted received signal (step S102 in FIG. 4). In this embodiment, the LLR derivation unit 222 performs demapping processing on symbols in a mid - riser type to generate LLRs. An example of the input - output characteristics of the mid - riser type is shown in FIG. 5.

[0029] Examples of the results of demapping processing by the symbol demapping circuit 22a of this embodiment for the case where the multi - value modulation method is 16QAM are shown in FIGS. 6 and 7. Also, an example of the results of demapping processing by the symbol demapping circuit 22a for the case where the multi - value modulation method is QPSK is shown in FIG. 8.

[0030] In FIGS. 6 to 8, only the coordinates (input amplitude) on the I - axis of the received symbols are shown. Similar to the above, for example, "31(+31.0)" of the input amplitude in FIGS. 6 and 7 means that 31 is used as the representative value for inputs in the range from +30.5 to +31.5. Similarly, for example, "15(+15.0)" of the input amplitude in FIG. 8 means that 15 is used as the representative value for inputs in the range from +14.5 to +15.5.

[0031] As shown in FIG. 9(A), the symbol demapping circuit 22a corresponding to 16QAM outputs the MSB and LSB for 64 - step input amplitudes represented by 6 bits, and the LLRs of these bits respectively. LLR:MSB in FIGS. 6 to 8 indicates the LLR of the MSB, and LLR:LSB indicates the LLR of the LSB.

[0032] Also, as shown in FIG. 9(B), the symbol demapping circuit 22a corresponding to QPSK outputs a 1 - bit output DT and the LLR of this bit for 32 - step input amplitudes represented by 5 bits. In both the cases of 16QAM and QPSK, the LLR represents 4 - step values from 0 to 3 by 2 bits.

[0033] As can be seen from the constellation shown in FIG. 10, in the case of 16QAM, there is one boundary on the I-axis where the value of the output bit of the symbol demapping circuit 22a changes for the MSB, while there are two boundaries for the LSB. In the example of FIG. 10, 80 indicates the boundary where the value of the MSB changes, and 81 and 82 indicate the boundaries where the value of the LSB changes.

[0034] Therefore, in the case of the symbol demapping circuit 22a corresponding to 16QAM, a mid-rise type input-output characteristic as shown in FIG. 11(A) for outputting 4-level LLRs of the MSB for input amplitudes in the range of "0" to "31", a mid-rise type input-output characteristic as shown in FIG. 11(B) for outputting 4-level LLRs of the MSB for input amplitudes in the range of "-32" to "-1", a mid-rise type input-output characteristic as shown in FIG. 11(C) for outputting 4-level LLRs of the LSB for input amplitudes in the range of "16" to "31", a mid-rise type input-output characteristic as shown in FIG. 11(D) for outputting 4-level LLRs of the LSB for input amplitudes in the range of "0" to "15", an input-output characteristic similar to FIG. 11(C) for outputting 4-level LLRs of the LSB for input amplitudes in the range of "-16" to "-1", and an input-output characteristic similar to FIG. 11(D) for outputting 4-level LLRs of the LSB for input amplitudes in the range of "-32" to "-17" need to be prepared.

[0035] In the case of the symbol demapping circuit 22a corresponding to QPSK, a mid-rise type input-output characteristic similar to FIG. 11(A) for outputting 4-level LLRs for input amplitudes in the range of "0" to "15" and a mid-rise type input-output characteristic similar to FIG. 11(B) for outputting 4-level LLRs for input amplitudes in the range of "-16" to "-1" may be prepared.

[0036] As shown in FIGS. 30 to 32, in the conventional technology, when the input amplitude is at the minimum value (-32 (-32.0) in 16QAM and -16 (-16.0) in QPSK), it becomes unused, and there is a problem that the data usage efficiency is poor. In contrast, in this embodiment, due to the input / output characteristics of the mid-riser type, the input amplitude is converted into LLR, so that LLR can be generated even when the input amplitude is at the minimum value, and the data usage efficiency can be improved.

[0037] Also, in this embodiment, due to the input / output characteristics of the mid-riser type, by converting the input amplitude into LLR, as shown in FIGS. 6 to 8, at the boundary where the output bit of the symbol demapping circuit 22a changes from "1" to "0", the LLR of the output bit "1" immediately before changing to "0" can be set to 0, and the LLR of the output bit "0" immediately after changing can also be set to 0. Also, at the boundary where the output bit of the symbol demapping circuit 22a changes from "0" to "1", the LLR of the output bit "0" immediately before changing to "1" can be set to 0, and the LLR of the output bit "1" immediately after changing can also be set to 0. In this way, in this embodiment, the problem that the generated value of LLR becomes unbalanced at the boundary where the value of the output bit changes can be solved.

[0038] Also, in this embodiment, since LLR is represented by 2 bits, the circuit scale of the symbol demapping circuit 22a and the error correction decoding circuit 23 can be reduced compared to the conventional case, and the power consumption can be reduced. However, it is necessary to maintain the ratio of 0 and 1 of LLR with respect to the conventional 4-bit representation of LLR.

[0039] Therefore, in this embodiment, a weighting processing unit 221 is provided in front of the LLR derivation unit 222 to perform weighting on the received signal subjected to multilevel modulation. As a result, it is possible to maintain the number of low likelihood (low bit reliability) assignments at the boundaries where the values of the output bits of the symbol demapping circuit 22a change. A specific example of the mid-tread type input-output characteristics of the conventional LLR derivation unit is shown in FIG. 12, a specific example of the mid-rise type input-output characteristics of the LLR derivation unit 222 of this embodiment is shown in FIG. 13, and a specific example of the input-output characteristics when the weighting processing unit 221 is provided in front of the LLR derivation unit 222 is shown in FIG. 14. In FIGS. 12 to 14, 300 shows the characteristics of the MSB LLR, and 301 shows the characteristics of the LSB LLR.

[0040] In the case of the symbol demapping circuit 22a corresponding to 16QAM, inside the weighting processing unit 221, there are a weighting processing unit for the MSB and a weighting processing unit for the LSB. That is, in the case of the symbol demapping circuit 22a corresponding to 16QAM, it is necessary to prepare the input-output characteristics of the weighting processing unit 221 for the MSB that performs weighting on the input amplitude in the range of "-32" to "31" to generate the output amplitude in the range of "-32" to "31". Also, it is necessary to prepare the input-output characteristics of the weighting processing unit 221 for the LSB that performs weighting on the input amplitude in the range of "0" to "31" to generate the output amplitude in the range of "0" to "31", and the input-output characteristics of the weighting processing unit 221 for the LSB that performs weighting on the input amplitude in the range of "-32" to "-1" to generate the output amplitude in the range of "-32" to "-1".

[0041] The LLR derivation unit 222 may derive the MSB LLR with the output of the weighting processing unit 221 for the MSB as the input, and derive the LSB LLR with the output of the weighting processing unit 221 for the LSB as the input.

[0042] Also, in the case of the symbol demapping circuit 22a corresponding to QPSK, it is only necessary to prepare the input-output characteristics of the weighting processing unit 221 that performs weighting on the input amplitude in the range of "-16" to "15" to generate the output amplitude in the range of "-16" to "15".

[0043] In this embodiment, a low likelihood means that the LLR is 0 or 1. In the prior art, at the boundary where the output bit of the symbol demapping circuit 22 changes from "1" to "0" or from "0" to "1", the number of LLRs of 0 or 1 is 3. On the other hand, in this embodiment, in order to solve the problem that the LLR becomes unbalanced at the boundary where the value of the output bit changes as described above, the number of LLRs of 0 increases by 1, so the number of LLRs of 0 or 1 at the boundary where the value of the output bit changes is 4.

[0044] Thus, in this embodiment, the allocation number of low likelihoods can be maintained at the boundary where the value of the output bit of the symbol demapping circuit 22a changes. In this embodiment, it is possible to solve the problem that correct discrimination between correction candidates becomes impossible during error correction due to the reduction of the bit width of the LLR, and the error correction decoding circuit 23 can correctly select and correct the output bit with a high error probability.

[0045] In this embodiment, an example of generating an LLR in 2-bit representation has been described, but an LLR in 3-bit representation may also be generated. An example of generating an LLR in 3-bit representation by the symbol demapping circuit 22a having the configuration shown in FIG. 3 is shown in FIGS. 15 to 20. FIGS. 15 to 18 show the results of demapping processing by the symbol demapping circuit 22a when the multilevel modulation scheme is 16QAM, and FIGS. 19 and 20 show the results of demapping processing by the symbol demapping circuit 22a when the multilevel modulation scheme is QPSK.

[0046] In FIGS. 15 to 20, only the coordinates (input amplitude) on the I axis of the received symbol are shown. In the examples of FIGS. 15 to 18, the symbol demapping circuit 22a corresponding to 16QAM outputs the MSB and LSB, and the LLRs of these bits, respectively, for the 128-level input amplitude represented by 7 bits.

[0047] Also, in the examples of FIGS. 19 and 20, the symbol demapping circuit 22a corresponding to QPSK outputs an output DT of 1 bit and the LLR of this bit for 64 levels of input amplitude represented by 6 bits. In either case of 16QAM or QPSK, the LLR represents 8 levels of values from 0 to 7 by 3 bits.

[0048] In the case of the symbol demapping circuit 22a corresponding to the examples of FIGS. 15 to 18, a mid-riser type input / output characteristic as shown in FIG. 11(A) for outputting the 8 levels of the MSB LLR for input amplitudes in the range of "0" to "63", a mid-riser type input / output characteristic as shown in FIG. 11(B) for outputting the 8 levels of the MSB LLR for input amplitudes in the range of "-64" to "-1", a mid-riser type input / output characteristic as shown in FIG. 11(C) for outputting the 8 levels of the LSB LLR for input amplitudes in the range of "32" to "64", a mid-riser type input / output characteristic as shown in FIG. 11(D) for outputting the 8 levels of the LSB LLR for input amplitudes in the range of "0" to "31", an input / output characteristic similar to FIG. 11(C) and a mid-riser type input / output characteristic for outputting the 8 levels of the LSB LLR for input amplitudes in the range of "-32" to "-1", and an input / output characteristic similar to FIG. 11(D) and a mid-riser type input / output characteristic for outputting the 8 levels of the LSB LLR for input amplitudes in the range of "-64" to "-33" need to be prepared.

[0049] In the case of the symbol demapping circuit 22a corresponding to the examples of FIGS. 19 and 20, a mid-riser type input / output characteristic similar to FIG. 11(A) for outputting the 8 levels of the LLR for input amplitudes in the range of "0" to "31" and a mid-riser type input / output characteristic similar to FIG. 11(B) for outputting the 8 levels of the LLR for input amplitudes in the range of "-32" to "-1" may be prepared.

[0050] Also, in the case of the symbol demapping circuit 22a corresponding to the examples of FIGS. 15 to 18, it is necessary to prepare the input / output characteristics of the weighting processing unit 221 for the MSB that performs weighting on the input amplitudes in the range of "-64" to "63" to generate output amplitudes in the range of "-64" to "63". Also, it is necessary to prepare the input / output characteristics of the weighting processing unit 221 for the LSB that performs weighting on the input amplitudes in the range of "0" to "63" to generate output amplitudes in the range of "0" to "63", and the input / output characteristics of the weighting processing unit 221 for the LSB that performs weighting on the input amplitudes in the range of "-64" to "-1" to generate output amplitudes in the range of "-64" to "-1".

[0051] In the case of the symbol demapping circuit 22a corresponding to the examples of FIGS. 19 and 20, it is sufficient to prepare the input / output characteristics of the weighting processing unit 221 that performs weighting on the input amplitudes in the range of "-32" to "31" to generate output amplitudes in the range of "-32" to "31".

[0052] Note that in FIGS. 6 to 8 and FIGS. 15 to 20, only the coordinates on the I-axis of the received symbol are shown, but the symbol demapping circuit 22a may perform the same processing on the coordinates (input amplitudes) on the Q-axis of the received symbol as on the coordinates on the I-axis.

[0053] [Second Embodiment] Next, a second embodiment of the present invention will be described. Also in this embodiment, the overall configurations of the transmission device 1 and the reception device 2a are the same as those in the first embodiment, so the description will be made using the reference numerals in FIGS. 1 and 2. In this embodiment, in addition to orthogonal modulation such as 16QAM and QPSK as the multi-value modulation method, a method to which PCS (Probabilistic Constellation Shaping) processing is applied will be described. In this embodiment, an example of PCS-16QAM in which PCS processing is applied to 16QAM will be described.

[0054] FIG. 21 is a block diagram showing the configuration of the symbol demapping circuit 22a of the receiving apparatus 2a of this embodiment. The symbol demapping circuit 22a includes a hard decision value derivation unit 220a, an LLR derivation unit 222a (likelihood information derivation unit), and a received amplitude adjustment unit 223.

[0055] The operation of the hard decision value derivation unit 220a is the same as that of the hard decision value derivation unit 220 of the first embodiment, but converts the PCS-16QAM signal into a bit string according to the characteristics corresponding to PCS-16QAM. The operation of the LLR derivation unit 222a is the same as that of the LLR derivation unit 222 of the first embodiment, but derives the LLR from the PCS-16QAM signal according to the characteristics corresponding to PCS-16QAM.

[0056] FIG. 22 shows the amplitude distribution of a 16QAM signal without PCS processing. TH1 in FIG. 22 indicates the MSB threshold at which the MSB becomes 1 or 0, and TH2 indicates the LSB threshold at which the LSB becomes 1 or 0. The LSB threshold of a 16QAM signal without PCS processing is "+32" of the symbol intermediate value.

[0057] FIG. 23 shows the amplitude distribution of the PCS-16QAM signal. In the case of a 16QAM signal subjected to PCS processing, the LSB threshold TH2 shifts outward. For the case where the multi-value modulation method is PCS-16QAM, FIGS. 24 and 25 show an example of the result of demapping processing by a conventional symbol demapping circuit. The bit string and the LLR are generated based on an SD (Soft Decision) table. "+0", "+1", "+2", and "+3" in FIGS. 24 and 25 indicate the input amplitude values of PCS-16QAM. The example of the SD table in FIGS. 24 and 25 shows the case where the LSB threshold TH2 is set to the input amplitude value "+2".

[0058] FIG. 26 shows the relationship between the LSB threshold shift amount of the SD table and the BER (Bit Error Rate). As described above, in PCS, the BER is improved by shifting the threshold of the SD table. In FIG. 26, 100 indicates the case where the standard deviation σ of the noise component of the PCS-16QAM signal is 0.51, 101 indicates the case where σ is 0.52, and 102 indicates the case where σ is 0.53.

[0059] However, in the case of changing the SD table, only integer shifts of +1 or +2 can be realized. Therefore, in this embodiment, the received amplitude adjustment unit 223 is provided. The received amplitude adjustment unit 223 multiplies the input amplitude value of the PCS-16QAM signal by, for example, 32 / 33.5. As a result, in this embodiment, without changing the SD table used by the hard decision value derivation unit 220a and the LLR derivation unit 222a, an LSB threshold shift equivalent to a +1.5 shift can be realized.

[0060] The effect of this embodiment will be described with reference to FIG. 27. The horizontal axis of FIG. 27 is the SNR (Signal to Noise ratio), and the vertical axis shows the BER after the error correction decoding circuit performs error correction decoding processing based on the LLR for the bit sequence output from the symbol demapping circuit 22a. 200 in FIG. 27 indicates the case without coding. 201 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit and a +1 LSB threshold shift is performed by changing the SD table. 202 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit and a +2 LSB threshold shift is performed by changing the SD table. 203 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit 22a in this embodiment.

[0061] As described above, in this embodiment, by providing the received amplitude adjustment unit 223, an LSB threshold shift equivalent to a +1.5 shift can be realized without changing the SD table, enabling high-performance and low-power error correction.

[0062] Each of the transmission device 1 and the reception device 2a described in the first and second embodiments can be configured by hardware logic such as, for example, an ASIC (application specific integrated circuit) or an FPGA (field-programmable gate array). Further, at least a part of each of the transmission device 1 and the reception device 2a may be realized by a computer. In this case, the CPU of each device executes the processes described in the first and second embodiments according to the programs stored in the memory.

Industrial Applicability

[0063] The present invention can be applied to a technique for decoding a received signal subjected to multilevel modulation.

Explanation of Signs

[0064] 1... transmission device, 2a... reception device, 10... error correction encoding circuit, 11... symbol mapping circuit, 12... modulation circuit, 13... DA conversion circuit, 20... AD conversion circuit, 21... demodulation circuit, 22a... symbol demapping circuit, 23... error correction decoding circuit, 220, 220a... hard decision value derivation unit, 221... weighting processing unit, 222, 222a... LLR derivation unit, 223... received amplitude adjustment unit.

Claims

1. A hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multi-valued modulation; A likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence; A weighting processing unit configured to perform weighting on the received signal subjected to multi-valued modulation so that the number of the likelihood information of 0 or 1 at a boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4; and The likelihood information derivation unit is a symbol demapping circuit, characterized in that it takes the received signal subjected to the weighting process as an input and represents the likelihood information in 2 bits.

2. A hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multi-valued modulation; A likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence; A weighting processing unit configured to perform weighting on the received signal subjected to multi-valued modulation so that the number of the likelihood information of 0 or 1 at a boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4; and The likelihood information derivation unit is a symbol demapping circuit, characterized in that it takes the received signal subjected to the weighting process as an input and derives the 2-bit likelihood information based on the input-output characteristics of a mid-rise type.

3. A received amplitude adjustment unit configured to adjust an input amplitude value of a received signal subjected to multi-valued modulation to 32 / 33.5 times in PCS reception processing; A hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted; A likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence; and The likelihood information derivation unit is a symbol demapping circuit, characterized in that it takes the received signal whose input amplitude value has been adjusted as an input and derives the likelihood information using an SD table in which the likelihood information with respect to the input amplitude is set.

4. A symbol demapping circuit according to any one of Claims 1 to 3; and An error correction decoding circuit configured to perform error correction decoding processing on the bit sequence based on the likelihood information and decode received data. A receiving apparatus comprising the error correction decoding circuit.

5. A first step of deriving a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multi-valued modulation; A second step of weighting the received signal subjected to the multi-valued modulation so that the number of likelihood information of 0 or 1 at a boundary where the value of the output bit of the first step changes becomes 4; A third step of deriving the likelihood information for each bit of the bit sequence, with the received signal subjected to the weighting process as an input, The third step includes a step of expressing the likelihood information in 2 bits, and a symbol demapping method characterized by this.

6. A first step of deriving a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal subjected to multi-valued modulation; A second step of weighting the received signal subjected to the multi-valued modulation so that the number of likelihood information of 0 or 1 at a boundary where the value of the output bit of the first step changes becomes 4; A third step of deriving the likelihood information for each bit of the bit sequence, with the received signal subjected to the weighting process as an input, The third step includes a step of deriving the 2-bit likelihood information based on the input-output characteristics of a mid-rise type, and a symbol demapping method characterized by this.

7. In PCS reception processing, a first step of adjusting an input amplitude value of a received signal subjected to multi-valued modulation to 32 / 33.5 times; A second step of deriving a bit sequence corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted; A third step of deriving likelihood information for each bit of the bit sequence, The third step includes a step of deriving the likelihood information using an SD table in which the likelihood information with respect to the input amplitude is set, with the received signal whose input amplitude value has been adjusted as an input, and a symbol demapping method characterized by this.

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