Gaming machine

Abstract

To provide a game machine capable of properly progressing games.SOLUTION: A game machine is provided, capable of being connected to a specific unit for lending game values. The game machine includes: control means for updating the number of game values, the number of game values being a total number of game values; and display means for displaying the number of game values. The control means repeats main processing and may sometimes perform, in the main processing, one or more update processing for updating the number of game values. The game machine performs timer interruption processing with a predetermined cycle and performs, in the timer interruption processing, display processing that at least includes processing for setting the number of game values to be displayed in the display means.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] Smart pachislot machines that can progress the game without the intervention of physical medals while maintaining the playability of slot machines have been studied (for example, Patent Document 1). In addition, smart pachinko machines that use a sealed circulation system and can progress the game without the player touching the game balls have been studied (for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such smart pachislot machines and smart pachinko machines, there is no need to provide a path for circulating game media such as game balls and medals outside the gaming machine. In smart pachislot machines, the physical game media itself becomes unnecessary. In this way, in smart pachislot machines, the game media itself is not used, and in smart pachinko machines, by using non-magnetic game balls, it becomes possible to prevent the act of gambling on the premise of using a metal game media. In addition, since there is no need to provide a mechanism for inserting and paying out game media inside the gaming machine, the design cost and manufacturing cost can be reduced. Furthermore, by centrally managing the lending of game media to players and the counting of acquired game media, it becomes possible to prevent fraud and suppress the element of chance.

[0005] On the other hand, for a configuration that uses an electronic game medium (game value) or a non-magnetic game medium instead of a physical game medium, a new mechanism is required to appropriately advance the game while managing the electronic game medium.

[0006] In view of such problems, an object of the present invention is to provide a gaming machine capable of appropriately advancing a game.

Means for Solving the Problems

[0007] In order to solve the above problems, the gaming machine of the present invention includes control means for updating the number of game values, display means for displaying the numbers related to the game, a substrate provided with predetermined electronic components, and a substrate case for housing the substrate. The control means repeats a main process, and in the main process, it may execute one or more update processes for updating the number of game values, executes a timer interrupt process at a predetermined cycle, and in the timer interrupt process, executes a display process including at least a process of setting the numbers related to the game to be displayed on the display means. An explosion-proof valve is formed on the top surface portion of the electronic component, the separation distance between the top surface portion of the electronic component and the top surface portion of the substrate case is longer than the distance from the outer peripheral portion to the center of the top surface portion of the electronic component, a through hole is provided in a portion of the top surface portion of the substrate case that faces the top surface portion of the electronic component, and the separation distance is longer than the length of the screw portion of a screw that is used in the gaming machine and can be inserted into the through hole. The diameter of the through hole is shorter than the diameter of the top surface of the electronic component. The explosion-proof valve is visible from the outside of the substrate case.

Effects of the Invention

[0008] According to the present invention, it becomes possible to appropriately advance the game.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] With reference to the accompanying drawings below, preferred embodiments of the present invention will be described in detail. The dimensions, materials, and other specific numerical values shown in such embodiments are merely examples for facilitating the understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown.

[0011] (First Embodiment: Smart Pachislo 100) The smart pachislo 100 can progress the game without the intervention of real medals while maintaining the gaming properties of a slot machine. Note that a slot machine is a conventional general gaming machine, which is different from the smart pachislo 100 in that it progresses the game with the intervention of real medals. In the smart pachislo 100, instead of real medals, electronic medals are used as electronic gaming values for the game.

[0012] (Mechanical Configuration of Smart Pachislo 100) As shown in the external view of FIG. 1, the smart pachislo 100 as a gaming machine is provided with a housing 102, and a front upper door 104 and a front lower door 106 that are rotatably arranged vertically side by side at one end of the front surface of the housing 102. At approximately the center of the lower part of the front upper door 104, a colorless and transparent symbol display window 108 made of a glass plate, a transparent resin plate, or the like is provided. At a position corresponding to the symbol display window 108 inside the housing 102, three reels 110 (left reel 110a, middle reel 110b, right reel 110c) are provided so as to be independently rotatable. On the outer peripheral surfaces of the left reel 110a, the middle reel 110b, and the right reel 110c, a plurality of types of symbols are respectively arranged in each of, for example, 20 equally divided regions. The player can visually recognize a total of nine consecutive symbols of the left reel 110a, the middle reel 110b, and the right reel 110c, which are located in the upper, middle, and lower stages, through the symbol display window 108.

[0013] An operation unit installation base 111 is formed at the upper part of the front lower door 106, and on the operation unit installation base 111, a counting switch 112, a gaming medal number display device 114, a bet switch 116, a start switch 118, a stop switch 120, a settlement switch 121, an effect switch 122, a main segment display unit 130, etc. are provided.

[0014] The counting switch 112 is composed of a push switch and detects an operation of transferring part or all of the electronically stored medals for gaming, which are electronically held in the smart pachislo 100, to a dedicated unit 350 described later. For the operation of the counting switch 112, a short press of less than 500 msec and a long press of 500 msec or more are prepared. In the case of a short press of the counting switch 112, one electronically stored medal is counted for each operation, and in the case of a long press, the electronically stored medals are counted 50 at a time at the timing of counting notifications every 300 msec. The total number of the electronically stored medals that can be used for gaming and are electronically held in such a smart pachislo 100 is referred to as the "number of gaming medals", and the storage unit that holds the electronically stored medals may be referred to as the "medal holding unit".

[0015] The gaming medal count display device 114 displays the total number of digitized medals held in the medal holding unit, that is, the number of gaming medals. However, the digitized medals bet are not included in the number of gaming medals. Therefore, the number obtained by subtracting the number of digitized medals bet from the digitized medals acquired by the player is displayed on the gaming medal count display device 114. The display of the number of gaming medals is represented as follows by a 5- or 6-digit 7-segment display or the like arranged at a position where the player can view it. That is, the numerical range is represented as 0 to 16382 (16368 medals + maximum payout number in one game (15 medals) - minimum input number (1 medal)) considering the maximum difference number in one business day. When the upper digit of the significant value is 0, the value is made blank (turned off). Here, when the value reaches a predetermined warning value, for example, 15000 or more, a holding number warning notification that prompts the player to count is executed, the lending process of digitized medals is restricted, and a test counting signal is output for about 3500 msec. The warning value is not limited to 15000, and various values can be set. However, even if the holding number warning notification is executed, the player can continue the game. Therefore, the number of gaming medals may increase. Then, when the value reaches a predetermined holding upper limit value, for example, 16369 or more, an error notification (medal over error notification) is executed to restrict the progress of the game. Specifically, acceptance of the bet switch 116, start switch 118, and settlement switch 121 is prohibited. Instead of when the value reaches 16369 or more, it is also possible to prohibit the payout of digitized medals until the player executes counting when the value is likely to reach 16369 or more. For example, when the value reaches 16357 or more, which is obtained by subtracting 12 medals (maximum payout number (for example, 15 medals) - specified number (for example, 3 medals)), which is the maximum difference number that can be obtained in one game, from 16369, the game may be stopped. Also, the gaming medal count display device 114 displays the updated number of gaming medals reflecting the update within approximately 300 msec after the number of gaming medals held in the smart pachislot 100 is updated. The holding upper limit value is not limited to 16369, and various values can be set.

[0016] The bet switch 116 inserts (bets) a predetermined number of digitized medals out of the digitized medals held in the medal holding unit. The bet switch 116 includes a max bet switch for inserting (betting) the specified number of digitized medals required for one game, and a 1 - bet switch for additionally inserting one digitized medal within the range of the specified number.

[0017] The start switch 118 is composed of, for example, a lever capable of detecting a tilting operation, and detects the start operation of the game by the player. The stop switches 120 (stop switch 120a, stop switch 120b, stop switch 120c) are provided corresponding to the left reel 110a, the middle reel 110b, and the right reel 110c respectively, and detect the stop operation of the player. The payout switch 121 detects an operation of returning all the digitized medals bet by one operation of the bet switch 116 to the medal holding unit. The effect switch 122 is composed of, for example, a push switch and a cross switch arranged vertically and horizontally, and detects the pressing operation and rotation operation of the player. The main segment display unit 130 is composed of two juxtaposed 7 - segment displays, and, for example, an error code indicating the type of error is displayed.

[0018] A liquid crystal display unit 124 for displaying various images associated with the effect is provided at approximately the center of the upper part of the front upper door 104. Also, effect lamps 126 composed of, for example, high - brightness light - emitting diodes (LEDs) are provided at the upper part and left and right of the front upper door 104. Also, speakers 128 for performing auditory effects such as sound effects and music are provided at the left and right positions of the front lower door 106.

[0019] In the smart pachislot 100, when the game can be started and a prescribed number of electronic medals are bet, the active lines are activated and the operation on the start switch 118 becomes valid. Here, the bet includes both the case of inserting the electronic medals held in the medal holding unit through the operation of the bet switch 116 and the case of automatically inserting the electronic medals based on the appearance of the replay symbol on the active lines. Also, the active lines are the lines for determining the winning of the winning symbols.

[0020] Then, when the start switch 118 is operated by the player, the game starts, various processes such as the winning type lottery are executed, and the left reel 110a, the middle reel 110b, and the right reel 110c are rotationally controlled. Thereafter, in response to the operations of the stop switches 120a, 120b, and 120c, the corresponding left reel 110a, middle reel 110b, and right reel 110c are stopped respectively. And, when the winning symbol that can receive the payout of the electronic medals wins according to the lottery result of the winning type lottery and the combination of the symbols displayed on the active lines, the number of electronic medals corresponding to the winning symbol is paid out (stored) to the medal holding unit and the game ends. When the player fails to win in the winning type that can receive the payout of the electronic medals or wins but does not win, the game ends when all of the left reel 110a, the middle reel 110b, and the right reel 110c stop.

[0021] In this embodiment, the above-described one game refers to a game in which, after either the insertion of the electronically converted medals held in the medal holding unit through the operation of the bet switch 116 or the automatic insertion of the electronically converted medals based on the replay symbol being displayed on the effective line, in response to the operation of the start switch 118 by the player, the left reel 110a, the middle reel 110b, and the right reel 110c are rotationally controlled and the winning type lottery is executed. Then, in response to the lottery result of the winning type lottery and the operations of the plurality of stop switches 120a, 120b, 120c by the player, the left reel 110a, the middle reel 110b, and the right reel 110c corresponding to the operated stop switches 120a, 120b, 120c are respectively stopped. When a winning combination that can receive the payout of the electronically converted medals wins, the game continues until the payout of the electronically converted medals is executed. Also, when the winning type for which the payout of the electronically converted medals can be received is a non-winning result or when a winning combination is selected but does not win, one game ends when all of the left reel 110a, the middle reel 110b, and the right reel 110c stop. However, the start of one game may be reinterpreted as the operation of the start switch 118 by the player instead of the above-described insertion of the electronically converted medals or the winning of the replay symbol. Also, the number of times such one game is repeated is defined as the number of games.

[0022] (Electrical Configuration of the Smart Pachislo 100) FIG. 2 is a block diagram showing a schematic electrical configuration of the smart pachislo 100 and the dedicated unit 350. As shown in FIG. 2, the smart pachislo 100 and the dedicated unit 350 are electrically connected via a lending device connection terminal board 206 for game balls or the like. The smart pachislo 100 is provided with a control board including a main control board 200 (main control unit) for controlling the progress of the game, a sub-control board 202 (sub-control unit) for controlling effects according to the progress of the game, and a medal number control board 204 for controlling the number of electronic medals (game medal numbers) held in the medal holding unit. Note that the transmission of electrical signals between the main control board 200 and the sub-control board 202 is limited to one direction from the main control board 200 to the sub-control board 202 from the viewpoint of preventing fraud and the like. Further, the dedicated unit 350 is provided with a dedicated unit control board 360 for transmitting and receiving electronic medals to and from the smart pachislo 100.

[0023] (Main control board 200) The main control board 200 has a semiconductor integrated circuit including a main CPU 200a which is a central processing unit, a main ROM 200b in which programs and the like are stored, a main RAM 200c which functions as a work area, etc., and comprehensively controls the entire smart pachislo 100. Note that the main RAM 200c retains data without being erased unless a setting change is made and RAM clearing is executed even when the power is turned off.

[0024] Further, the main control board 200 has functional units such as an initialization means 300, a bet means 302, a winning type lottery means 304, a reel control means 306, a determination means 308, a payout control means 310, a game state control means 312, an effect state control means 314, a command transmission means 316, etc., in which the main CPU 200a functions in cooperation with the main RAM 200c based on the program stored in the main ROM 200b.

[0025] On the main control board 200, various detection signals are received from the bed switch 116, start switch 118, stop switches 120a, 120b, 120c, and settlement switch 121. Based on the received detection signals, the main CPU 200a executes various processes.

[0026] The initialization means 300 executes the initialization process on the main control board 200. The bet means 302 bets the electronic medals for use in the game. The winning type lottery means 304 performs a winning type lottery to determine the success or failure of the winning combination, more specifically, the success or failure of the winning type including the winning combination, based on the operation of the start switch 118, as will be described in detail later.

[0027] The reel control means 306 controls the rotation of the left reel 110a, middle reel 110b, and right reel 110c in response to the operation of the start switch 118, and controls the stop of the corresponding left reel 110a, middle reel 110b, and right reel 110c in response to the operation of the stop switches 120a, 120b, and 120c corresponding to the rotating left reel 110a, middle reel 110b, and right reel 110c, respectively.

[0028] In addition, a reel drive control unit 150 is connected to the main control board 200. This reel drive control unit 150 drives the stepping motor 152 based on the rotation start signals of the left reel 110a, middle reel 110b, and right reel 110c transmitted from the reel control means 306 in response to the operation signal of the start switch 118. Also, the reel drive control unit 150 stops the drive of the stepping motor 152 based on the stop signals of the left reel 110a, middle reel 110b, and right reel 110c transmitted from the reel control means 306 and the detection signals of the rotation position detection circuit 154 in response to the operation signal of the stop switch 120.

[0029] The determination means 308 determines whether or not the symbol combination corresponding to the winning combination is displayed on the effective line. Here, when the symbol combination corresponding to the winning combination is displayed on the effective line, it may simply be referred to as a winning. The payout control means 310 pays out the electronic medals to the medal holding unit by the number (value amount) corresponding to the winning combination based on the fact that the symbol combination corresponding to the winning combination is displayed on the effective line (winning).

[0030] The game state control means 312 refers to the result of the winning type lottery and the determination result of the determination means 308, and shifts the game state to any one of a plurality of types of game states. Further, the effect state control means 314 refers to the result of the winning type lottery, the determination result of the determination means 308, and the transition information of the game state, and shifts the effect state to any one of a plurality of types of effect states. The game states include a non-internal game state, an internal middle game state that is shifted by winning a bonus combination in the non-internal game state, and a bonus game state that is shifted by the symbol combination corresponding to the bonus combination being displayed on the effective line in the internal middle game state. Further, the effect states include a non-AT (assist time) effect state in which an assist effect for assisting the winning of a specific combination (correct combination) is not executed when winning a winning type in which the specific combination (correct combination) and another winning combination (incorrect combination) overlap, and an AT effect state in which an assist effect is executed. Note that the specific combination refers to a winning combination that is more advantageous than other winning combinations, including not only the payout of electronic medals due to the winning of the winning combination but also all game benefits obtained by the winning of the winning combination.

[0031] The command transmission means 316 sequentially determines game-related commands associated with the operations of the bet means 302, the winning type lottery means 304, the reel control means 306, the determination means 308, the payout control means 310, the game state control means 312, the effect state control means 314, etc., and sequentially transmits the determined commands to the sub-control board 202.

[0032] In addition, a random number generator (random number generation means) 200d is provided on the main control board 200. The random number generator 200d sequentially increments a count value and resets the count value when counting for a predetermined number of times (changes the number sequence to determine an initial value), thereby looping the count value within a predetermined numerical range. In the main control board 200, a random number value is obtained by extracting the count value from the random number generator 200d at a predetermined time point. The random number value (hereinafter referred to as the winning type lottery random number) generated by the random number generator 200d of the main control board 200 is used for the gaming benefits given to the player, for example, for the winning type lottery means 304 to determine the winning type.

[0033] (Sub-control board 202) In addition, similar to the main control board 200, the sub-control board 202 includes various semiconductor integrated circuits including a sub-CPU 202a which is a central processing unit, a sub-ROM 202b storing programs and the like, and a sub-RAM 202c functioning as a work area, etc., and controls the effects in particular based on commands from the main control board 200. Also, similar to the main RAM 200c, a backup power source (not shown) is connected to the sub-RAM 202c, and the data is retained without being erased even when the power is turned off. Note that, similar to the main control board 200, a random number generator (random number generation means) 202d is also provided on the sub-control board 202, and the random number value (hereinafter referred to as the effect lottery random number) generated by the random number generator 202d is mainly used to determine the mode of the effect.

[0034] In addition, in the sub-control board 202, the sub-CPU 202a has functional parts such as an initialization determination means 330, a command reception means 332, and an effect control means 334 which function by cooperating with the sub-RAM 202c based on the program stored in the sub-ROM 202b.

[0035] The initialization determination means 330 executes the initialization process in the sub-control board 202. The command reception means 332 receives commands from other control boards such as the main control board 200 and performs processing on the commands.

[0036] The performance control means 334 receives a detection signal from the performance switch 122 and determines the performance of the game performed by each device of the liquid crystal display unit 124, the speaker 128, and the performance lamp 126 based on the received command. Specifically, the performance control means 334 determines the image data displayed on the liquid crystal display unit 124 and the lighting data for the performance through lighting devices such as the performance lamp 126, and also determines the audio data constituting the audio to be output from the speaker 128. Then, the performance control means 334 executes the determined performance of the game. Note that the performance includes auxiliary performances.

[0037] (Medal number control board 204) Also, the medal number control board 204 is connected to the main control board 200 and has various semiconductor integrated circuits including a medal CPU 204a which is a central processing unit, a medal ROM 204b storing programs, etc., and a medal RAM 204c functioning as a work area, and manages the electronic medals used for the game. Further, the medal number control board 204 is connected to the dedicated unit 350 through a lending device connection terminal board 206 for game balls, etc.

[0038] Here, the lending device connection terminal board 206 for game balls, etc. is a connection terminal board for connecting the smart pachislo 100 and the dedicated unit 350, and receives signals related to the lending of electronic medals, transmits the lending reception result of the electronic medals, transmits signals related to the counting of the electronic medals, and transmits each information of the smart pachislo 100.

[0039] (Dedicated unit 350) The dedicated unit 350 is installed near the smart pachislo 100 and can lend electronic medals to the player and count the electronic medals obtained by the player. The dedicated unit 350 is provided with a dedicated unit control board 360. Connected to the dedicated unit control board 360 are a cash input unit 362, a card insertion unit 364, a lending switch 366, a return switch 368, a game switch 370, a frequency display device 372, and an acquired medal number display device 374.

[0040] The cash input unit 362 functions as an insertion slot for inserting cash. The card insertion unit 364 enables the insertion and withdrawal of a card medium capable of storing electronic medals. The lending switch 366 is composed of a push switch and detects an operation of transferring electronic medals corresponding to the frequency of cash held in the dedicated unit 350 to the smart pachislo 100. The return switch 368 is composed of a push switch and detects an operation of transferring the electronic medals held in the dedicated unit 350 to the card medium and pulling out the card medium from the dedicated unit 350 through the card insertion unit 364. The game switch 370 is composed of a push switch and detects an operation of transferring the electronic medals held in the dedicated unit 350 to the smart pachislo 100. The frequency display device 372 displays the frequency held in the dedicated unit 350, that is, the frequency corresponding to the cash inserted from the cash input unit. The acquired medal number display device 374 displays the number of acquired medals, which is the total number of electronic medals held in the dedicated unit 350.

[0041] FIG. 3 is an external view for explaining a schematic mechanical configuration of the smart pachislo 100 and the dedicated unit 350. Here, while referring to FIG. 3, the flow of starting a game and the flow of ending a game in the smart pachislo 100 will be described.

[0042] When a player attempts to play a game on the smart pachislot 100, first, the player inserts cash into the cash insertion unit 362 of the dedicated unit 350 shown in FIG. 3. Then, the frequency display device 372 of the dedicated unit 350 displays the frequency corresponding to the inserted cash (for example, "10" for an insertion of one thousand yen). When the player operates the lending switch 366, the digitized medals corresponding to the frequency held in the dedicated unit 350 (for example, "50") are transferred to the smart pachislot 100 at once. Then, the number of digitized medals transferred (for example, "50") is displayed on the game medal number display device 114 of the smart pachislot 100. In this way, the process of lending digitized medals from the dedicated unit control board 360 to the medal number control board 204 of the smart pachislot 100 may be referred to as the lending process. Specifically, when the smart pachislot 100 receives a lending notice from the dedicated unit 350 described later, if the lending notice is normal, it receives the transfer of digitized medals and notifies "normal" in the lending receipt result response. On the other hand, when the message length and the command value in the lending notice are normal but other information is abnormal, the smart pachislot 100 notifies "abnormal" in the lending receipt result response described later. Also, when the lending notice is not received normally, or when the message length and the command value of the lending notice are abnormal, the smart pachislot 100 discards the received message without performing an error display and waits until it can receive a lending notice with at least a normal message length and command. In addition, when the lending process cannot be performed, that is, when the gaming machine information notice described later is abnormal, when the counted medal number in the counting notice described later (the number of digitized medals transferred to the dedicated unit 350 at once) is "1" or more, when the number of game medals displayed on the game medal number display device 114 is 15,000 or more, when the checksum of the received lending notice is abnormal, when the lending serial number of the received lending notice is not consecutive, when the number of lent medals in the received lending notice is "51" or more, or when, in the gaming machine information notice transmitted from the medal CPU 204a to the dedicated unit 350 described later, information other than the hall control / fraud monitoring information is notified, the smart pachislot 100 notifies "abnormal" in the lending receipt result response.

[0043] Subsequently, when the player operates the bet switch 116, electronic medals are bet. At this time, on the game medal number display device 114, a value obtained by subtracting the number of bet electronic medals (for example, "3") (for example, "47") is displayed. In this way, the player can start the game. Thus, the process of inserting (betting) electronic medals from the medal number control board 204 may be referred to as the insertion process. If, as a result of the game, a small winning combination with a payout number of 11 is won, the number of paid-out electronic medals (for example, "11") is displayed as a payout display on a part of the liquid crystal display unit 124, and on the game medal number display device 114, a value obtained by adding the number of paid-out electronic medals (for example, "58") is displayed. Thus, the process of paying out electronic medals to the medal number control board 204 as a result of the game may be referred to as the payout process.

[0044] Note that after the player operates the bet switch 116 and electronic medals are bet, and before the start switch 118 is operated (game start), if the settlement switch 121 is operated, the number of bet electronic medals (for example, "3") is added to the game medal number display device 114 (for example, it becomes "50"), and the bet state is released. Thus, the process of settling the inserted electronic medals and adding them to the medal number control board 204 may be referred to as the settlement process. As will be described later, although the operations of the settlement process and the insertion process are different, the processes themselves corresponding to the operations are the same. Therefore, in the following, it is also possible to replace the parts described using the insertion process with the settlement process with the interpretation of inserting negative electronic medals and apply them.

[0045] When the player finishes the game, the player operates the count switch 112 to transfer the electronic medals held in the medal holding unit to the dedicated unit 350. Then, the number of game medals held in the medal holding unit is displayed on the acquired medal number display device 374 of the dedicated unit 350, and "0" is displayed on the game medal number display device 114. In this way, the process in which the electronic medals are transferred from the medal number control board 204 of the smart pachislot 100 to the dedicated unit control board 360 and counted is sometimes referred to as the counting process. Subsequently, when the player operates the return switch 368, the electronic medals held in the dedicated unit 350 are transferred to the card, and the card is pulled out from the dedicated unit 350 through the card insertion part 364. In this way, the player can store the acquired electronic medals in the card medium.

[0046] When the player attempts to play the game again, instead of using cash, the player can insert the card medium with the accumulated electronic medals into the card insertion part 364 and play the game with the electronic medals accumulated in the card medium. Then, the electronic medals accumulated in the card medium are transferred to the dedicated unit 350, and the total number of the electronic medals accumulated in the card medium is displayed on the acquired medal number display device 374. The player can transfer the electronic medals held in the dedicated unit 350 to the smart pachislot 100 by operating the game switch 370 instead of the lending switch 366.

[0047] When the lending switch 366 or the counting switch 112 is operated, the medal CPU 204a executes the lending process and the counting process of the electronic medals, and sends a command to that effect to the main CPU 200a. The main CPU 200a that has received the command sends a command to that effect to the sub-CPU 202a. Then, when the electronic medals are actually lent out or counted in the lending process and the counting process, the sub-CPU 202a outputs a predetermined sound representing the movement of the electronic medals from the speaker 128. In the counting process, the sub-CPU 202a may output a predetermined sound from the speaker 128 either in the case of a short press or a long press of the counting switch 112, or may output a predetermined sound from the speaker 128 only in either the short press or the long press of the counting switch 112. Also, when the operation of the counting switch 112 in the counting process is completed (for example, when the button is released), the sub-CPU 202a may output a predetermined voice indicating that the counting is completed, or may output a predetermined voice for preventing the player from forgetting to withdraw the card from the card insertion unit 364 after the completion of the counting process. In this way, the player can audibly confirm that the lending process and the counting process are being properly executed. Also, the sub-CPU 202a may notify that the lending process and the counting process are being executed not only through the speaker 128 but also through each device such as the liquid crystal display unit 124 and the effect lamp 126. Here, although the CPU (Central Processing Unit) is cited as an example of the control subject for explanation, various arithmetic elements capable of arithmetic operations such as MPU (Micro Processor Unit), DSP (Digital Signal Processor), and FPGA (Field Programmable Gate Array) can be applied.

[0048] In such a smart pachislot 100, since physical medals are not required, it is possible to prevent acts such as pseudo-medal insertion and the use of illegally brought-in medals. Also, since there is no need to provide a mechanism for inserting and paying out game media inside the gaming machine, the design cost and manufacturing cost can be reduced. Furthermore, by centrally managing the lending of game media to players and the counting of acquired game media, etc., fraud prevention becomes possible. Also, by centrally managing data, it is possible to suppress the element of chance and, as a result, strengthen measures against addiction.

[0049] FIG. 4 is an external view for explaining the mechanical configuration of the game medal number display device 114. In FIG. 4, the direction of arrow F indicates the front direction of the smart pachislot 100, and the direction of arrow B indicates the back direction of the smart pachislot 100. The game medal number display device 114 displays the number of game medals.

[0050] As shown in FIG. 4, the game medal number display device 114 is housed in the housing 113 together with the counting switch 112. The housing 113 is arranged in the upper right part of the operation unit installation base 111 of the smart pachislot 100 shown in FIG. 1. That is, the game medal number display device 114 is provided at a position corresponding to the position where the medal insertion port is arranged in a slot machine where the game progresses using physical medals. Thereby, the space of the medal insertion port, which becomes unnecessary by introducing the smart pachislot 100, can be effectively utilized. Also, since the game medal number display device 114 displays the number of game medals, its usage purpose is common in terms of the medal insertion port used for adding medals and handling medals (electronic medals), and players do not feel a sense of discomfort about the presence of the game medal number display device 114.

[0051] In addition, the game medal number display device 114 includes collective light emitters L1 to L5, which are 7-segment LEDs having seven light-emitting elements. Each of the collective light emitters L1 to L5 can display any digit from 0 to 9, and displays the number of game medals by emitting light from the segments. The collective light emitters L1 to L5 are provided side by side in the left-right direction of the smart pachislot 100. Therefore, in the example of FIG. 4, the collective light emitters L1 to L5 can display a maximum of five-digit numbers. However, the number of the collective light emitters L1 to L5 is not limited to five, and may be six (six digits) or more.

[0052] The collective light emitters L1 to L5 are housed in the housing 113. Here, the light emitted by the collective light emitters L1 to L5 passes through the front surface of the housing 113 and reaches the outside. Thereby, the player can visually recognize the number of game medals displayed by the collective light emitters L1 to L5 through the housing 113. On the other hand, the appearance of the members inside the housing 113 is blocked by the housing 113 and is not visually recognized from the outside. Therefore, the player can be made to visually recognize the number of game medals integrally without making the player aware that the collective light emitters L1 to L5 are divided into five electrical elements. Hereinafter, the display mode of the game medal number display device 114 via the parallel port and the serial port of the medal CPU 204a will be described.

[0053] FIG. 5 is a block diagram showing the electrical configuration of the game medal number display device 114. Here, the number of game medals is displayed on the game medal number display device 114 by outputting parallel signals (data signals and common signals) from the parallel ports (PORT1, PORT2) of the medal CPU 204a. In FIG. 5, the game medal number display device 114 is composed of driver circuits P1, P2, a collective resistor R1, and collective light emitters L1 to L5 arranged on a light-emitting substrate 114a. The connector of the medal number control board 204 and the connector of the light-emitting substrate 114a are connected directly or via a harness.

[0054] The driver circuit P1 is composed of, for example, a transistor array such as "62783", and supplies a drive current to the OUT terminals (O8 to O1) in response to the input to the IN terminals (I8 to I1). The driver circuit P2 is composed of, for example, an inverted output transistor array such as "62083", and supplies an inverted drive current to the OUT terminals (O8 to O1) in response to the input to the IN terminals (I8 to I1). Note that the terminals not connected by the shift register circuits Q1 and Q2 and the driver circuits P1 and P2 are unused (reserved) terminals. The driver circuits P1 and P2 reflect the parallel signals (data signals and common signals) of the medal CPU 204a input to the IN terminals (I8 to I1) as the same signals or inverted signals to the OUT terminals (O8 to O1).

[0055] In addition, the collective light emitters L1 to L5 on the light emitting substrate 114a are 7-segment LEDs as described above. Each of the collective light emitters L1 to L5 has a common terminal (C) in which the anode terminals or cathode terminals of a plurality of LEDs are shared. When a potential difference occurs (when current flows) between the common terminal (C) and the segment terminals (a to g, dp) through the collective resistor R1, the corresponding segment emits light (lights up). Here, an example in which the cathode terminal is used as the common terminal (cathode common) will be described.

[0056] In the example of FIG. 5, the driver circuit P2 functions as a common output circuit that switches and outputs in time division the common signal that specifies the collective light emitter to be lit among the collective light emitters L1 to L5. The driver circuit P1 functions as a data output circuit that commonly outputs the data signal indicating the data for causing the collective light emitters L1 to L5 specified by the common signal to emit light. In this way, the five data corresponding to the collective light emitters L1 to L5 are switched and displayed for each of the collective light emitters L1 to L5 in time division according to the common signal. In this way, the lighting method of displaying the collective light emitters L1 to L5 in time division may be referred to as a dynamic lighting method.

[0057] FIG. 6 is a block diagram showing another electrical configuration of the game medal number display device 114. Here, the number of game medals is displayed on the game medal number display device 114 by outputting a serial signal from the serial port (SO) of the medal CPU 204a. In FIG. 6, the game medal number display device 114 is composed of a shift register circuit Q1, Q2, driver circuits P1, P2, a collective resistor R1, and collective light emitters L1 to L5 arranged on a light emitting substrate 114a. Here, the driver circuits P1, P2, the collective resistor R1, and the collective light emitters L1 to L5 are substantially equal in function to the driver circuits P1, P2, the collective resistor R1, and the collective light emitters L1 to L5 described in FIG. 5. And the connector of the medal number control board 204 and the connector of the light emitting substrate 114a are connected directly or via a harness.

[0058] The shift register circuits Q1 and Q2 are composed of shift registers such as the "74595" of the TTL series, for example, and latch and shift the serial signal of the medal CPU 204a input to the serial input terminal (SI) to the shift register at the rising or falling timing of the clock terminal (SCK). Here, the serial signal is composed of, for example, 16 bits, the upper 8 bits contain common information, and the lower 8 bits contain data information.

[0059] Then, the shift register circuits Q1 and Q2 latch the value of the shift register to the output register at the rising or falling timing of the latch terminal (RCK), and output the value of the output register from the output terminals (QH to QA). Also, the serial signal input to the serial input terminal (SI) is output from the serial output terminal (QH') after being shifted by the shift register, and is transmitted to another shift register connected in a daisy chain. For example, in the example of FIG. 6, the serial output terminal (QH') of the shift register circuit Q1 is connected to the serial input terminal (SI) of the shift register circuit Q2. Therefore, the medal CPU 204a can transmit information to the two shift register circuits Q1 and Q2 that handle 8-bit serial signals using only a 16-bit serial signal.

[0060] Similar to FIG. 5, the driver circuit P1 supplies a drive current to the OUT terminals (O8 to O1) in response to the input to the IN terminals (I8 to I1). Also, similar to FIG. 5, the driver circuit P2 supplies an inverted drive current to the OUT terminals (O8 to O1) in response to the input to the IN terminals (I8 to I1). Note that the terminals not connected by the shift register circuits Q1 and Q2 and the driver circuits P1 and P2 are unused (reserved) terminals.

[0061] Also, similar to FIG. 5, each of the collective light emitters L1 to L5 has a common terminal (C) in which the anode terminals or cathode terminals of a plurality of LEDs are shared. When a potential difference (when current flows) occurs between the common terminal (C) and the segment terminals (a to g, dp) through the collective resistor R1, the corresponding segment emits light (lights up).

[0062] In the example of FIG. 6, the shift register circuit Q2 and the driver circuit P2 function as a common output circuit that switches and outputs, in a time-division manner, a common signal that specifies the collective light emitter to be lit among the collective light emitters L1 to L5. Also, the shift register circuit Q1 and the driver circuit P1 function as a data output circuit that commonly outputs a data signal indicating data for causing the collective light emitters L1 to L5 specified by the common signal to emit light. In this way, five data corresponding to the collective light emitters L1 to L5 are switched and displayed in a time-division manner on each of the collective light emitters L1 to L5 (dynamic lighting method).

[0063] In this way, the medal CPU 204a can appropriately display the maximum number of five digits of game medals by displaying numerical values in a time-division manner on each of the collective light emitters L1 to L5 by the dynamic lighting method.

[0064] Hereinafter, the specific processing in the main control board 200 will be described based on a flowchart.

[0065] (Main processing of the main control board 200) FIG. 7 is a flowchart showing the main processing of the main control board 200. Here, first, along with the main processing of the main control board 200, an outline of one game after initialization will be described, and then details of each process will be explained. Also, here, the processes related to the features of the present embodiment will be described in detail, and the description of the configurations unrelated to the features of the present embodiment will be omitted. Also, although detailed description will be omitted, when each process is performed, the switches (bet switch 116, start switch 118, stop switches 120a, 120b, 120c) used in each process are enabled at the start of the process and disabled at the end of the process.

[0066] (Step S100) When the power of the smart pachislot 100 is turned on via the power switch and it becomes energized, the initialization means 300 executes an initialization process in preparation for the start of the game. Also, the initialization means 300 can also change the settings. The setting change is to change the set value indicating the degree of advantage in stages (for example, in 6 stages). The setting change also includes resetting to the same set value (a process of changing the current set value to the same set value as the current set value (overwriting, maintaining)). The initialization means 300 generates backup data at any time while the power is on, and causes the main RAM 200c to hold the backup data. Therefore, even if an unexpected power failure (power cut) occurs, in this initialization process, it is possible to return to the state before the power cut using the held backup data. For example, even if an unexpected power cut occurs during the rotation of the reel 110, after the return operation, each reel 110 starts again from the rotating state. Therefore, in the initialization process, basically, the main RAM 200c is not initialized (RAM cleared).

[0067] (Step S200) Subsequently, through the operation of the bet switch 116 by the player, the betting means 302 bets the electronic medals. Further, the command transmission means 316 generates an insertion command indicating that the operation has been performed, and transmits the generated insertion command to the sub-control board 202. Further, the command transmission means 316 transmits a game medal insertion command including transmission information indicating the required number of inserted medals to the medal number control board 204.

[0068] (Step S300) Next, the winning type lottery means 304 enables the game start operation for the start switch 118 and shifts to the operation waiting state of the start switch 118. Here, the winning type lottery means 304, in response to the operation of the start switch 118 by the player, acquires one winning type lottery random number at the time when the start switch 118 is operated from the winning type lottery random numbers updated by the random number generator 200d of the main control board 200. Then, the winning type lottery means 304 determines one winning type lottery table corresponding to the currently set game state from the winning type lottery table, determines which winning area in the determined winning type lottery table the acquired winning type lottery random number corresponds to, and determines the winning type or non-winning of the determined winning area as the lottery result. Further, when the winning combination "RBB" is determined in the winning type lottery, the game state control means 312 shifts the game state from the non-internal game state to the RBB internal middle game state. Further, after the lottery result is determined in response to the operation of the start switch 118, the command transmission means 316 generates a winning type command including the lottery result (winning type or non-winning) of the winning type lottery and information regarding the game state, and transmits the generated winning type command to the sub-control board 202.

[0069] (Step S400) When the start switch 118 is operated, the reel control means 306 drives the stepping motor 152 to rotate the left reel 110a, the middle reel 110b, and the right reel 110c. In this reel rotation process, when a predetermined time (for example, 4.1 seconds) has elapsed (wait) from the rotation start time of the left reel 110a, the middle reel 110b, and the right reel 110c in the previous game, the rotation of the left reel 110a, the middle reel 110b, and the right reel 110c in the current game is started. When all of the left reel 110a, the middle reel 110b, and the right reel 110c reach steady rotation, the process proceeds to step S500.

[0070] (Step S500) Subsequently, the reel control means 306 activates the stop switches 120a, 120b, and 120c and, when receiving an operation of the stop switches 120a, 120b, and 120c by the player, performs stop control on any one of the left reel 110a, the middle reel 110b, and the right reel 110c corresponding to the operation. Further, when any one of the stop switches 120a, 120b, and 120c is operated, the command transmission means 316 generates a stop command (first stop command, second stop command, third stop command) indicating the information of the operated stop switch 120a, 120b, or 120c each time the operation is made, and sequentially transmits the generated stop command to the sub-control board 202.

[0071] (Step S600) Next, the determination means 308 determines which of the predetermined combinations the symbol combination displayed on the effective line A, which is the line for determining the winning of the winning combination, corresponds to (the winning combination that has won), and according to the symbol combination, if it is within the advantageous section and a minor winning combination has won, the net increase counter is updated. Here, the advantageous section is a game section that is advantageous to the player, including a game section having the performance related to the instruction function, that is, a game section that executes an auxiliary effect (instruction function), etc. Also, different from the advantageous section, a game section where an auxiliary effect cannot be executed is called a non-advantageous section. Note that the advantageous section is a game section in which, as a result of a lottery or the like related to the operation of the auxiliary effect being performed on the main control board 200, when the auxiliary effect is activated, information indicating the content of the instruction may be transmitted to a peripheral board such as the sub-control board 202 only when it is displayed on the notification means so that the content of the instruction can be identified on the main control board 200. Further, the game state control means 312, in the game state inside the RBB, if the symbol combination displayed on the effective line A is the symbol combination corresponding to the winning combination "RBB", shifts the game state from the game state inside the RBB to the game state during RBB operation. Also, the command transmission means 316 generates a winning command including the symbol combination displayed on the effective line A and the number of paid-out electronic medals when a symbol combination corresponding to a minor winning combination is displayed on the effective line A, and transmits the generated winning command to the sub-control board 202.

[0072] (Step S700) Also, based on the symbol combination (stop mode of the reel 110) displayed on the effective line A, the payout control means 310, for example, when a symbol combination corresponding to a minor winning combination is displayed on the effective line A, executes the payout process of the electronic medals corresponding to the minor winning combination, and when a symbol combination corresponding to a replay winning combination is displayed on the effective line A, executes a process for automatically placing a bet in the next game. Also, when the payout process of the electronic medals is performed, the command transmission means 316 generates a payout command indicating that the payout process has been performed, and transmits the generated payout command to the sub-control board 202. Further, the command transmission means 316 transmits a payout end command including transmission information indicating the number of paid-out medals to the medal number control board 204.

[0073] (Step S800) When a predetermined number of electronic medals are paid out in the game state during RBB operation, the game state control means 312 shifts the game state from the game state during RBB operation to a non-internal game state. Further, the effect state control means 314 changes the effect state and changes between the advantageous section and the non-advantageous section. Further, when the game state or the effect state is changed, the command transmission means 316 generates a game transition command including the changed game state or effect state, etc., and transmits the generated game transition command to the sub-control board 202. Thus, when the game transition process S800 ends, the one game ends.

[0074] One game is executed through a series of processes from step S200 to step S800. Thereafter, steps S200 to S800 are repeated.

[0075] (Main process and timer interrupt process of medal number control board 204) FIG. 8 is a flowchart showing the main process (main loop process) of the medal number control board 204. Here, the processes related to the features of the present embodiment will be described in detail, and the description of the configurations unrelated to the features of the present embodiment will be omitted.

[0076] (Step S900) When the power of the smart pachislot 100 is turned on via the power switch and the medal number control board 204 is energized, the medal CPU 204a executes initialization processing in preparation for the start of the game. While the power is on, the medal CPU 204a generates backup data at any time and causes the medal RAM 204c to hold the backup data. Therefore, even if an unexpected power failure (power cut) occurs, in this initialization process, it is possible to return to the state before the power cut using the held backup data. For example, even if an unexpected power cut occurs while the electronic medals are held in the medal holding unit, the game starts from the state where the electronic medals are held after the recovery operation. Therefore, in the initialization process, basically, the initialization (RAM clear) of the medal RAM 204c is not performed.

[0077] (Step S910) When the initialization process ends, the medal CPU 204a determines whether an update event for the number of game medals in the medal holding unit has occurred. If an update event for the number of game medals occurs, the medal CPU 204a executes an update process for updating the number of game medals according to the update event. First, the medal CPU 204a determines whether there is a request to insert or settle electronic medals from the main CPU 200a. If there is a request to insert or settle electronic medals, the process proceeds to step S912. If there is no request to insert or settle electronic medals, the process proceeds to step S920.

[0078] (Step S912) When there is a request to insert electronic medals from the main CPU 200a, the medal CPU 204a executes an insertion process for subtracting the number of game medals in response to the insertion of electronic medals. When there is a request to settle electronic medals from the main CPU 200a, the medal CPU 204a executes a settlement process for adding the inserted electronic medals to the number of game medals.

[0079] (Step S920) Next, the medal CPU 204a determines whether there is a request to pay out the electronic medal from the main CPU 200a. If there is a request to pay out the electronic medal, the process proceeds to step S922. If there is no request to pay out the electronic medal, the process proceeds to step S930.

[0080] (Step S922) When there is a request to pay out the electronic medal from the main CPU 200a, the medal CPU 204a executes a payout process of adding the paid-out electronic medal to the number of game medals.

[0081] (Step S930) Subsequently, the medal CPU 204a determines whether there is a request to lend out the electronic medal from the dedicated unit 350. If there is a request to lend out the electronic medal, the process proceeds to step S932. If there is no request to lend out the electronic medal, the process proceeds to step S940.

[0082] (Step S932) When there is a request to lend out the electronic medal from the main CPU 200a, the medal CPU 204a executes a lending process of adding the lent-out electronic medal to the number of game medals.

[0083] (Step S940) Next, the medal CPU 204a determines whether the counting switch 112 has been operated by the player. If the counting switch 112 has been operated, the process proceeds to step S942. If the counting switch 112 has not been operated, the process proceeds to step S950.

[0084] (Step S942) When the counting switch 112 is operated by the player, the medal CPU 204a notifies the dedicated unit 350 of the count and executes a counting process of subtracting the counted electronic medal from the number of game medals.

[0085] (Step S950) The medal CPU 204a monitors whether an error has occurred in the medal number control board 204 itself, or in the main control board 200 and the dedicated unit 350. If an error has occurred, it executes error monitoring processing to limit the functions affected by the error, and repeats the processing (main processing) from step S910.

[0086] In this way, in the main processing of the medal number control board 204, when an update event of the number of game medals occurs, update processing of the number of game medals is executed according to the update event. If no update event of the number of game medals occurs, only error monitoring processing and the like are performed.

[0087] Among the above-mentioned update processes of the number of game medals (insertion process, settlement process, payout process, lending process, counting process), for the insertion process, settlement process, and payout process targeting the main control board 200, since operations corresponding to each process cannot be accepted simultaneously, those processes are not executed simultaneously either. Also, the lending process and counting process targeting the dedicated unit 350 are not executed simultaneously because the communication timings are different. Therefore, even if update events of the number of game medals overlap, only one of the insertion process, settlement process, and payout process overlaps with one of the lending process and counting process, and the main processing itself does not take a long time.

[0088] FIG. 9 is a flowchart showing the timer interrupt processing of the medal number control board 204. Here, the medal CPU 204a executes timer interrupt processing according to the timing of the timer interrupt (for example, a cycle of 1.49 msec).

[0089] (S960) When a timer interrupt occurs, the medal CPU 204a executes input processing for inputting various signals monitored by the medal number control board 204. The medal CPU 204a acquires, for example, the state (ON / OFF) of the counting switch 112 and the state (ON / OFF) of the VL connection signal described later, and holds them in the medal RAM 204c.

[0090] (S970) Next, the medal CPU 204a executes arithmetic processing for calculating various variables that require time management and should be executed within the timer interrupt processing. The medal CPU 204a updates, for example, various timers by the interrupt period.

[0091] (S980) Subsequently, the medal CPU 204a executes output processing for outputting various signals monitored by the medal number control board 204 to complete the timer interrupt processing. The medal CPU 204a outputs, for example, a clear signal due to timeout according to the result of the timer updated in step S970.

[0092] Also, in the output processing S980, the medal CPU 204a also outputs lighting information to the collective light emitters L1 to L5. Specifically, the medal CPU 204a indicates the number of game medals at that time in five digits, and at the timing of the timer interrupt, any one of the digits is displayed on the corresponding collective light emitter. The numerical range of the number of game medals is represented by 0 to 16382 in consideration of the maximum difference number of medals in one business day. When the upper digit of the significant numerical value is 0, the numerical value is blank (extinguished). For example, if the number of game medals is 1234. Then, the five-digit numerical value displayed on the collective light emitters L1 to L5 is "01234", but the uppermost "0" is not displayed. Therefore, in the game medal number display device 114, the uppermost digit is not displayed, and the lower four digits are displayed as "1", "2", "3", and "4".

[0093] As described with reference to FIGS. 4 to 6, the medal CPU 204a displays the number of game medals on the collective light emitters L1 to L5 by the dynamic lighting method. However, in the dynamic lighting method, if the time division of the collective light emitters L1 to L5 is not made uniform, the light amounts of the collective light emitters L1 to L5 will not be uniform. Therefore, in the present embodiment, in the timer interrupt process, the collective light emitters L1 to L5 are switched one by one at each timer interrupt timing, thereby ensuring the uniformity of the light amounts of the collective light emitters L1 to L5. That is, the medal CPU 204a displays the numerical value of the corresponding digit only on one of the collective light emitters L1 to L5 for each timer interrupt process, and in the next timer interrupt process, it displays the numerical value of the corresponding digit on another collective light emitter. The medal CPU 204a sequentially displays numerical values on different collective light emitters, and when the display of all of the collective light emitters L1 to L5 is completed (when the timer interrupt process ends five times), it also repeats the display from one of the collective light emitters L1 to L5. For example, the medal CPU 204a repeats the display such as collective light emitter L1 → collective light emitter L2 → collective light emitter L3 → collective light emitter L4 → collective light emitter L5 → collective light emitter L1 →... every time a timer interrupt occurs. In this way, it is possible to appropriately display the number of game medals on the collective light emitters L1 to L5 while ensuring the uniformity of the light amounts of the collective light emitters L1 to L5.

[0094] However, if the updated number of game medals is directly displayed on the collective light emitters L1 to L5, there is a possibility that the display mode unintended by the game medal number display device 114 will occur due to the overlap of the update timing and the display timing of the number of game medals. Therefore, in order to appropriately display the number of game medals on the collective light emitters L1 to L5, the medal CPU 204a sets the number of game medals as the number of display medals in the medal RAM 204c at a predetermined timing, and in the timer interrupt process, it displays the set number of display medals on the collective light emitters L1 to L5. Hereinafter, the timing for setting the number of game medals as the number of display medals will be considered.

[0095] As described with reference to FIG. 8, the number of gaming medals is updated at the timing when an update event of the number of gaming medals occurs in the main process. Here, it is assumed that the medal CPU 204a sets the number of gaming medals to the number of display medals every time an update event of the number of gaming medals occurs. For example, when there is a request for inserting (settling) an electronic medal from the main CPU 200a, the medal CPU 204a executes an insertion process (settlement process) of subtracting (adding) the number of gaming medals in response to the insertion of the electronic medal, and sets the number of gaming medals after subtraction to the number of display medals. Also, when there is a request for paying out an electronic medal from the main CPU 200a, the medal CPU 204a executes a payout process of adding the paid-out electronic medal to the number of gaming medals, and sets the number of gaming medals after addition to the number of display medals. Further, when there is a request for lending out an electronic medal from the main CPU 200a, the medal CPU 204a executes a lending process of adding the lent-out electronic medal to the number of gaming medals, and sets the number of gaming medals after addition to the number of display medals. Also, when the counting switch 112 is operated by the player, the medal CPU 204a notifies the dedicated unit 350 of the count, executes a counting process of subtracting the counted electronic medals from the number of gaming medals, and sets the number of gaming medals after subtraction to the number of display medals.

[0096] In this way, if the number of game medals is set to the number of display medals every time an update event for the number of game medals occurs, the number of display medals is also updated at the timing when the game medals are updated, so it becomes possible to quickly display the number of display medals that has just completed the update process. However, if the specification is such that the next process can be shifted only after the display (displaying all of the collective light emitters L1 to L5) of the number of display medals to the game medal number display device 114 of the number of display medals is completed after setting the number of game medals to the number of display medals every time an update event for the number of game medals occurs, the setting process and the display process of the number of display medals occur in each update process, so the processing load, processing time, and program capacity increase. Also, for example, when the insertion process and the lending process occur simultaneously, the setting process and the display process of the number of display medals by the lending process are after the completion of the setting process and the display process of the number of display medals by the insertion process. Eventually, the display process of the number of display medals by the final lending process becomes slow. Also, when the insertion process and the lending process occur simultaneously, the number of display medals set in the insertion process is immediately updated in the lending process, and the setting process and the display process of the number of display medals by the insertion process are wasted.

[0097] Therefore, it is assumed that the medal CPU 204a sets the number of game medals to the number of display medals after all the update events for the number of game medals in the main process shown in FIG. 8 have ended. For example, the medal CPU 204a sets the updated number of game medals to the number of display medals after all of the insertion process (settlement process), payout process, lending process, and counting process have ended, before the error monitoring process S950, during the error monitoring process S950, or after the error monitoring process S950.

[0098] In this way, if the number of game medals is set to the display medal number after all the update events of the number of game medals are completed, the final number of game medals updated in each update process can be set to the display medal number at once. Therefore, compared with the case where the number of game medals is set to the display medal number every time an update event of the number of game medals occurs, an increase in processing load, processing time, and program capacity can be suppressed. Also, even when the insertion process and the lending process occur simultaneously, since the setting process and the display process of the display medal number by the insertion process are not performed, it is possible to prevent a delay in the display process of the display medal number and the setting process and the display process of the display medal number by the insertion process from being wasted. However, since the setting and display of the display medal number are the last in the main process, the display timing is delayed compared with the case where the number of game medals is set to the display medal number every time an update event of the number of game medals occurs.

[0099] As described above, in the timer interrupt process shown in FIG. 9, the medal CPU 204a displays the number of display medals on the collective light emitters L1 to L5 by the dynamic lighting method. Therefore, it is conceivable that the medal CPU 204a sets the number of game medals to the number of display medals before the output process S980 in the timer interrupt process shown in FIG. 9, particularly before the medal CPU 204a outputs the lighting information to the collective light emitters L1 to L5. For example, the medal CPU 204a sets the updated number of game medals to the number of display medals before the arithmetic process S970, during the arithmetic process S970, or after the arithmetic process S970 and before the output process S980.

[0100] In this way, setting the number of game medals to the number of display medals before the output process S980 in the timer interrupt process means that the number of display medals is set immediately before the medal CPU 204a displays the number of display medals on the collective light emitters L1 to L5. Therefore, it becomes possible to display the number of game medals immediately before (the latest) to be displayed on the collective light emitters L1 to L5 on the collective light emitters L1 to L5.

[0101] Also, the timer interrupt process is independent of the main process and is executed at a short cycle, such as 1.49 msec. Therefore, the medal CPU 204a can set the number of game medals to the number of display medals at a short cycle and display the number of display medals on the collective light emitters L1 to L5. Thus, compared with the case of setting the number of game medals to the number of display medals in the main process that takes a long time, it is possible to display the number of display medals more quickly.

[0102] Also, the timer interrupt process is independent of the main process. Even if the main process is in the middle, that is, even when the update process (insertion process, settlement process, payout process, lending process, counting process) is being executed, the process is executed after temporarily stopping that process. Therefore, in a state where the main process has stopped, the latest number of game medals updated immediately before in the main process can be set as the number of display medals. Thus, compared with the case of setting the number of game medals to the number of display medals after all the update events of the number of game medals have ended in the main process, it is possible to display the latest number of display medals. Also, compared with the case of setting the number of game medals to the number of display medals every time an update event of the number of game medals occurs, an increase in processing load, processing time, and program capacity can be suppressed. For example, even when the insertion process and the lending process occur simultaneously, since the latest number of game medals updated by either process is referred to, it is possible to prevent a delay in the display process of the number of display medals and a waste of the setting process and display process of the number of display medals due to the insertion process.

[0103] As described above, here, the number of game medals (number of display medals) updated immediately before can be quickly displayed, so that the player can appropriately grasp the latest number of game medals.

[0104] As described above, the smart pachisuro machine 100 is a gaming machine that can be connected to a specific unit (e.g., dedicated unit 350) that lends out gaming values (e.g., electronic medals), and includes control means (e.g., medal CPU 204a) for managing the number of gaming values (e.g., the number of gaming medals), which is the total number of gaming values, and display means (e.g., gaming medal number display device 114) for displaying the number of gaming values. The control means repeats the main process, and in the main process, it may execute one or more update processes (e.g., insertion process, settlement process, payout process, lending process, counting process) for updating the number of gaming values, executes timer interrupt processing at a predetermined cycle, and in the timer interrupt processing, executes a display process that at least includes a process of setting the number of gaming values to be displayed on the display means (e.g., setting the number of gaming medals to the number of medals for display).

[0105] Here, as an example of the display process, in the timer interrupt process, the case where the medal CPU 204a sets the number of gaming medals to the number of medals for display and displays the number of medals for display on the gaming medal number display device 114 has been described. However, the display process is not limited to such a case, and it suffices if the medal CPU 204a either sets the number of gaming medals to the number of medals for display or displays the number of medals for display on the gaming medal number display device 114 in at least the timer interrupt process. Also, here, as an example of the display process, in the same timer interrupt process, the case where the medal CPU 204a sets the number of gaming medals to the number of medals for display and displays the number of medals for display on the gaming medal number display device 114 has been described. However, the display process is not limited to such a case, and it is also possible that in one of two timer interrupt processes with different interrupt timings or interrupt periods, the medal CPU 204a sets the number of gaming medals to the number of medals for display, and in the other, the medal CPU 204a displays the number of medals for display on the gaming medal number display device 114.

[0106] Also, here, an example was given in which the medal CPU 204a sets the number of game medals to the number of display medals in the timer interrupt process regardless of which of the collective light emitters L1 to L5 is the display target. However, if update processes (input process, settlement process, payout process, lending process, counting process) for updating the number of game medals overlap, in a predetermined timer interrupt process, the number of game medals updated in the payout process is set to the number of display medals, and before the display of the number of display medals is completed (before the timer interrupt process ends 5 times), the number of game medals updated in the counting process may be set to the number of display medals and the display of the number of display medals may be started. Therefore, the medal CPU 204a may determine whether the number of game medals has changed in the timer interrupt process, and if the number of game medals has changed, set the number of game medals to the number of display medals and limit newly setting the number of game medals to the number of display medals until the display of the number of display medals is completed (until the timer interrupt process ends 5 times). In this way, the number of display medals can be appropriately displayed on the game medal number display device 114. Also, regardless of whether the number of game medals has changed in the timer interrupt process, when the medal CPU 204a sets the number of game medals to the number of display medals, it may limit newly setting the number of game medals to the number of display medals until the display of the number of display medals is completed (until the timer interrupt process ends 5 times).

[0107] Also, here, the medal CPU 204a has been described as an example of the control means. However, this is not limited to such a case. As shown in FIG. 10(c) described later, when the main CPU 200a controls the progress of the game and also functions as the medal CPU 204a to manage the electronic medals, the main CPU 200a can also be applied as the control means.

[0108] (Relationship between substrates) Also, here, as shown in FIG. 2, an example was given in which in the smart pachislot 100, a medal number control board 204 is provided separately from the main control board 200 and the medal number control board 204 operates independently. However, this is not limited to such a case, and the configurations of the boards and CPUs can be made different.

[0109] FIG. 10 is an explanatory diagram for explaining another substrate configuration. In the above-described embodiment, as shown in FIG. 10(a), a main CPU 200a (first control unit) for controlling the progress of the game is arranged on the main control board 200, and a medal CPU 204a (second control unit) for managing the electronic medals used in the game is arranged on the medal number control board 204. The main control board 200 and the medal number control board 204 are connected via a harness, and the medal number control board 204 and the game ball lending device connection terminal board 206 are connected via a harness. Such a game ball lending device connection terminal board 206 receives power supply (VL) from the dedicated unit 350, uses the power as an input of an insulating element such as a photocoupler, generates a VL connection signal indicating the connection state with the dedicated unit 350, and outputs it to the medal number control board 204. The medal number control board 204 can determine that power is being supplied from the dedicated unit 350, in other words, the dedicated unit 350 is powered on and is properly connected to the dedicated unit 350, based on the ON / OFF of the VL connection signal. With such a substrate configuration, it is possible to minimize the modification of the configuration of the existing main control board 200 and the increase in the occupied area, so that the design cost can be reduced.

[0110] Note that the medal number control board 204 does not necessarily have to be separate from the main control board 200, and may be integrally formed with the main control board 200 as long as its function is satisfied. Specifically, as shown in FIG. 10(b), both a main CPU 200a for controlling the progress of the game and a medal CPU 204a for managing the electronic medals used in the game may be arranged on the main control board 200, and the main control board 200 and the game ball lending device connection terminal board 206 may be connected via a harness. Here, by arranging both the main CPU 200a and the medal CPU 204a on a single main control board 200, connectors and harnesses used for information exchange between the two can be eliminated, the occupied area can be reduced, and the reliability of information transmission can be improved.

[0111] Also, in the example of FIG. 10(c), the main CPU 200a arranged on the main control board 200 manages the electronically converted medals used in the game instead of the medal CPU 204a, and the main control board 200 and the connection terminal board 206 for a game ball lending device or the like are connected via a harness. Here, on the main control board 200, since the main CPU 200a controls the progress of the game and manages the electronically converted medals, the connection line responsible for information exchange between the main CPU 200a and the medal CPU 204a becomes unnecessary, and the occupied area can be further reduced, and the reliability of information transmission can be improved.

[0112] Here, at least the main control board 200 must be enclosed in the main board case for anti-tampering. In addition, when the medal number control board 204 having a function of managing the electronically converted medals used in the game is separate, it must be enclosed in the main board case together with the main control board 200.

[0113] FIG. 11 is an explanatory diagram for explaining the enclosure mode of the case. For example, as shown in FIG. 10(a), when the main control board 200, the medal number control board 204, and the connection terminal board 206 for a game ball lending device or the like are formed separately, the main control board 200 and the medal number control board 204 are connected, and the medal number control board 204 and the connection terminal board 206 for a game ball lending device or the like are connected, as shown in FIG. 11(a), it is conceivable to enclose the main control board 200, the medal number control board 204, and the connection terminal board 206 for a game ball lending device or the like in one main board case 200e. Here, as shown in FIG. 11(a), an example is described in which the main control board 200 and the medal number control board 204 are integrally formed by directly and fixedly connecting the connectors to each other without using a harness, but the two may be connected via a harness.

[0114] Also, as shown in FIGS. 10(b) and 10(c), when the main CPU 200a and the medal CPU 204a are arranged on the main control board 200, or when the main CPU 200a is arranged alone and the main control board 200 and the lending device connection terminal board 206 for game balls or the like are connected via a harness, in a state where the main control board 200 and the lending device connection terminal board 206 for game balls or the like are connected, as shown in FIG. 11(b), the main control board 200 may be individually enclosed in the main board case 200e and the lending device connection terminal board 206 for game balls or the like may be enclosed in the connection terminal board case 206e, or as shown in FIG. 11(c), it is conceivable to enclose both the main control board 200 and the lending device connection terminal board 206 for game balls or the like in one main board case 200e.

[0115] In any case, here, the main control board 200, the medal number control board 204, and the lending device connection terminal board 206 for game balls or the like are all enclosed in a case. Also, in this case, the structure must be such that it is easy to check not only the front surface of the board but also the back surface of the board. <{

[0116] In the examples shown in FIGS. 10(a) and 10(b), in the smart pachislot 100, the main CPU 200a and the medal CPU 204a operate independently, and while the main CPU 200a controls the progress of the game, the medal CPU 204a manages the electronic medals used in the game.

[0117] FIG. 12 is an explanatory diagram for explaining a CPU and areas (used area or unused area) that execute each function of the smart pachislot 100. In FIG. 12, “◎” indicates a general execution unit in the case where functions are shared by two CPUs, namely the main CPU 200a and the medal CPU 204a, as shown in FIGS. 10(a) and 10(b). “○” indicates an executable execution unit, and “×” indicates an unexecutable execution unit. Here, the used area is an area where instruction codes and program data of a program that executes some or all of the processes for controlling the progress of the game, as shown in FIG. 7, are stored. The unused area is an area where instruction codes and program data of a program that executes some or all of the test processes for gaming machines and security-related processes, which are not defined to be stored in the used area and do not affect the progress of the game, are stored. For example, when functions are shared by two CPUs, generally, in the used area of the medal CPU 204a, it undertakes functions such as controlling the game medal number display device 114 and controlling communication with the dedicated unit 350 (indicated by “◎” in FIG. 12), but in the used area of the main CPU 200a, it is also possible to undertake some or all of them (indicated by “○” in FIG. 12).

[0118] (Communication between the smart pachislot and the dedicated unit) With the functional units as described above, the smart pachislo 100 and the dedicated unit 350 ensure their normal operations by exchanging various types of information (telegrams) via serial communication. Note that the serial communication is an asynchronous communication method with full-duplex communication control. For example, the communication speed is 62,500 bps, and each byte of data is represented by a 1-bit start bit, 8-bit data bits, and a 1-bit stop bit. At this time, the character transmission time is 0.16 msec to 3.9 msec. If the next start bit cannot be received within 3.9 msec, that character is regarded as one telegram. For example, from the smart pachislo 100 (here, for example, the medal CPU 204a on the medal number control board 204) to the dedicated unit 350, the following gaming machine information notifications, counting notifications, and lending receipt result responses are performed through such serial communication.

[0119] Figs. 13 to 16 are explanatory diagrams for explaining the format of the gaming machine information notification. As shown in Fig. 13, the gaming machine information notification transmits one of the three types of gaming machine information, namely gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information, to the dedicated unit 350, and the telegram length is variable, ranging from 18 to 57 bytes. Specifically, the first byte of the telegram of the gaming machine information notification indicates the telegram length (12h to 39h), and the second byte indicates "01h" which represents the type of command (here, the gaming machine information notification). The third byte indicates a sequence number from 00h to FFh as the sequence number. Such a sequence number notifies 00h at power-on and increments by 1 each time a notification is made. However, for the next notification after FFh, it is 01h instead of 00h.

[0120] The fourth byte indicates the type of gaming machine. Bit 7 of the gaming machine type indicates the management medium, where gaming balls are represented by "0" and gaming medals are represented by "1". Bits 6 to 4 indicate the group classification, where the Japan Industrial Workers' Federation is represented by "0" and the Japan Electrical Manufacturers' Association is represented by "1". Bits 3 to 0 indicate the type of gaming machine, where a pachinko machine is represented by "1", a rotating drum type gaming machine is represented by "2", an arranged ball gaming machine is represented by "3", and a jan-ken gaming machine is represented by "4". The fifth byte indicates the type of gaming machine information. For example, if the gaming machine information is gaming machine performance information, it is "00h"; if the gaming machine information is gaming machine installation information, it is "01h"; if the gaming machine information is hall control - illegal monitoring information, it is "02h". From the sixth byte, the gaming machine information (either gaming machine performance information, gaming machine installation information, or hall control - illegal monitoring information) is indicated in variable length.

[0121] For example, if the type of gaming machine information is "00h", the gaming machine performance information is represented by 51 bytes as gaming machine information. As shown in FIG. 14, it includes the total number of inserted medals, the total number of paid - out medals, MY (the maximum difference in the number of medals), the total number of paid - out medals for devices, the total number of consecutive paid - out medals for devices, the device ratio, the consecutive device ratio, the favorable interval ratio, the indicated - in device ratio, the device status ratio, the number of gaming sessions, reserve, reservation 1, and reservation 2. After the gaming machine performance information is transferred to the dedicated unit 350, it is further transmitted to a gaming machine information center (not shown). Here, MY indicates the difference in the number of medals, which is the difference between the number of inserted medals (number of inserted electronic medals) and the number of paid - out medals (number of paid - out medals) after the power is reset. Also, as MY, instead of or in addition to the difference in the number of medals after the power is reset, the difference in the number of medals when the lowest difference is set to 0 can also be adopted. Among such information, the byte order of the total number of inserted medals, the total number of paid - out medals, MY, the total number of paid - out medals for devices, the total number of consecutive paid - out medals for devices, and the number of gaming sessions is little - endian.

[0122] Also, if the game machine information type is "01h", the game machine installation information is represented by 40 bytes as the game machine information. As shown in FIG. 15, it includes the main control chip ID number, the main control chip manufacturer code, the main control chip product code, the medal count control chip ID number, the medal count control chip manufacturer code, and the medal count control chip product code. Here, for the main control chip ID number (9 bytes) and the medal count control chip ID number (9 bytes), the upper 4 bytes are represented by 0, the following 4 bytes are represented by the chip individual number or the chip code, and the lowermost byte is represented by the identification code (LEM50A = "21h", LES50A = "22h", LEM7OA = "23h", IDNAC8701 = "41h", IDNAC8702 = "42h", IDNAC8703 = "43h"). However, when the medal CPU 204a is not installed, all 9 bytes are represented by 0. Note that the byte order of the main control chip ID number, the main control chip manufacturer code, the main control chip product code, the medal count control chip ID number, the medal count control chip manufacturer code, and the medal count control chip product code is big-endian.

[0123] Also, if the gaming machine information type is "02h", the hall control - illegal monitoring information is represented by 12 to 16 bytes as gaming machine information. As shown in FIG. 16, it includes the number of gaming medals, the number of inserted medals, the number of paid - out medals, main control state 1, main control state 2, the gaming machine error state, gaming machine illegal 1, gaming machine illegal 2, gaming machine illegal 3, the number of gaming information, type information 1, count information 1, type information 2, and count information 2. Here, the relationship among the number of gaming medals, the number of inserted medals, and the number of paid - out medals is "the number of gaming medals" = the "number of gaming medals" transmitted last time - "the number of inserted medals" + "the number of paid - out medals" + "the number of lent medals" received after the "number of gaming medals" transmitted last time - "the number of counted medals" transmitted after the "number of gaming medals" transmitted last time. Therefore, if such a relationship is not satisfied, it can be determined that the hall control - illegal monitoring information is abnormal. Also, the signal during setting change in bit 0 of gaming machine illegal 1 indicates that the setting change process is being performed (the power is turned on with the setting key ON). The signal during setting confirmation in bit 1 of gaming machine illegal 1 indicates that the confirmation process of the set value is in progress. The illegal detection signal 1 in bit 2 of gaming machine illegal 1 indicates that a communication error has occurred in the main CPU 200a. The illegal detection signals 2 and 3 in bits 3 and 4 of gaming machine illegal 1 indicate that an arbitrarily defined illegal act has been detected. Also, the setting door open signal in bit 0 of gaming machine illegal 2 indicates that when a door is provided in the setting change device that accepts the setting change operation by the administrator in the setting change process, the door provided in the setting change device is in an open state. The door open signal in bit 1 of gaming machine illegal 2 indicates that the front lower door 106 is in an open state. Note that if no door is provided in the setting change device, the setting door open signal is not used, and a fixed value "0" is set as a reserved signal at the bit position of the setting door open signal. Also, if the illegal detection signals 2 and 3 are not used, a fixed value "0" is set as a reserved signal at such bit positions. Also, other signals of gaming machine illegal 1, gaming machine illegal 2, and gaming machine illegal 3 may be set with a fixed value "0" as a reserved signal. These signals must be continuously output for a predetermined time of not less than a lower - limit time (for example, 3 seconds) for countermeasures against cheating.Also, when an event that interrupts the output of signals, such as a power failure (power cut-off), occurs during the output of these signals, the signal timing timer that has been timing for a predetermined time may be reset, and the signal being confirmed for setting may be output again for the predetermined time. Alternatively, the value of the signal timing timer at the time of power failure may be saved, and when the power is turned on (when power failure is restored), the timing may be resumed from the saved value of the signal timing timer, and the signal being confirmed for setting may be output. In this case, the total time for which the signal being confirmed for setting is output before and after the power failure becomes the predetermined time. The game information consisting of the combination of type information 1 and count information 1 or the combination of type information 2 and count information 2 indicates either the specified number (when the start switch 118 is operated) or the number of paid-out medals (when the game ends) depending on type information 1 and 2, and the number of medals is indicated by count information 1 and 2. During replay, the specified number during re-game operation is notified. The number of game information indicates the number of game information. When the number of game information is 0, the four items of type information 1, count information 1, type information 2, and count information 2 are not transmitted.

[0124] Figure 17 is an explanatory diagram for explaining the format of the count notification. The count notification transmits the count cumulative medal number, which will be described later, to the dedicated unit 350, and the telegram length is a fixed length of 7 bytes. Specifically, the first byte of the telegram indicates the telegram length (07h), the second byte indicates "02h" indicating the type of command (here, the count notification). The third byte indicates the sequence number from 00h to FFh as the count serial number. Such a count serial number notifies 00h when the power is turned on and increments by 1 each time a notification is made. However, the next notification after FFh is 01h instead of 00h. The fourth byte indicates the number of counted medals. The number of counted medals is the number of digitized medals counted at the timing of the count notification. The fifth byte indicates the count cumulative medal number. The count cumulative medal number is the value obtained by accumulating the number of counted medals after being cleared to 0000h when the power of the smart pachislo 100 is turned on, and the value after FFFFh is 0000h. The seventh byte indicates the checksum.

[0125] FIG. 18 is an explanatory diagram for explaining the format of the lending reception result response. The lending reception result response responds with the reception result when there is a lending notice from the dedicated unit 350, and the telegram length is a fixed length of 5 bytes. Specifically, the first byte of the telegram indicates the telegram length (05h), and the second byte indicates "03h" indicating the type of command (here, the lending reception result response). The third byte indicates a sequence number from 00h to FFh as the lending serial number. Such a lending serial number notifies 00h at power-on, and if the lending medal number reception result described later is normal, it directly reflects the lending serial number received from the dedicated unit 350. If the lending medal number reception result is abnormal, it reflects the lending serial number when the lending medal number reception result was normally received from the dedicated unit 350 previously. The fourth byte indicates the lending medal number reception result (normal = 00h, abnormal = 01h). The fifth byte indicates the checksum.

[0126] In addition, the following lending notice is given from the dedicated unit 350 to the smart pachislo 100 (here, for example, the medal CPU 204a).

[0127] FIG. 19 is an explanatory diagram for explaining the format of the lending notice. The lending notice is for the dedicated unit 350 to transmit the number of lent medals to the smart pachislot 100 when receiving a counting notice from the smart pachislot 100, and the telegram length is a fixed length of 5 bytes. Specifically, the first byte of the telegram indicates the telegram length (05h), and the second byte indicates "13h" indicating the type of command (here, the lending notice). The third byte indicates a sequence number from 00h to FFh as the lending serial number. Such a lending serial number notifies 00h at power-on and increments by 1 each time a notice is sent. However, the next notice after FFh is 01h instead of 00h. The fourth byte indicates the number of lent medals. The number of lent medals indicates the number of lent electronic medals. In addition, when the gaming machine information notice has not been received, when it is notified other than the gaming machine information type "02h: Hall Control / Irregular Monitoring Information", or when the counted medal number in the counting notice is notified as "1" or more, the number of lent medals "0" is notified. The fifth byte indicates the checksum.

[0128] Note that the smart pachislot 100 can be set not to communicate with the dedicated unit 350 when a specific abnormality occurs inside. For example, as specific abnormalities, when a backup abnormality or a RAM (RWM) abnormality occurs, or when the manufacturer code does not match, the medal CPU 204a of the smart pachislot 100 issues a manufacturer code mismatch error (operation stop error) without completing its startup process and restricts the start of communication with the dedicated unit 350.

[0129] FIG. 20 is a timing chart showing the notification timings of the gaming machine information notification, the count notification, the lending notification, and the lending receipt result response. As shown in FIG. 20, the smart pachislo 100 (here, for example, the medal CPU 204a) transmits the gaming machine information notification to the dedicated unit 350 at a cycle of 300 msec (300 msec or more and 310 msec or less) from the completion of the startup of the smart pachislo 100. Also, the smart pachislo 100 transmits the count notification to the dedicated unit 350 within 100 msec (90 msec or more and 100 msec or less) from the start of the gaming machine information notification. The dedicated unit 350 transmits the lending notification to the smart pachislo 100 within 170 msec from the start of the reception of the count notification. The smart pachislo 100 notifies the dedicated unit 350 of the lending receipt result response within 10 msec after the completion of the reception of the lending notification. In this way, it is possible to secure a time of 20 msec or more from the time when the smart pachislo 100 notifies the lending receipt result response until the next gaming machine information notification is performed.

[0130] FIG. 21 is an explanatory diagram for explaining the transmission timing of the gaming machine information notification. As described above, the gaming machine information notification is notified to the dedicated unit 350 at a cycle of 300 msec. The gaming machine information notification includes three types of gaming machine information: gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information. As shown in FIG. 21, their notification timings and priorities are different. For example, the gaming machine installation information is notified 60 seconds after the start of the smart pachislo 100 is completed, and thereafter at a cycle of 60 seconds. Also, the gaming machine performance information is notified 180 seconds after the start of the smart pachislo 100 is completed, and thereafter at a cycle of 180 seconds. The hall control / fraud monitoring information is notified at a cycle of 300 msec after the start of the smart pachislo 100 is completed. However, the three notifications may overlap in their transmission timings. When the transmission timings overlap, the gaming machine information notifications are sequentially notified according to the priorities. For example, at 180 seconds, when the gaming machine performance information, the gaming machine installation information, and the hall control / fraud monitoring information overlap, if there is no update of the main control state in the hall control / fraud monitoring information and there is no gaming information, first, the gaming machine installation information with a higher priority is notified, the gaming machine performance information is notified 300 msec later, and the hall control / fraud monitoring information is notified 300 msec later. Also, at 60 seconds, when the gaming machine installation information and the hall control / fraud monitoring information overlap, if there is no update of the main control state in the hall control / fraud monitoring information and there is no gaming information, first, the gaming machine installation information with a higher priority is notified, and the hall control / fraud monitoring information is notified 300 msec later. However, if there is an update of the main control state in the hall control / fraud monitoring information or there is gaming information, first, the hall control / fraud monitoring information with a higher priority is notified, and then the gaming machine installation information and the gaming machine performance information are notified. With such a configuration, the smart pachislo 100 and the dedicated unit 350 can confirm the gaming machine information notifications (gaming machine performance information, gaming machine installation information, hall control / fraud monitoring information), the count notification, the lending notification, and the lending receipt result response with each other at appropriate timings and appropriate priorities.

[0131] (VL connection signal) As described with reference to FIG. 10, the lending device connection terminal board 206 for game balls or the like receives power supply from the dedicated unit 350, uses such power as the input of an insulating element such as a photocoupler, generates a VL connection signal indicating the connection state with the dedicated unit 350, and outputs it to the medal CPU 204a of the medal number control board 204. Note that the medal CPU 204a may or may not transmit a command indicating that it has received the VL connection signal to the main CPU 200a. When the medal CPU 204a transmits a command indicating that it has received the VL connection signal to the main CPU 200a, the main CPU 200a restricts (prohibits) the startup of only the main control board 200, only the medal number control board 204, or both the main control board 200 and the medal number control board 204, or stops the progress of the game according to whether the command indicates the reception of the VL connection signal. Also, when the medal CPU 204a does not transmit a command indicating that it has received the VL connection signal to the main CPU 200a, the medal CPU 204a can individually restrict (prohibit) the startup of the medal number control board 204 or stop the progress of the game.

[0132] Here, if the VL connection signal is ON, it can be determined that the smart pachislo 100 is properly connected to the dedicated unit 350 and the power of the dedicated unit 350 is ON, so each process targeting the main CPU 200a and the dedicated unit 350 can be performed. On the other hand, if the VL connection signal is OFF, the smart pachislo 100 determines that it is not properly connected (not connected) to the dedicated unit 350 or the power of the dedicated unit 350 is OFF, and restricts the progress of the game. Specifically, if the VL connection signal is OFF, the smart pachislo 100 executes a game stop process. In such a game stop process, the game is restricted (the bet of electronic medals, the operation of the settlement switch 121, the processes for the progress of the game based on the operation of the start switch 118, and the counting process are all restricted (prohibited)) as an error state of the main control board 200. At this time, if the VL connection signal is OFF, the main CPU 200a and the medal CPU 204a may not be started.

[0133] Here, the counting process refers to the process of transferring some or all of the electronically converted medals held in the medal holding unit to the dedicated unit 350 in response to the operation of the player's counting switch 112. Specifically, when the counting switch 112 is not accepted, when the number of game medals in the medal holding unit is 0, when the VL connection signal is OFF, and in the case of a non-countable state, "0" is set as the counted medal number (counted value number). When a short press of the counting switch 112 is accepted, "1" is set as the counted medal number. When a long press of the counting switch 112 is accepted, if the number of game medals in the medal holding unit is less than 50, all the electronically converted medals (number of game medals) are set as the counted medal number. If it is 50 or more, "50" is set as the counted medal number. Then, the counted medal number is added to the cumulative counted medal number, and the counting serial number is updated. The smart pachislo 100 executes a checksum that regards the data sequence of the counting notification telegram as a sequence of integer values to obtain the sum, and sends a counting notification to the dedicated unit 350. In parallel with this, the counted medal number is subtracted from the number of game medals held in the medal holding unit.

[0134] Here, when the counting switch 112 is operated while the game is playable, the counting process is always executed. "While the game is playable" refers to the state where the smart pachislot 100 and the dedicated unit 350 are connected and both are powered on (a state where a player can borrow electronic medals, play a game on the smart pachislot 100, and count the results of the game). Note that if the power of the smart pachislot 100 is on but the power of the dedicated unit 350 is off, or if the smart pachislot 100 and the dedicated unit 350 are not connected, the smart pachislot 100 may accept an operation of the counting switch 112 but the counted medal number may disappear. Therefore, the operation of the counting switch 112 is invalidated and that period is not included in "while the game is playable". Also, during the initialization process after power-on, during setting changes, during setting confirmation, and during an error state where a return process such as reset is required, when the smart pachislot 100 cannot proceed (play) the game as a single unit, it is not included in "while the game is playable". During such an initialization process after power-on, during setting changes, during setting confirmation, and during an error state where a return process such as reset is required, the counting process may or may not be executed.

[0135] Thus, if the VL connection signal is ON, the smart pachislot 100 proceeds with the game and accepts the counting process while the game is playable. On the other hand, if the VL connection signal is OFF, the smart pachislot 100 executes the game stop process and restricts (prohibits) all processes for game progress based on the bet of electronic medals, the operation of the settlement switch 121, the operation of the start switch 118, and the above-described counting process. This is because, as described above, when the VL connection signal is OFF, it can be determined that the smart pachislot 100 is not properly connected to the dedicated unit 350 or the power of the dedicated unit 350 is off.

[0136] As described with reference to FIG. 20, the smart pachislo 100 (for example, medal CPU 204a) transmits a count notification including information on the counted number of medals to the dedicated unit 350. Here, for example, when the smart pachislo 100 and the dedicated unit 350 are not properly connected (for example, not connected), or when the dedicated unit 350 is powered off and the dedicated unit 350 is not properly prepared to receive the count notification, if the smart pachislo 100 receives an input operation (for example, a pressing operation) of the count switch 112 and transmits the count notification to the dedicated unit 350, the counted number of medals based on the input operation may disappear. If the counted number of medals disappears, the total number of digitized medals decreases, resulting in an inconsistency in the digitized medals. In the present embodiment, an inconsistency means that due to an unintended disappearance or increase in the digitized medals, the total number of digitized medals obtained by summing the number of game medals and the number of acquired medals, which is the total number of digitized medals held by the dedicated unit 350, is different before and after the input operation of the count switch 112. For example, when the total number of game medals is counted by the count switch 112, if the number of game medals held by the smart pachislo 100 before the count is different from the number of acquired medals transferred to the dedicated unit 350 by the count, an inconsistency has occurred.

[0137] Therefore, before sending the count notification to the dedicated unit 350, the smart pachislo 100 (for example, medal CPU 204a) determines whether the dedicated unit 350 is connected by checking the ON / OFF of the VL connection signal indicating the connection state with the dedicated unit 350. When the VL connection signal is OFF, indicating that the dedicated unit 350 is not connected, the smart pachislo 100 sets the counted number of medals to "0" in order to limit the counting process itself.

[0138] When the counted medal number is set to "0", the smart pachislo 100 subtracts the counted medal number "0" from the game medal number to update the game medal number. That is, the updated game medal number does not substantially change from before the update. The smart pachislo 100 displays the updated game medal number on the game medal number display device 114. Since the game medal number does not substantially change, the display on the game medal number display device 114 also does not change.

[0139] Also, the smart pachislo 100 transmits a count notification including information on the counted medal number set to "0" to the dedicated unit 350. If the dedicated unit 350 is not connected, the dedicated unit 350 cannot properly receive the count notification, so the acquired medal number does not change. Since the acquired medal number does not change, the display on the acquired medal number display device 374 also does not change.

[0140] In this way, when the counted medal number is set to "0", neither the game medal number of the smart pachislo 100 nor the acquired medal number of the dedicated unit 350 changes, so the total number of digitized medals also does not change. Therefore, in the smart pachislo 100, the counting process is not executed, and it is possible to avoid the digitized medals disappearing in response to the input operation of the count switch 112. That is, in the smart pachislo 100, it is possible to avoid the occurrence of inconsistencies in the digitized medals.

[0141] FIG. 22 is a flowchart showing the flow of the count switch monitoring process in the medal CPU 204a. The count switch monitoring process is executed when the count switch 112 is pressed. Here, the processes related to the present embodiment will be described, and the processes not related to the present embodiment will be omitted. The numerical values of step S in such a figure are used only in the description of this figure.

[0142] As shown in FIG. 22, when the medal CPU 204a detects the pressing of the counting switch 112, specifically, when it detects the ON edge of the counting switch 112 (YES in S1), it acquires the VL connection signal and determines whether the VL connection signal is ON (S2). When the VL connection signal is ON (YES in S2), the medal CPU 204a starts the timing of the timer counter included in the smart pachislo 100 (S3). The timer counter starts timing in response to the detection of the ON edge of the counting switch 112 and times from the ON edge to the OFF edge. Next, the medal CPU 204a determines whether the OFF edge of the counting switch 112 has been detected (S4). When the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether a predetermined time (for example, 500 msec) has elapsed since the start of the timing of the timer counter (S5). When the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the process of step S4. When the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long-press flag to ON (S6) and returns to the process of step S4. The long-press flag is a flag for identifying a long press. When it is ON, it indicates a long press, and when it is OFF, it indicates not a long press (i.e., a short press).

[0143] When the OFF edge of the counting switch is detected (YES in S4), the medal CPU 204a determines whether the long-press flag is OFF (S7). When the long-press flag is OFF (YES in S7), the medal CPU 204a sets the counted medal number to "1" and proceeds to the process of step S9. The set counted medal number is stored in a predetermined register or RAM. When the long-press flag is ON (NO in S7), the medal CPU 204a proceeds to the process of step S9. In step S9, the medal CPU 204a clears (turns OFF) the long-press flag. The medal CPU 204a clears the timer counter and ends the counting switch monitoring process.

[0144] When the ON edge of the counting switch 112 is not detected (NO in S1), the counting switch monitoring process ends without performing any processing. When the VL connection signal is OFF (NO in S2), the medal CPU 204a sets the counted medal number to "0" (S11) and ends the counting switch monitoring process. Note that the counted medal number "0" is stored in a predetermined register or RAM. That is, even if the counting switch 112 is pressed, if the VL connection signal is OFF, the counted medal number is set to "0", and the operation of counting the player's electronic medals is not accepted or is invalidated even if accepted.

[0145] Figure 23 is a flowchart showing the flow of the counting process in the medal CPU 204a. The counting process is a process related to updating the count of the number of game medals, and is executed at an interrupt timing that is repeated at a predetermined period (for example, 300 ms) regardless of the pressing operation of the counting switch 112. Here, the processes related to the present embodiment will be described, and the processes not related to the present embodiment will be omitted. The numerical values of step S in such a figure are used only in the description of this figure.

[0146] As shown in Figure 23, when the interrupt timing that is repeated at a predetermined period arrives, the medal CPU 204a acquires the VL connection signal and determines whether the VL connection signal is ON (S21). When the VL connection signal is ON (YES in S21), the medal CPU 204a proceeds to the process of step S23. When the VL connection signal is OFF (NO in S21), the medal CPU 204a sets the counted medal number to "0" (S22) and proceeds to the process of step S23. Note that the counted medal number "0" is stored in a predetermined register or RAM. In step S23, the medal CPU 204a acquires the current number of game medals from the medal holding unit (S23).

[0147] Next, the medal CPU 204a determines whether the long-press flag is ON (S24). If the long-press flag is ON (YES in S24), the medal CPU 204a determines whether the number of game medals acquired in step S23 is 50 or more (S25). If the number of game medals is 50 or more (YES in S25), the medal CPU 204a sets the counted medal number to 50 (S26) and proceeds to the process of step S28. If the number of game medals is less than 50 (NO in S25), the medal CPU 204a sets the number of game medals to the counted medal number (S27) and proceeds to the process of step S28. The counted medal number set in step S26 or step S27 is stored in a predetermined register or RAM. Also, if the long-press flag is OFF (NO in S24), the process proceeds to step S28.

[0148] In step S28, the medal CPU 204a acquires the latest counted medal number stored from the register or RAM in which the counted medal number is stored (S28). For example, assume that immediately before this counting process, a counting switch monitoring process (see FIG. 22) was performed and the counted medal number was set to 1. In this case, in step S28 of the counting process (see FIG. 23), the medal CPU 204a acquires the counted medal number 1 stored in a predetermined register or RAM. Also, if the counted medal number was set to 50 in step S26 of this counting process, the medal CPU 204a acquires the counted medal number 50 stored in a predetermined register or RAM. Also, if the number of game medals less than 50 was set to the counted medal number in step S27 of this counting process, the medal CPU 204a acquires the number of game medals less than 50 stored in a predetermined register or RAM as the counted medal number. Also, if the counted medal number was set to 0 in step S11 of the counting switch monitoring process (see FIG. 22) or in step S22 of the counting process (see FIG. 23), the medal CPU 204a acquires the counted medal number 0 stored in a predetermined register or RAM.

[0149] Next, the medal CPU 204a subtracts the acquired counted medal number from the acquired number of game medals to update the number of game medals (S29). For example, when the acquired counted medal number is "1", the number of medals obtained by subtracting "1" from the currently acquired number of game medals becomes the updated (subtracted) number of game medals. Also, when the acquired counted medal number is "50", the number of medals obtained by subtracting "50" from the currently acquired number of game medals becomes the updated number of game medals. Further, when the number of game medals less than "50" is acquired as the counted medal number, all the game medals less than "50" as the counted medal number are subtracted from the currently acquired number of game medals, and the updated number of game medals becomes "0". Also, when the acquired counted medal number is "0", the number of medals obtained by subtracting "0" from the currently acquired number of game medals becomes the updated number of game medals. That is, when the counted medal number is "0", the number of game medals does not substantially change.

[0150] Next, the medal CPU 204a updates the display of the number of game medals on the game medal number display device 114 to the number of game medals derived in step S29 (S30). Next, the medal CPU 204a generates a count notification including information on the acquired counted medal number and transmits it to the dedicated unit 350 (S31). Next, the medal CPU 204a clears the counted medal number in response to the completion of the count notification (S32) and ends the counting process.

[0151] In this way, the medal CPU 204a checks the ON / OFF of the VL connection signal, and when the VL connection signal is OFF, sets the counted medal number to "0". Therefore, if the VL connection signal is OFF, even if the count switch 112 is pressed, the updated number of game medals does not substantially change from the updated number of game medals before the update. Also, if the VL connection signal is OFF, since the dedicated unit 350 cannot appropriately receive the count notification, the number of acquired medals also does not change. For this reason, even if the count notification is transmitted even though the dedicated unit 350 is not appropriately prepared to receive the count notification, in the smart pachislot 100, it is possible to avoid the disappearance and increase of the digitized medals and the occurrence of inconsistencies in the digitized medals.

[0152] Also, as shown in FIG. 22, the medal CPU 204a sets the counted medal number to "0" immediately before updating the number of game medals, that is, immediately before sending a count notification. Therefore, in the smart pachislot 100, the counted medal number can be more surely set to "0", and the occurrence of inconsistencies in the electronically converted medals can be more surely avoided.

[0153] Also, the smart pachislot 100 determines the ON / OFF of the VL connection signal in both the count switch monitoring process and the counting process. If the VL connection signal is OFF, the counted medal number is set to "0". As a result, for example, among the determination process of the VL connection signal in the count switch monitoring process and the determination process of the VL connection signal in the counting process, the counted medal number is set to "0" at the timing of the determination process of the VL connection signal that is executed first after the VL connection signal becomes OFF. Therefore, the counted medal number can be set to "0" at an early stage. Further, since the smart pachislot 100 determines the ON / OFF of the VL connection signal in both the count switch monitoring process and the counting process, there are two opportunities to determine the ON / OFF of the VL connection signal. Compared with the mode where there is one opportunity to determine the ON / OFF of the VL connection signal, the counted medal number can be more surely set to "0".

[0154] Also, in the smart pachislot 100, the medal CPU 204a performs the count switch monitoring process and the counting process. The storable capacity of the ROM or RAM (storage unit) in the medal number control board 204 is smaller than that of the main ROM 200b or the main RAM 200c (storage unit), but since the processing load is small, the free capacity is large as a result. Therefore, even if it is a program that performs the determination of the ON / OFF of the VL connection signal and the process of setting the counted medal number to "0" when the VL connection signal is OFF in both the count switch monitoring process and the counting process, it does not compress the storable capacity in the medal number control board 204.

[0155] Note that the smart pachislo 100 may determine the ON / OFF of the VL connection signal in either the counting switch monitoring process or the counting process, and may omit the determination of the ON / OFF of the VL connection signal in the other process. In this case, it is more preferable to omit the determination of the ON / OFF of the VL connection signal in the counting switch monitoring process and perform the determination of the ON / OFF of the VL connection signal in the counting process. Also, in the smart pachislo 100, the ON / OFF of the VL connection signal may be determined before the update of the number of game medals or the counting notification. If the VL connection signal is OFF, the counted medal number may be set to "0", and it is not limited to the mode of determining the ON / OFF of the VL connection signal within the counting switch monitoring process or the counting process.

[0156] Also, when the smart pachislo 100 is powered on, if the startup of the dedicated unit 350 is slower than the startup of the smart pachislo 100, the VL connection signal may be delayed in becoming ON accordingly, which may result in an error. In this case, by notifying the error, particularly by temporarily setting the output from the speaker 128 to a low level, the influence of the unintended error notification can be reduced.

[0157] Also, when the smart pachislo 100 is powered on, the main CPU 200a may wait for a predetermined standby time (for example, 10 sec) and wait for the sub CPU 202a and the medal number control board 204 to start up. Such a standby time may be a time obtained by adding a time with certainty (for example, 5 seconds) to the startup time of the CPU (for example, 0 to 100 msec).

[0158] (Counting process) As described above, the medal CPU 204a of the smart pachislo 100 performs a counting process of transferring at least a part of the digitized medals held in the medal holding unit to the dedicated unit 350 in response to the operation of the counting switch 112 by the player.

[0159] FIG. 24 is a timing chart for explaining the counting process. Here, the medal CPU 204a measures the time during which the counting switch 112 is continuously operated in order to grasp the counting mode (short press or long press) desired by the player. For example, as shown in FIG. 24(a), when a short press of the counting switch 112, that is, an operation of less than 500 msec is received (time point a), "1" is set as the counted medal number. When the 300 msec cycle (predetermined transmission cycle) by the timer interrupt shown in FIG. 20 arrives (time point b), "1" is subtracted from the number of game medals. Here, it is assumed that the number of game medals has been subtracted from "30" by "1" and has become "29". Note that such counted medal number and number of game medals are variables held in the RAM by the medal CPU 204a. Then, the smart pachislo 100 transmits a counting notification to the dedicated unit 350. When the dedicated unit 350 receives the counting notification, it adds the counted medal number (here, "1") indicated by the counting notification to the acquired medal number (for example, "0"), and displays the addition result (for example, "1") on the acquired medal number display device 374.

[0160] Also, for example, as shown in FIG. 24(b), when the player continues to operate the counting switch 112 and when the 300 msec cycle arrives (time point c), if a long press of the counting switch 112, that is, an operation continued for 500 msec or more is received, when the number of game medals in the medal holding unit is 50 or more, "50" is set as the counted medal number, and when it is less than 50, the total number is set as the counted medal number. Here, it is assumed that the number of game medals is "30", and by the long press, the total number "30" is set as the counted medal number. Accordingly, the number of game medals "30" is subtracted in full, and the number of game medals becomes "0". Then, the smart pachislo 100 transmits a counting notification to the dedicated unit 350 and clears the counted medal number (sets it to "0"). When the dedicated unit 350 receives the counting notification, it adds the counted medal number (here, "30") indicated by the counting notification to the acquired medal number (for example, "0"), and displays the addition result (for example, "30") on the acquired medal number display device 374.

[0161] Note that, as described above, when the counting switch 112 is operated while the game is playable, the counting process is always executed. Therefore, when the player operates the counting switch 112 during the progress of the game, the payout of the electronic medals in the progress of the game and the counting process may be executed continuously in a short time. For example, as shown in FIG. 24(c), when the number of game medals is "30", a small winning combination is achieved according to the progress of the game, and assuming that there is a payout of 15 electronic medals (time point d). The medal CPU 204a receives a payout end command including the payout number, adds the payout number "15" to the game medal number "30", and updates the game medal number to "45" at once. At this time, in parallel, the player continues to operate the counting switch 112, and when the 300 msec cycle arrives (time point e), if the medal CPU 204a receives a long press of the counting switch 112, that is, an operation continued for 500 msec or more, all the electronic medals (here "45") are set as the counted medal number. Along with this, the game medal number "45" is subtracted in full, and the game medal number becomes "0". Then, the smart pachislot 100 transmits a counting notification to the dedicated unit 350 and clears the counted medal number. When receiving the counting notification, the dedicated unit 350 adds the counted medal number (here "45") indicated by the counting notification to the acquired medal number (for example, "0"), and displays the addition result (for example, "45") on the acquired medal number display device 374.

[0162] Here, depending on the timing of the winning of the small winning combination and the operation of the counting switch 112, the counting process is executed immediately after the payout of the electronic medals. Therefore, the game medal number changes to "30" → "45" → "0" each time. However, if the payout process of the electronic medals and the counting process are executed continuously within the 300 msec cycle for transmitting the counting notification, only the result will be notified in the counting notification. Therefore, regardless of the transition of the game medal number from "30" → "45" → "0", the dedicated unit 350 will only display the change of the acquired medal number from "0" → "45" on the acquired medal number display device 374.

[0163] As shown in FIG. 24, regardless of the timing when the number of game medals changes, that is, the timing when the payout process or counting process of the electronic medals is executed, and without waiting for the change in the number of game medals due to the payout process of the electronic medals to be displayed on the game medal number display device 114, when the cycle for sending a counting notification arrives, if the counting switch 112 has been continuously operated for a predetermined time (for example, 500 msec) or more, a part or all (here, all "45") of the number of game medals is sent as the counted medal number to the dedicated unit 350. Therefore, even when the payout process and the counting process of the electronic medals overlap, depending on the timing, the cycle for sending a counting notification arrives. Along with a long press, the number of game medals changes from "30" to "0", and after sending "30" as the counted medal number to the dedicated unit 350, due to the payout process of the electronic medals, the number of game medals changes from "0" to "15". Again, when the cycle for sending a counting notification arrives, along with a long press, the number of game medals changes from "15" to "0", and there may be a case where "15" is sent as the counted medal number to the dedicated unit 350. Then, the display content of the acquired medal number display device 374 may change from "0" to "30" to "45", and as shown in FIG. 24(c), the display content of the acquired medal number display device 374 may also change from "0" to "45". However, since the player has already started counting the number of game medals by long-pressing the counting switch 112, it suffices to confirm that the display content of the acquired medal number display device 374, which was "0", finally becomes "45" by combining the number of game medals and the payout amount of the electronic medals. Therefore, the difference in the change pattern of the number of game medals on the acquired medal number display device 374 does not affect the progress of the game.

[0164] Here, when the medal CPU 204a arrives at a cycle for sending a count notification regardless of the timing of the change in the number of game medals, if the count switch 112 has been continuously operated for a predetermined time (for example, 500 msec) or more, a part or all of the number of game medals (here, "45") is transmitted to the dedicated unit 350. Thus, the player can quickly grasp the final number of acquired medals without having to wait for the display update of the acquired medal number display device 374, and can quickly start the next operation, so that the operability of the smart pachislo 100 can be improved.

[0165] Also, here, the medal CPU 204a always accepts the operation of the count switch 112 regardless of the number of game medals (even if the number of game medals is "0"), and measures the time during which the count switch 112 is continuously operated.

[0166] For example, if the number of game medals is "0", the counted medal number in the count notification will be "0" regardless of whether the counting process is executed. Therefore, when the number of game medals is "0", it is conceivable not to execute the counting process or not to measure the time during which the count switch 112 is continuously operated. However, as shown in Fig. 24(c), if an electronic medal payout process occurs, even if the number of game medals before the payout process is "0", the counting process can be executed for the paid-out electronic medal (number of game medals). At this time, if the time during which the count switch 112 is continuously operated is measured only after the number of game medals becomes a number other than "0" (after the payout process is completed), the counting process will be delayed accordingly, and the operability will deteriorate.

[0167] Here, since the medal CPU 204a measures the time during which the counting switch 112 is continuously operated regardless of the number of game medals, it becomes possible to surely determine a long press when the cycle for transmitting a counting notification arrives. Therefore, the player can quickly grasp the final number of acquired medals and promptly start the next operation, improving the operability of the smart pachislo 100. Also, on the program executed by the medal CPU 204a, determinations (branches) such as whether the number of game medals is "0" or not become unnecessary, reducing the processing load and the memory capacity.

[0168] Note that the cycle for transmitting a counting notification (for example, 300 msec) by the medal CPU 204a and the cycle for updating the display of the game medal number display device 114 (a predetermined display cycle by timer interrupt: for example, 1 msec) are managed independently. Therefore, depending on the time relationship between the timings of the above-described payout process and counting process of the electronic medals and the display update timing of the game medal number display device 114, the display mode of the game medal number in the game medal number display device 114 will be different.

[0169] FIG. 25 is a timing chart for explaining the display mode of the game medal number. Here, as shown in FIG. 24(c), as the game progresses, a small winning occurs, and assuming that 15 electronic medals are paid out. Also, in parallel with this, when the player continues to operate the counting switch 112 and when the 300 msec cycle arrives, if the medal CPU 204a receives a long press of the counting switch 112, that is, an operation continued for 500 msec or more, all the electronic medals (here, "45") are set as the counted medal number. Here, the number of game medals changes from "30" to "45" by the payout process of the electronic medals and from "45" to "0" by the counting process. Also, in the dedicated unit 350, the number of acquired medals changes from "0" to "45" by the counting process.

[0170] For example, as shown in Fig. 25(a), assume that the display content of the game medal number display device 114 is updated (changed) between the payout process and the counting process of the electronic medal. Then, when the cycle for updating the display of the game medal number display device 114 arrives (time point f) in response to the change in the game medal number from "30" to "45" due to the payout process of the electronic medal, the medal CPU 204a changes the display of the game medal number on the game medal number display device 114 from "30" to "45". Similarly, when the cycle for updating the display of the game medal number display device 114 arrives (time point g) in response to the change in the game medal number from "45" to "0" due to the counting process, the medal CPU 204a changes the display of the game medal number on the game medal number display device 114 from "45" to "0".

[0171] Here, after the payout process of the electronic medal is executed and after the counting process is executed, the display content of the game medal number display device 114 is updated respectively. Therefore, as the game medal number changes from "30" to "45" to "0", the display on the game medal number display device 114 will also change from "30" to "45" to "0". In this case, the player can grasp the change in the game medal number from "30" to "45" to "0" through the game medal number display device 114.

[0172] Also, for example, as shown in Fig. 25(b), assume that both the payout process and the counting process of the electronic medal are executed during the cycle for updating the display of the game medal number display device 114. Then, the medal CPU 204a changes the game medal number from "30" to "45" due to the payout process of the electronic medal and from "45" to "0" due to the counting process. However, when the cycle for updating the display of the game medal number display device 114 arrives (time point h), since the game medal number has already become "0", the medal CPU 204a directly changes the display of the game medal number on the game medal number display device 114 from "30" to "0".

[0173] Here, after both the payout process and the counting process of the electronic medals have been executed, the display content of the game medal count display device 114 is updated. Therefore, while the number of game medals once increases from "30" to "45" and then decreases to "0", the display of the game medal count display device 114 immediately decreases from "30" and changes to "0". In this case, the player can grasp that the number of game medals has changed from "30" to "0" through the game medal count display device 114.

[0174] Here, if we try to let the player grasp that the number of game medals has changed step by step, such as from "30" to "45" to "0", through the game medal count display device 114, the medal CPU 204a has to wait for the display content of the game medal count display device 114 to be updated before performing the counting process, and thus the counting process will be delayed accordingly. In addition, in order to let the player recognize the update of the display of the game medal count display device 114, it is necessary to lengthen the display time to a recognizable extent, so the counting process will be delayed accordingly and the operability will deteriorate.

[0175] Here, as shown in FIG. 25, regardless of whether the display content of the game medal number display device 114 is updated according to the change in the number of game medals, when the cycle for sending a counting notification arrives, the medal CPU 204a transmits part or all of the number of game medals (here, all "45") as the counted medal number to the dedicated unit 350. Therefore, when the number of game medals changes from "30" → "45" → "0", as shown in FIG. 25(a), the number of game medals on the game medal number display device 114 may change from "30" → "45" → "0", or as shown in FIG. 25(b), the number of game medals on the game medal number display device 114 may change from "30" → "0". However, since the player has already started counting the number of game medals by long-pressing the counting switch 112, it is only necessary to confirm that the display content of the game medal number display device 114, which was originally "30", has finally become "0". In addition, the player only needs to confirm that the display content of the acquired medal number display device 374, which was originally "0", has finally become "45" when combined with the payout of game medals and digitized medals. Therefore, the difference in the change pattern of the number of game medals on the game medal number display device 114 does not affect the progress of the game.

[0176] Here, when the medal CPU 204a transmits at least part of the number of game medals (here, "45") to the dedicated unit 350 when the cycle for sending a counting notification arrives regardless of the change timing of the number of game medals and the counting switch 112 has been continuously operated for a predetermined time (for example, 500 msec) or more, the player can quickly grasp the final number of game medals without waiting for the display update of the game medal number display device 114 and can quickly start the next operation. Therefore, it is possible to improve the operability of the smart pachislo 100.

[0177] Note that here, through FIGS. 24 and 25, an example where the payout process and counting process of digitized medals are continuously executed has been described. However, the change in the number of game medals is not limited to such processes and can target various processes such as the insertion process of digitized medals.

[0178] Incidentally, as described with reference to FIG. 20, the smart pachislo 100 (e.g., medal CPU 204a) transmits game machine information notifications to the dedicated unit 350 at a predetermined cycle (e.g., a 300 msec cycle). Further, the smart pachislo 100 transmits a count notification to the dedicated unit 350 100 msec after transmitting the game machine information notification to the dedicated unit 350. That is, the smart pachislo 100 transmits a count notification including information on the counted medal number to the dedicated unit 350 at a predetermined cycle (e.g., a 300 msec cycle), similar to the game machine information notification.

[0179] Also, the count switch 112 is an input operation unit that receives a predetermined input operation (e.g., a pressing operation) by the player. The smart pachislo 100 (e.g., medal CPU 204a) is capable of receiving a signal indicating the input operation from the count switch 112 (input operation unit). The smart pachislo 100 sets the counted medal number as described later based on the signal received from the count switch 112. The smart pachislo 100 subtracts the set counted medal number from the current game medal number at the above-described predetermined cycle (e.g., 300 msec) to update the game medal number, and updates the display of the game medal number display device 114 to the updated game medal number at any time at a cycle different from the predetermined cycle (e.g., 1 msec).

[0180] When the update of the game medal number is completed, the display content of the game medal number display device 114 is updated immediately, for example, at 1 msec, so that the display content is updated at substantially a predetermined cycle (e.g., 300 msec). From this, the smart pachislo 100 changes the display content (i.e., the game medal number displayed by the game medal number display device 114) in the game medal number display device 114 based on the signal received from the count switch 112 at substantially a predetermined cycle (e.g., 300 msec).

[0181] The smart pachislot 100 also transmits a counting notification including information on the set number of counted medals to the dedicated unit 350 at the above-mentioned predetermined cycle (for example, 300 msec). In other words, the smart pachislot 100 outputs a counting notification to the outside based on the signal received from the counting switch 112 at a predetermined cycle.

[0182] Furthermore, the dedicated unit 350 updates the number of earned medals based on the received counting notification, and updates the display of the earned medal count display device 374 to the updated number of earned medals at a cycle (e.g., 1 msec) different from the predetermined cycle. When the dedicated unit 350 completes updating the number of earned medals based on the counting notification, the display content of the earned medal count display device 374 is updated immediately, for example, in 1 msec, so that the display content is updated approximately at a predetermined cycle (e.g., 300 msec). Therefore, the dedicated unit 350 updates the display of the earned medal count display device 374 substantially at a predetermined cycle (300 msec) based on the counting notification received from the smart pachislot 100.

[0183] Here, it is possible that a player may press the counting switch 112 multiple times in rapid succession. In such a case, the smart pachislot 100 may receive (be inputted with) a signal indicating a pressing operation multiple times within one cycle (e.g., within 300 msec) of a predetermined cycle (e.g., 300 msec cycle). The smart pachislot 100 is designed to display the dedicated unit 350 appropriately even if such multiple pressing operations are performed within one cycle.

[0184] Specifically, when the smart pachislo 100 (for example, medal CPU 204a) receives signals from the counting switch 112 a plurality of times during one cycle, only one of the signals for one time among the plurality of times is made valid. More specifically, even if the smart pachislo 100 receives signals from the counting switch 112 a plurality of times during one cycle, the counted medal number corresponding to the pressing operation of the counting switch 112 is fixedly set to "1". Then, the smart pachislo 100 updates the display on the game medal number display device 114 based on the one valid signal (more specifically, based on the counted medal number "1"), and outputs a signal (for example, counting notification) to the outside.

[0185] FIG. 26 is a flowchart showing the flow of the counting switch process in the medal CPU 204a. The counting switch process is executed when the counting switch 112 is pressed. The counting switch process corresponds to the processes from step S3 to step S10 that are performed when step S1 in FIG. 22 is YES. Here, the processes related to the present embodiment will be described, and the processes not related to the present embodiment will be omitted. The numerical values of step S in such a figure are used only in the description of this figure.

[0186] As shown in FIG. 26, when the medal CPU 204a detects the pressing of the counting switch 112 (specifically, when detecting the ON edge of the counting switch 112), it starts the timing of the timing counter included in the smart pachislo 100 (S3). The medal CPU 204a determines whether the OFF edge of the counting switch 112 has been detected (S4). If the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether a predetermined time (for example, 500 msec) has elapsed since the start of the timing of the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the process of step S4. If the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long-press flag to ON (S6), and returns to the process of step S4.

[0187] When the OFF edge of the count switch is detected (YES in S4), the medal CPU 204a determines whether the long-press flag is OFF (S7). When the long-press flag is OFF (YES in S7), the medal CPU 204a sets the counted medal number to "1" and proceeds to the process of step S9. The set counted medal number is stored in a predetermined register or RAM. When the long-press flag is ON (NO in S7), the medal CPU 204a proceeds to the process of step S9. In step S9, the medal CPU 204a clears (sets to OFF) the long-press flag. The medal CPU 204a clears the timing counter and ends the count switch process. Here, in step S8, the counted medal number is not incremented by "1", but is set to "1".

[0188] FIG. 27 is a time chart for explaining the setting of the counted medal number. As shown in FIG. 27, for example, at time point a, the number of game medals is "50", and a count notification including information on the counted medal number "0" is transmitted from the smart pachislot 100 to the dedicated unit 350, and it is assumed that the number of acquired medals is "50". Then, it is assumed that the pressing operation of the count switch 112 is performed 3 times before 300 msec for one cycle elapses from time point a.

[0189] The above-described count switch process starts at the ON edge of the pressing operation of the count switch 112, and at the OFF edge in the pressing operation, if it is a short press, the counted medal number "1" is set. Each time the count switch 112 is short-pressed, the counted medal number "1" is repeatedly set. Therefore, for example, even if it is the third short press in one cycle, the counted medal number is set to "1" instead of "3".

[0190] At time point b when 300 msec for one cycle has elapsed since time point a, as described above with reference to FIG. 23, the smart pachislo 100 subtracts the set counted medal number “1” from the current number of game medals “50” to derive the number of game medals “49”. The smart pachislo 100 updates the display of the number of game medals on the game medal number display device 114 from “50” to “49”. In this way, even if the pressing operation is performed three times during one cycle, if the number immediately before the display update of the game medal number display device 114 is, for example, “50”, the display is updated to “49” instead of being updated to “47”.

[0191] Also, at time point b, the smart pachislo 100 transmits a count notification including the information of the counted medal number “1” to the dedicated unit 350. When the dedicated unit 350 receives the count notification, it adds the received counted medal number “1” to the acquired medal number “50” to derive the acquired medal number “51”. The dedicated unit 350 updates the display of the acquired medal number on the acquired medal number display device 374 from “50” to “51”. In this way, even if the pressing operation is performed three times during one cycle, if the number immediately before the display update of the acquired medal number display device 374 is, for example, “50”, the display is updated to “51” instead of being updated to “53”.

[0192] That is, the medal CPU 204a can update the display of the acquired medal number display device 374 of the dedicated unit 350 to increase by one every predetermined period (for example, 300 msec) by setting the counted medal number to “1” even if the pressing operation is performed multiple times during one cycle. For example, instead of the display content of the acquired medal number display device 374 jumping from “50” to “53”, it changes continuously by one from “50” to “51”. Therefore, in the smart pachislo 100, the acquired medal number can be appropriately displayed on the acquired medal number display device 374 of the dedicated unit 350, and it is possible to suppress giving the player a sense of distrust.

[0193] In the above-mentioned smart pachislo 100, when a signal (e.g., ON edge) of the counting switch 112 is received (input) multiple times during one cycle, only the signal for one time out of the multiple times is made valid. However, the smart pachislo 100 may process all the received signals as valid when a signal (e.g., ON edge) of the counting switch 112 is received multiple times during one cycle.

[0194] FIG. 28 is a flowchart showing the flow of the counting switch process according to a modified example in which all signals received multiple times are processed as valid. The flowchart of FIG. 28 is different from the flowchart of FIG. 26 in that step S8 of the flowchart of FIG. 26 is changed to step S18, and the other steps are the same as those of the flowchart of FIG. 26.

[0195] As shown in FIG. 28, when the long-press flag is OFF (YES in S7), the smart pachislo 100 increments the counted medal number by "1" (increments by 1 only).

[0196] FIG. 29 is a time chart for explaining the setting of the counted medal number according to a modified example in which all signals received multiple times are processed as valid. As shown in FIG. 29, it is assumed that the pressing operation of the counting switch 112 is performed 3 times until 300 msec for one cycle elapses from time point c.

[0197] The counting switch process in this modified example starts at the ON edge of the pressing operation of the counting switch 112, and at the OFF edge of the pressing operation, if it is a short press, the counted medal number is incremented by "1". Therefore, each time the counting switch 112 is short-pressed during one cycle, the counted medal number increases by "1". For example, at the second OFF edge during one cycle, the counted medal number is set to "2", and at the third OFF edge during one cycle, the counted medal number is set to "3".

[0198] At time point d when 300 msec corresponding to one cycle has elapsed since time point c, as described with reference to FIG. 23, the smart pachislo 100 subtracts the set counted medal number "3" from the current number of game medals "50" to derive the number of game medals "47". The smart pachislo 100 updates the display of the number of game medals on the game medal number display device 114 so as to decrease by "1" in order, such as "50" → "49" → "48" → "47".

[0199] Also, at time point d, since the smart pachislo 100 has been pressed three times during one cycle, it transmits a count notification including information on the counted medal number "3" to the dedicated unit 350. When receiving the count notification, the dedicated unit 350 adds the received counted medal number "3" to the acquired medal number "50" to derive the acquired medal number "53". The dedicated unit 350 updates the display of the acquired medal number on the acquired medal number display device 374 so as to increase by "1" in order, such as "50" → "51" → "52" → "53".

[0200] Thus, even in the modification example that effectively processes all of the plurality of signals, the acquired medal number can be appropriately displayed on the acquired medal number display device 374 of the dedicated unit 350.

[0201] (Counting sound) As described above, in the smart pachislo 100, when the counting switch 112 is operated and the counting process is executed, a counting sound (notifying the movement of the digitized medals) for notifying that the counting switch 112 has been operated is output from the speaker 128. Similarly, in the smart pachislo 100, when the lending switch 366 is operated and the lending process is executed, a lending sound (notifying the movement of the digitized medals) for notifying that the lending switch 366 has been operated is output from the speaker 128. Note that the lending process refers to a process of lending some or all of the digitized medals by transmitting information for lending some or all of the digitized medals from the dedicated unit 350 to the smart pachislo 100 in response to the operation of the lending switch 366 of the player. Hereinafter, the output of the counting sound and the lending sound will be described by taking the counting sound as an example.

[0202] As explained using Figure 24 etc., the medal CPU 204a sets the counted medal number to "0" when the count switch 112 is not operated, sets the counted medal number to "1" when the count switch 112 is short-pressed, and sets the counted medal number to "50" (or the entire number if the number of game medals is 50 or less) when the count switch 112 is long-pressed. Then, when the timing for sending a count notification arrives, which occurs every 300 msec, the medal CPU 204a sends a count notification including information on the set counted medal number to the dedicated unit 350.

[0203] When the medal CPU 204a transmits a counting notification including information on the counted medal number ("1," "50," or any number between "1" and "50") indicating that the counting switch 112 has been operated to the dedicated unit 350, the medal CPU 204a also transmits a signal indicating that the counting process has been performed (counting notification trigger signal) to the main control board 200 along with the transmission of the counting notification. When the main CPU 200a of the main control board 200 receives the counting notification trigger signal from the medal count control board 204, it transmits a counting sound notification to the sub-control board 202 instructing the output of a counting sound. When the sub-CPU 202a of the sub-control board 202 receives the counting sound notification through the main control board 200, it outputs the counting sound through the speaker 128. As a result, the counting sound is continuously output while the counting process is being executed in accordance with the operation of the counting switch 112.

[0204] In addition, the medal CPU 204a is not limited to transmitting the count notification trigger signal at the timing of transmitting the count notification containing information on the number of counted medals indicating that the count switch 112 has been operated. For example, the medal CPU 204a may transmit the count notification trigger signal at the timing when the number of counted medals indicating that the count switch 112 has been operated is set and then the number of game medals reflecting the set number of counted medals is displayed on the game medal number display device 114.

[0205] The smart pachislot 100 may be provided with a total of seven speakers 128, including two upper speakers, two lower speakers, two tweeters, and one bass speaker. The upper speakers are provided, for example, on the left and right sides of the symbol display window 108 on the upper front door 104. The upper speakers are installed on the back of the upper front door 104, and openings are provided in front of the upper speakers on the upper front door 104. The lower speakers are provided, for example, on the left and right sides of the lower front door 106. The lower speakers are installed on the back of the lower front door 106, and openings are provided in front of the lower speakers on the lower front door 106. For example, one tweeter is provided near the left upper speaker and one tweeter is provided near the right upper speaker. The tweeter is installed on the back of the upper front door 104, and an opening is provided in the upper front door 104 in front of the tweeter. The bass speaker is provided, for example, near the reel 110 inside the housing 102. No opening is provided in the housing 102 in front of the bass speaker. The upper and lower speakers output, for example, mid-range sounds. The tweeter outputs, for example, high-range sounds. The bass speaker is, for example, a woofer, and outputs low-range or deep-bass sounds. The counting sound can be output from any of the upper speaker, lower speaker, tweeter, and bass speaker.

[0206] Here, during a game, various sounds are output to effectively liven up the game, such as sound effects (e.g., background music), lines of characters used in the game (e.g., "Bonus confirmed"), and sound effects (SE). Hereinafter, these various sounds related to the game will be collectively referred to as game sounds. When the counting switch 112 is operated during a game, a counting sound may be output in addition to (overlap with) the above game sounds in response to the operation of the counting switch 112.

[0207] FIG. 30 is a diagram for explaining the operation when a game sound and a counting sound overlap. FIG. 30(a) shows an example of the volume when there is no overlap between the game sound and the counting sound, and only the game sound is output among the game sound and the counting sound. As shown in FIG. 30(a), the game sound can be output from each speaker at the maximum value (100%) of the volume that can be set for each speaker. Here, the larger the volume of the speaker, the larger the current flowing through the voice coil of the speaker, and the larger the current flowing through the voice coil of the speaker, the higher the temperature of the speaker. When there is no overlap between the game sound and the counting sound, as shown in FIG. 30(b), even when the game sound is output, the temperature of each speaker does not exceed the upper limit value of the allowable temperature of each speaker (hereinafter referred to as the allowable temperature upper limit value). Note that in FIG. 30(b), the temperature of an arbitrary one of the speakers is illustrated.

[0208] FIG. 30(c) shows an example of the volume when an overlap occurs between the game sound and the counting sound. FIG. 30(c) shows a case where the game sound is output at the maximum value (100%) of the volume that can be set for each speaker and the counting sound is output at the maximum value (100%) of the volume that can be set for each speaker. Thus, when the game sound and the counting sound overlap, if both the game sound and the counting sound are output at the maximum volume (the maximum value of the volume that can be set), as shown in FIG. 30(d), the temperature of each speaker may exceed the allowable temperature upper limit value of each speaker. Then, in some cases, the speaker whose temperature exceeds the allowable temperature upper limit value may be damaged. Note that in FIG. 30(d), the temperature of an arbitrary one of the speakers is illustrated.

[0209] Therefore, as shown in FIG. 30(e), when overlap occurs between the game sound and the counting sound, the volume of the game sound is decreased with respect to the maximum volume, and the volume of the counting sound is output at the maximum volume (the maximum value of the settable volume (100%)). For example, in the upper speaker, the volume of the game sound is decreased by 10% with respect to the maximum volume, and the game sound is output at 90% of the volume. In the lower speaker, the tweeter, and the woofer, the volume of the game sound is decreased by 50% with respect to the maximum volume, and the game sound is output at 50% of the volume.

[0210] Then, as shown in FIG. 30(f), even when the game sound and the counting sound are output in overlap, it is possible to suppress the temperature of each speaker from exceeding the upper limit value of the allowable temperature of each speaker. As a result, damage to the speaker can be prevented. Also, although the volume of the game sound is decreased with respect to the maximum volume, since the game sound is output, it is possible to suppress giving the player a sense of discomfort regarding the progress of the game, and the game can proceed appropriately.

[0211] Also, in the example of FIG. 30(e), the amount of decrease in the volume of the game sound output from the lower speaker, the tweeter, and the woofer is larger than the amount of decrease in the volume of the game sound output from the upper speaker. Since the upper speaker outputs the middle-range sound close to the player's ear, the player is sensitive to the sound of the upper speaker, and if the amount of decrease in the volume of the game sound output from the upper speaker is large, the player is likely to feel the decrease in volume, and the effect of the game sound may be reduced. On the other hand, since the lower speaker, the tweeter, and the woofer are relatively far from the player's ear, even if the amount of decrease in the volume of the lower speaker, the tweeter, and the woofer is increased compared to the upper speaker, the player is less likely to feel the decrease in volume, and the reduction of the effect of the game sound is suppressed. From these, by making the amount of decrease in the volume of the game sound output from the lower speaker, the tweeter, and the woofer larger than the amount of decrease in the volume of the game sound output from the upper speaker, it is possible to prevent damage to the speaker while suppressing the reduction of the effect of the game sound.

[0212] Note that, among the upper speaker, lower speaker, tweeter, and woofer, the amount of decrease in the volume of the game sound output from speakers other than the upper speaker is not limited to being greater than the amount of decrease in the volume of the game sound output from the upper speaker. For example, among a plurality of speakers arranged at a plurality of positions in the smart pachislot 100, the amount of decrease in the volume of the game sound output from speakers other than a specific speaker may be made greater than the amount of decrease in the volume of the game sound output from the specific speaker. Even in this aspect, damage to the speaker can be prevented, and the game can proceed appropriately.

[0213] Also, in all of the upper speaker, lower speaker, tweeter, and woofer, the amount of decrease in the volume of the game sound may be made the same. Even in this aspect, damage to the speaker can be prevented, and the game can proceed appropriately.

[0214] Also, in the smart pachislot 100, it is necessary to ensure that the total current value obtained by summing the currents flowing through each part of the smart pachislot 100 (hereinafter referred to as the total current value of the housing 102) does not exceed the upper limit value of the current allowed for the housing 102 (hereinafter referred to as the allowable current upper limit value). When the game sound and the counting sound are output overlappingly, in addition to the current for outputting the game sound, a current for outputting the counting sound also flows. Therefore, when the game sound and the counting sound overlap, the temperature of each speaker rises, and there is a risk that the total current value of the housing 102 will exceed the allowable current upper limit value.

[0215] As described above, when the game sound and the counting sound overlap, by reducing the volume of the game sound with respect to the maximum volume and outputting the counting sound at the maximum volume, it is also possible to suppress the total current value of the housing 102 from exceeding the allowable current upper limit value. As a result, damage to each part of the housing 102 can be prevented. Also, by reducing the volume of the game sound, the total current value of the housing 102 can be suppressed, so it is also possible to reduce the size of the power supply.

[0216] In Fig. 30(e), the volume of the upper speaker was set to 90%, and the volumes of the lower speaker, tweeter, and woofer were set to 50%. However, the numerical values of the volume of the game sound are for example only, and the volume of the game sound may be set to any numerical value in consideration of the temperature of each speaker and the total current value of the cabinet 102.

[0217] Fig. 31 is a flowchart for explaining the counting sound process executed by the effect control means 334. The numerical values of step S in such a figure are to be used only in the explanation of this figure. The counting sound process is a process of outputting a counting sound from each speaker based on the reception of a counting sound notification.

[0218] The effect control means 334 determines, for example, whether a counting sound notification has been received at a predetermined period (S1). When a counting sound notification has been received (YES in S1), the effect control means 334 sets the volume of the game sound to be decreased (S2). For example, the effect control means 334 sets the volume setting value of the track of the game sound, such as the track of the effect sound, the track of the lines, the track of the SE, etc., to a predetermined volume value smaller than the volume setting value immediately before receiving the counting sound notification (normal time). As a result, the volume of the game sound output from each speaker decreases.

[0219] After the setting for decreasing the volume of the game sound is completed, the effect control means 334 outputs a sound signal indicating the counting sound to each speaker (S3). As a result, the counting sound is output from each speaker. The effect control means 334 outputs the counting sound each time a counting sound notification is received. For example, when the counting switch 112 is being long-pressed, the counting sound is output while it is being long-pressed.

[0220] Furthermore, if the counting sound notification has not been received as a result of determining at a predetermined period whether it has been received (NO in S1), the performance control means 334 determines whether the counting sound is being output (S4). If it determines that the counting sound is being output (YES in S4), the performance control means 334 stops outputting sound signals indicating the counting sound to each speaker (S5). This stops the output of the counting sound that has been output from each speaker. For example, if the long press of the counting switch 112 is released, the output of the counting sound is stopped in response to the release of the long press.

[0221] After the counting sound stops, the performance control means 334 sets the volume of the game sound to return to the volume immediately before receiving the counting sound notification (normal volume) (S4), and ends the counting sound process. As a result, the volume of the game sound output from each speaker returns to the normal volume.

[0222] As described above, the smart pachislot 100, an example of a gaming machine connectable to a specific unit (e.g., the dedicated unit 350) that lends gaming value, includes gaming value control means (e.g., the medal count control board 204) that manages gaming value (e.g., electronic medals) and presentation control means 334 that controls presentations. The presentation control means 334 outputs game sounds corresponding to the progress of a game through an audio output unit (e.g., each speaker). The gaming value control means (e.g., the medal count control board 204) may perform a counting process to transfer the gaming value to the specific unit. In the smart pachislot 100, an example of a gaming machine, a counting sound is output to notify the user that the counting process is being performed, and the volume of the game sounds is reduced during the counting process. This allows the game to proceed appropriately and prevents damage to the speaker due to the speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0223] In addition, when the game sounds and the lending sounds overlap, the volume of the game sounds may be reduced and output from each speaker, and the lending sounds may be output from each speaker, as in the case when the game sounds and the counting sounds overlap. In this case, too, the volume of the game sounds output from speakers other than a specific speaker among the multiple speakers arranged in multiple positions on the smart pachislot 100 may be reduced by more than the volume of the game sounds output from a specific speaker, or the volume of the game sounds may be reduced by the same amount for all speakers, including the upper speaker, lower speaker, tweeter, and bass speaker. These modes also allow the game to proceed appropriately and prevent damage to the speakers due to the speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0224] In addition, the amount of reduction in the volume of the game sounds when the game sounds and counting sounds overlap may be the same as the amount of reduction in the volume of the game sounds when the game sounds and lending sounds overlap (the reduction amounts may not be different), or may be different.

[0225] For example, the amount of reduction in the volume of the game sounds when the game sounds and the lending sounds overlap (e.g., a reduction of 25%) may be less than the amount of reduction in the volume of the game sounds when the game sounds and the counting sounds overlap (e.g., a reduction of 50%). Generally, it is assumed that the lending switch 366 is operated more frequently than the counting switch 112. Therefore, by reducing the amount of reduction in the volume of the game sounds when they overlap with the lending sounds compared to the amount of reduction in the volume of the game sounds when they overlap with the counting sounds, it is possible to prevent the player from feeling uncomfortable about the progress of the game.

[0226] Also, for example, the amount of decrease in the volume of the game sound when the game sound and the counting sound overlap (e.g., a 25% decrease) may be made less than the amount of decrease in the volume of the game sound when the game sound and the lent-out sound overlap (e.g., a 50% decrease). When the counting switch 112 is operated in a state where the number of game medals is relatively large, a relatively long press operation or a relatively large number of short press operations may be performed, and it is assumed that the operation frequency of the counting switch 112 will instantaneously increase or the operation time will become longer. Therefore, by making the amount of decrease in the volume of the game sound when overlapping with the counting sound less than the amount of decrease in the volume of the game sound when overlapping with the lent-out sound, it is possible to suppress giving the player a sense of discomfort regarding the progress of the game.

[0227] Also, the counting sound and the lent-out sound may be the same sound or different sounds. Different sounds may be, for example, those with different sound types (the sounds themselves), different pitches (intervals), different lengths, different rhythms, or different phrases. When the counting sound and the lent-out sound are different sounds, for example, the counting sound may be an ascending phrase (ascending system phrase) and the lent-out sound may be a descending phrase (descending system phrase), or the counting sound may be a descending phrase (descending system phrase) and the lent-out sound may be an ascending phrase (ascending system phrase). An ascending phrase (ascending system phrase) is a group of sounds composed of multiple sounds and whose pitch increases as the sounds are emitted. A descending phrase (descending system phrase) is a group of sounds composed of multiple sounds and whose pitch decreases as the sounds are emitted.

[0228] When the lending switch 366 is operated, basically, the digitized medals are moved from the dedicated unit 350 to the smart pachislot 100 in units of 50. However, when the lending switch 366 is operated, the entire amount of the digitized medals held in the dedicated unit 350 may be moved from the dedicated unit 350 to the smart pachislot 100.

[0229] Also, when the game sound and the lending sound overlap, or even if the lending switch 366 is operated regardless of whether there is an overlap with the game sound, the lending sound may not be output from each speaker. Since the lending notification transmitted from the dedicated unit 350 to the smart pachislot 100 is performed at a cycle of 300 msec, a time lag may occur from when the lending switch 366 is operated until the smart pachislot 100 receives the lending notification. When the time lag becomes relatively long, there is a risk of giving the player a sense of discomfort regarding the lending. By not outputting the lending sound, it is possible to avoid giving the player a sense of discomfort regarding the lending. Similarly, when the game sound and the counting sound overlap, or even if the counting switch 112 is operated regardless of whether there is an overlap with the game sound, the counting sound may not be output from each speaker. By not outputting the counting sound, it is possible to avoid giving the player a sense of discomfort regarding the counting.

[0230] Also, in the smart pachislot 100, when various errors such as a door opening error occur during the progress of the game, error information is displayed on the liquid crystal display unit 124 and the main segment display unit 130 along with the occurrence of the error, and an error sound is output from the speaker 128. There may be a case where such an error sound and the counting sound overlap. Here, first, the error types that output the error sound will be described.

[0231] (Error type) FIG. 32 is an explanatory diagram for explaining errors managed by the main control board 200. As shown in FIG. 32, a "backup error" represented by error code "E7" occurs when backup of the main RAM (RWM) 200c of the main control board 200 fails, and can be recovered by executing a setting change. A "door open error" represented by error code "E8" occurs when at least one of the front upper door 104 or the front lower door 106 is detected to be open, and is automatically recovered by closing both the front upper door 104 and the front lower door 106. A "RWM error" represented by error code "EA" occurs when reading and writing to the main RAM (RWM) 200c of the main control board 200 cannot be performed normally, and can be recovered by executing a setting change. A "setting value error" represented by error code "EC" occurs when an abnormal setting value is displayed, and can be recovered by executing a setting change. The "medal over error," represented by the error code "EH," occurs when the number of game medals exceeds, for example, 16,369. It automatically recovers when the counting process reduces the number of game medals to less than 16,369. The "dispensing device connection error," represented by the error code "EL," occurs when the dedicated unit 350 jig is not connected. It automatically recovers when the jig is connected. The "medal count control error," represented by the error code "EP," occurs when an abnormality occurs in communication with the medal count control board 204. It can be recovered by turning the power back on. The "play limit error," represented by the error code "Ey," occurs when the difference number counter exceeds a specified difference number, for example, 19,000, and can be recovered by changing the settings. Note that the specified difference number is not limited to 19,000 and can be set to various values. Such error codes are displayed on the main segment display unit 130. The main segment display unit 130 normally displays nothing (the segment LEDs are off). Only when an error such as the one described above occurs, does the error code continue to be displayed until the error is resolved.

[0232] When an error such as the one described above occurs, the performance control means 334 can display error information such as "Please call an attendant" on the liquid crystal display unit 124, or can output a warning sound and a voice such as "Please call an attendant" from the speaker 128. For example, in the case of a "stop error" represented by the error code "Ey," it is possible to display a message such as "Complete function in operation" on the liquid crystal display unit 124, but not output an error sound.

[0233] Figure 33 is an explanatory diagram for explaining errors managed by the medal count control board 204. The error code of such an error is displayed on the medal segment display unit 204d arranged on the medal count control board 204. The medal segment display unit 204d is composed of one seven-segment display.

[0234] As shown in FIG. 33, a "backup error 2" represented by error code "7" occurs when the backup of the medal RAM (RWM) 204c of the medal count control board 204 fails. This error can be resolved by turning the power back on while pressing an error release switch (not shown) on the medal count control board 204. An "RWM error 2" represented by error code "A" occurs when the medal RAM (RWM) 204c of the medal count control board 204 cannot be read or written normally. This error can be resolved by changing the settings. An "lending device connection error 2" represented by error code "L" occurs when the dedicated unit 350 jig is not connected. This error is automatically resolved by connecting the jig. A "main control communication error" represented by error code "P" occurs when an abnormality occurs in communication with the main control board 200. This error can be resolved by turning the power back on. An "manufacturer code error" represented by error code "U" occurs when the manufacturer codes of the medal count control board 204 and the main control board 200 do not match. This error can be resolved by replacing either board to match the manufacturer codes. The error code ".", i.e., the "medal count clear notification" represented by the seven-segment dot, occurs when the power is turned on while pressing the medal count clear button (not shown) and the medal count is cleared, and automatically returns to normal five seconds after transitioning to a medal insertion ready state. Note that the "medal count clear notification" occurs even if this process is performed when the medal count is 0. The error code "all flashing," i.e., "preparing to start" where all seven-segment LEDs are flashing, occurs while waiting for communication with the main control board 200 to begin, and automatically returns to normal when a startup command is received from the main control board 200. Note that if the "preparing to start" state continues, it can be determined that some kind of error has occurred in the main control board 200.

[0235] Here, the main CPU 200a monitors errors in the medal count control board 204 in addition to errors in the main control board 200. On the other hand, the medal CPU 204a monitors errors in the medal count control board 204, but does not monitor errors in the main control board 200.

[0236] In addition, the errors managed by the main control board 200 shown in FIG. 32 and the errors managed by the medal number control board 204 shown in FIG. 33 have the following relationship. For example, when a "lending device connection error 2" represented by the error code "L" occurs in the medal number control board 204, the main CPU 200a of the main control board 200 issues a "lending device connection error" represented by the error code "EL" in the main control board 200 in response to such a "lending device connection error 2". Therefore, the "lending device connection error 2" and the "lending device connection error" can be considered the same error. Also, when communication cannot be established between the main CPU 200a and the medal CPU 204a, or when the established communication is disconnected, the main CPU 200a issues a "medal number control error" represented by the error code "EP" in the main control board 200, and the medal CPU 204a issues a "main control communication error" represented by the error code "P" in the medal number control board 204. Therefore, the "lending device connection error" and the "medal number control error" of the main control board 200 occur at the same timing as the "lending device connection error 2" and the "main control communication error" of the medal number control board 204, respectively.

[0237] During the occurrence of the above-described errors, the progress of the game is restricted. For example, while a door opening error occurs, the player cannot progress the game. However, even when an error occurs, the above-described lending process and counting process may be executable in some cases.

[0238] For example, when an error occurs such as "Backup Error 2" (a game value control event) represented by error code "7", "RWM Error 2" (a game value control event) represented by error code "A", "Lending Device Connection Error 2" (a game value control event) represented by error code "L", "Manufacturer Code Error" (a game value control event) represented by error code "U", or "Startup Preparation in Progress" (a game value control event) represented by error code "All Lights Flashing", as shown in FIG. 33, both the lending process and the counting process are restricted. However, for "Game Medal Count Clear Notification" represented by error code ".", since it has no relation to the lending process or the counting process, the lending process and the counting process are possible. Also, for "Main Control Communication Error" represented by error code "P", the lending process and the counting process are both restricted only while "Lending Device Connection Error 2" represented by error code "L" occurs, and if "Lending Device Connection Error 2" represented by error code "L" does not occur, the lending process and the counting process are possible. Here, as game value control events, mainly errors managed by the medal count control board 204 have been described as examples. However, it is not limited to such cases, and any error indicating that it has become difficult to transfer (lend, count) electronic medals between the medal count control board 204 and the dedicated unit 350 is acceptable.

[0239] Also, when an error (main control event) managed by the main control board 200 occurs alone on the main control board 200 while no error occurs on the medal count control board 204, lending processing and counting processing can be performed. Therefore, even if a "door open error" represented by the error code "E8" occurs, it does not affect the medal count control board 204, so lending processing and counting processing are possible. Also, even if a "stop error" represented by the error code "Ey" occurs, lending processing and counting processing are possible. Thus, a player can perform counting processing to make the number of game medals less than 16369 and can voluntarily cancel the "stop error". Here, errors managed by the main control board 200 are described as main control events. However, this is not limited to such cases, and any other error that occurs in a state where the transfer (lending processing, counting processing) of electronic medals is possible between the medal count control board 204 and the dedicated unit 350 may be used.

[0240] As described above, in the smart pachislot 100 that can be connected to a specific unit (for example, the dedicated unit 350) that lends out game values, a game value number holding unit that holds the number of game values (for example, the number of game medals), which is the total number of game values (for example, electronic medals) that can be used in the game, and a control unit that manages the game values (for example, the medal CPU 204a, the main CPU 200a) are provided. The control unit may execute lending processing to move game values from the specific unit to the smart pachislot 100, and may execute counting processing to move game values from the smart pachislot 100 to the specific unit. When a main control event (for example, "door open error", "stop error") and a game value control event different from the main control event (for example, "backup error 2", "lending device connection error 2") occur, the progress of the game is restricted (for example, the progress of the game is stopped). When a main control event occurs, at least one of lending processing and counting processing can be executed. When a game value control event occurs, both lending processing and counting processing are restricted. Thereby, even when an error occurs, lending processing and counting processing can be appropriately controlled.

[0241] Here, when an error sound is output in response to the occurrence of an error such as the above, the error sound and the counting sound may overlap. When the error sound and the counting sound overlap, both the error sound and the counting sound may be output from each speaker without lowering the volume of the error sound. Similarly, when the error sound and the lending sound overlap, both the error sound and the counting sound may be output from each speaker without lowering the volume of the error sound. Because the error sound has a higher priority than the game sound, outputting the error sound without lowering the volume of the error sound makes it easier for hall staff and others to recognize that an error has occurred.

[0242] Furthermore, when the error sound and the counting sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the counting sound may be output from each speaker by reducing the volume of the counting sound, or the counting sound may not be output from each speaker. Similarly, when the error sound and the rental sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the rental sound may be output from each speaker by reducing the volume of the rental sound, or the rental sound may not be output from each speaker. According to this embodiment, it is possible to easily make the hall staff or the like aware that an error has occurred while preventing the temperature of each speaker or the total current value of the housing 102 from exceeding the upper limit value.

[0243] Here, the main CPU 200a manages whether or not the difference in the number of inserted electronic medals (betting number) and the number of paid-out medals since the power supply is reset reaches a first specified difference number (specified value). When the first specified difference number is reached, the so-called complete function that restricts the progress of the game may be activated. When such a complete function is activated, the effect control means 334 displays complete operation information for notifying that the complete function is activated on the liquid crystal display unit 124, and outputs a complete operation sound for notifying that the complete function is activated from each speaker. Further, the main CPU 200a manages whether or not the difference number reaches a second specified difference number that is a predetermined difference number less than the first specified difference number at which the complete function is activated. When the second specified difference number is reached, it may be configured to suggest that the activation of the complete function is approaching (there is a possibility of reaching the first specified difference number). The effect control means 334 may output a complete operation suggestion sound for suggesting that the activation of the complete function is approaching from each speaker. Hereinafter, the complete operation sound and the complete operation suggestion sound are collectively referred to as the complete function sound.

[0244] When the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the counting sound may be output from each speaker. Similarly, when the complete function sound and the lending sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the lending sound may be output from each speaker. Since the complete function sound has a higher priority than the game sound, by outputting the complete function sound without reducing the complete function sound, it is possible to make it easier for the player or the like to recognize that the activation of the complete function is approaching or that the complete function is activated.

[0245] Furthermore, when the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the counting sound may be output from each speaker by reducing the volume of the counting sound, or the counting sound may not be output from each speaker. Similarly, when the complete function sound and the lending sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the lending sound may be output from each speaker by reducing the volume of the lending sound, or the lending sound may not be output from each speaker. This embodiment makes it possible to easily notify a player that the complete function is approaching activation or that the complete function has been activated, while preventing the temperature of each speaker or the total current value of the cabinet 102 from exceeding an upper limit.

[0246] Furthermore, when the completion function sound and the counting sound overlap, the volume of the completion function sound may be lowered and the completion function sound may be output from each speaker, or the completion function sound may not be output from each speaker and the counting sound may be output from each speaker. Similarly, when the completion function sound and the lending sound overlap, the volume of the completion function sound may be lowered and the completion function sound may be output from each speaker, or the completion function sound may not be output from each speaker and the lending sound may be output from each speaker. This embodiment makes it possible to make the counting sound or the lending sound more easily noticeable to players and the like while preventing the temperature of each speaker and the total current value of the cabinet 102 from exceeding their upper limits.

[0247] Furthermore, when the game sounds and the complete function sound overlap, the volume of the game sounds may be lowered and output from each speaker, and the complete function sound may be output from each speaker. This embodiment makes it possible to appropriately progress or limit the game, and also prevents damage to the speakers due to their temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0248] Also, when the game sound and the complete function sound overlap, the game sound may be output from each speaker without reducing the volume of the game sound, and the complete function sound may be output from each speaker. According to this aspect, it becomes possible to appropriately progress or limit the game.

[0249] Also, when the game sound and the complete function sound overlap, the game sound may be output from each speaker without reducing the volume of the game sound, the volume of the complete function sound may be reduced and the complete function sound may be output from each speaker, or the complete function sound may not be output from each speaker. According to this aspect, it becomes possible to appropriately progress or limit the game, and it is possible to prevent damage to the speaker due to the temperature of the speaker and damage to the housing 102 due to the total current value of the housing 102.

[0250] The medal CPU 204a manages whether the number of game medals (the number of held game values) has become less than a predetermined number, and when the number of game medals has become less than the predetermined number, it may notify that the number of game medals has decreased. In this case, the effect control means 334 performs a possession number warning notification for notifying that the number of game medals has decreased. Specifically, the effect control means 334 displays possession number warning information on the liquid crystal display unit 124 and outputs a possession number warning sound from each speaker.

[0251] When the counting sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker without reducing the volume of the possession number warning sound, and the counting sound may be output from each speaker. Similarly, when the lending sound and the possession number warning sound overlap, the possession number warning sound may be output from each speaker without reducing the volume of the possession number warning sound, and the lending sound may be output from each speaker. According to this aspect, it is possible to make it easier for the player to recognize the possession number warning sound and the counting sound, or the possession number warning sound and the lending sound.

[0252] When the counting sound and the holding number warning sound overlap, the volume of the holding number warning sound may be decreased and the holding number warning sound may be output from each speaker, or the holding number warning sound may not be output from each speaker, and the counting sound may be output from each speaker. Similarly, when the lending sound and the holding number warning sound overlap, the volume of the holding number warning sound may be decreased and the holding number warning sound may be output from each speaker, or the holding number warning sound may not be output from each speaker, and the lending sound may be output from each speaker. According to this aspect, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value, the counting sound or the lending sound can be made easily recognizable to the player.

[0253] When the counting sound and the holding number warning sound overlap, the holding number warning sound may be output from each speaker, the volume of the counting sound may be decreased and the counting sound may be output from each speaker, or the counting sound may not be output from each speaker. Similarly, when the lending sound and the holding number warning sound overlap, the holding number warning sound may be output from each speaker, the volume of the lending sound may be decreased and the lending sound may be output from each speaker, or the lending sound may not be output from each speaker. According to this aspect, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value, the holding number warning sound can be made easily recognizable to the player.

[0254] When the error sound and the holding number warning sound overlap, the error sound may be output from each speaker without decreasing the volume of the error sound, and the holding number warning sound may be output to each speaker without decreasing the volume of the holding number warning sound. According to this aspect, both the error sound and the holding number warning sound can be made easily recognizable to the player or the like.

[0255] When the error sound and the holding quantity warning sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, and the volume of the holding quantity warning sound may be reduced and the holding quantity warning sound may be output to each speaker, or the holding quantity warning sound may not be output from each speaker. Depending on the content of the error, the error sound may have a higher priority than the holding quantity warning sound. In such a case, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value, the error sound with a higher priority can be made easier for a player or the like to recognize.

[0256] When the error sound and the holding quantity warning sound overlap, the holding quantity warning sound may be output to each speaker without reducing the volume of the holding quantity warning sound, and the volume of the error sound may be reduced and the error sound may be output from each speaker, or the error sound may not be output from each speaker. Depending on the content of the error, the holding quantity warning sound may have a higher priority than the error sound. In such a case, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value, the holding quantity warning sound with a higher priority can be made easier for a player or the like to recognize.

[0257] When the complete function sound and the holding quantity warning sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the holding quantity warning sound may be output to each speaker without reducing the volume of the holding quantity warning sound. According to this aspect, both the complete function sound and the holding quantity warning sound can be made easier for a player or the like to recognize.

[0258] When the complete function sound and the holding quantity warning sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the volume of the holding quantity warning sound may be reduced and the holding quantity warning sound may be output from each speaker, or the holding quantity warning sound may not be output from each speaker. According to this aspect, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value, the complete function sound can be made easier for a player or the like to recognize.

[0259] When the complete function sound and the holding number warning sound overlap, the volume of the complete function sound may be decreased and the complete function sound may be output from each speaker, or the complete function sound may not be output from each speaker, and the holding number warning sound may be output from each speaker without decreasing the volume of the holding number warning sound. According to this aspect, it is possible to make it easier for a player or the like to recognize the holding number warning sound while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit value.

[0260] (Volume of the counting sound) As described above, the game state includes a bonus game state. The bonus game state is a favorable state that is more favorable to the player than other game states. In addition, the effect state includes an AT effect state. The AT effect state is a favorable state that is more favorable to the player than other effect states. Note that the favorable state is not limited to the bonus game state and the AT effect state, and may be any state favorable to the player, such as an RT game state in which the winning probability of a replay combination is set high, an ART game state in which the AT effect state and the RT game state are advanced simultaneously, a chance zone (CZ), etc.

[0261] The effect control means 334 outputs various sounds such as game sounds according to the progress of the game. In this way, the effect control means 334 also functions as a sound control means for controlling the output of sounds according to the progress of the game.

[0262] When it is a favorable state that is favorable to the player, the effect control means 334 (sound control means) outputs a predetermined sound such as BGM and character voices at a first volume through a voice output unit such as a speaker. Here, the predetermined sound includes system sounds according to operations of the bet switch 116, the start switch 118, the stop switch 120, etc. The first volume indicates a normal volume without any restrictions. Also, the first volume can be adjusted through the menu screen in the smart pachislo 100.

[0263] Here, when in an advantageous state, if an operation during game progress is not performed for a predetermined time (if the time when the operation during game progress is not performed continues for a predetermined time or longer), the smart pachislot 100 as a gaming machine may enter a volume adjustment state. The volume adjustment state indicates a state where the volume of a predetermined sound is restricted to a second volume that is smaller than a first volume. The second volume may include volume zero, that is, muting. In the case of muting, the predetermined sound is not output from the sound output unit.

[0264] As described above, the medal number control board 204 is gaming value control means for managing gaming values (for example, electronic medals). The medal number control board 204 may perform a counting process for transferring gaming values to a specific unit (for example, the dedicated unit 350). Further, the medal number control board 204 may perform a lending process in which gaming values are transferred from a specific unit (for example, the dedicated unit 350). Since the counting process and the lending process can be performed at arbitrary timings as described above, for example, they may be performed during an advantageous state, and further, they may also be performed during the above-described volume adjustment state during an advantageous state.

[0265] When in an advantageous state, the effect control means 334 outputs a counting sound for notifying that the counting process is being performed at a third volume through the sound output unit in response to the execution of the counting process. The third volume has no relation to the first volume and the second volume of the above-described predetermined sound. However, the third volume may be larger than the first volume, may be the same volume as the first volume, or may be larger than the second volume although it is less than the first volume. Note that the counting sound, the lending sound, and the settlement sound are included in the transfer sound for transferring electronic medals and are distinguished from the game sounds.

[0266] As described above, when shifting to the volume adjustment state when in an advantageous state, the effect control means 334 restricts the volume of the predetermined sound from the first volume to the second volume. However, even if the effect control means 334 shifts to the volume adjustment state when in an advantageous state, the counting sound is output at the third volume. That is, the volume of the counting sound is not restricted.

[0267] The medal CPU 204a transmits a counting notification in accordance with the player's operation of the counting switch 112, and transmits a signal indicating that the counting process has been performed (counting notification trigger signal) to the main control board 200. Upon receiving the counting notification trigger signal, the main CPU 200a transmits a counting sound notification instructing the output of a counting sound to the sub-control board 202. The sub-CPU 202a can receive the counting sound notification through the main control board 200. Upon receiving the counting sound notification, the performance control means 334 outputs the counting sound at a third volume through the audio output unit.

[0268] As described above, different tracks are assigned to different types of game sounds, such as tracks for performance sounds, character voices, and sound effects (SE). Furthermore, counting sounds and lending sounds are assigned transfer sound tracks separate from the game sound tracks. The counting sounds and lending sounds may be assigned the same track or different tracks. The settlement sound that notifies the user that a settlement process is being performed in response to the operation of the settlement switch 121 may also be assigned a track different from the game sounds.

[0269] When the performance control means 334 transitions to the volume adjustment state, it limits the volume of the predetermined sound track (tracks other than the counting sound track) from the first volume to the second volume. At this time, the volume of the counting sound track is maintained at the third volume. Because the volume of the counting sound track is maintained at the third volume, the performance control means 334 can output the counting sound at the third volume even if a counting process is performed in the volume adjustment state.

[0270] This makes it easier for players and parlor staff to recognize that counting processing is taking place in the smart pachislot 100, which is an example of a gaming machine, and allows the game to proceed appropriately.

[0271] Further, when in the advantageous state, in response to the execution of the lending process, the presentation control means 334 outputs a lending sound for notifying that the lending process is being performed through the voice output unit at the third volume. Even if the presentation control means 334 shifts to the volume adjustment state when in the advantageous state, the lending sound is output at the third volume. That is, the volume of the lending sound is not restricted.

[0272] In response to receiving a lending notification transmitted from the dedicated unit 350, the medal CPU 204a transmits a signal (lending notification trigger signal) indicating that the lending process has been performed to the main control board 200. When the main CPU 200a receives the lending notification trigger signal from the medal number control board 204, it transmits a lending sound notification for instructing the output of the lending sound to the sub-control board 202. The sub CPU 202a can receive the lending sound notification through the main control board 200. When the presentation control means 334 receives the lending sound notification, it outputs the lending sound through the voice output unit at the third volume.

[0273] When the presentation control means 334 shifts to the volume adjustment state, it restricts the volume of a track of a predetermined sound (a track other than the counting sound track) from the first volume to the second volume. At this time, the volume of the track of the lending sound is maintained at the third volume. Since the volume of the track of the lending sound is maintained at the third volume, even if the lending process is performed in the volume adjustment state, the presentation control means 334 can output the lending sound at the third volume.

[0274] As a result, in the smart pachislo 100 which is an example of a gaming machine, it becomes easier for the player, the hall staff, etc. to recognize that the lending process is being performed, and the game can proceed appropriately.

[0275] FIG. 34 is a flowchart for explaining the flow of the volume control process executed by the presentation control means 334. The numerical values of step S in such a figure are used only in the explanation of this figure. The volume control process is a process for controlling the volume of the sound output from the voice output unit. In FIG. 34, for the sake of convenience of explanation, the counting sound is described, and the explanation of the lending sound is omitted because it is the same as the explanation of the counting sound.

[0276] The performance control means 334 determines whether it is in a favorable state at a predetermined period (S1). If it is not in a favorable state (NO in S1), the performance control means 334 ends the volume control process.

[0277] If it is in a favorable state (YES in S1), the performance control means 334 determines whether the time during which no operation in the game progress has been performed has elapsed for a predetermined time (S2). If the predetermined time has not elapsed (NO in S2), the performance control means 334 sets the volume of the predetermined sound to the first volume (S3). Then, the performance control means 334 outputs a sound signal indicating the predetermined sound to the audio output unit (S4). Thereby, the predetermined sound is output from the audio output unit at the first volume.

[0278] If the predetermined time has elapsed (YES in S2), the performance control means 334 restricts the volume of the predetermined sound to the second volume (S5), and enters the volume adjustment state. Then, the performance control means 334 outputs a sound signal indicating the predetermined sound to the audio output unit (S4). Thereby, the predetermined sound is output from the audio output unit at the second volume.

[0279] After outputting the sound signal of the predetermined sound, the performance control means 334 determines whether it has received a counting sound notification (S10). If it has received a counting sound notification (YES in S10), the performance control means 334 outputs the sound signal of the counting sound to the audio output unit for a predetermined time (S11), and ends the volume control process. Thereby, regardless of whether it is in the volume adjustment state or not, the counting sound is output from the audio output unit at the third volume.

[0280] If it has not received a counting sound notification (NO in S10), the performance control means 334 determines whether it is outputting the counting sound (S13). If it determines that it is not outputting the counting sound (NO in S12), the performance control means 334 ends the volume control process.

[0281] When it is determined that a counting sound is being output (YES in S12), the effect control means 334 stops outputting a sound signal indicating the counting sound from the voice output unit (S13), and ends the volume control process. As a result, the output of the counting sound being output from the voice output unit stops. For example, when the long press of the counting switch 112 is released, the output of the counting sound stops in response to the release of the long press.

[0282] In this way, with a configuration that maintains the third volume without restricting the volume for the counting process and the lending process, it becomes easier for players, hall staff, etc. to recognize that the counting process and the lending process are being performed, and the game can proceed appropriately.

[0283] (Communication between the main CPU and the medal CPU) In the above, the communication between the smart pachislo 100 and the dedicated unit 350 was described. However, specifically, in parallel with the serial communication between the medal CPU 204a and the dedicated unit 350 described above, inside the smart pachislo 100, the main CPU 200a and the medal CPU 204a are in serial communication, and the medal CPU 204a acquires information by transmitting and receiving commands with the main CPU 200a, and based on that information, notifies the dedicated unit 350 described above of the information. Note that the serial communication has, for example, a communication speed of 125000 bps, and each byte of data is represented by a 1-bit start bit, 8-bit data bits, and a 1-bit stop bit. Here, the relationship between the main CPU 200a and the medal CPU 204a, which is the stage before the notification from the medal CPU 204a to the dedicated unit 350, is explained, and the communication between the two is described in detail.

[0284] (Contents held in the RAM) Here, with reference to FIGS. 10(a) and 10(b), an example was described in which the main CPU 200a and the medal CPU 204a are provided separately, each CPU has its own ROM and RAM, and processing is performed based on independent programs. However, for example, information such as the total number of inserted medals, the total number of paid-out medals, MY (maximum MY), the total number of paid-out service items, the total number of consecutive paid-out service items, and the number of game plays is information that is commonly accumulated when the power is turned on and maintained until reset when the power is restored after a power failure. Here, if the main CPU 200a manages some of the information and the medal CPU 204a independently manages other information, the following problems occur. That is, if the power of either the main CPU 200a or the medal CPU 204a is turned off and the other's power remains on, for example, the total number of inserted medals and the total number of paid-out medals may be counted from a reset state, while the total number of paid-out service items and the total number of consecutive paid-out service items may be counted in an accumulated state without being reset. Therefore, information involving accumulation such as the total number of inserted medals, the total number of paid-out medals, MY (maximum MY), the total number of paid-out service items, the total number of consecutive paid-out service items, and the number of game plays shall be managed by one CPU. For example, here, the main CPU 200a manages all such information. With such a configuration, information inconsistency can be avoided, and the game can be appropriately advanced.

[0285] (Priority of error) When betting on electronic medals, during payout processing, settlement processing, and counting processing, the main CPU 200a refers to the number of inserted electronic medals, the number of paid-out medals, the total number of inserted medals, the total number of paid-out medals, etc., and checks that there is no inconsistency in the relationship. If there is an inconsistency, an error may be notified. Also, the main CPU 200a may check that the number of inserted medals is 1 or more and 3 or less when betting on electronic medals, and that the number of paid-out medals is 0 or more and 15 or less during the payout processing of electronic medals, and if it is not within that range, an error may be notified. Such processing may be performed in the used area or in the unused area. In addition to the above, the main CPU 200a may also check the specified number corresponding to the game state.

[0286] Here, it is assumed that the medal CPU 204a is configured to perform its own error determination process in addition to errors in the main CPU 200a. In such a configuration, if errors occur simultaneously in the main CPU 200a and the medal CPU 204a, the error occurring in the main CPU 200a may be given priority and reported via a device such as the speaker 128. It is also possible to set specific errors that may occur simultaneously in the main CPU 200a and the medal CPU 204a (for example, errors determined to be serious problems, such as backup errors or errors indicating abnormal RAM read / write operations), and to report the specific errors via a device if errors occur simultaneously in the main CPU 200a and the medal CPU 204a. Furthermore, if multiple errors occur simultaneously in the medal CPU 204a, the most recently occurring error may be given priority and reported via a device such as the game medal count display device 114. Furthermore, it is also possible to set priorities for multiple errors in advance, and if multiple errors occur simultaneously in the medal CPU 204a, to report the errors based on the set priorities. By predetermining the priority of error notification in this way, it becomes possible to respond quickly and effectively according to the urgency and priority of the error. For example, if multiple errors occur, the error with the highest priority, error 1, is notified. Here, when the cause of the error is removed and an error release operation is performed, error notification 1 at that time is erased, and the error with the next highest priority is sequentially notified. In other words, error notification 1 is erased in response to the release operation of error 1. Furthermore, in addition to the case where error notification 1 is erased in response to the release operation of error 1, it is also possible to control multiple error notifications whose causes have been removed to be erased simultaneously in response to the release operation of error 1. In this case, when an error release operation is performed, multiple error notifications whose causes have been removed are erased, and the error with the highest priority among the errors whose causes have not been removed is notified.In addition, in the medal number control board 204, individual devices such as 7-segment displays are separately installed. When an error occurs in the medal CPU 204a, it may be notified by the individual device instead of, or in addition to, the game medal number display device 114.

[0287] (RAM abnormality) Also, for the processing of RAM abnormalities among the errors, in the main CPU 200a, it is assumed to be performed in the unused area, and in the medal CPU 204a, it is assumed to be performed in the used area. This is because there is no room in the capacity of the used area in the main CPU 200a, while there is room in the capacity of the used area in the medal CPU 204a. With such a configuration, it is possible to appropriately progress the game while suppressing an increase in the memory capacity in the main ROM 200b.

[0288] (Command transmission / reception) The main CPU 200a transmits a predetermined command to the medal CPU 204a. For example, when the bet switch 116 is operated, the main CPU 200a may transmit a game medal insertion command composed of identification information, transmission information indicating the required number of inserted medals, and a checksum to the medal CPU 204a. Also, when the start switch is operated, the main CPU 200a may transmit a start lever press command composed of identification information, transmission information indicating the required number of inserted medals, and a checksum to the medal CPU 204a. Also, when the payout ends, the main CPU 200a may transmit a payout end command composed of identification information, transmission information indicating the number of paid-out medals, and a checksum to the medal CPU 204a. Also, when one game ends, the main CPU 200a may transmit a one-game end command composed of identification information, transmission information related to the winning ratio, and a checksum to the medal CPU 204a. Also, when starting up, the main CPU 200a may transmit a startup command composed of identification information, transmission information required at startup, transmission information related to the winning ratio, and a checksum to the medal CPU 204a. Also, when the internal state changes, an error occurs, or an error is cleared, the main CPU 200a may transmit a state transition command composed of identification information and a checksum to the medal CPU 204a. The length of the above-described commands can be arbitrarily set. Note that the main CPU 200a calculates transmission information related to the winning ratio (information related to the use of electronic medals (game values) and information related to the acquisition of electronic medals (game values)), that is, the total number of inserted medals, the total number of paid-out medals, MY (maximum difference number of medals), total number of paid-out medals for accessory devices, total number of consecutive paid-out medals for accessory devices, accessory device ratio, consecutive accessory device ratio, advantageous section ratio, designated accessory device ratio, accessory device state ratio, number of games shown in FIG. 14, and transmits them to the medal CPU 204a. The medal CPU 204a extracts a part of the transmission information related to the winning ratio from the command received from the main CPU 200a and stores it in the RAM of the medal number control board 204. The main CPU 200a may calculate the transmission information related to the winning ratio in the used area or in the unused area. Also, the medal CPU 204a may hold the transmission information related to the winning ratio in the used area of the RAM or in the unused area.Also, the medal CPU 204a may transfer the transmission information related to the role ratio to the RAM in the used area or in the unused area.

[0289] Among the above game medal input commands, start lever press commands, payout end commands, one-game end commands, startup commands, and state transition commands, for the game medal input commands, start lever press commands, payout end commands, one-game end commands, and startup commands, the main CPU 200a transmits them to the medal CPU 204a within the main loop, and for the state transition commands, the main CPU 200a transmits them to the medal CPU 204a within the timer interrupt (for example, with a period of 1.49 msec).

[0290] Also, the medal CPU 204a can determine an error based on the commands received from the main CPU 200a. For example, in the game medal input command, payout end command, and one-game end command, the medal CPU 204a extracts the number of inserted and paid-out electronic medals and checks that there is no inconsistency with the total number of inserted and paid-out electronic medals. Also, the medal CPU 204a checks that the number of inserted electronic medals is not zero when receiving the start lever press command. Also, the medal CPU 204a may check that there is no inconsistency with the specified number of electronic medals corresponding to the game state in the game medal input command. Also, the main CPU 200a controls a 1-bit confirmation signal indicating that the payout end command is to be transmitted in I / O other than serial communication, and if the confirmation signal does not indicate that the payout end command is to be transmitted, the medal CPU 204a may discard the received command regardless of whether the received command is the payout end command.

[0291] Here, assume that the command sent from the main CPU 200a to the medal CPU 204a is of variable length. Then, when the medal CPU 204a starts receiving the command, since the length of the command is unknown, it becomes unclear how long the reception state of the command should be maintained and at what timing the command analysis should start. When the command is made variable length in this way, by indicating in the identification information what kind of command it is and what the length of the command is in bytes, the medal CPU 204a can easily understand the command.

[0292] Also, for example, when there are bits in the identification information to which no information is assigned, the "replay state", which is information necessary for the medal CPU 204a, can be assigned to those bits. In this way, the empty area of the transmission data can be effectively utilized, and there is no need to generate a separate program for generating and transmitting a 1-byte command called the replay state.

[0293] Also, the medal CPU 204a sends a predetermined command to the main CPU 200a. For example, when the medal CPU 204a receives the above commands (game medal insertion command, start lever press command, payout end command, startup command) from the main CPU 200a, it may send a reply command composed of identification information, transmission information indicating the number of insertable medals and the number of game medals, and a checksum to the main CPU 200a. The main CPU 200a can determine an error by checking the checksum of the reply command received from the medal CPU 204a. Note that the medal CPU 204a does not send a reply command for the end-of-one-game command and the state transition command.

[0294] Here, let us suppose that a predetermined bit of the identification information of the reply command is associated with an "ACK" indicating that the medal CPU 204a has successfully received the command sent from the main CPU 200a. This "ACK" is processed independently of other bits. For example, if the predetermined bit of the identification information is 1, the main CPU 200a can proceed to the next game process regardless of the contents of the other bits. Furthermore, if a bit other than the predetermined bit is set, the main CPU 200a performs processing corresponding to the set bit while continuing the game. This configuration makes it possible to effectively utilize the area of the identification information and increase the efficiency of information transfer.

[0295] Furthermore, such communication between the main CPU 200a and the medal CPU 204a may be continuously performed or may be subject to a predetermined restriction. For example, bidirectional communication between the main CPU 200a and the medal CPU 204a may be initiated upon completion of a win type lottery or an AT lottery by operation of the start switch 118, and may be restricted upon completion of one game. In this embodiment, when the start switch 118 is operated, a random number is acquired (latched) from the random number generator 200d and used as a win type lottery random number for the win type lottery or for the AT lottery. Here, communication between the main CPU 200a and the medal CPU 204a is not performed until completion of a win type lottery or an AT lottery by operation of the start switch 118, and communication is initiated upon completion of the win type lottery or an AT lottery by operation of the start switch 118. This eliminates the risk that communication between the main CPU 200a and the medal CPU 204a will affect the latch timing of the random number, making it possible to appropriately acquire random numbers.

[0296] 10(a) and 10(b), when the main CPU 200a and the medal CPU 204a are provided separately, they transmit information using commands via the serial communication described above. On the other hand, when the main CPU 200a manages the electronic medals used in games instead of the medal CPU 204a, as shown in FIG. 10(c), the information is held as a common internal variable in the main RAM 200c.

[0297] (Command Management) As described above, a plurality of types of commands (game medal insertion command, start lever press command, payout end command, one game end command, startup command, state transition command) are transmitted as information from the main CPU 200a to the medal CPU 204a. Also, a reply command is transmitted from the medal CPU 204a to the main CPU 200a. If the main CPU 200a normally receives the reply command and its content indicates "ACK", the main CPU 200a can assume that the communication between the main CPU 200a and the medal CPU 204a has been completed normally and proceed to the next process.

[0298] However, the communication between the main CPU 200a and the medal CPU 204a does not always complete normally. For example, although the main CPU 200a has transmitted a command normally, the medal CPU 204a may not be able to receive the command normally for some reason. Also, although the medal CPU 204a has normally received a command from the main CPU 200a and has normally transmitted a reply command for that command, the main CPU 200a may not be able to receive the reply command normally for some reason. However, in any case, the main CPU 200a cannot determine whether the medal CPU 204a has normally received the command. Therefore, in order to proceed with the process, the main CPU 200a will retransmit the command that was transmitted immediately before to the medal CPU 204a.

[0299] Here, an example where the transmission of the payout end command does not complete normally is illustrated. In the former case, that is, when the main CPU 200a has transmitted the command normally but the medal CPU 204a cannot receive the command normally, since the medal CPU 204a has not effectively processed the payout end command itself, even if the main CPU 200a retransmits the payout end command, if the medal CPU 204a can normally receive the retransmitted payout end command, no problem will occur.

[0300] However, in the latter case, that is, when the medal CPU 204a normally receives the command from the main CPU 200a and normally transmits the reply command for that command, but the main CPU 200a cannot normally receive the reply command, the medal CPU 204a is highly likely to effectively process the payout end command. For example, assume that the medal CPU 204a normally receives the payout end command and adds the number of paid-out medals included in the payout end command to the number of game medals. The medal CPU 204a normally transmits the reply command, but the main CPU 200a cannot determine whether the reply command has been normally received. Then, if the main CPU 200a cannot normally receive the reply command and re-transmits the payout end command, and the medal CPU 204a normally receives that payout end command, the number of paid-out medals included in the payout end command may be further added to the number of game medals. Then, for one payout trigger of the electronic medal, the number of paid-out medals will be repeatedly added to the number of game medals multiple times, and the player will obtain game benefits improperly. Also, when the harness between the main control board 200 and the medal number control board 204 is operated to fraudulently transmit the payout end command multiple times, an event may occur in which the number of paid-out medals is repeatedly added to the number of game medals multiple times in the same way as above.

[0301] Therefore, in the present embodiment, the command transmitted from the main CPU 200a to the medal CPU 204a is made valid only once appropriately. Specifically, when the medal CPU 204a continuously receives the same type of command from the main CPU 200a (external), the same type of command received after the second time is invalidated, and the process for that command is not performed. Here, the command refers to the game medal insertion command, start lever press command, payout end command, one game end command, startup command, and state transition command described above. For example, if the payout end command is received after the payout end command without receiving any other commands, it means that the same type of command has been continuously received. Note that when the main CPU 200a continuously receives the same type of command two or more times, the same type of command received after the second time is not necessarily invalidated. For example, when the operation of the 1 bet switch is continuously performed two or more times, or when the same type of command is continuously received two or more times under a predetermined situation where continuous reception of the command is allowed, the medal CPU 204a may also validly process the same type of command received after the second time.

[0302] Also, when the medal CPU 204a receives a predetermined command from the main CPU 200a, it may invalidate the predetermined commands received after the first received predetermined command until it receives a specific command different from the predetermined command. For example, once the medal CPU 204a receives an ejection end command from the main CPU 200a, it invalidates the subsequently received ejection end commands until it receives a specific command, such as a start lever press command. At this time, the predetermined commands received after the first received predetermined command become valid only when a specific command is received. Even if commands or information other than the specific command are received between the first reception of the predetermined command and the next reception, the subsequently received ejection end commands are invalidated. For example, once the medal CPU 204a receives an ejection end command as a predetermined command from the main CPU 200a, until it receives a start lever press command as a specific command, even if it receives other game medal insertion commands, one game end command, startup command, or state transition command, the subsequently received ejection end commands are invalidated.

[0303] Here, an example is given to explain that when the medal CPU 204a receives a predetermined command from the main CPU 200a and processes the predetermined commands received after the first received predetermined command as valid on the condition that a specific command is received. However, not limited to the specific command, the medal CPU 204a may process the predetermined commands received after the first received predetermined command as valid on the condition that it receives some command or arbitrary information other than the predetermined command.

[0304] Figs. 35 to 38 are flowcharts showing the flow of command reception processing in the medal CPU 204a. Here, the processing related to the present embodiment will be described, and the processing not related to the present embodiment, such as the generation processing of specific commands, etc., will be omitted. The numerical values of step S in such figures are used only in the description of this figure. Also, here, a 1-byte buffer (input request buffer, IN signal confirmation buffer, payout confirmation buffer, main reception command error buffer) is used as a flag, and the two values of "0h" and "FFh" are switched. Here, the reason for using a byte value instead of a bit value as the flag is that in the case of a bit value, after reading the byte value, a process of further determining the bit itself must be executed, and the total command size for determination becomes longer instead. Note that each of the above buffers used as a flag is backed up and is not initialized even when the power is turned off.

[0305] As shown in Fig. 35, when the medal CPU 204a normally receives a command from the main CPU 200a, it determines whether the received command (received command) is a startup command (S1). As a result, if the received command is a startup command (YES in S1), the medal CPU 204a performs a game machine installation information reception process for receiving game machine installation information (S2), performs a manufacturer code confirmation process for confirming the main control chip manufacturer code (S3), and ends the command reception process. Such manufacturer code confirmation processing will be described in detail later. Also, if the received command is not a startup command (NO in S1), the medal CPU 204a determines whether the received command is a payout end command (S4). As a result, if the received command is a payout end command (YES in S4), the medal CPU 204a executes a payout number setting process (S5) and ends the command reception process. Such payout number setting processing will be described in detail later.

[0306] Also, if the received command is not a payout end command (NO in S4), the medal CPU 204a determines whether the received command is a game end command for one game (S6). As a result, if the received command is a game end command for one game (YES in S6), the medal CPU 204a performs a game machine performance information setting process for setting game machine performance information (S7) and ends the command reception process. Also, if the received command is not a game end command for one game (NO in S6), the medal CPU 204a determines whether the received command is a state transition command (S8). As a result, if the received command is a state transition command (YES in S8), the medal CPU 204a executes a main control state reception process (S9) for receiving the main control state and ends the command reception process.

[0307] Also, if the received command is not a state transition command (NO in S8), the medal CPU 204a executes an input request number update process (S10) for updating the input request number of the electronic medals and determines whether the received command is a start lever press command (S11). As a result, if the received command is a start lever press command (YES in S11), the medal CPU 204a executes a game start process (S12) and ends the command reception process. Such a game start process will be described in detail later. Also, if the received command is not a start lever press command (NO in S11), the medal CPU 204a ends the command reception process.

[0308] In the flowchart of FIG. 35, processing is executed exclusively and independently according to which of a plurality of types of commands is received. For example, if the received command is a payout end command, the payout number setting process (S5) is performed, but the game start process (S12) is not performed. If the received command is a start lever press command, the game start process (S12) is performed, but the payout number setting process (S5) is not performed. In the present embodiment, the payout number setting process (S5) executed in response to the reception of the payout end command and the game start process (S12) executed in response to the reception of the start lever press command are managed independently, and the medal CPU 204a appropriately manages the commands received by switching the payout confirmation buffer and the IN signal confirmation buffer.

[0309] (Manufacturer code confirmation process) When the medal CPU 204a is powered on, it resets (turns off) the communication permission flag. Here, the communication permission flag is a flag for controlling whether communication between the medal CPU 204a and the dedicated unit 350 is possible. When such a communication permission flag is ON (valid), the medal CPU 204a can communicate with the dedicated unit 350, and when the communication permission flag is OFF (invalid), the medal CPU 204a does not execute (start) communication with the dedicated unit 350.

[0310] In the manufacturer code confirmation process (S3) shown in FIG. 36, the medal CPU 204a extracts (acquires) the manufacturer code (identifier) from the startup command (information) received from the main CPU 200a (S3-1), and compares it with the manufacturer code (specific identifier) of the medal number control board 204, which is held in advance in the medal ROM 204b of the medal number control board 204, to determine whether they match (S3-2). Here, the manufacturer code is an identifier that can uniquely identify the manufacturer that manufactured the smart pachislo 100. Therefore, if the main control board 200 and the medal number control board 204 are boards of the same manufacturer, the manufacturer codes match, and if the main control board 200 and the medal number control board 204 are boards of different manufacturers, the manufacturer codes are different.

[0311] As a result of comparing the manufacturer codes, if they match (YES in S3-2), the medal CPU 204a turns on the communication permission flag (S3-3) and ends the manufacturer code confirmation process. On the other hand, if they do not match (NO in S3-2), the medal CPU 204a turns off the communication permission flag (maintains OFF if already OFF) (S3-4), sets a manufacturer code mismatch error managed by the medal CPU 204a (S3-5), and ends the manufacturer code confirmation process. In this case, since the communication permission flag is OFF, the medal CPU 204a cannot execute communication with the dedicated unit 350, and as a result, the progress of the game is restricted. The error counter will be described in detail later.

[0312] Then, every time at the timing when the medal CPU 204a transmits a notification (game machine information notification, count notification, loan reception result response) to the dedicated unit 350 shown in FIG. 20, the medal CPU 204a checks the communication permission flag, and if the communication permission flag is ON, the notification can be transmitted.

[0313] Also, when the medal CPU 204a receives a loan notification from the dedicated unit 350, if the timing is appropriate and the communication permission flag is ON, the medal CPU 204a executes processing for the loan notification. Also, if the timing is not appropriate or the communication permission flag is OFF, the medal CPU 204a receives the loan notification but ignores (discards) the loan notification and does not execute processing for the loan notification. Here, the appropriate timing is about 170 msec after the medal CPU 204a transmits a count notification or about 270 msec after the medal CPU 204a transmits a game machine information notification, as shown in FIG. 20.

[0314] In this way, after establishing communication with the main CPU 200a (first control unit), the medal CPU 204a (second control unit) receives a startup command (information) from the main CPU 200a and acquires a manufacturer code (identifier) from the startup command. Then, when the medal CPU 204a determines that the manufacturer code is equal to a predetermined manufacturer code (specific identifier), it enables communication with the dedicated unit 350. With such a configuration, when the connection relationship between the medal CPU 204a and the main CPU 200a is correct and communication is properly performed, the medal CPU 204a can communicate with the dedicated unit 350. Therefore, since communication between the medal CPU 204a and the dedicated unit 350 is not started in a state where communication between the medal CPU 204a and the main CPU 200a is not properly performed, it becomes possible to appropriately perform processing among the medal CPU 204a, the main CPU 200a, and the dedicated unit 350.

[0315] Here, it is confirmed by the startup command when the power of the smart pachislot 100 is turned on that communication between the medal CPU 204a and the main CPU 200a is properly performed. The startup command is the earliest transmitted among the commands (startup command, game medal insertion command, start lever press command, payout end command, one game end command, state transition command) that the main CPU 200a transmits to the medal CPU 204a. Therefore, communication between the medal CPU 204a and the main CPU 200a can be confirmed early prior to other commands (game medal insertion command, start lever press command, payout end command, one game end command, state transition command), and communication between the medal CPU 204a and the dedicated unit 350 can be started early.

[0316] Note that the information for confirming that the communication between the medal CPU 204a and the main CPU 200a is properly performed is not limited to the startup command, and may be other commands (game medal insertion command, start lever press command, pay-out end command, one-game end command, state transition command). Thus, it becomes possible to confirm that the communication between the medal CPU 204a and the main CPU 200a is properly performed by any of these commands.

[0317] Also, here, it is confirmed that the communication between the medal CPU 204a and the main CPU 200a is properly performed by the manufacturer code included in the startup command. However, not limited to such a case, any identifier that can identify the connection relationship between the main CPU 200a and the medal CPU 204a (the connection relationship between the main control board 200 and the medal number control board 204) is sufficient. For example, game machine information or chip ID, which is transmission information required at startup and included in the startup command, or any identifier included in other commands (game medal insertion command, start lever press command, pay-out end command, one-game end command, state transition command) can also be used.

[0318] Also, here, an example in which a command is transmitted from the main CPU 200a (first control unit) to the medal CPU 204a (second control unit) in the smart pachislo 100 has been described. However, not limited to such a case, for example, it can be applied to serial communication between various independent CPUs as the first control unit and the second control unit, such as between other boards in the smart pachislo 100.

[0319] In the payout number setting process (S5) shown in FIG. 37, the medal CPU 204a sets 0h in the input request buffer (S5-1) and sets 0h in the IN signal confirmation buffer (S5-2). Here, by setting 0h in the IN signal confirmation buffer, the invalidation of the start lever press command received in the game start process (S12) described later is released. Subsequently, the medal CPU 204a determines whether the payout confirmation buffer is 0h (S5-3). As a result, if the payout confirmation buffer is not 0h (NO in S5-3), it means that the reception of the payout end command is not the first time, so the medal CPU 204a ends the payout number setting process. On the other hand, if the payout confirmation buffer is 0h (YES in S5-3), it means that the reception of the payout end command is the first time, so the medal CPU 204a sets FFh in the payout confirmation buffer (S5-4) to invalidate the payout end command for the second and subsequent times. Next, the medal CPU 204a determines whether the payout number is 16 or more (S5-5). As a result, if the payout number is 16 or more (YES in S5-5), the medal CPU 204a sets FFh in the main reception command error buffer (S5-6) and ends the payout number setting process.

[0320] On the other hand, if the payout number is 15 or less (NO in S5-5), the medal CPU 204a determines whether the replay is in operation (S5-7). As a result, if the replay is not in operation (NO in S5-7), the medal CPU 204a determines whether the payout number is 0 (S5-8). As a result, if the payout number is 0 (YES in S5-8), the medal CPU 204a ends the payout number setting process. On the other hand, if the payout number is not 0 (NO in S5-8), the medal CPU 204a adds the payout number to the number of game medals to update the number of game medals (S5-9) and sets the payout number to the payout medal number (S5-10). In this way, the number of game medals is appropriately updated. When the payout number is set to the payout medal number (S5-10), or if the replay is in operation (YES in S5-7), the medal CPU 204a performs a game information setting process for setting game information (S5-11) and ends the payout number setting process.

[0321] In the game start process (S12) shown in FIG. 38, the medal CPU 204a determines whether the IN signal confirmation buffer is 0h (S12-1). As a result, if the IN signal confirmation buffer is not 0h (NO in S12-1), it means that the start lever press command has not been received for the first time, so the medal CPU 204a ends the game start process. On the other hand, if the IN signal confirmation buffer is 0h (YES in S12-1), it means that the start lever press command has been received for the first time, so the medal CPU 204a sets FFh in the IN signal confirmation buffer (S12-2), invalidates the start lever press commands after the second time, performs a game information setting process for setting game information (S12-3), sets 0h in the payout confirmation buffer (S12-4), and ends the game start process. Here, by setting 0h in the payout confirmation buffer, the invalidation of the payout end command received in the payout number setting process (S5) is released. Note that in the above, step S12-4 is to be executed when the determination in S12-1 is YES, but it may also be executed before step S12-1.

[0322] Here, when the medal CPU 204a continuously receives the same type of payout end commands from the main CPU 200a, the payout end commands received after the second time are invalidated. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 37, the medal CPU 204a determines that it is the first reception of the payout end command, switches the payout confirmation buffer to FFh, and normally executes the processes after step S5-6 for the payout number. After that, even if the payout end command is received next, since it is determined in step S5-3 that the payout confirmation buffer is not 0h (it is FFh), the processes after step S5-6 for the payout number are not performed (the payout end command is invalidated).

[0323] Also, when the medal CPU 204a receives a start lever press command from the main CPU 200a under the condition of invalidating the paid-out end command received in this way, it cancels the invalidation of the paid-out end command. Specifically, if the payout confirmation buffer is 0h in step S5-3 of FIG. 37, the medal CPU 204a switches the payout confirmation buffer to FFh and invalidates the paid-out end commands received thereafter. However, when a start lever press command is received thereafter, the payout confirmation buffer is reset to 0h in step S12-4 of FIG. 38. Therefore, when the paid-out end command is received next, it is determined that the payout confirmation buffer is 0h in step S5-3 of FIG. 37, that is, the paid-out end command is received for the first time, and the processing after step S5-4 for the payout number will be executed normally.

[0324] Also, when the medal CPU 204a continuously receives start lever press commands of the same type from the main CPU 200a, it invalidates the start lever press commands received after the second time. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 38, the medal CPU 204a determines that it is the first reception of the start lever press command, switches the IN signal confirmation buffer to FFh, and normally executes the game information setting process in step S12-3. After that, even if the start lever press command is received next, since it is determined that the IN signal confirmation buffer is not 0h (it is FFh) in step S12-1, the game information setting process in step S12-3 is not performed (the start lever press command is invalidated).

[0325] Also, when the medal CPU 204a receives the payout end command from the main CPU 200a after invalidating the start lever press command received in this way, it cancels the invalidation of the start lever press command. Specifically, if the IN signal confirmation buffer is 0h in step S12-1 of FIG. 38, the medal CPU 204a switches the IN signal confirmation buffer to FFh and invalidates the start lever press commands received thereafter. However, when the payout end command is received, the IN signal confirmation buffer is reset to 0h in step S5-2 of FIG. 37. Therefore, when the start lever press command is received next, the IN signal confirmation buffer is 0h in step S12-1 of FIG. 38, that is, it is determined that the start lever press command is received for the first time, and the game information setting process in step S12-3 is normally executed.

[0326] In this way, when a command is received continuously multiple times, with the configuration of invalidating the same type of command received after the second time, it becomes impossible to execute a process that should originally be executed only once multiple times according to that command, and the game progresses appropriately. Also, even if an unauthorized board is attached between the main control board 200 and the medal number control board 204 and the command is illegally transmitted multiple times by this unauthorized board, the command is invalidated, so game profits are not improperly obtained.

[0327] Here, when the payout end command is received continuously multiple times, the payout confirmation buffer is switched to invalidate the receptions after the second time. Also, when the start lever press command is received continuously multiple times, the IN signal confirmation buffer is switched to invalidate the receptions after the second time. Since the payout end command and the start lever press command are processed exclusively, originally, one buffer would be sufficient. However, if the two values of one buffer are respectively assigned to the allowance of the payout end command and the allowance of the start lever press command, when one buffer allows either the payout end command or the start lever press command and does not allow the other, if a backup abnormality occurs in the medal CPU 204a or a setting change occurs in the main control board 200, the other command that should be allowed may not be allowed, and there is a risk that the game will not proceed. Therefore, here, buffers (payout confirmation buffer, IN signal confirmation buffer) are provided for the payout end command and the start lever press command respectively, and when predetermined initialization conditions such as backup abnormality and setting change are satisfied, both buffers are set to 0h to transition to a state where any command is allowed. With such a configuration, even when a backup abnormality occurs in the medal CPU 204a or a setting change occurs in the main control board 200, the game can proceed appropriately.

[0328] Note that the present embodiment can also be implemented with one buffer by separately providing a state in which one buffer, for example, the command confirmation buffer, allows both the payout end command and the start lever press command. For example, a state that allows both the payout end command and the start lever press command is set to 0h, a state that allows only the payout end command and does not allow the start lever press command is set to 1h, and a state that allows only the start lever press command and does not allow the payout end command is set to 2h. When the medal CPU 204a receives the payout end command, it switches the command confirmation buffer to 2h in order to invalidate receptions after the second time when the payout end command is received continuously multiple times. When the medal CPU 204a receives the start lever press command, it switches the command confirmation buffer to 1h in order to invalidate receptions after the second time when the start lever press command is received continuously multiple times. When a predetermined initialization condition such as backup abnormality or setting change is satisfied, the command confirmation buffer is set to 0h to transition to a state that allows any command.

[0329] Here, a command has been described as an example of information transmitted and received between the main CPU 200a and the medal CPU 204a. However, the present invention is not limited to such a case, and various contents such as data and signals can be included.

[0330] (Anti-fraud signal) As described with reference to FIG. 36, when the communication permission flag is ON in the medal number control board 204, the medal CPU 204a can establish communication with the dedicated unit 350 and transmit notifications (game machine information notification, count notification, loan reception result response). Then, when an abnormality is detected during the progress of the game, the medal CPU 204a transmits a predetermined signal or a specific signal to the dedicated unit 350. Here, as the predetermined signal and the specific signal transmitted to the dedicated unit 350, a signal for preventing fraud (anti-fraud signal) is commonly cited as an example. Specifically, the medal CPU 204a transmits the anti-fraud signal to the dedicated unit 350 through "Game Machine Fraud 1", "Game Machine Fraud 2", and "Game Machine Fraud 3" in the hall computer fraud monitoring information of the game machine information notification shown in FIG. 16. However, the predetermined signal and the specific signal do not necessarily have to be the same signal, and neither is limited to the anti-fraud signal, and various signals transmitted from the medal CPU 204a to the dedicated unit 350 can be applied. When the dedicated unit 350 receives such an anti-fraud signal, it transmits it to the hall computer.

[0331] For example, when the confirmation process of the set value is performed, a signal being confirmed during setting as an anti-fraud signal is output at bit 1 of game machine fraud 1. Also, when an abnormality is detected in the smart pachislo 100, fraud detection signals 1, 2, and 3 as anti-fraud signals are output at bits 2 to 4 of game machine fraud 1. Further, when the front lower door 106 is opened, a door open signal as an anti-fraud signal is output at bit 1 of game machine fraud 2. Such an anti-fraud signal must be continuously output for at least 3 seconds. Here, an example will be described in which the medal CPU 204a continuously outputs the anti-fraud signal to the dedicated unit 350 for 5 seconds.

[0332] If an event that interrupts the output of the anti-tampering signal, such as a power failure (power cut-off), occurs during the output of the anti-tampering signal, the signal timing timer that has been timing for 5 seconds is reset. After the interruption event is resolved, such as after the power is restored, the anti-tampering signal is output again for 5 seconds. In this case, the total time for which the anti-tampering signal is output becomes 5 seconds or more, and the dedicated unit 350 can surely recognize the anti-tampering signal. Here, the signal timing timer is composed of a down-counter and is used to time a predetermined time (here, 5 seconds) required to maintain the output of the anti-tampering signal.

[0333] However, depending on the timing when an abnormality occurs in the smart pachislo 100, there may be a case where sufficient time for outputting the anti-tampering signal cannot be ensured. For example, assume that the power is turned on with the front lower door 106 open. Then, the medal CPU 204a attempts to continuously output the door open signal as the anti-tampering signal at bit 1 of the gaming machine fraud 2 for 5 seconds immediately after the power is turned on. However, as described above, after establishing communication with the main CPU 200a, the medal CPU 204a receives the startup command from the main CPU 200a and confirms that the manufacturer code in the startup command is correct before it can send the gaming machine information notification to the dedicated unit 350 for the first time. That is, even if the timing starts counting for 5 seconds immediately after the power is turned on with the front lower door 106 open, the anti-tampering signal is not output to the dedicated unit 350 until it is confirmed that the manufacturer code in the startup command is correct. Then, the start of output of the anti-tampering signal is delayed, sufficient time for output of the anti-tampering signal is not ensured, and it becomes difficult for the dedicated unit 350 to surely recognize the anti-tampering signal.

[0334] In addition, after the medal number control board 204 is powered on, it can start operating normally in about 1 second, for example. However, since the main control board 200 performs initialization processing of the main control board 200 itself and transmission of information necessary for initialization processing of the sub-control board 202, it takes time for the main control board 200 itself to start functioning normally. Then, after the main CPU 200a starts normal functions, it sends a startup command to the medal CPU 204a. Then, it may take 5 seconds or more (for example, 10 seconds) until the medal CPU 204a confirms that the manufacturer code in the startup command is correct. In this case, the medal CPU 204a cannot output an anti-tampering signal while the front lower door 106 is open and the signal timing timer is counting for 5 seconds immediately after the power is turned on, and the dedicated unit 350 cannot recognize the anti-tampering signal.

[0335] Therefore, in this embodiment, the transmission of the anti-tampering signal is started on the condition that the communication permission flag is ON.

[0336] FIG. 39 is a flowchart showing the flow of the anti-tampering signal output process. The numerical values of step S in such a figure are used only in the description of this figure. Here, it is assumed that the power is turned on with the front lower door 106 open.

[0337] After the power is turned on, when it is recognized through the door switch (a switch that detects the opening of the front lower door 106) that the front lower door 106 is in an open state, the medal CPU 204a sets the door open signal in bit 1 of the gaming machine fraud 2 as an anti-fraud signal (S1). However, at this stage, since the communication permission flag is OFF, the anti-fraud signal is not output to the dedicated unit 350. Also, the medal CPU 204a sets a count value corresponding to 5 seconds in the signal timing timer (S2). However, at this stage, the progress (timing) of the signal timing timer is restricted (countdown is not performed). Note that when the door switch detects the opening of the front lower door 106, a signal to that effect may be acquired by both the main CPU 200a and the medal CPU 204a, or either one of them may acquire it. Therefore, the medal CPU 204a may recognize indirectly through the main CPU 200a that the front lower door 106 is in an open state, or may directly recognize through the signal from the door switch that the front lower door 106 is in an open state.

[0338] Then, the medal CPU 204a determines whether the communication permission flag is ON, that is, after establishing communication with the main CPU 200a, whether it has received a startup command from the main CPU 200a and determined that the manufacturer code in the startup command is correct (S3). As a result, while the communication permission flag is OFF (NO in S3), the medal CPU 204a repeats the process of step S3. For example, when the power is turned on, the main control board 200 transmits necessary information such as its own initialization process and the initialization process of the sub-control board 202, and then transmits a startup command (manufacturer code) to the medal CPU 204a. Therefore, during this period, the communication permission flag remains OFF and the anti-fraud signal is not output.

[0339] On the one hand, when the communication permission flag is ON (YES in S3), the medal CPU 204a establishes communication with the dedicated unit 350 and starts outputting an anti-fraud signal (door open signal) by transmitting a gaming machine information notification (S4). Also, when outputting the anti-fraud signal, the medal CPU 204a starts the progress of the signal timing timer (S5). In this way, while the signal timing timer is counting, the setting of the anti-fraud signal is maintained and the output of the anti-fraud signal continues. Here, the medal CPU 204a has previously set the door open signal in bit 1 of gaming machine fraud 2 as the anti-fraud signal and set a count value in the signal timing timer. When the set communication permission flag is ON, that is, when the start condition for the progress of the signal timing timer is satisfied, an example has been described in which the progress of the signal timing timer is started and the anti-fraud signal is output. However, not limited to such a case, when the medal CPU 204a recognizes that the front lower door 106 is in an open state, it sets a door open flag indicating that the door is open. When the start condition for the progress of the signal timing timer is satisfied, at that timing, on the condition that the door open flag is set, as the anti-fraud signal, the door open signal in bit 1 of gaming machine fraud 2 is set, a count value is set in the signal timing timer, the progress of the signal timing timer is started, and the anti-fraud signal may be output.

[0340] Subsequently, the medal CPU 204a determines whether the signal timing timer has completed counting 5 seconds (S6). As a result, if 5 seconds have not been reached (NO in S6), the medal CPU 204a repeats the process of step S6. On the other hand, if 5 seconds have been completed (YES in S6), the medal CPU 204a resets the anti-fraud signal, for example, the door open signal in bit 1 of gaming machine fraud 2 (S7). In this way, the output of the anti-fraud signal ends. Such output processing of the anti-fraud signal may be performed within the usage area of the medal number control board 204, or since such processing is security-related processing, it may be performed in an unused area. By performing the output processing of the anti-fraud signal in the unused area in this way, it becomes possible to effectively utilize the usage area.

[0341] In this way, an anti-fraud signal is generated, and the medal CPU 204a starts communication with the main CPU 200a. After starting communication with the main CPU 200a (after turning on the communication permission flag), it measures time for a predetermined period with a signal timing timer. While measuring time for the predetermined period, it transmits the anti-fraud signal to the dedicated unit 350. With this configuration, as long as the dedicated unit 350 has already started up, the dedicated unit 350 can surely receive the anti-fraud signal for the output continuation time of the anti-fraud signal. Thus, fraud in the smart pachislo 100 can be surely prevented.

[0342] In addition, when a power failure occurs during the output of the anti-fraud signal, the medal CPU 204a may reset the signal timing timer that has been measuring time for a predetermined period (for example, 5 seconds), and after confirming again that the communication permission flag is ON, output the anti-fraud signal to the dedicated unit 350 for a predetermined period. Also, if it is possible to save the count value of the signal timing timer when a power failure occurs, the medal CPU 204a saves the count value of the signal timing timer at the time of power failure, and at the time of power-on (when power failure resumes), after confirming that the communication permission flag is ON, resumes timing from the saved count value of the signal timing timer and outputs the anti-fraud signal to the dedicated unit 350.

[0343] Also, here, an example was given in which when the medal CPU 204a recognizes that the front lower door 106 is open, it sets a door open signal as an anti-fraud signal in bit 1 of the gaming machine fraud 2. However, this is not limited to such a case. For example, in a setting change process, when a door is provided in a setting change device that accepts a setting change operation by an administrator, the medal CPU 204a may recognize that the door provided in the setting change device is open and output a set door open signal as an anti-fraud signal in bit 0 of the gaming machine fraud 2. In that case, as described above, the medal CPU 204a may advance the signal timing timer after the communication permission flag is ON and the communication between the medal CPU 204a and the dedicated unit 350 is established. Also, here, an example was given in which a door switch is provided in the front lower door 106 and the medal CPU 204a recognizes that the front lower door 106 is open through the door switch. However, this is not limited to such a case. A door switch may be provided in the front upper door 104 and the medal CPU 204a may recognize that the front upper door 104 is open through the door switch. Or door switches may be provided in both the front upper door 104 and the front lower door 106, and the medal CPU 204a may recognize that both the front upper door 104 and the front lower door 106 are open through the door switch. In this case, similar to the above-described front lower door 106, when the door switch detects the opening of the front upper door 104, the signal to that effect may be acquired by both the main CPU 200a and the medal CPU 204a, or either one of them may acquire it. Therefore, similar to the front lower door 106, the medal CPU 204a may recognize indirectly through the main CPU 200a that the front upper door 104 is open, or may directly recognize through the signal from the door switch that the front upper door 104 is open. Also, when a door other than the front upper door 104 and the front lower door 106, for example, a door having a projector, is provided in the housing 102, a door switch may be provided in such a door and the medal CPU 204a may recognize that the door is open through the door switch.

[0344] Also, here, an example was given in which the medal CPU 204a ensures the output duration of the anti-fraud signal by advancing the signal timing timer after the communication permission flag is turned ON. However, this is not limited to such a case. Instead of the medal CPU 204a, a signal timing timer may be provided in the main CPU 200a, and the main CPU 200a may ensure the output duration of the anti-fraud signal by advancing the signal timing timer after it becomes possible to transmit the startup command. Specifically, when the startup command becomes transmissible, or when the startup command is transmitted to the medal CPU 204a, the main CPU 200a starts outputting the anti-fraud signal (door open signal) and starts advancing the signal timing timer. Also, the main CPU 200a ends the output of the anti-fraud signal in response to the signal timing timer having counted 5 seconds. At this time, the output process of the anti-fraud signal shown in FIG. 39 may be performed within the usage area of the main control board 200, or since such processing is security-related processing, it may be performed in the non-usage area. By performing the output process of the anti-fraud signal in the non-usage area in this way, it becomes possible to effectively utilize the usage area.

[0345] Also, here, an example was given in which the medal CPU 204a advances the signal timing timer after the communication permission flag is turned ON. However, this is not limited to such a case. In addition to the communication permission flag being ON, after confirming the medal insertable state described later, or after confirming that the VL connection signal is ON, the signal timing timer may be advanced. With such a configuration, the medal CPU 204a can surely ensure the output duration of the anti-fraud signal after normally establishing communication with the main CPU 200a and the dedicated unit 350. Thus, the administrator can surely prevent fraud.

[0346] Also, here in the smart pachislo 100, an example was described where the medal CPU 204a generates an anti-fraud signal in response to detection of an abnormality, starts counting a predetermined time after starting communication with the main CPU 200a, and continuously transmits the anti-fraud signal to the dedicated unit 350 while the predetermined time is being counted. However, this is not limited to such a case. Even if the frame CPU of the smart pachinko generates an anti-fraud signal in response to detection of an abnormality, starts counting a predetermined time after starting communication with the main CPU, and continuously transmits the anti-fraud signal to the dedicated unit while the predetermined time is being counted, it may be acceptable. Also, here in the smart pachislo 100, an example was described where, instead of the medal CPU 204a, after the main CPU 200a becomes capable of transmitting a startup command, the signal timing timer is advanced to ensure the output continuation time of the anti-fraud signal. However, in the smart pachinko as well, the main CPU can ensure the output continuation time of the anti-fraud signal by advancing the signal timing timer after it becomes capable of transmitting a startup command, instead of the frame CPU. Note that such output processing of the anti-fraud signal may be performed within the used area of the main control board of the smart pachinko, or it may be performed in an unused area.

[0347] In the above, an example was described of outputting anti-fraud signals such as a setting confirmation signal, a fraud detection signal 1, a fraud detection signal 2, a fraud detection signal 3, and a door open signal to the dedicated unit 350 through "Game Machine Fraud 1", "Game Machine Fraud 2", and "Game Machine Fraud 3" in the hall computer - fraud monitoring information of the game machine information notification shown in FIG. 16. However, the anti-fraud signal is not limited to such a case. As shown in FIG. 16, for example, it includes a signal during setting change and detection of clearing the number of game medals.

[0348] The signal during setting change is arranged in bit 0 of "Game Machine Fraud 1" in the hall computer - fraud monitoring information of the game machine information notification, and is a signal output during execution of the setting change process (under predetermined conditions). When such a signal during setting change is output to the dedicated unit 350, a security signal is also output to the dedicated unit 350 accordingly.

[0349] The game medal count clear detection is a signal that is arranged in bit 3 of "Game Machine Fraud 2" in the hall computer's illegal monitoring information for game machine information notification and is output when the game medal count held in the smart pachislot 100 is cleared to 0 (under predetermined conditions). For example, when electronic medals remain as the game medal count in the smart pachislot 100 at the end of the hall's business hours or at the start of business the next day (including cases where the player left them unconsciously and cases where they left them intentionally), the hall staff clears the game medal count so that the game medal count becomes 0 at the start of business. The occurrence of such game medal count clear detection is stored in the hall computer, and the administrator can retrospectively confirm whether the game medal count was cleared and the clearance time. Also, it becomes possible to use the output history of the game medal count clear detection as proof that the game medal count was cleared or not cleared.

[0350] When the dedicated unit 350 receives a setting change in progress signal or a game medal count clear detection, it transmits it to the hall computer. When the hall computer receives a setting change in progress signal or a game medal count clear detection, while the output continues, a notification indicating that a setting change in progress signal or a game medal count clear detection has been received is made. For example, a data lamp is lit. The setting change in progress signal continues to be output until the end of a normal game after the power-on of the smart pachislot 100 even if the setting change has already ended, in order to ensure the lighting time of the data lamp. During that time, the data lamp continues to be lit. Also, for the game medal count clear detection as well, when it is specified to light the data lamp, it continues to be output until the end of a normal game in the smart pachislot 100 in order to ensure the lighting time of the data lamp. During that time, the data lamp continues to be lit. However, in this case, in order to stop the output of the setting change in progress signal or the game medal count clear detection, the hall staff must execute one game on the smart pachislot 100, imposing a work burden to make a large number of smart pachislot 100s playable in a short time.

[0351] Therefore, here, the duration of the signal during setting change and the output of the detection of clearing the number of game medals is not set until the end of one game, but is limited to a predetermined time like the signal during setting confirmation, the fraud detection signal 1, the fraud detection signal 2, the fraud detection signal 3, the door open signal, etc.

[0352] However, for the anti-fraud signals such as the signal during setting confirmation, the fraud detection signal 1, the fraud detection signal 2, the fraud detection signal 3, and the door open signal, the medal CPU 204a starts timing for 5 seconds after the communication permission flag is turned on. For the signal during setting change and the detection of clearing the number of game medals, in addition to the communication permission flag being turned on, the game must be possible, that is, the medal insertion state must be available. The medal insertion state indicates a state where betting on electronic medals is possible, and the VL connection signal indicating the connection state with the dedicated unit 350 is ON, and the transition occurs on the condition that there are no other errors. Therefore, the medal CPU 204a can indirectly grasp that the VL connection signal is ON through the medal insertion state (game possible state). Also, the medal insertion state is managed by the main CPU 200a, and the medal CPU 204a can refer to the medal insertion state through the command transmitted from the main CPU 200a. Note that the medal insertion state may be managed by the medal CPU 204a. Here, by the medal CPU 204a grasping that the communication permission flag is ON and the medal insertion state is available, not only can it be confirmed that the communication between the main CPU 200a and the medal CPU 204a is normally established, but it is also possible to confirm that the communication between the medal CPU 204a and the dedicated unit 350 is normally established.

[0353] Figure 40 is a flowchart showing the flow of the output process of the anti-fraud signal. The numerical values of step S in such a figure are used only in the description of this figure. Here, it is assumed that the power is turned on in a state where the number of game medals has been cleared.

[0354] After power-on, when the medal CPU 204a recognizes that it is in a predetermined condition, that is, the number of game medals has been cleared, it sets the detection of the clearing of the number of game medals in bit 3 of the gaming machine fraud 2 as an anti-fraud signal (S1). However, at this stage, since the communication permission flag is OFF, the anti-fraud signal is not output to the dedicated unit 350. Also, the medal CPU 204a sets a count value corresponding to 5 seconds in the signal timing timer (S2). However, at this stage, the progress (timing) of the signal timing timer is restricted (countdown is not performed).

[0355] Then, the medal CPU 204a determines whether the communication permission flag is ON and whether the medal insertion enabled state is established (S3). As a result, while the communication permission flag is OFF or the medal insertion enabled state is not established (NO in S3), the medal CPU 204a repeats the process of step S3. For example, when the power is turned on, the main control board 200 transmits information necessary for the initialization process of the main control board 200 itself and the initialization process of the sub-control board 202, and then transmits a startup command (manufacturer code) to the medal CPU 204a. Also, immediately after the power is turned on, since the VL connection signal is OFF, the medal insertion enabled state is not established. Therefore, during such a period, the anti-fraud signal is not output.

[0356] On one hand, if the communication permission flag is ON and the medal insertion is possible (YES in S3), the medal CPU 204a establishes communication with the dedicated unit 350 and starts outputting the anti-fraud signal by transmitting a gaming machine information notification (S4). Also, the medal CPU 204a starts the progress of the signal timing timer along with the output of the anti-fraud signal (S5). In this way, while the signal timing timer is counting, the setting of the anti-fraud signal is maintained and the output of the anti-fraud signal continues. Here, the medal CPU 204a has previously set the detection of clearing the number of gaming medals in bit 3 of gaming machine fraud 2 as the anti-fraud signal and set a count value in the signal timing timer. If the communication permission flag is ON and the medal insertion is possible, that is, when the start condition of the progress of the signal timing timer is satisfied, an example has been described in which the progress of the signal timing timer is started and the anti-fraud signal is output. However, not limited to such a case, when the medal CPU 204a recognizes that the number of gaming medals has been cleared, it sets a medal number clear flag indicating that the number of gaming medals has been cleared. When the start condition of the progress of the signal timing timer is satisfied, at that timing, on the condition that the medal number clear flag is set, it sets the detection of clearing the number of gaming medals in bit 3 of gaming machine fraud 2 as the anti-fraud signal, sets a count value in the signal timing timer, starts the progress of the signal timing timer, and outputs the anti-fraud signal.

[0357] Subsequently, the medal CPU 204a determines whether the signal timing timer has counted 5 seconds (S6). As a result, if 5 seconds have not yet been reached (NO in S6), the medal CPU 204a repeats the process of step S6. On the other hand, if 5 seconds have been counted (YES in S6), the medal CPU 204a resets the detection of the game medal number clear as an anti-cheat signal in bit 3 of the gaming machine fraud 2 (S7). Thus, the output of the anti-cheat signal ends. Such output processing of the anti-cheat signal may be performed within the used area of the medal number control board 204, or since this processing is security-related processing, it may also be performed in an unused area. By performing the output processing of the anti-cheat signal in the unused area in this way, it becomes possible to effectively utilize the used area.

[0358] In this way, an anti-cheat signal is generated, the medal CPU 204a starts communicating with the main CPU 200a, and after confirming the connection with the dedicated unit 350 (being in a state where medals can be inserted), the signal timing timer counts for a predetermined time. While the predetermined time is being counted, the medal CPU 204a transmits the anti-cheat signal to the dedicated unit 350. With this configuration, after the medal CPU 204a has successfully established communication with the main CPU 200a and the dedicated unit 350, it...

Claims

Claim 1 control means for updating the game value number; display means for displaying the numbers related to the game; a substrate provided with predetermined electronic components; a substrate case for housing the substrate; comprising: the control means: repeats the main process; in the main process, one or more update processes for updating the game value number may be executed; executes a timer interrupt process at a predetermined cycle; in the timer interrupt process, executes a display process including at least a process of setting the numbers related to the game to be displayed on the display means; an explosion-proof valve is formed on the top surface of the electronic component; the separation distance between the top surface of the electronic component and the top surface of the substrate case is longer than the distance from the outer peripheral portion to the center of the top surface of the electronic component; a through hole is provided in a portion of the top surface of the substrate case that faces the top surface of the electronic component; the separation distance is longer than the length of the screw portion of a screw that is used in the gaming machine and can be inserted into the through hole; the diameter of the through hole is shorter than the diameter of the top surface of the electronic component; A gaming machine in which the explosion-proof valve is visible from the outside of the substrate case.

Images