Gaming machine

Abstract

To provide a game machine capable of favorably acquiring numerical value information in a lottery.SOLUTION: A main-side MPU 142 includes a control IC 148 and a hard random number circuit 146. The hard random number circuit 146 includes a control-side CPU 142 that sets up "1" to a latched status 113 on the basis on a fact that a detection signal SG1 is changed over from a LOW state to a HI state, the detection signal being output from the start detection sensor 41a for detecting a state of a start lever. When the detection signal SG1 is in the HI state, and "1" is set up in the latched status 113, the control IC 148 acquires numerical value information input in an input terminal TA3 of the control IC 148 as a random number and executes a lottery processing of a winning combination using the random number.SELECTED DRAWING: Figure 32

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As a type of gaming machine, pachinko machines, slot machines, etc. are known. In these gaming machines, various controls are executed in a control device to control the progress of the game. Also, numerical information is used when executing various controls in the control device.

[0003] For example, a configuration is known in which an internal lottery is conducted based on the establishment of a predetermined lottery condition, and a privilege is given to the player according to the result of the internal lottery. In this internal lottery, when a predetermined lottery condition is established, numerical information for lottery is acquired from an updating means for updating the numerical information, and it is determined whether or not the acquired numerical information corresponds to winning information (see, for example, Patent Document 1). Also, a configuration is known in which numerical information is acquired based on the establishment of a predetermined acquisition condition, and specific effects or notifications are performed based on the result of the internal lottery performed using the numerical information.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in a gaming machine such as the above example, it is necessary to suitably acquire numerical information at the time of lottery, and there is still room for improvement in this regard.

[0006] The present invention has been made in view of the above-exemplified circumstances, etc., and an object thereof is to provide a gaming machine capable of suitably acquiring numerical information at the time of lottery.

Means for Solving the Problem

[0007] In order to solve the above problems, the invention according to claim 1 includes numerical update means for updating numerical information, storage execution means for storing the numerical information updated by the numerical update means in acquisition storage means based on the occurrence of a first trigger, control means for executing special processing using the numerical information stored in the acquisition storage means based on the occurrence of a second trigger, in a gaming machine provided with: the storage execution means includes: information setting means for setting acquired information when the first trigger occurs and the numerical information is stored in the acquisition storage means; rewriting means for rewriting the numerical information stored in the acquisition storage means with the numerical information updated by the numerical update means at that time when the first trigger occurs again in a situation where the acquired information has already been set; and is provided with: the control means includes: determination means for determining whether or not the second trigger has occurred each time a monitoring timing is reached; control execution means for executing the special processing on at least one condition that the acquired information is set when it is determined by the determination means that the second trigger has occurred; and is provided with: The update period of the numerical information in the numerical value update means is configured to be shorter than the period required from the occurrence of one monitoring timing in the determination means to the occurrence of the next monitoring timing. Even when the numerical information is rewritten by the rewriting means, control for setting the acquired information is executed, which is characterized in that.

Effects of the Invention

[0008] According to the present invention, it is possible to suitably acquire numerical information at the time of lottery.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] <First Embodiment> Hereinafter, a first embodiment when the present invention is applied to a slot machine which is a type of gaming machine will be described in detail with reference to the drawings. FIG. 1 is a front view of the slot machine 10.

[0011] The slot machine 10 includes a housing 11 that forms its outer shell. The housing 11 is formed in a box shape that is open to the front as a whole by fixing a plurality of wooden panels. A front door 12 is attached to the front side of the housing 11. The front door 12 is supported by the housing 11 so as to be able to open and close the internal space of the housing 11 with its left side as a rotation axis. Note that the front door 12 is locked in a non-openable state by a locking device provided on its back surface, and this locked state is released by an unlocking operation with a predetermined key to the key cylinder 14.

[0012] A game panel 20 for notifying the player of the game state is provided on the upper part of the central portion of the front door 12. The game panel 20 is formed with three vertically long display window portions 21L, 21M, and 21R arranged side by side horizontally. The display window portions 21L, 21M, and 21R are formed of a transparent or translucent material, and the inside of the slot machine 10 can be viewed through each of the display window portions 21L, 21M, and 21R.

[0013] A reel unit 31 is provided in the housing 11. The reel unit 31 includes a left reel 32L, a middle reel 32M, and a right reel 32R, each formed in a cylindrical shape. Each of the reels 32L, 32M, and 32R is rotatably supported such that its central axis becomes the rotation axis of the reel. The rotation axes of the reels 32L, 32M, and 32R are arranged on the same axis extending in a substantially horizontal direction, and each of the reels 32L, 32M, and 32R corresponds one-to-one with each of the display window portions 21L, 21M, and 21R. Therefore, a part of the surface of each of the reels 32L, 32M, and 32R is in a visible state through the corresponding display window portions 21L, 21M, and 21R. Also, when the reels 32L, 32M, and 32R rotate forward, the surfaces of the reels 32L, 32M, and 32R are projected as if they are moving downward from top to bottom through each of the display window portions 21L, 21M, and 21R.

[0014] Each of these reels 32L, 32M, and 32R is connected to a stepping motor (not shown), and each reel 32L, 32M, 32R can be rotationally driven individually, that is, independently, by driving each stepping motor.

[0015] Various operation units for the player to perform start and stop operations of the game using each reel 32L, 32M, 32R are collectively arranged in an operation bulging portion 25 provided in front of the slot machine 10 rather than the game panel 20 below the game panel 20. The various operation units collectively arranged in the operation bulging portion 25 will be described in detail below.

[0016] On the left front side of the operation bulging portion 25, a start lever 41 that is operated to start the rotation of each reel 32L, 32M, 32R is provided. When this start lever 41 is operated while medals are bet, each reel 32L, 32M, 32R starts rotating simultaneously.

[0017] On the front surface of the operation bulging portion 25, to the right of the start lever 41, stop buttons 42, 43, 44 that are operated to individually stop each rotating reel 32L, 32M, 32R are provided. Each stop button 42, 43, 44 is respectively arranged directly below the display window portions 21L, 21M, 21R corresponding to the reel 32L, 32M, 32R to be stopped. Each stop button 42, 43, 44 becomes in a state where it can be stopped when a predetermined time has elapsed since the left reel 32L started rotating.

[0018] Note that the rotation of each reel 32L, 32M, 32R is started based on the operation of the start lever 41, and each reel 32L, 32M, 32R stops rotating based on the operation of each stop button 42, 43, 44. The period until the execution of various processes such as the awarding of game media and the management of the game state is completed corresponds to one game (or game round).

[0019] On the upper right side of the operation projection part 25, there is a medal insertion port 45 for inserting medals. Medals inserted from the medal insertion port 45 are guided to the hopper device 53 in the housing 11 by a selector 52 provided on the back surface of the front door 12 if they can be inserted, and are guided to the medal tray 59 from a medal discharge port 58 provided at the lower front part of the front door 12 if they cannot be inserted. The hopper device 53 has a function of paying out the medals stored in the storage tank to the medal tray 59 through the medal discharge port 58 when a winning corresponding to the awarding of medals is established on the active line.

[0020] At a position below the medal insertion port 45 on the front surface of the operation projection part 25, there is a return button 46 that is pressed when the medals inserted into the medal insertion port 45 are jammed in the selector 52. Also, on the upper left side of the operation projection part 25, there are a first credit insertion button 47 for inserting the maximum number of virtual medals that can be bet at one time, which are stored in the RAM 144 of the main control device 140 described later, a second credit insertion button 48 for inserting two virtual medals at one time, and a third credit insertion button 49 for inserting one virtual medal at one time. In this slot machine 10, the gaming medium is a concept including medals and virtual medals.

[0021] At a position to the left of the start lever 41 on the front surface of the operation projection part 25, there is a settlement button 51. This slot machine 10 has a credit function of storing surplus inserted medals and payout medals at the time of winning as virtual medals in the RAM 144 of the main control device 140 described later until a predetermined maximum value (equivalent to 50 medals) is reached. When the settlement button 51 is operated in a situation where virtual medals are stored, the virtual medals are paid out as real medals from the medal discharge port 58.

[0022] Inside the housing 11, on the left side of the hopper device 53, a power supply device 54 is provided. The power supply device 54 includes a power switch that is operated when the power is turned on or off, a reset button for resetting various states of the slot machine 10, and a setting key insertion hole that is operated to change the setting state of the slot machine 10 within the range from "Setting 1" to "Setting 6".

[0023] <The symbols attached to each reel 32L, 32M, 32R> Next, the symbols attached to each reel 32L, 32M, 32R will be described.

[0024] Figure 2 shows the symbol arrangements of the left reel 32L, the middle reel 32M, and the right reel 32R. As shown in the figure, 21 symbols are arranged in a row on each of the reels 32L, 32M, 32R. Also, numbers from 0 to 20 are assigned corresponding to each of the reels 32L, 32M, 32R, but these numbers are for the main control device 140 to recognize the symbols that can be visually confirmed from the display window parts 21L, 21M, 21R, and are not actually attached to the reels 32L, 32M, 32R. However, in the following description, these numbers will be used for the explanation.

[0025] The symbols include 7 types: "Bell" symbol (for example, the 20th on the left reel 32L), "Replay" symbol (for example, the 19th on the left reel 32L), "Watermelon" symbol (for example, the 18th on the left reel 32L), "Red 7" symbol (for example, the 15th on the left reel 32L), "BAR" symbol (for example, the 10th on the left reel 32L), "Cherry" symbol (for example, the 9th on the left reel 32L), and "White 7" symbol (for example, the 5th on the left reel 32L). And the number and arrangement order of various symbols on each of the reels 32L, 32M, 32R are completely different.

[0026] FIG. 3 is a front view of the display window portions 21L, 21M, and 21R. Each of the display window portions 21L, 21M, and 21R is formed such that among the 21 symbols attached to the corresponding reels 32L, 32M, and 32R, three symbols are visible in their entirety. For this reason, when all of the reels 32L, 32M, and 32R are stopped, nine symbols are in a visible state through the display window portions 21L, 21M, and 21R.

[0027] In this slot machine 10, one main line ML is set so as to connect the positions where the symbols of each of the reels 32L, 32M, and 32R are visible. The main line ML is a line connecting the middle symbols of the left reel 32L, the middle symbol of the middle reel 32M, and the middle symbol of the right reel 32R. When the rotation of each of the reels 32L, 32M, and 32R is started with a specified number of game media bet, and a winning corresponding to a winning combination is established on the main line ML, at least one of the benefits of awarding game media, the benefit of re - gaming, and the transition of the game state is given.

[0028] That is, in this slot machine 10, only one main line ML is set as the line on which a winning can be established. And the main line ML is set as a line extending in a straight line. Therefore, even if a combination of symbols that is a winning target is established on lines such as a sub - line S1 connecting the upper symbol of the left reel 32L, the middle symbol of the middle reel 32M, and the lower symbol of the right reel 32R, a sub - line S2 connecting the upper symbol of the left reel 32L, the upper symbol of the middle reel 32M, and the upper symbol of the right reel 32R, a sub - line S3 connecting the lower symbol of the left reel 32L, the lower symbol of the middle reel 32M, and the lower symbol of the right reel 32R, and a sub - line S4 connecting the lower symbol of the left reel 32L, the middle symbol of the middle reel 32M, and the upper symbol of the right reel 32R, no winning is established.

[0029] Hereinafter, with reference to FIG. 4, the correspondence between the winning symbol combinations and the benefits awarded when winning will be described. FIG. 4 is an explanatory diagram for explaining the correspondence between the winning symbol combinations and the benefits awarded when winning.

[0030] As minor winning awards for which game media are awarded, there are a first supplementary winning award, a second supplementary winning award, a third supplementary winning award, a bell winning award, a watermelon winning award, and a cherry winning award. Specifically, when the stop symbol of the left reel 32L on the main line ML is the "bell" symbol, the stop symbol of the middle reel 32M is the "replay" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a first supplementary winning award. Also, when the stop symbol of the left reel 32L on the main line ML is the "watermelon" symbol, the stop symbol of the middle reel 32M is the "bell" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a second supplementary winning award. Also, when the stop symbol of the left reel 32L on the main line ML is the "replay" symbol, the stop symbol of the middle reel 32M is the "bell" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a third supplementary winning award. The number of game media to be awarded in the case of any of the first supplementary winning award to the third supplementary winning award is "1" in a game state other than the BB state described later. On the other hand, the first supplementary winning award to the third supplementary winning award are excluded from the winning targets in the BB state described later.

[0031] When the stop symbol of the left reel 32L on the main line ML is the "bell" symbol, the stop symbol of the middle reel 32M is the "bell" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a bell winning award. The number of game media to be awarded in the case of a bell winning award is "9" in a game state other than the BB state described later, and "8" in the BB state described later.

[0032] When the stop symbol of the left reel 32L on the main line ML is the "Watermelon" symbol, the stop symbol of the middle reel 32M is either the "Watermelon" symbol or the "Cherry" symbol, and the stop symbol of the right reel 32R is either the "Watermelon" symbol or the "White 7" symbol, a watermelon win occurs. The number of gaming media to be awarded in the case of a watermelon win is "7" in a gaming state other than the BB state, and "8" in the BB state described later.

[0033] When the stop symbol of the left reel 32L on the main line ML becomes the "Cherry" symbol, a cherry win occurs regardless of the stop symbols of the middle reel 32M and the right reel 32R. The number of gaming media to be awarded in the case of a cherry win is "2" in a gaming state other than the BB state. On the other hand, a cherry win is excluded from the winning targets in the BB state.

[0034] As winning awards with the privilege of replay that enable playing the next game without betting on gaming media, there are a normal replay award, a first RT replay award, a second RT replay award, a first fall replay award, and a second fall replay award. Specifically, on the main line ML, when the stop symbol of the left reel 32L is the "replay" symbol, the stop symbol of the middle reel 32M is the "replay" symbol, and the stop symbol of the right reel 32R is the "replay" symbol, or when the stop symbol of the left reel 32L is the "replay" symbol, the stop symbol of the middle reel 32M is the "cherry" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a normal replay award. On the main line ML, when the stop symbol of the left reel 32L is the "bell" symbol, the stop symbol of the middle reel 32M is the "replay" symbol, and the stop symbol of the right reel 32R is the "replay" symbol, it is a first RT replay award. On the main line ML, when the stop symbol of the left reel 32L is the "watermelon" symbol, the stop symbol of the middle reel 32M is the "replay" symbol, and the stop symbol of the right reel 32R is the "replay" symbol, it is a second RT replay award. On the main line ML, when the stop symbol of the left reel 32L is the "replay" symbol, the stop symbol of the middle reel 32M is the "cherry" symbol, and the stop symbol of the right reel 32R is the "replay" symbol, it is a first fall replay award. On the main line ML, when the stop symbol of the left reel 32L is the "replay" symbol, the stop symbol of the middle reel 32M is the "replay" symbol, and the stop symbol of the right reel 32R is the "bell" symbol, it is a second fall replay award.

[0035] When any of the above replay awards is won, it becomes possible to play the next game without the need for a new bet on the gaming media. Specifically, in a game where three gaming media are bet, when any of the replay awards is won, it becomes possible to start the next game in a state where three gaming media are bet without the need for a new bet on the gaming media.

[0036] Among the above various replay winning awards, the first RT replay winning award, the second RT replay winning award, the first fall replay winning award, and the second fall replay winning award not only serve as an opportunity to grant the benefits of the replay winning award but also as an opportunity to shift the lottery mode. In this slot machine 10, a plurality of lottery modes are set so that the types of roles subject to lottery and the winning probabilities of each role are different in the lottery process of the role (Figure 11). The transition between these lottery modes occurs when a replay winning award that serves as an opportunity to shift the lottery mode is established.

[0037] As state transition winning awards where only the transition of the game state is performed, there are the first BB winning award and the second BB winning award. Specifically, when the stop symbol of the left reel 32L on the main line ML is the "red 7" symbol, the stop symbol of the middle reel 32M is the "red 7" symbol, and the stop symbol of the right reel 32R is the "red 7" symbol, it is the first BB winning award. When the stop symbol of the left reel 32L on the main line ML is the "white 7" symbol, the stop symbol of the middle reel 32M is the "white 7" symbol, and the stop symbol of the right reel 32R is the "white 7" symbol, it is the second BB winning award. When the first BB winning award or the second BB winning award is established, the game state shifts to the BB state. Here, the BB state is a game state in which the expected number of game media granted per unit game number is higher than any other game state except the BB state.

[0038] Specifically, it wins in a higher probability (for example, 1 / 2) than in other gaming states for the role that enables the Bell winning to occur. When winning for that role, the Bell winning occurs regardless of the stop order of each reel 32L, 32M, 32R and the stop operation timing of the stop buttons 42 to 44 with respect to the rotational positions of each reel 32L, 32M, 32R. Also, it wins in a higher probability (for example, 1 / 4) than in other gaming states for the role that enables the Watermelon winning to occur. When winning for that role, the Watermelon winning occurs regardless of the stop order of each reel 32L, 32M, 32R and the stop operation timing of the stop buttons 42 to 44 with respect to the rotational positions of each reel 32L, 32M, 32R. As a result, even in a configuration where there are multiple types of winning awards that are the objects of granting game media in the BB state, when winning for the role corresponding to the winning award that is the object of granting game media, the winning corresponding to that winning role will surely occur. Also, the number of game media granted when these Bell winning and Watermelon winning occur is the same number, specifically, it is "8". As a result, even in a configuration where there are multiple types of winning awards that are the objects of granting game media in the BB state, the number of game media granted when the winning occurs is the same number regardless of the type of winning award.

[0039] The BB state continues across multiple games and ends when an end condition is met based on the occurrence of an event according to the execution content of the game. The end condition is arbitrary, but in this slot machine 10, it is set as an end condition that the total number of game media granted since the start of the BB state is equal to or more than the end reference number. The BB state is set to a first BB state and a second BB state, and the end reference numbers are different between these first BB state and second BB state. In the first BB state, the end reference number is more than 5 times the fixed grant number when a winning that is the target of granting game media occurs in the BB state and is equal to or less than 6 times the fixed grant number. Specifically, it is set to "41". On the other hand, in the second BB state, the end reference number is more than 11 times the fixed grant number when a winning that is the target of granting game media occurs in the BB state and is equal to or less than 12 times the fixed grant number. Specifically, it is set to "89". With this configuration, in the first BB state, the winning that is the target of granting game media is surely established only 6 times, and in the second BB state, the winning that is the target of granting game media is surely established only 12 times. Also, in a configuration where there are multiple types of winning that are the target of granting game media in the BB state, when winning a role corresponding to the winning that is the target of granting game media, the winning corresponding to the winning role is surely established. Therefore, in the first BB state, only 6 games in which the player wins a role corresponding to the winning that is the target of granting game media surely occur, and in the second BB state, only 12 games in which the player wins a role corresponding to the winning that is the target of granting game media surely occur.

[0040] <Device for executing various notifications and various effects> Next, a device for executing various notifications and various effects will be described.

[0041] As shown in Fig. 1, an upper lamp 64 and an image display device 66 are provided above the front door 12, and a speaker 65 is provided below the front door 12. The upper lamp 64 is subjected to light emission control in a manner corresponding to the abnormality when an abnormality occurs in the slot machine 10, and is also subjected to light emission control in a manner corresponding to the winning result. Further, the upper lamp 64 is subjected to light emission control so that a light emission effect corresponding to the display effect in the image display device 66 is performed. The speakers 65 are provided as a pair on the left and right, and when an abnormality occurs in the slot machine 10, sound output control is performed so that a sound or voice corresponding to the abnormality is output, and sound output control is performed so that a sound or voice corresponding to the winning result is output. Further, the speaker 65 is subjected to sound output control so that a sound output effect corresponding to the display effect in the image display device 66 is performed.

[0042] The image display device 66 has a display surface 66a, and when an abnormality occurs in the slot machine 10, display control is performed so that an image corresponding to the abnormality is displayed on the display surface 66a. Further, the image display device 66 performs display control so that images corresponding to the winning results of the roles in the internal lottery and the winning results in each game are displayed on the display surface 66a.

[0043] <Electrical Configuration of Slot Machine 10> Next, the electrical configuration of this slot machine 10 will be described based on the block diagram of Fig. 5.

[0044] The main control device 140 includes a main control board 141 that controls the main game. An MPU 142 equipped with a hardware random number circuit 146 and a control IC 148 is mounted on the main control board 141. The hardware random number circuit 146 includes a random number generation means and the like for updating the random numbers used in the winning or losing lottery of the roles. Details of the hardware random number circuit 146 will be described later. It should be noted that it is not an essential configuration that the hardware random number circuit 146 and the control IC 148 are integrated into one chip with respect to the MPU 142, and they may be individually chipped.

[0045] The control IC 148 is a CPU that executes main processing (Figure 7) and timer interrupt processing (Figure 8) using a program. The control IC 148 incorporates a ROM 143 that stores various control programs and fixed-value data executed by the control IC 148, and a RAM 144 that is a memory for temporarily storing various data and the like when executing the control programs stored in the ROM 143. Further, the control IC 148 is provided with a clock circuit 145 that outputs a clock signal with a predetermined period, and a frequency division circuit 147 is provided at an intermediate position in the signal path between the clock circuit 145 and the control unit of the control IC 148.

[0046] The frequency division circuit 147 functions as a frequency changing means for changing the period of the clock signal from the clock circuit 145, and is configured to output a changed clock signal for specifying the activation timing of the timer interrupt processing by the control IC 148. Specifically, the frequency division circuit 147 outputs a changed clock signal with an interval of a specific period of 1.49 msec to the control IC 148. The control IC 148 executes a process of confirming the occurrence of a specific signal form such as the rising or falling of such a changed clock signal, and activates periodic processing (timer interrupt processing) with the occurrence of the specific signal form as at least one condition. In this case, the execution period of the periodic processing is the period (1.49 msec) of the changed clock signal.

[0047] Note that it is not an essential configuration that the ROM 143 and the RAM 144 are integrated into one chip with respect to the control IC 148, and they may be configured as individual chips.

[0048] The MPU 142 is provided with an input port and an output port, respectively. On the input side of the MPU 142, there are connected various sensors such as a reel unit 31 (more specifically, a reel index sensor that individually detects that each of the reels 32L, 32M, and 32R has made one rotation), stop detection sensors 42a, 43a, and 44a that individually detect the operations of the respective stop buttons 42, 43, and 44, a inserted medal detection sensor 45a that detects the medals inserted from the medal insertion slot 45, credit insertion detection sensors 47a, 48a, and 49a that individually detect the operations of the respective credit insertion buttons 47, 48, and 49, a settlement detection sensor 51a that detects the operation of the settlement button 51, a payout detection sensor of the hopper device 53, a reset detection sensor 56a that detects the operation of the reset button 56, a setting key detection sensor 57a that detects that a setting key has been inserted into the setting key insertion hole 57, etc. Signals from these respective sensors are input into the MPU 142.

[0049] Here, a detection signal SG1 from a start detection sensor 41a that detects the operation of the start lever 41 is input into a hardware random number circuit 146 and a control IC 148. The detection signal SG1 is a signal that rises from a LOW state to a HI state when the start lever 41 is depressed by the player and returns from the HI state to the LOW state when the depression operation ends. Details of the connection mode between the start detection sensor 41a and the hardware random number circuit 146, and the connection mode between the start detection sensor 41a and the control IC 148 will be described later.

[0050] On the output side of the MPU 142, there are connected a reel unit 31 (more specifically, a stepping motor for rotating each of the reels 32L, 32M, and 32R), a payout motor of the hopper device 53, a sub-control device 150, etc. In each game, the rotation drive control of each of the reels 32L, 32M, and 32R of the reel unit 31 is performed by the MPU 142, and when a small winning combination is established and the payout of medals is executed, the drive control of the hopper device 53 is performed by the MPU 142. Also, commands are transmitted from the MPU 142 to the sub-control device 150 at each timing of each game.

[0051] On the input side of the MPU 142, a power failure monitoring circuit provided in the power supply device 54 is connected (not shown). The power supply device 54 is equipped with a power supply unit that supplies driving power to each electronic device of the slot machine 10 including the main control device 140, and a power failure monitoring circuit. The power failure monitoring circuit monitors the voltage applied from the external power supply to the power supply unit, and outputs a power failure signal to the MPU 142 when the voltage drops below the reference voltage. The MPU 142 executes processing during a power failure upon receiving the power failure signal, and enables a return to the processing state before the power failure after the restoration of power. Further, the power supply device 54 is provided with a power supply unit during power failure for supplying backup power as power during power failure to the RAM 144 in a situation where the supply of operating power from the external power supply is interrupted. Thereby, even in a situation where the supply of operating power from the external power supply is interrupted, data is stored and held in the RAM 144 in a situation where backup power can be supplied by the power supply unit during power failure (for example, for one or two days). However, by performing the ON operation of the power of the slot machine 10 while pressing the reset button provided in the power supply device 54, the data stored and held in the RAM 144 is initialized.

[0052] The sub-control device 150 includes a sub-control board 151 for executing execution control of various notifications and various effects. An MPU 152 is mounted on the sub-control board 151. The MPU 152 stores a ROM 153 that stores various control programs and fixed-value data executed by the MPU 152, a RAM 154 that is a memory for temporarily storing various data and the like when executing the control programs stored in the ROM 153, a clock circuit 155 that outputs a rectangular wave of a predetermined frequency, and a built-in interrupt circuit, data input / output circuit, random number generation circuit, and the like.

[0053] Note that it is not an essential configuration that the ROM 153 and the RAM 154 are integrated into one chip with respect to the MPU 152, and they may be configured as individual chips. Further, in the RAM 154, backup power is supplied from the power-off power supply unit of the power supply device 54 in a situation where the supply of operating power from an external power supply is cut off, and data is stored and held in the RAM 154 in a situation where the backup power is supplied (for example, one or two days). However, by performing the ON operation of the power supply of the slot machine 10 while pressing the reset button 56 provided in the power supply device 54, the data stored and held in the RAM 154 is initialized.

[0054] The MPU 152 is provided with an input port and an output port, respectively. On the input side of the MPU 152, the MPU 142 of the main control device 140 is connected as already described, and various commands are received from the MPU 142.

[0055] On the output side of the MPU 152, an upper lamp 64, a speaker 65, and an image display device 66 are connected. The MPU 152 executes light emission control of the upper lamp 64, sound output control of the speaker 65, and display control of the image display device 66 based on the commands received from the MPU 142 of the main control device 140, so as to perform various notifications and various effects.

[0056] In the following description, for convenience of explanation, the MPU 142, the ROM 143, and the RAM 144 of the main control device 140 are referred to as the main-side MPU 142, the main-side ROM 143, and the main-side RAM 144, respectively, and the MPU 152, the ROM 153, and the RAM 154 of the sub-control device 150 are referred to as the sub-side MPU 152, the sub-side ROM 153, and the sub-side RAM 154, respectively.

[0057] <Configuration of the main control board 141> Next, the configuration of the main control board 141 will be described in detail with reference to the block diagram of FIG. 6.

[0058] As shown in FIG. 6, the control IC 148 includes input terminals TA1 to TA3 and an output terminal TA4. Further, as shown in FIG. 6, the hardware random number circuit 146 includes an update circuit 101 for updating a random number used for determining the success or failure of a role, a latch register 102 into which the random number updated by the update circuit 101 is written, and a control circuit 103 capable of grasping the timing at which the start lever 41 is operated using the detection signal SG1.

[0059] The control circuit 103 includes a CPU 114 that executes processing using a program. The CPU 114 included in the control circuit 103 is referred to as a control-side CPU 114. The control-side CPU 114 includes a ROM 115 in which a program for executing a management operation (FIG. 19) is stored, a RAM 116 having an area for temporarily storing information, input terminals TB1 and TB2, and output terminals TB3 and TB4.

[0060] Here, in the management operation (FIG. 19), the control-side CPU 114 detects the rising edge of the detection signal SG1 input to the control-side CPU 114 from the LOW state to the HI state, and when it is determined that the HI state of the detection signal SG1 is maintained until 12.8 μs has elapsed from the timing of the detection, a latch signal that is a pulse signal is transmitted to the latch register 102, and "1" is set in the latched status 113. Details of the management operation will be described later.

[0061] Next, the connection mode between the start detection sensor 41a and the control IC 148, and the connection mode between the start detection sensor 41a and the hardware random number circuit 146 will be described. As shown in FIG. 6, one signal line output from the start detection sensor 41a branches into two on the main control board 141. One of the signal lines is connected to the input terminal TA1 of the control IC 148, and the other of the signal lines is connected to the input terminal TB1 of the control-side CPU 114 that constitutes the hardware random number circuit 146. Therefore, when noise is mixed into one of the signal lines after branching, it is possible to avoid a situation where the influence of the noise reaches the other.

[0062] Next, the update circuit 101 will be described. As shown in FIG. 6, the update circuit 101 includes a clock circuit 104 that outputs a clock signal of a predetermined frequency (for example, 16 MHz), a random number generation circuit 106 that generates an M-sequence random number to be updated at each update timing, and a random number counter 105 that stores the random number. Here, the control IC 148 operates based on a clock circuit 145 (FIG. 5) within the control IC 148. On the other hand, the update circuit 101 operates based on a clock circuit 104 within the update circuit 101 that operates independently of the clock circuit 145 within the control IC 148. For this reason, the update timing of the random number in the update circuit 101 is not affected by the processing executed by the control IC 148.

[0063] The random number counter 105 has a 2-byte storage area, and random numbers from "1" to "65535" are stored in the random number counter 105. The 2-byte storage area is composed of 16 positive-edge type D flip-flop circuits (D-FFs). The D-FFs constituting the random number counter 105 are referred to as D-FFs 105a to 105p for the random number counter. The D-FFs 105a to 105p for the random number counter have a clock terminal (CLK terminal), a D terminal, and a clear terminal (CLR terminal) as input terminals, and a Q terminal as an output terminal.

[0064] As shown in FIG. 6, the signal line output from the clock circuit 104 branches into two within the update circuit 101, and one of the branched signal lines further branches into 16 within the update circuit 101 and is connected to the CLK terminals of 16 D-FFs 105a to 105p for the random number counter. For this reason, the clock signal output from the clock circuit 104 is input to the CLK terminals of the D-FFs 105a to 105p for the random number counter.

[0065] The other of the signal lines branched from the clock circuit 104 is connected to the random number generation circuit 106 via the inversion circuit 107. Triggered by the rising edge of the signal input to the random number generation circuit 106 via the inversion circuit 107, the 16-bit data output from the random number generation circuit 106 to the D terminals of the D-FFs 105a to 105p for the random number counter is updated. The D-FFs 105a to 105p for the random number counter output the signal input to the D terminal from the Q terminal at the timing when the signal input to the CLK terminal rises.

[0066] The update timing of the random number generated by the random number generation circuit 106 and the update timing of the random number stored in the random number counter 105 are offset by half the period of the signal output from the clock circuit 104. Therefore, in the update circuit 101, the update of the data output from the random number generation circuit 106 and the update of the signal output from the Q terminals of the 16 D-FFs 105a to 105p for the random number counter in the random number counter 105 are alternately repeated.

[0067] Specifically, since the clock signal output from the clock circuit 104 is 16 MHz, the clock signal rises with a period of 62.5 ns. Therefore, the data update in the random number generation circuit 106 occurs at a period of 62.5 ns, and the data in the random number counter 105 is updated between the update of the data in the random number generation circuit 106 and the update to the next data. As already described, since the execution period of the timer interrupt process executed by the control IC 148 is 1.49 msec, the random number update interval is sufficiently shorter than the execution period of the timer interrupt process. Note that a configuration may be adopted in which negative edge type D-FFs are used for the D-FFs 105a to 105p for the random number counter instead of positive edge type D-FFs.

[0068] Here, the random number stored in the random number counter 105 is a 16-bit binary number. Also, the random number generation circuit 106 is a hard circuit that generates an M-sequence random number. The M-sequence random number is a pseudo-random number with a period. And the period of the M-sequence random number updated by the random number generation circuit 106 is "65535". In the random number generation circuit 106, the second random number is generated based on a preset initial value other than "0", and the third random number is generated based on the second random number. In this way, in the random number generation circuit 106, the random number represented by a 16-bit binary number is updated, and after 65535 numbers are output to the random number counter 105 one by one, it returns to the initial value. In this way, in the M-sequence random number, the order of the random numbers output by the preset initial value is determined, and since each number from "1" to "65535" appears once within one period, the probability of winning a role can be set according to the number of numbers set as the numbers corresponding to the winning of the role.

[0069] Note that the random number updated by the random number counter 105 is not limited to the M-sequence random number. For example, every time the update circuit 101 reaches the update timing, "1" is added to the random number stored in the random number counter 105, and when the value of the random number counter 105 becomes "65535", the random number counter 105 may be cleared to "0". The main point is that the configuration should be such that the result of the win / loss determination of the role performed using the random number does not deviate to a specific result.

[0070] Next, the latch register 102 into which the numerical information of the random number stored in the random number counter 105 of the update circuit 101 is written will be described. The latch register 102 has a 2-byte storage area similar to the random number counter 105 of the update circuit 101. Specifically, the latch register 102 includes 16 positive edge-triggered D-FFs. The D-FFs constituting the latch register 102 are referred to as latch register D-FFs 102a to 102p. The latch register D-FFs 102a to 102p have a CLK terminal, a D terminal, and a CLR terminal as input terminals, and a Q terminal as an output terminal.

[0071] The D terminals of the D-FFs 102a to 102p for the latch register are connected to the signal lines coming from the Q terminals of the D-FFs 105a to 105p for the random number counter. Specifically, both the numerical information stored in the random number counter 105 of the update circuit 101 and the numerical information stored in the latch register 102 are 16-bit binary numbers. The Q terminals of the D-FFs 105a to 105p for the random number counter where the nth digit numerical information is stored in the random number counter 105 are connected to the D terminals of the D-FFs 102a to 102p for the latch register that store the nth digit numerical information in the latch register 102. Here, n is a natural number from 1 to 16.

[0072] The CLK terminals of the D-FFs 102a to 102p for the latch register are connected by signal lines to the output terminal TB4 of the control-side CPU 114. Specifically, one signal line coming from the output terminal TB4 of the control-side CPU 114 branches into 16 lines and enters the CLK terminals of the respective D-FFs 102a to 102p for the latch register. Also, the Q terminals of the D-FFs 102a to 102p for the latch register are connected to the input terminal TA3 of the control IC 148.

[0073] Next, the configuration for obtaining the numerical information of the random number used by the control IC 148 for the determination of the suitability of the role will be described. The control-side CPU 114 outputs a latch signal from the output terminal TB4 to the CLK terminals of the D-FFs 102a to 102p for the latch register when the detection signal SG1 input to the control-side CPU 114 rises from the LOW state to the HI state and the HI state is maintained for a certain period (12.8 μs).

[0074] Here, the latch signal is a pulse signal that rises from the LOW state to the HI state and then falls from the HI state to the LOW state. By configuring to wait for 12.8 μs after the detection signal SG1 input to the control circuit 103 rises, it is possible to prevent the latch signal from being transmitted triggered by noise less than 12.8 μs entering the input terminal TB1 of the control-side CPU 114.

[0075] Since the D-FFs 102a to 102p for the latch register are positive edge-triggered, when a latch signal is sent from the control-side CPU 114 to the latch register 102, the random numbers stored in the random number counter 105 are written into the latch register 102, and the written random numbers are output to the input terminal TA3 of the control IC 148.

[0076] Specifically, in synchronization with the rising edge of the signal input to the CLK terminals of the D-FFs 102a to 102p for the latch register, the numerical information that was output from the Q terminals of the D-FFs 105a to 105p for the random number counter and input to the D terminals of the D-FFs 102a to 102p for the latch register is output from the Q terminals of the D-FFs 102a to 102p for the latch register. When it is time to obtain the random numbers used for determining the success or failure of the role, the control IC 148 obtains the numerical information that is output from the Q terminals of the D-FFs 102a to 102p for the latch register and input to the input terminal TA3 of the control IC 148.

[0077] Note that the random number counter 105 and the latch register 102 may be configured to include negative edge-triggered D-FFs instead of positive edge-triggered D-FFs. Also, the random number counter 105 and the latch register 102 may be configured to include an RS flip-flop circuit or a JK flip-flop circuit instead of D-FFs.

[0078] Next, the latched status 113 will be described. As shown in FIG. 6, the control circuit 103 includes a latched status 113 in which "1" is set at the timing when the random number stored in the random number counter 105 is written into the latch register 102. The latched status 113 is a status register composed of one positive edge-triggered T flip-flop circuit (T-FF). The latched status, which is a T-FF, has a T terminal 113b and a CLR terminal 113c as input terminals, and a Q terminal 113a as an output terminal as shown in FIG. 6. The latched status 113 inverts the signal output from the Q terminal 113a in synchronization with the rising edge of the signal input to the T terminal 113b from the LOW state to the HI state.

[0079] Specifically, when a signal of "0" is being output from the Q terminal 113a, the signal output from the Q terminal 113a is inverted to "1" in synchronization with the rising edge of the signal input to the T terminal 113b. Also, when a signal of "1" is being output from the Q terminal 113a, the signal output from the Q terminal 113a is inverted to "0" in synchronization with the rising edge of the signal input to the T terminal 113b. The signal output from the Q terminal 113a is cleared to "0" when the signal input to the CLR terminal 113c rises from the LOW state to the HI state.

[0080] Here, the state in which "0" is set in the latched status 113 is the state in which "0" is being output from the Q terminal 113a of the latched status 113. Also, the state in which "1" is set in the latched status 113 is the state in which "1" is being output from the Q terminal 113a of the latched status 113.

[0081] The T terminal 113b of the latched status 113 is connected to the output terminal TB3 of the control-side CPU 114 by a single signal line. When the value “0” is set in the latched status 113, the control-side CPU 114 sends a short pulse signal to the T terminal 113b of the latched status 113, thereby inverting the signal output from the Q terminal 113a of the latched status 113 and setting the value “1” in the latched status 113.

[0082] Specifically, when the control-side CPU 114 detects that the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 has risen from the LOW state to the HI state and determines that the HI state has continued for 12.8 μs or more, the control-side CPU 114 transmits a latch signal from the output terminal TB4 to the CLK terminals of the D-FFs 102a to 102p for the latch register, and transmits a pulse signal from the output terminal TB3 to the T terminal 113b of the latched status 113 to set the value “1” in the latched status 113. For this reason, when the numerical information of the random number stored in the random number counter 105 is written into the latch register 102, the value “1” is set in the latched status 113.

[0083] The control-side CPU 114 raises the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113 on the condition that the value “0” is set in the latched status 113, thereby inverting the signal output from the Q terminal 113a of the latched status 113 from the LOW state to the HI state. As a result, the value “1” is set in the latched status 113. When the value “1” has already been set in the latched status 113, the control-side CPU 114 maintains the state in which the value “1” is set in the latched status 113 without transmitting a pulse signal. For this reason, even if the start lever 41 is operated when the value “1” is set in the latched status 113, the value set in the latched status 113 does not invert from “1” to “0” due to this operation.

[0084] Here, when the control-side CPU 114 determines that the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 rises from the LOW state to the HI state and the HI state continues for 12.8 μs or more, even if "1" is set in the latched status 113, a latch signal is output to the latch register 102 to update the numerical information of the random number stored in the latch register 102.

[0085] A specific example will be given below to explain the situation where the start lever 41 is operated with "1" set in the latched status 113. Noise may be input only to the input terminal TB1 of the control-side CPU 114, causing "1" to be set in the latched status 113. Here, the control IC 148 starts the game on the conditions that it is a period when the game can be started, the rise of the detection signal SG1 is detected in the control IC 148, and "1" is set in the latched status 113.

[0086] Therefore, even if "1" is set in the latched status 113 due to noise entering the input terminal TB1 of the control-side CPU 114, since the rise of the detection signal SG1 is not detected in the control IC 148, the game is not started and the state where "0" is set in the latched status 113 is maintained. In this state, when the start lever 41 is operated, the numerical information stored in the latch register 102 is updated to the numerical information of the random number corresponding to the current operation of the start lever 41 while the "1" set in the latched status 113 is maintained.

[0087] In this way, by adopting a configuration in which the random number stored in the latch register 102 is updated when the start lever 41 is operated with "1" set in the latched status 113, the possibility that the random number stored in the latch register 102 due to noise is used for the determination of success or failure of the role can be reduced.

[0088] Also, the signal line extending from the Q terminal of the latched status 113 branches into two on the control circuit 103. One of the branched signal lines is connected to the input terminal TA2 of the control IC 148, and the other of the branched signal lines is connected to the input terminal TB2 of the control-side CPU 114. Therefore, the signal output from the Q terminal 113a of the latched status 113 is input to both the control IC 148 and the control-side CPU 114.

[0089] The control IC 148 can determine whether or not "1" is set in the latched status 113 of the control circuit 103 by grasping the signal input to the input terminal TA2 of the control IC 148. Also, the control-side CPU 114 can determine whether or not "1" is set in the latched status 113 by grasping the signal input to the input terminal TB2 of the control-side CPU 114.

[0090] Also, the CLR terminal 113c of the latched status 113 is connected to the output terminal TA4 of the control IC 148 by a single signal line. The control IC 148 can clear the latched status 113 to "0" by raising the signal output to the CLR terminal 113c of the latched status 113 from the LOW state to the HI state.

[0091] When the control-side CPU 114 detects that the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 has risen from the LOW state to the HI state, it uses a timer counter to determine whether the HI state has been maintained for 12.8 μs. Specifically, counting by the timer counter is started at the timing when the rise of the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 from the LOW state to the HI state is detected. When the counting starts, the timer counter counts time in units of 0.1 μs. If the HI state of the detection signal SG1 is not maintained until the timer counter finishes counting 12.8 μs, the timer counter is reset.

[0092] Next, the conditions for the control IC 148 to obtain the random number input to the input terminal TA3 of the control IC 148 will be described. The control IC 148 obtains the random number input to the input terminal TA3 of the control IC 148 and uses it for determining the success or failure of the role under the conditions that it is a period during which the game can start, the rise of the detection signal SG1 input to the control IC 148 is detected, and "1" is set in the latched status 113 in the timer interrupt process (Fig. 8) executed at a cycle of 1.49 ms.

[0093] Since the random number input to the input terminal TA3 of the control IC 148 is updated to the random number for the operation of the start lever 41 this time at the timing when "1" is set in the latched status 113, by adopting a configuration in which the control IC 148 obtains the random number on the condition that "1" is set in the latched status 113, it is possible to avoid the control IC 148 from obtaining the random number before the update (the previous random number).

[0094] In The timing at which the player operates the start lever 41 is an arbitrary timing that is not affected by the timing at which the control IC 148 performs timer interrupt processing. For this reason, the timer interrupt processing may be executed before 12.8 μs has elapsed since the detection signal SG1 input to the control circuit 103 rises. At this time, the random number input to the input terminal TA3 of the control IC 148 is the previous random number. In this case, since the condition that "1" is set in the latched status 113 is not satisfied, the control IC 148 does not acquire a random number. In this case, since the game is not started by the operation of the start lever 41 this time, the player needs to operate the start lever 41 again.

[0095] <Processing executed by the control IC 148> Next, the processing executed by the control IC 148 will be described. First, the main processing started in the control IC 148 when the supply of operating power to the control IC 148 is started will be described with reference to the flowchart of FIG. 7.

[0096] In the main processing, first, initialization processing is executed (step S101). In the initialization processing, interrupts by timer interrupt processing are permitted, and further, various initial settings for the register group and I / O devices in the control IC 148 are performed.

[0097] After the initialization process is completed, it is determined whether the setting key is inserted into the setting key insertion hole 57 and the ON operation is performed (step S102). If the ON operation is performed (step S102: YES), and if the reset button 56 is not ON-operated when the power switch 55 is ON-operated (step S103: NO), a partial clear process is executed (step S104). If the reset button 56 is ON-operated when the power switch 55 is ON-operated (step S103: YES), a full clear process is executed (step S105). That is, when the setting value of the slot machine 10 is changed without performing an operation for initializing the main-side RAM 144, a partial clear process is executed, and when an operation for initializing the main-side RAM 144 is performed, a full clear process is executed.

[0098] In the partial clear process, a part of the areas in the main-side RAM 144 is initialized, and in the full clear process, all areas in the main-side RAM 144 are initialized. In the partial clear process, except for the area in which data indicating whether it is in the BB state is stored in the main-side RAM 144, the area in which data indicating the total number of gaming media granted in the BB state is stored, the area in which data indicating the type of lottery mode described later is stored, and the area in which data indicating the setting value is stored, each area of the main-side RAM 144 is cleared to "0". In this case, the area in which the winning combination is stored is cleared to "0". In the full clear process, all areas of the main-side RAM 144 are cleared to "0" including the areas that are not the execution targets of "0" clearing in the partial clear process. As a result, even if the partial clear process is executed, the BB state is maintained as the state before power-off, and when the full clear process is executed, it becomes the normal gaming state regardless of the state before power-off.

[0099] Note that the present invention is not limited to the above configuration, and when the power is turned off in the BB state and the partial clear process is executed, it may be configured to be in a state other than the BB state. Also, even if the partial clear process is executed, the area in which data indicating winning the BB combination is stored may not be cleared to "0".

[0100] After the processing of step S104 or step S105 is executed, a winning probability setting process is executed (step S106). In the winning probability setting process, the current setting value is read, provided that the setting key is inserted and turned ON, and the current setting value is displayed on a predetermined display unit provided on the gaming panel 20. If the area for storing setting value data in the main RAM 144 has been initialized immediately before the winning probability setting process, the setting value displayed on the predetermined display unit is "1," which corresponds to "Setting 1." In the winning probability setting process, the setting value is updated by 1 each time the reset button 56 is operated, and the updated setting value is displayed on the predetermined display unit. If the reset button 56 is operated when the setting value is "Setting 6," the setting value is updated to "Setting 1." The winning probability setting process is terminated when the setting key is released from ON after the start lever 41 is operated. In this case, the display of the setting value on the predetermined display unit is terminated.

[0101] After executing the winning probability setting process, a power restoration command is sent to the sub-side MPU 152 (step S107). The power restoration command is a command for the sub-side MPU 152 to recognize that the main process has ended after the supply of operating power to the control IC 148 has started, and that normal processing and timer interrupt processing can now be executed. Upon receiving the power restoration command, the sub-side MPU 152 executes processing corresponding to the start of the supply of operating power. In this case, if the all-clear process (step S105) has been executed, corresponding data is set in the power restoration command. When a power restoration command with this data set is received, the sub-side MPU 152 initializes the sub-side RAM 154; when a power restoration command without this data set is received, the sub-side MPU 152 does not initialize the sub-side RAM 154. After sending the power restoration command, the sub-side MPU 152 transitions to normal processing (step S108). The normal processing will be described in detail later.

[0102] If the setting key has not been turned on in the main process (step S102: NO), the power restoration process from step S109 onward is executed. The power restoration process is a process for restoring the state of the slot machine 10 to the state before the power was cut off. In the power restoration process, the main RAM 144 is checked to determine whether the setting value of the slot machine 10 is normal (step S109). Specifically, if the setting value is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or "7" or greater, it is determined to be abnormal. If the setting value is normal, it is checked whether a power outage flag is set to "1" (step S110). The power outage flag is provided in the main RAM 144, and if the supply of operating power to the control IC 148 is stopped and a predetermined power outage process is executed normally, the power outage flag is set to "1." If the power outage flag is set to "1," it is checked whether the RAM determination value is normal (step S111). Specifically, the checksum value of the main RAM 144 is checked to see if it is normal.

[0103] If the determinations in steps S109 to S111 are all affirmative, this means that the power outage processing at the time of the previous power outage was executed normally. In this case, the value of the stack pointer saved in the main RAM 144 is written to the stack pointer of the control IC 148, and the data saved in the main RAM 144 is restored to the register of the control IC 148, thereby restoring the state of the register of the control IC 148 to the state before the power was cut off (step S112). In addition, the power outage flag of the main RAM 144 is cleared to "0" (step S113). Thereafter, a power recovery command is sent to the sub-MPU 152 (step S114), and then the address before the power was cut off is restored (step S115).

[0104] On the other hand, when a negative determination is made in any of steps S109 to S111, an operation prohibition process is executed. In the operation prohibition process, the execution of the next timer interrupt process (Fig. 8) is prohibited (step S116), all output ports of the control IC 148 are cleared to "0" to turn off all actuators connected to the output ports (step S117), and an error notification process for notifying the hall administrator or the like of the occurrence of an error is executed (step S118). Then, an infinite loop occurs. The operation prohibition process is released when the all-clear process (step S105) is executed.

[0105] Next, the timer interrupt process executed by the control IC 148 will be described with reference to the flowchart of Fig. 8. Note that the timer interrupt process is activated every 1.49 msec.

[0106] In the register save process (step S201), the values of all registers in the control IC 148 used in the normal process described later are saved to the main-side RAM 144. In step S202, it is checked whether the power failure flag is set to "1". When the power failure flag is set to "1", the process proceeds to step S203 and the power failure process is executed. The power failure flag is set when a power failure signal from the power failure monitoring circuit of the power supply device 54 is input to the control IC 148. In the power failure process, first, it is determined whether the transmission of the command has been completed. If the transmission has not been completed, this process is terminated and the timer interrupt process is resumed to complete the transmission of the command. When the transmission of the command has been completed, the value of the stack pointer of the control IC 148 is saved to the main-side RAM 144. Thereafter, the output state of the output port of the control IC 148 is cleared and all actuators (not shown) are turned off. Then, a determination value for determining whether the data in the main-side RAM 144 is normal when the power failure is resolved is calculated and saved to the main-side RAM 144, and subsequent RAM access is prohibited. After performing the above processes, in preparation for the power supply being completely cut off and the process being unable to be executed, an infinite loop is entered.

[0107] If the power failure flag is not set to "1" in step S202, various processes after step S204 are performed. In step S204, a watchdog timer clear process is performed to initialize the value of the watchdog timer for monitoring the occurrence of malfunction. In step S205, an interrupt end declaration process is performed to enable the control IC148 itself to set the next timer interrupt. In step S206, a start command setting process (Fig. 9) is executed.

[0108] In the start command setting process, the start command flag 144c (Fig. 6) is set to "1" on the condition that a random number corresponding to the current operation of the start lever 41 has already been input to the input terminal of the control IC148. When the start command flag 144c is set to "1", a random number will be acquired in step S501 of the lottery process (Fig. 11) described later. Here, the random number corresponding to the current operation of the start lever 41 is the random number that is written from the random number counter 105 to the latch register 102 when the detection signal SG1 rises from the LOW signal to the HI signal due to the operation of the start lever 41, and the rise of the detection signal SG1 is used as an opportunity.

[0109] On the other hand, if the random number input to the input terminal of the control IC148 has not been updated to the random number corresponding to the current operation of the start lever 41, the start command flag 144c is not set to "1". In this situation, the control IC148 does not acquire a random number. Here, the situation where the random number corresponding to the current operation of the start lever 41 is not acquired is a situation where the start command setting process is executed before 12.8 μsec has elapsed after the detection signal SG1 input to the input terminal of the control circuit 103 rises from the LOW signal to the HI signal. Details of the start command setting process will be described later.

[0110] In step S207, a stepping motor control process is performed to drive each stepping motor to rotate each reel 32L, 32M, and 32R. In step S208, the status of various sensors connected to the input ports is read, and a sensor monitoring process is performed to monitor whether the read results are normal. In step S209, a timer subtraction process is performed to subtract values from each counter and timer. In step S210, a counter process is performed to output the count results of the number of gaming media bets and the number of payouts to the outside.

[0111] In step S211, a command output process is performed to send various commands to the sub-side MPU 152. In step S212, a port output process is performed to output data corresponding to the I / O device from the input / output port. In step S213, the values of each register saved in the main-side RAM 144 in the previous step S201 are restored to the corresponding register in the control IC 148. Thereafter, in step S214, an interrupt enable process is performed to enable the next timer interrupt, and this series of timer interrupt processes is terminated.

[0112] Next, the start command setting process executed in step S206 of the timer interrupt process (FIG. 8) will be described with reference to the flowchart of FIG. 9. The start command setting process is executed by the control IC 148.

[0113] First, in step S301, it is determined whether or not the start possible flag 144a (FIG. 5) is set to "1." Here, the start possible flag 144a is a flag stored in the main RAM 144, and is set to "1" when it is possible to start a game, and is cleared to "0" when the game has started. Specifically, the start possible flag 144a is set to "1" in step S406 of the normal processing (FIG. 10) described later, and is cleared to "0" in step S409. If it is possible to start a game (step S301: YES), the process proceeds to step S302.

[0114] In step S302, it is determined whether the signal storage flag 144d (FIG. 5) is "0." Here, the signal storage flag 144d is a flag stored in the main RAM 144. The signal storage flag 144d stores the state of the detection signal SG1 input to the control IC 148 at the time when the start command setting process is performed. The signal storage flag 144d is set to "1" when the detection signal SG1 is in a HI state, and is cleared to "0" when the detection signal SG1 is in a LOW state.

[0115] Specifically, in steps S304 and S315 of this start command setting process, the signal storage flag 144d is set to "1," and in step S314, the signal storage flag 144d is cleared to "0." In step S302, if the signal storage flag 144d is "0" (step S302: YES), the process proceeds to step S303.

[0116] In step S303, it is determined whether the detection signal SG1 input to the control IC 148 is in a HI state. A positive determination in step S303 means that the detection signal SG1, which was in a LOW state in the previous start command setting process, has become a HI state in this start command setting process. In other words, this means that a rising edge of the detection signal SG1 has been detected. If a rising edge of the detection signal SG1 has been detected (step S303: YES), in step S304, the signal storage flag 144d is set to "1." This stores the fact that the detection signal SG1 input to the control IC 148 was in a HI state at the time when the current start command setting process was performed.

[0117] In the next step S305, it is determined whether or not "1" is set in the latched status 113. Specifically, it is determined whether or not the numerical information output from the Q terminal of the latched status 113 and input to the input terminal of the control IC 148 is "1."

[0118] If the latched status 113 is set to "1" (step S305: YES), this means that the random number corresponding to the current operation of the start lever 41 has already been stored in the latch register 102, and therefore, in step S306, the start command flag 144c (FIG. 5) is set to "1." Here, the start command flag 144c is a flag stored in the main RAM 144. If the start command flag 144c is set to "1," the processing from step S408 onward of the normal processing (FIG. 10), which will be described later, is executed to start the game. The start command flag 144c is cleared to "0" in step S408 of the normal processing (FIG. 10).

[0119] In the following step S307, the error counter 144b (FIG. 5) is cleared to "0," and in step S308, the latched status 113 is cleared to "0," thereby terminating this start command setting process. Here, the error counter 144b is a counter arranged in the main RAM 144. The error counter 144b is a counter that counts the number of consecutive events that result in a negative determination when a rising edge of the detection signal SG1 input to the control IC 148 is detected in a state where the game can be started, and the control IC 148 determines whether or not "1" is set in the latched status 113 (when the process of step S305 is executed).

[0120] If "1" is not set in the latched status 113 (step S305: NO), then in step S309, "1" is added to the error counter 144b, and in step S310, it is determined whether the value of the error counter 144b is "3". If the value of the error counter 144b is "1" or "2" (step S310: NO), the current start command setting process is terminated as it is. On the other hand, if the value of the error counter 144b is "3" (step S310: YES), it means that the negative determination in step S305 has occurred three times in a row. In this case, the connection between the start detection sensor 41a and the control circuit 103 may be disconnected, and the detection signal SG1 may not reach the control circuit 103. Therefore, in step S311, the error counter 144b is cleared to "0", and in step S312, an abnormality notification process is performed and an infinite loop is entered.

[0121] In the abnormality notification process, an abnormality notification indicating that an abnormality has occurred is executed by the upper lamp 64, the speaker 65, and the image display device 66, and an external output for abnormality is performed to the hall computer of the game hall. By notifying the administrator of the game hall that the connection between the start detection sensor 41a and the control circuit 103 may be disconnected, it is possible to avoid a situation where the game does not start even when the start lever 41 is operated.

[0122] If "1" is not set in the startable flag 144a in step S301, or if the signal storage flag is not "0" in step S302, then a process of storing the state of the detection signal SG1 input to the control IC 148 at the timing when the current start command setting process was performed (the processes of steps S313 to S315) is executed.

[0123] Specifically, in step S313, it is determined whether the detection signal SG1 input to the control IC 148 is in a LOW state. If the detection signal SG1 is in a LOW state (step S313: YES), the signal storage flag 144d is cleared to "0" in step S314. If the detection signal SG1 is in a HIGH state (step S313: NO), the signal storage flag 144d is set to "1" in step S315.

[0124] In this start command setting process, if the rising edge of the detection signal SG1 input to the control IC 148 is not detected and therefore step S306 for setting the start command flag 144c to "1" is not performed, the latched status 113 is cleared to "0".

[0125] Specifically, after a negative determination in step S303, after the processing in step S314, or after the processing in step S315, the latched status 113 is cleared to "0" in step S316, and the start command setting process ends. More specifically, regarding step S316, the control IC 148 transmits a pulse signal to the CLR terminal of the latched status 113. The latched status 113 is cleared to "0" in synchronization with the rising edge of the signal input to the CLR terminal.

[0126] In this way, even if a rising edge of the detection signal SG1 is detected when the game can be started, by keeping the start command flag 144c at "0" if the latched status 113 is set to "0", it is possible to avoid a situation in which the random number stored in the latch register 102 before the current operation of the start lever 41 is acquired by the control IC 148 as the current random number.

[0127] Furthermore, if the start command setting process is executed within 12.8 μs after the detection signal SG1 input to the control circuit 103 rises, the latched status 113 is set to "1" after the start command setting process. Also, if noise of 12.8 μs or more is mixed only into the input terminal of the control circuit 103, the latched status 113 is set to "1." If the state in which the latched status 113 is set to "1" is maintained for a long time, the start lever 41 is more likely to be operated while the latched status 113 is set to "1."

[0128] In this case, the control IC 148 may acquire an old random number and determine whether the hand is successful or not based on the old random number, just as in the case where the latched status 113 is not used. In contrast, the control IC 148 may be configured to clear the latched status 113 to "0" in all start command setting processes in which the rising edge of the detection signal SG1 input to the control IC 148 is not detected, thereby reducing the possibility that the control IC 148 will acquire an old random number.

[0129] Next, the normal processing executed by the control IC 148 will be described with reference to the flowchart of FIG.

[0130] First, in step S401, an interrupt permission process is performed to permit the next timer interrupt, and in step S402, a start waiting process is executed. In the start waiting process, it is determined whether any replay wins occurred in the previous game. If any replay wins occurred, an automatic insertion process is performed to automatically insert virtual medals in the same number as the previous bet number, and the start waiting process is terminated. If no replay wins occurred, it is determined whether the settlement button 51 has been operated, and if the settlement button 51 has been operated, a medal return process is performed to pay out medals in the same number as the credited virtual medals.

[0131] At the start timing of the medal return process, the start possible flag 144a (FIG. 5) and the start command flag 144c (FIG. 5) are cleared to "0." By clearing the start possible flag 144a to "0" at the start timing of the medal return process, the period during which the game can be started ends. This makes it possible to avoid a situation in which the start command flag 144c may be set to "1" in the start command setting process (FIG. 9) even though the medals have been returned.

[0132] Also, there may be a case where the start command setting process (FIG. 9) is executed at a timing after a negative determination is made in step S407 and before the medal return process is executed in step S402, and the start command flag 144c is set to "1." If the medal return process is executed with the start command flag 144c set to "1" and the start command flag 144c is not cleared to "0," the game will start the next time the number of medals bet reaches the specified number, even if the player does not operate the start lever 41. In contrast, by clearing the start command flag 144c to "0" at the start of the medal return process, it is possible to avoid a situation in which the game starts before the player operates the start lever 41.

[0133] After the medal return process is completed or if the settlement button 51 has not been operated, it is determined whether medals have been inserted or the credit insertion buttons 47-49 have been operated between the previous start waiting process and the current start waiting process, and if either has been done, a medal insertion process is carried out to change the number of bets, etc., and the start waiting process is terminated. Also, if neither medals have been inserted nor the credit insertion buttons 47-49 have been operated between the previous start waiting process and the current start waiting process, the start waiting process is terminated.

[0134] After executing the waiting process for the start of step S402, in step S403, it is determined whether the number of bet medals has reached a specified number (in this embodiment, "3"). If the number of bets has not reached the specified number (step S403: NO), the process returns to the waiting process for the start of step S402. If the number of bets has reached the specified number (step S403: YES), in step S404, it is determined whether "1" is set in the startable flag 144a.

[0135] If "1" is not set in the startable flag 144a (step S404: NO), in step S405, a pulse signal is sent to the CLR terminal of the latched status 113 to clear the latched status 113 to "0". By clearing the latched status 113 to "0" immediately after the game becomes startable, it becomes possible to determine whether the start lever 41 has been operated after the game becomes startable, even if "1" was set in the latched status 113 before the game became startable.

[0136] After clearing the latched status 113 to "0" in step S405, in step S406, "1" is set in the startable flag 144a. The startable flag 144a is a flag that is set to "1" when the game is in a startable state and is cleared to "0" in step S409 with the start of the game.

[0137] After making an affirmative determination in step S404, or after performing the process of step S406, in step S407, it is determined whether "1" is set in the start command flag 144c. The start command flag 144c is a flag that is set to "1" when the start lever 41 is operated in a game startable state and a random number corresponding to the current operation of the start lever 41 is input to the input terminal of the control IC 148. If "1" is not set in the start command flag 144c (step S407: NO), the process returns to the waiting process for the start of step S402.

[0138] When "1" is set in the start command flag 144c (step S407: YES), the start command flag 144c is cleared to "0" in step S408, and the start enable flag 144a is cleared to "0" in step S409. When the start enable flag 144a is cleared to "0", a negative determination is made in step S301 of the start command setting process (Figure 9), and the processes after step S302 are not executed, so "1" is no longer set in the start command flag 144c during the game.

[0139] In step S410, after enabling the main line ML, a reception prohibition process is executed. By executing the reception prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal is discharged to the medal tray 59 without being detected by the inserted medal detection sensor 45a. In step S411, a lottery process (hereinafter also referred to as the role lottery process) for performing the role lottery in the current game is executed, and in step S412, a reel control process for driving and controlling each reel 32L, 32M, 32R in a manner corresponding to the result of the role lottery process in the current game is executed.

[0140] Here, the details of the reel control process will be described below. In the reel control process, first, a rotation start process for starting the rotation of each reel 32L, 32M, 32R is performed. In the rotation start process, it is confirmed whether a predetermined wait time (for example, 4.1 seconds) has elapsed since the rotation of the reels 32L, 32M, 32R corresponding to the result of the role lottery process (Figure 11) started in the previous game. If not, the process waits until the wait time has elapsed. The details of the role lottery process will be described later.

[0141] When the waiting time has elapsed, the waiting time for the next game is reset, and rotation start information is set in the motor control storage area provided in the main-side RAM 144. By performing such processing, the acceleration process of the stepping motor is started in the stepping motor control process of step S207 in the timer interrupt process (FIG. 8), and each reel 32L, 32M, 32R starts rotating. Thereafter, it waits until each reel 32L, 32M, 32R rotates at a predetermined rotational speed at a constant speed, and the rotation start process ends. Further, when the rotational speeds of the respective reels 32L, 32M, 32R become constant speeds, the control IC 148 lights up lamps (not shown) of the respective stop buttons 42 to 44 to notify the player or the like that it has become possible to generate a stop command.

[0142] Thereafter, it is determined that a stop command has been generated on the condition that any one of the stop buttons 42 to 44 has been operated and the operated stop buttons 42 to 44 are the stop buttons 42 to 44 corresponding to the rotating reels. It waits until the conditions for generating the stop command are satisfied, and when the stop command is generated, a stop command is set. The stop command is a command for causing the sub-side MPU 152 to recognize which of the stop buttons 42 to 44 has been operated to generate the stop command. When the stop command is set, a stop control process for stopping the rotating reel is performed.

[0143] In the stop control process, the symbol number of the reached symbol that has reached the base position (the lower stage in this embodiment) at the timing when the stop buttons 42 to 44 are operated is confirmed. Specifically, the symbol number of the reached symbol that has reached the base position is confirmed based on the number of excitation pulses output since the detection signal of the reel index sensor was input. Thereafter, based on the stop information stored in the main-side RAM 144, the slip number of the reel to be stopped this time is calculated.

[0144] In this slot machine 10, as the stop mode for stopping each reel 32L, 32M, 32R when the stop button 42-44 is operated, there are five stop modes available: a stop mode for stopping the reached symbol that has reached the base position as it is, a stop mode for stopping the corresponding reel after sliding it by one symbol, a stop mode for stopping it after sliding it by two symbols, a stop mode for stopping it after sliding it by three symbols, and a stop mode for stopping it after sliding it by four symbols. In this stop control process, one of the values "0" to "4" is calculated as the number of slips based on the stop information stored in the main RAM 144.

[0145] Then, the calculated slip count is added to the symbol number of the reached symbol to determine the symbol number of the stop symbol that will actually stop at the base position. Then, it is determined whether the symbol number of the reached symbol of the reel to be stopped this time is equal to the symbol number of the stop symbol, and if so, a reel stop process is performed to stop the reel rotation. Then, it is determined whether all reels 32L, 32M, and 32R have stopped. If all reels 32L, 32M, and 32R have not stopped, a second stop information setting process is performed, and the process waits until the conditions for issuing a stop command are met. If a stop command is issued, a stop command command is set again and stop control process is performed.

[0146] Here, the stop information is information for making the stop mode of each reel 32L, 32M, 32R correspond to the result of the lottery process for winning combinations (FIG. 11). By using the stop information, it is possible to calculate the number of slips (specifically, "0" to "4") for the reaching symbol that has reached the base position when each stop button 42 to 44 is operated to stop. As the stop information, slip number data indicating the correspondence between each symbol and the number of slips is stored in advance in the main ROM 143 in correspondence with each lottery result and the stop order of each reel 32L, 32M, 32R. However, without being limited thereto, the slip number data corresponding to each lottery result and the stop order of each reel 32L, 32M, 32R may be derived during the rotation of the reels 32L, 32M, 32R.

[0147] As processes for setting the stop information, there are a first stop information setting process executed in step S509 of the lottery process (Fig. 11) described later and a second stop information setting process executed in this reel control process. In the first stop information setting process, the stop information is set according to the result of the role lottery process. In the second stop information setting process, the stop information stored in the main RAM 144 in the first stop information setting process or the previous second stop information setting process is changed after the reel stops. In the second stop information setting process, the stop information is changed based on the set winning data, the stop order of the reels 32L, 32M, 32R, and the stop symbols of the stopped reels 32L, 32M, 32R.

[0148] When it is determined that all the reels 32L, 32M, 32R have stopped, the winning determination process is executed. In the winning determination process, the types of symbols stopped on the main line ML in each of the reels 32L, 32M, 32R are grasped. And when the combination of symbols stopped and displayed on the main line ML in each of the reels 32L, 32M, 32R is the combination of symbols corresponding to the role that won in the current role lottery process, the winning corresponding process is executed as the establishment of the winning of the winning role. In the winning corresponding process, if the winning is a small role winning, the number of medals to be paid out is set in the main RAM 144 so as to enable the granting of game media in the media granting process. On the other hand, if the winning is a replay winning, a flag setting process is executed so that the automatic input process is executed in the next start waiting process (the process of step S402 in the normal process (Fig. 10)).

[0149] After executing the winning determination process, the winning result command is set as the output target to the sub MPU 152. The winning result command includes data indicating the presence or absence of the establishment of the current winning, and also includes data indicating the type of the winning if the winning is established. Further, the winning result command includes data indicating which of the normal mode, the first RT mode, and the second RT mode the lottery mode is when the current game ends.

[0150] Returning to the description of the normal process (FIG. 10), after performing the reel control process in step S412, in step S413, a medium giving process is executed. In the medium giving process, when a small winning has been established in the current game, a process for giving the player the corresponding number of gaming media for the small winning is executed. Specifically, when giving virtual medals, a value corresponding to the current small winning is added to the credit counter provided in the main-side RAM 144, and when the value of the credit counter has reached the upper limit storage number, the hopper device 53 is driven and controlled so that the number of medals exceeding the upper limit storage number is paid out to the medal tray 59.

[0151] After executing the medium giving process in step S413, in step S414, a corresponding process at the end of the game is executed to enable setting of the gaming state corresponding to the result of the current game, and in step S415, an external output setting process is executed to output the state of the slot machine 10 to the management computer of the gaming hall. Then, in step S416, an acceptance permission process is executed and the process returns to step S401. By executing the acceptance permission process, the medals inserted from the medal insertion slot 45 are collected by the hopper device 53 after being detected by the inserted medal detection sensor 45a.

[0152] Next, the lottery process executed in step S411 of the normal process (FIG. 10) will be described with reference to the flowchart of FIG. 11.

[0153] First, a random number acquisition process is executed in step S501. In the random number acquisition process, a random number used for determining whether a winning is obtained is acquired. Specifically, by acquiring the numerical information output from the Q terminals of the 16 latch register D-FFs 102a to 102p and input to the input terminal TA3 of the control IC 148, numerical information of a random number which is a 16-bit binary number is acquired. In the subsequent step S502, a lottery table for determining whether a winning is obtained is read from the main-side ROM 143.

[0154] Here, in this slot machine 10, winning probabilities of six levels from "Setting 1" to "Setting 6" are prepared in advance. By inserting a setting key into the setting key insertion hole 57, turning it on, and performing a predetermined operation, it is possible to set which winning probability to execute the lottery process based on. Note that "Setting n+1" has a more advantageous winning probability for the player than "Setting n". Also, even for the same level of setting values, there are three types of lottery modes with different lottery tables in the control IC 148, namely the normal mode, the first RT mode, and the second RT mode. Further, as a gaming state, there is a BB state separately from the states of these respective lottery modes. In step S502, a lottery table corresponding to the combination of the current setting value and the current gaming state is selected.

[0155] Taking the case of "Setting 3" and the non-BB state as an example, the lottery tables corresponding to the normal mode, the first RT mode, and the second RT mode will be described. First, the lottery table for the normal mode selected in the case of the normal mode will be described. FIG. 12 is an explanatory diagram for explaining the lottery table for the normal mode. In the following description, the explanatory diagram of FIG. 13 will be appropriately referred to.

[0156] As shown in FIG. 12, an index value IV is set in the lottery table for the normal mode. For each index value IV, a winning combination is associated therewith and a point value PV is set. The point value PV determines the winning probability of the corresponding lottery combination in relation to the maximum value ("65535") of the free run counter.

[0157] Specifically, bell winning data and first supplementary winning data are set for the index value IV = 1. When winning occurs with the index value IV = 1, as shown in FIG. 13, when the first stop (the reel at which the stop command first occurred) is the left reel 32L, a bell winning will surely occur regardless of the types of the second stop target and the third stop target reels and the operation timing of each stop button 42 to 44. Otherwise, a first supplementary winning will surely occur.

[0158] In the slot machine 10, reel control is performed on each of the reels 32L, 32M, and 32R, allowing up to four symbols to slide after the stop buttons 42-44 are operated. In other words, reel control is performed on each of the reels 32L, 32M, and 32R, allowing the reels 32L, 32M, and 32R to stop within a specified time (190 msec) after the stop buttons 42-44 are operated. This reel control makes it easier to achieve a winning combination corresponding to a winning symbol and prevents a winning combination corresponding to a non-winning symbol from being achieved. However, because the amount of rotation of the reels 32L, 32M, and 32R that can slide is limited as described above, if five or more symbols exist among the symbols that constitute a winning combination on one of the reels 32L, 32M, and 32R, depending on the timing of the operation of the corresponding stop button 42-44, the symbols may not stop on the main line ML (this phenomenon is also known as a "missed win"). The first to third supplementary wins, bell win, watermelon win and various replay wins are winning patterns that will not result in a miss if the reels 32L, 32M and 32R are stopped in the corresponding order, while the cherry win, first BB win and second BB win are winning patterns that may result in a miss depending on the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation position of the reels 32L, 32M and 32R.

[0159] As shown in Fig. 12, bell winning data and second supplementary winning data are set for index value IV=2. When a win occurs with index value IV=2, as shown in Fig. 13, if the first stop is the center reel 32M, the bell winning is surely achieved regardless of the types of reels for the second and third stop targets and the operation timing of each stop button 42 to 44, and in other cases the second supplementary winning is surely achieved.

[0160] For index value IV = 3, as shown in FIG. 12, bell winning data and third supplementary winning data are set. When winning occurs with index value IV = 3, as shown in FIG. 13, when the first stop is the right reel 32R, the bell winning is surely established regardless of the types of the reels for the second stop target and the third stop target and the operation timing of each of the stop buttons 42 to 44. In other cases, the third supplementary winning is surely established.

[0161] For index value IV = 4, as shown in FIG. 12, only watermelon winning data is set. When winning occurs with index value IV = 4, as shown in FIG. 13, the watermelon winning is established regardless of the stop order of the reels 32L, 32M, and 32R. Also, when winning occurs with index value IV = 4, the watermelon winning is surely established regardless of the operation timing of each of the stop buttons 42 to 44.

[0162] For index value IV = 5, as shown in FIG. 12, only cherry winning data is set. When winning occurs with index value IV = 5, as shown in FIG. 13, the cherry winning may be established regardless of the stop order of the reels 32L, 32M, and 32R. However, depending on the operation timing of the left stop button 42 with respect to the rotational position of the left reel 32L, the cherry winning may not be established.

[0163] For index value IV = 6, as shown in FIG. 12, first BB winning data is set. When winning occurs with index value IV = 6, as shown in FIG. 13, the first BB winning may be established regardless of the stop order of the reels 32L, 32M, and 32R. However, depending on the operation timing of each of the stop buttons 42 to 44, the first BB winning may not be established. Also, for index value IV = 7, as shown in FIG. 12, second BB winning data is set. When winning occurs with index value IV = 7, as shown in FIG. 13, the second BB winning may be established regardless of the stop order of the reels 32L, 32M, and 32R. However, depending on the operation timing of each of the stop buttons 42 to 44, the second BB winning may not be established.

[0164] Here, winning data other than the first BB winning data and the second BB winning data is erased in the game in which a win occurs, regardless of whether a win is achieved or not, and is not carried over to games following the game in which the win occurred. In contrast, the first BB winning data and the second BB winning data are stored and held until the corresponding BB winning occurs, even in games following the game in which a win occurred, except when the master RAM 144 is cleared. In this case, in a game in which the first BB winning data or the second BB winning data is carried over, the index values IV corresponding to the first BB winning data and the second BB winning data are excluded from the lottery. This makes it possible to prevent new BB winning data from being stored even when the first BB winning data or the second BB winning data is already stored and held, and to prevent multiple BB winning data from being accumulated and stored.

[0165] As shown in Fig. 12, normal replay winning data and first real-time replay winning data are set for index values IV = 8 to 11. In this case, if a win occurs with index value IV = 8, as shown in Fig. 13, if the first stop is the center reel 32M, the second stop (the reel on which the second stop command was issued) is the left reel 32L, and the third stop (the reel on which the last stop command was issued) is the right reel 32R, the first real-time replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. In other cases, the normal replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. Also, if a win occurs with index value IV = 9, if the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the first real-time replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. In other cases, the normal replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=10, and the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the center reel 32M, then the first RT replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44, and in all other cases, the normal replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=11, and the first stop is the right reel 32R, the second stop is the center reel 32M, and the third stop is the left reel 32L, then the first RT replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44, and in all other cases, the normal replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44.

[0166] When the lottery table for the normal mode of FIG. 12 is selected, the probability of winning when the index value IV = 1, the probability of winning when the index value IV = 2, and the probability of winning when the index value IV = 3 are each approximately 1 / 5.0, the probability of winning when the index value IV = 4 is approximately 1 / 77, the probability of winning when the index value IV = 5 is approximately 1 / 423, the probability of winning when the index value IV = 6 is approximately 1 / 131, the probability of winning when the index value IV = 7 is approximately 1 / 655, the probability of winning when the index value IV = 8, the probability of winning when the index value IV = 9, the probability of winning when the index value IV = 10, and the probability of winning when the index value IV = 11 are each approximately 1 / 28.0.

[0167] Here, in the lottery table for the normal mode, as already described, as the winning data for the index values IV = 8 to 11, in addition to the normal replay winning data, the first RT replay winning data is set (see FIG. 12). The probability of winning any one of these index values IV = 8 to 11 is approximately 1 / 7.0. And when winning with any one of the index values IV = 8 to 11, when the stop order of the first stop, the second stop, and the third stop of the reels 32L, 32M, and 32R becomes the stop order corresponding to the winning combination, the first RT replay prize is established and the lottery mode shifts from the normal mode to the first RT mode. When shifting to the first RT mode, the lottery table referred to in the lottery process (FIG. 11) becomes the lottery table for the first RT mode.

[0168] Next, the lottery table for the first RT mode selected when it is "Setting 3" and in the first RT mode will be described. FIGS. 14 and 15 are explanatory diagrams for explaining the lottery table for the first RT mode.

[0169] In the lottery table for the first RT mode, as shown in FIG. 14, the winning combination data set for each of the index values IV = 1 to 7 and the winning probability of each index value IV are the same as those in the lottery table for the normal mode (FIG. 12). In this case, winning combinations that enable the awarding of game media are set for the index values IV = 1 to 5, and since the winning combination data and the respective winning probabilities set for each of the index values IV = 1 to 5 are the same, the types of winning combinations that enable the awarding of game media and their winning probabilities are the same for each of the normal mode and the first RT mode. Also, BB winning data is set for the index values IV = 6 to 7 in the same way as in the lottery table for the normal mode, and the winning probability is the same as that in the lottery table for the normal mode. That is, the probability of winning either BB combination in the normal mode and the first RT mode is the same.

[0170] The winning candidate data set after the index value IV = 8 is different from the normal mode. Specifically, in the lottery table for the first RT mode, as shown in FIG. 14, as the winning data for index values IV = 8 to 11, in addition to the normal replay winning data, the second RT replay winning data is set. The probability of winning any of these index values IV = 8 to 11 is approximately 1 / 10.1. When winning with the index value IV = 8, as shown in FIG. 15, when the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, the second RT replay winning occurs surely regardless of the operation timing of each stop button 42 to 44, and in other cases, the normal replay winning occurs surely regardless of the operation timing of each stop button 42 to 44. Also, when winning with the index value IV = 9, when the first stop is the middle reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the second RT replay winning occurs surely regardless of the operation timing of each stop button 42 to 44, and in other cases, the normal replay winning occurs surely regardless of the operation timing of each stop button 42 to 44. Also, when winning with the index value IV = 10, when the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, the second RT replay winning occurs surely regardless of the operation timing of each stop button 42 to 44, and in other cases, the normal replay winning occurs surely regardless of the operation timing of each stop button 42 to 44. Also, when winning with the index value IV = 11, when the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, the second RT replay winning occurs surely regardless of the operation timing of each stop button 42 to 44, and in other cases, the normal replay winning occurs surely regardless of the operation timing of each stop button 42 to 44.In the first RT mode, when the index value IV is elected as any of 8 to 11 and the stop order of the first stop, second stop, and third stop of the reels 32L, 32M, and 32R becomes the stop order corresponding to the winning combination, the second RT replay winning is established and the lottery mode shifts from the first RT mode to the second RT mode. When shifting to the second RT mode, the lottery table referred to in the lottery process (Figure 11) becomes the lottery table for the second RT mode.

[0171] As shown in FIG. 14, in the lottery table for the first RT mode, in addition to the normal replay winning data, the first fall replay winning data is set as the winning data with the index value IV = 12 to 17. The probability of winning any of these index values IV = 12 to 17 is approximately 1 / 10.9.

[0172] When winning with an index value IV = 12 in the lottery table for the first RT mode, as shown in Fig. 15, if the first stop is the left reel 32L, the second stop is the middle reel 32M, and the third stop is the right reel 32R, a normal replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Also, when winning with an index value IV = 13, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the middle reel 32M, a normal replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Also, when winning with an index value IV = 14, if the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, a normal replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Also, when winning with an index value IV = 15, if the first stop is the middle reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, a normal replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Also, when winning with an index value IV = 16, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, a normal replay win will surely occur regardless of the operation timing of each stop button 42 - 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 - 44.Also, when winning occurs with the index value IV = 17, if the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, a normal replay win will surely occur regardless of the operation timing of each stop button 42 to 44. Otherwise, a first fall replay win will surely occur regardless of the operation timing of each stop button 42 to 44. When the first fall replay win is established, the lottery mode shifts to the normal mode. When shifting to the normal mode, the lottery table referred to in the lottery process (Fig. 11) becomes the lottery table for the normal mode.

[0173] In the lottery table for the first RT mode, only the normal replay winning data is set for the index value IV = 18. The probability of winning with the index value IV = 18 is set higher than the probability of winning other winning combinations, specifically, it wins with a probability of about 1 / 6.7. And when winning occurs with this index value IV = 18, a normal replay win is established regardless of the stop order of the reels 32L, 32M, 32R and the stop operation timing of each of the reels 32L, 32M, 32R.

[0174] In the lottery table for the first RT mode, winning combinations that enable a replay win are set for the index values IV = 8 to 18. And since the winning probabilities of these winning combinations are set to the probabilities as already described, the winning probability of the winning combinations that enable a replay win (hereinafter also referred to as the replay probability) in the first RT mode is about 1 / 2.9. In contrast, the replay probability in the normal mode is about 1 / 7.0. That is, the first RT mode is a gaming state with a higher replay probability than the normal mode.

[0175] Next, the lottery table for the second RT mode, which is selected when it is "Setting 3" and is the second RT mode, will be described. FIGS. 16 and 17 are explanatory diagrams for explaining the lottery table for the second RT mode.

[0176] In the lottery table for the second RT mode, as shown in FIG. 16, the winning combination data set for each of the index values IV=1 to 7 and the winning probabilities for each index value IV are the same as those in the lottery table for the normal mode (FIG. 12) and the lottery table for the first RT mode (FIG. 14). In this case, a combination that allows the award of game media is set for the index values IV=1 to 5, and since the winning combination data and the winning probabilities set for each of the index values IV=1 to 5 are the same, the types of combinations that allow the award of game media and the winning probabilities for those combinations are the same in the normal mode, the first RT mode, and the second RT mode. In addition, BB winning data is set for the index values IV=6 to 7, similar to the lottery table for the normal mode and the lottery table for the first RT mode, and the winning probabilities are the same as those in the lottery table for the normal mode and the lottery table for the first RT mode. In other words, the probability of winning any of the BB combinations is the same in the normal mode, the first RT mode, and the second RT mode.

[0177] The winning combination data set for index value IV=8 and onwards differs from those in the normal mode and the first RT mode. In detail, in the lottery table for the second RT mode, as shown in Fig. 16, second fall replay winning data is set as winning data for index value IV=8 to 13 in addition to normal replay winning data. The probability of winning any of these index values IV=8 to 13 is approximately 1 / 5.5.

[0178] 17, if the first stop is the left reel 32L, the second stop is the center reel 32M, and the third stop is the right reel 32R, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the second fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Also, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the center reel 32M, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the second fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=10, and the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=11, and the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=12, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44.Also, when winning occurs with the index value IV = 13, if the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, the normal replay winning will surely occur regardless of the operation timing of each stop button 42 to 44. Otherwise, the second fall replay winning will surely occur regardless of the operation timing of each stop button 42 to 44. When the second fall replay winning is established, the lottery mode shifts to the first RT mode. When shifting to the first RT mode, the lottery table referred to in the lottery process (Figure 11) becomes the lottery table for the first RT mode.

[0179] Only the normal replay winning data is set for the index value IV = 14 in the lottery table for the second RT mode. The probability of winning with the index value IV = 14 is set higher than the probability of winning other roles. Specifically, the winning probability is about 1 / 6.3. And when winning occurs with this index value IV = 14, the normal replay winning will be established regardless of the stop order of the reels 32L, 32M, 32R and the stop operation timing of each of the reels 32L, 32M, 32R.

[0180] In the lottery table for the second RT mode, roles that enable a replay win to occur are set for index values IV = 8 to 14. And since the winning probabilities of these roles are set to the probabilities as already explained, the winning probability of the role that enables a replay win to occur in the second RT mode (hereinafter also referred to as the replay probability) is approximately 1 / 2.9. On the other hand, the replay probability in the normal mode is approximately 1 / 7.0. That is, the second RT mode is a gaming state with a higher replay probability than the normal mode. Meanwhile, the replay probability in the first RT mode is approximately 1 / 2.9. That is, the second RT mode has the same replay probability as the first RT mode. However, the configuration is not limited to the case where the replay probability in the first RT mode is the same as the replay probability in the second RT mode. For example, it may be a configuration where the replay probabilities in the first RT mode and the second RT mode are slightly different but approximately the same, or it may be a configuration where the second RT mode has a higher replay probability than the first RT mode, or it may be a configuration where the first RT mode has a higher replay probability than the second RT mode.

[0181] The lottery table for the normal mode, the lottery table for the first RT mode, and the lottery table for the second RT mode are set in a one-to-one correspondence with each of "Setting 1" to "Setting 6," and the higher the setting value, the higher the probability of winning the BB role. However, the replay probability set in each lottery mode is the same or approximately the same regardless of the setting value. Also, if any of the BB roles has been won, the first BB role and the second BB role are excluded from the lottery target regardless of whether it is the normal mode, the first RT mode, or the second RT mode, so that the BB role is not won twice. In addition to the lottery table for the normal mode, the lottery table for the first RT mode, and the lottery table for the second RT mode, the main ROM 143 also stores a BB lottery table that is referenced in the lottery process (FIG. 11) when the first BB state or the second BB state is in effect. In the BB lottery table, only three types of roles are set as the roles to be selected: Bell, Watermelon, and Regular Replay, and the probability of winning the Bell role is set to approximately 1 / 2, the probability of winning the Watermelon role is set to approximately 1 / 4, and the probability of winning the Regular Replay role is set to approximately 1 / 4. As a result, the expected number of game media awarded per unit number of games in the BB state is higher than in other game states.

[0182] Returning to the explanation of the lottery process (FIG. 11), after selecting a lottery table in step S502, the index value IV is set to "1" in step S503, and a judgment value DV to be used when determining whether a winning combination has been achieved is set in step S504. In this judgment value setting process, a point value PV corresponding to the current index value IV is added to the current judgment value DV to set a new judgment value DV. Note that in the first judgment value setting process, the random number value acquired in step S501 is set as the current judgment value DV, and the point value PV corresponding to the current index value IV of "1" is added to this random number value to set a new judgment value DV.

[0183] In the following step S505, a judgment is made as to whether the combination corresponding to the index value IV has been won or not. In the judgment of whether the combination has been won or not, it is judged whether or not the judgment value DV has exceeded "65535". If it has exceeded "65535" (step S505: YES), in step S506, a winning data acquisition process is executed to set the winning combination data corresponding to the index value IV at that time in the master RAM 144. In the winning data acquisition process, all of the winning data set for the current index value IV in the lottery table being referenced is set in the master RAM 144. If the winning data is winning data other than BB winning data, the set state of the winning data is cleared to "0" after the end of the current game regardless of whether a win corresponding to the winning data has been achieved or not, and if it is BB winning data, it is cleared to "0" if a win is achieved.

[0184] If the judgment value DV does not exceed "65535" (step S505: NO), it means that the winning combination corresponding to the index value IV has not been achieved. In such a case, in step S507, 1 is added to the index value IV, and in step S508, it is determined whether or not there is a winning combination corresponding to the index value IV, i.e., whether or not there is a target for judgment as to whether it is a winning combination. Specifically, it is determined whether or not the index value IV to which 1 has been added exceeds the maximum value of the index value IV set in the lottery table. If there is a target for judgment as to whether it is a winning combination, the process returns to step S504, and the judgment of the winning combination continues. At this time, in step S504, the point value PV corresponding to the current index value IV is added to the judgment value DV used to judge whether or not the previous winning combination was achieved (i.e., the current judgment value DV) to obtain a new judgment value DV, and in step S505, the winning combination is judged based on the judgment value DV.

[0185] When the process of step S506 is executed, or when a negative determination is made in step S508, it means that the determination of the validity of the role has ended. In this case, in step S509, a first stop information setting process for setting stop information for reel stop control is executed. The stop information set here is information for making the stop modes of the respective reels 32L, 32M, and 32R correspond to the result of the role lottery process.

[0186] In the subsequent step S510, a game start command is set as a transmission target to the sub-side MPU152. The game start command is a command for causing the sub-side MPU152 to recognize that a new game has started, and is a command for causing the sub-side MPU152 to recognize the result of the current role lottery process in the control IC148, and is transmitted to the sub-side MPU152 in the command output process (step S212) in the timer interrupt process (FIG. 8).

[0187] Next, the corresponding process at the end of the game executed in step S414 of the normal process (FIG. 10) will be described with reference to the flowchart of FIG. 18. The corresponding process at the end of the game is executed when the rotation of all the reels 32L, 32M, and 32R stops in each game.

[0188] First, in step S601, it is determined whether or not a winning corresponding to the winning BB role has been established in the situation of winning the first BB role or the second BB role. When the corresponding winning has been established (step S601: YES), in step S602, BB start processing is executed. In the BB start processing, if the first BB winning has been established, a "1" is set in the first BB flag provided in the main-side RAM144, and a "41", which is the end reference number in the first BB state, is set in the end reference number counter provided in the main-side RAM144. On the other hand, if the second BB winning has been established, a "1" is set in the second BB flag provided in the main-side RAM144, and an "89", which is the end reference number in the second BB state, is set in the end reference number counter of the main-side RAM144.

[0189] The first BB flag is a flag for the control IC 148 to identify that it is in the first BB state, and the second BB flag is a flag for the control IC 148 to identify that it is in the second BB state. When "1" is set in the first BB flag or the second BB flag, the BB lottery table will be referred to in the role lottery process (Figure 11). The end criterion number counter is a counter for the control IC 148 to identify whether the total number of game media given in the BB state has reached the end criterion number which is the end condition of the BB state. The value set in the end criterion number counter is subtracted by the number of game media given by the winning every time a winning for the object of giving game media is established in the BB state. And when the value of the end criterion number counter after the subtraction becomes "0", the control IC 148 determines that the rotation of reels 32L, 32M, and 32R in the final game in the current BB state has stopped. In addition, even when the value of the end criterion counter becomes "0" at the stage where a part of the predetermined number is subtracted from the end criterion counter when a winning that gives a predetermined number of game media is established in the BB state, the predetermined number of game media is given.

[0190] If a negative determination is made in step S601, then in step S603, it is determined whether it is either the first BB state or the second BB state. If it is either the first BB state or the second BB state (step S603: YES), then in step S604, the BB process is executed to end the corresponding process at the end of this game. In the BB process, if game media are given in the current game, the value of the end criterion number counter in the main side RAM 144 is subtracted accordingly. When the value of the end criterion number counter after the subtraction is "0", the process for ending the BB state is executed.

[0191] When it is not in the BB state and the BB winning has not been established (steps S601 and S603: NO), at step S605, it is determined whether the promotion condition is satisfied. If the promotion condition is satisfied (step S605: YES), at step S606, the process of changing the lottery table at the time of promotion is executed, and the corresponding process at the end of this game is terminated. Specifically, when it is specified that the first RT replay winning has occurred in this game, the lottery table to be used in the lottery process for the roles is changed to the lottery table for the first RT mode to shift to the first RT mode. When it is specified that the second RT replay winning has occurred in this game, the lottery table to be used in the lottery process for the roles is changed to the lottery table for the second RT mode to shift to the second RT mode.

[0192] If a negative determination is made at step S605, at step S607, it is determined whether the fall condition is satisfied. If the fall condition is not satisfied (step S607: NO), the corresponding process at the end of this game is terminated as it is. If the fall condition is satisfied (step S607: YES), at step S608, the process of changing the lottery table at the time of fall is executed, and the corresponding process at the end of this game is terminated. Specifically, when it is specified that the second fall replay winning has occurred in this game, the lottery table to be used in the lottery process for the roles is changed to the lottery table for the first RT mode to shift to the first RT mode. When it is specified that the first fall replay winning has occurred in this game, the lottery table to be used in the lottery process for the roles is changed to the lottery table for the normal mode to shift to the normal mode.

[0193] <Management operation in the control-side CPU 114> Next, the management operation in the control-side CPU 114 will be described with reference to the flowchart of FIG. 19.

[0194] First, in step S701, it waits until the detection signal SG1 input to the control-side CPU 114 becomes LOW. Then, when the detection signal SG1 input to the control-side CPU 114 becomes LOW (step S701: YES), in step S702, it waits until the detection signal SG1 input to the control-side CPU 114 becomes HI. And when the detection signal SG1 input to the control-side CPU 114 becomes HI (step S702: YES), it proceeds to step S703. That is, when the control-side CPU 114 detects the rising edge of the detection signal SG1 input to the control-side CPU 114 from LOW to HI, it proceeds to step S703.

[0195] In step S703, it starts counting the time during which the HI state of the detection signal SG1 input to the control-side CPU 114 continues using a timer counter. The time during which the HI state continues is counted in units of 0.1 μs. In step S704, it determines whether the detection signal SG1 is in the HI state. If it is in the HI state (step S704: YES), in step S705, it determines whether 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 became HI.

[0196] In step S705, if 12.8 μs has not elapsed since the detection signal SG1 input to the control-side CPU 114 became HI, it returns to the determination in step S704. And in step S705, when 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 became HI, it proceeds to step S706.

[0197] In step S706, the counting of time using the timer counter is stopped, and the timer counter is reset. In step S707, a latch signal, which is a pulse signal, is transmitted to the CLK terminals of the D-FFs 102a to 102p for the latch register. As a result, the numerical information of the random numbers stored in the random number counter 105 is written into the latch register 102.

[0198] In the subsequent step S708, "1" is set in the latched status 113, and the process returns to step S701. Specifically, the control-side CPU 114 raises the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113 on the condition that the signal output from the Q terminal 113a of the latched status 113 and input to the input terminal TB2 of the control-side CPU 114 is in the LOW state. As a result, "1" is set in the latched status 113. Also, when the signal output from the Q terminal 113a of the latched status 113 and input to the input terminal TB2 of the control-side CPU 114 is in the HI state, the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113 is maintained. As a result, the state in which "1" is set in the latched status 113 is maintained.

[0199] Also, when a negative determination is made in step S704, that is, when the detection signal SG1 input to the control-side CPU 114 returns to the LOW state before 12.8 μs has elapsed after the detection signal SG1 becomes the HI state, it is considered that the detection signal SG1 has risen due to short noise of less than 12.8 μs being mixed into the input terminal of the control-side CPU 114. In this case, in step S709, the counting of time by the timer counter is stopped and the timer counter is reset, and the process returns to the process of step S702.

[0200] In this way, the control-side CPU 114 sets the latched status 113 to "1" on the condition that it detects the rising edge of the detection signal SG1 input to the control-side CPU 114. Therefore, even when the start lever 41 is pressed down and the pressing operation continues for a long time, a latch signal, which is a pulse signal, is transmitted to the CLK terminal of the latch register D-FFs 102a to 102p in response to one pressing operation, and the latched status 113 is set to "1" only once. Even if the start lever 41 is pressed down for a long time, the latch signal is not transmitted repeatedly.

[0201] Furthermore, the control-side CPU 114 sets the latched status 113 to "1" even during a game. However, the control IC 148 is configured to set the start command flag 144c to "1" in the start command setting process (FIG. 9), with one condition being that the game is ready to start. Then, in the normal process (FIG. 10), the control IC 148 is configured to clear the latched status 113 to "0" when the start timing of the period when the game is ready to start arrives. For this reason, even if the latched status 113 is set to "1" during a game, this does not trigger the setting of the start command flag 144c to "1."

[0202] <Timing at which the control IC 148 acquires the random number> Next, the timing at which the control IC 148 acquires a random number will be described with reference to the time charts of FIGS.

[0203] First, a slot machine that does not have the latched status 113 will be described with reference to Figure 20. This slot machine will be referred to as a first slot machine for comparison. The first slot machine for comparison differs from the slot machine 10 of this embodiment in that it does not have the latched status 113.

[0204] Figure 20 is a time chart for explaining the timing at which the control IC acquires a random number from the latch register in the first slot machine for comparison. Figure 20(a) shows the state of the detection signal input to the control IC, Figure 20(b) shows the state of the signal storage flag, Figure 20(c) shows the state of the detection signal input to the control CPU, Figure 20(d) shows the timing at which the random number stored in the random number counter is written to the latch register, Figure 20(e) shows the timing at which the start command setting process (Figure 9) is executed in the control IC, and Figure 20(f) shows the timing at which the control IC acquires the random number output from the latch register and input to the input terminal of the control IC.

[0205] As shown in Figures 20(a) and (c), when a player operates the start lever, the detection signal input to the control IC and the control CPU rises from a LOW state to a HIGH state at time t1. The control CPU sends a latch signal to the latch register at time t4, 12.8 μs after the input detection signal rises. As shown in Figure 20(d), at time t4 when the latch register receives the latch signal, the numerical information of the random number stored in the random number counter is written to the latch register.

[0206] As shown in FIG. 20(e), the start command setting process is performed at t2, which is after t1 when the detection signal rises and before t4 when the random number numerical information is written to the latch register. As shown in FIG. 20(a), the detection signal input to the control IC is in a HI state at t2. Therefore, as shown in FIG. 20(b), the control IC sets the signal memory flag to "1" at t2. This indicates that the control IC has detected the rising edge of the detection signal. Therefore, as shown in FIG. 20(f), in the lottery process (FIG. 11) executed at t3, which is after t2 and before t4, the control IC acquires the random number numerical information input to the input terminal of the control IC.

[0207] Since the timing t3 at which the control IC acquires the numerical information of the random number is earlier than the timing t4 at which the random number corresponding to the operation of the start lever this time is written into the latch register, the control IC will acquire the numerical information of the random number written into the latch register before the operation of the start lever this time. Thus, when the latched status 113 is not used, a random number not corresponding to the operation of the start lever may be used for the determination of success or failure of the role.

[0208] For example, after a game result advantageous to the player is obtained, there may be fraud in which the detection signal is raised from the LOW state to the HI state so that the start command setting process is performed before the random number corresponding to the operation of the start lever is written into the latch register. If such fraud is committed, the control IC will acquire the numerical information of the same random number as the previous time. Therefore, there is a problem that an advantageous game result for the player continues due to fraud.

[0209] As shown in FIGS. 20(a) and (c), at the timing t5 after the timing t4, the detection signal input to the control IC and the control-side CPU falls from the HI state to the LOW state. Then, as shown in FIG. 20(e), the start command setting process is executed at the timing t6. As shown in FIG. 20(a), the detection signal input to the control IC at the timing t6 is in the LOW state. Therefore, as shown in FIG. 20(b), the control IC clears the signal storage flag to "0" at the timing t6.

[0210] After the timing t6, the game performed using the random number acquired by the control IC at the timing t2 ends, and the game can be started again. Then, as shown in FIG. 20(a), at the timing t7 after the timing t6, the detection signal input to the control IC rises from the LOW state to the HI state. However, as shown in FIG. 20(c), the detection signal input to the control-side CPU 114 at the timing t7 does not rise.

[0211] Therefore, as shown in FIG. 20(d), no new random number numerical information is written into the latch register triggered by the rising edge of the detection signal at timing t7. The numerical information stored in the latch register remains the same as the random number numerical information written at timing t4.

[0212] As shown in FIG. 20(e), the start command setting process is executed at timing t8, which is between the timing t7 when the detection signal input to the control IC rises and the timing t10 when the detection signal input to the control IC falls. As shown in FIG. 20(a), the detection signal input to the control IC is in the HI state at timing t8. Therefore, as shown in FIG. 20(b), the control IC sets “1” in the signal storage flag at timing t8. Thereby, the control IC detects the rising edge of the detection signal input to the control IC.

[0213] As shown in FIG. 20(f), in the lottery process (FIG. 11) executed at timing t9, which is after the timing t8 when the control IC detects the rising edge of the detection signal and before the timing t10, the random number input to the input terminal of the control IC is acquired. The numerical information of the random number acquired at timing t9 is the same as the random number numerical information written from the random number counter to the latch register at timing t4.

[0214] As described for t7 to t10, when the detection signal input to the control-side CPU does not rise and only the detection signal input to the control IC rises, problems occur in a slot machine that does not have the latched status 113. For example, when noise is mixed only into the input terminal of the control IC, a problem occurs in that the game is started triggered by the noise. Also, when the start lever is operated with the signal line connecting the start detection sensor and the control-side CPU disconnected, a problem occurs in that the determination of winning or losing is made based on an old random number that does not correspond to the operation timing of the current start lever.

[0215] Next, for the case of obtaining the numerical information of the random number input to the control IC on the condition that the rising edge of the detection signal input from a slot machine without the latched status 113 is detected and it is confirmed twice in a row that the detection signal is in the HI state, the following description will be given. In the following description, the slot machine will be the second slot machine to be compared.

[0216] The second slot machine to be compared is different from the slot machine 10 of the present embodiment in that it does not have the latched status 113 and obtains the numerical information of the random number input to the input terminal of the control IC on the condition that the detection signal input to the control IC is in the LOW state → HI state → HI state in the start command setting process (Fig. 9) executed three times in a row.

[0217] The timing at which the control IC of the second slot machine to be compared obtains the numerical information of the random number input to the input terminal of the control IC will be described with reference to the time chart of Fig. 21. Fig. 21(a) shows the state of the detection signal input to the control IC, Fig. 21(b) shows the state of the detection signal input to the control side CPU, Fig. 21(c) shows the timing at which the numerical information of the random number stored in the random number counter is written into the latch register, Fig. 21(d) shows the timing at which the start command setting process is executed in the control IC, Fig. 21(e) shows the timing at which the control IC obtains the numerical information of the random number input to the input terminal of the control IC, and Fig. 21(f) shows the connection state between the start detection sensor and the control side CPU.

[0218] As shown in Figure 21(a), the start command setting process is executed at timing t1. As shown in Figure 21(f), at timing t1, the start detection sensor and the control-side CPU are connected, and the detection signal output from the start detection sensor is input to the control-side CPU. Also, as shown in Figure 21(a), at timing t1, the detection signal input to the control IC is in a LOW state. After that, when the start lever is pressed down at timing t2, as shown in Figures 21(a) and 21(b), the detection signal input to the control IC and the detection signal input to the control-side CPU rise from a LOW state to a HIGH state.

[0219] As shown in Fig. 21(d), the start command setting process is executed at timing t3, which is 12.8 μs before timing t2. As shown in Fig. 21(a), the detection signal input to the control IC at timing t3 is in the HI state.

[0220] At t4, which is after t3 and 12.8 μs after t2, the control CPU determines that the detection signal input to the control CPU has risen from a LOW state to a HIGH state and that this HIGH state has been maintained for 12.8 μs or more. The control CPU then sends a latch signal to the CLK terminal of the latch register D-FF. As a result, the random number stored in the random number counter at t4 is written to the latch register, as shown in Figure 21(c).

[0221] Thereafter, as shown in FIG. 21(d), a start command setting process is executed at timing t5. As shown in FIG. 21(a), the detection signal input to the control IC at timing t5 is in a HI state. Since the detection signals input to the control IC at timings t1, t3, and t5 change from a LOW state to a HI state and back to a HI state, as shown in FIG. 21(e), in the lottery process (FIG. 11) executed at timing t6 after timing t5, the control IC acquires the numerical information of the random number input to the input terminal of the control IC and starts the game. The numerical information of the random number acquired by the control IC at timing t6 is the numerical information of the random number corresponding to the current operation of the start lever 41.

[0222] 21(a) and 21(b), the detection signal input to the control IC and the detection signal input to the control CPU each return to a LOW state at time t7, which is after time t6. The game also ends after time t7.

[0223] Thereafter, as shown in Fig. 21(d), the start command setting process is executed at timing t8. As shown in Fig. 21(a), the detection signal input to the control IC at timing t8 is in a LOW state.

[0224] If the start lever is subsequently pressed insufficiently, the detection signal input to the control IC and the detection signal input to the control-side CPU will both be in the HI state from time t9 to time t11, as shown in Figures 21(a) and 21(b). Here, the time interval from time t9 to time t11 is less than 12.8 μs. An insufficient press of the start lever refers to a press in which the start lever is held down for less than 12.8 μs.

[0225] In this case, the HI state of the detection signal input to the control CPU does not continue for 12.8 μs or more, so the insufficient pressing operation does not cause the control CPU to send a latch signal to the CLK terminal of the latch register D-FF. Therefore, as shown in Figure 21, the numerical information of the random number stored in the random number counter is not written to the latch register.

[0226] As shown in FIG. 21(d), the start command setting process is executed at timing t10, which is between timing t9 and timing t11. As shown in FIG. 21(a), the detection signal input to the control IC is in a HI state at timing t10. Then, after timing t11, noise is mixed only into the input terminal of the control IC. As a result, the detection signal input to the control IC is in a HI state from timing t12 to timing t15, as shown in FIG. 21(a).

[0227] In this case, as shown in Fig. 21(d), the start command setting process is executed at timing t13, which is between timing t12 and timing t15. As shown in Fig. 21(a), the detection signal input to the control IC at timing t13 is in a HI state.

[0228] Because the detection signal input to the control IC at times t8, t10, and t13 changed from LOW state to HIGH state and back to HIGH state, as shown in Figure 21(e), in the lottery process (Figure 11) executed at time t14 after time t13, the control IC acquires the numerical information of the random number input to the input terminal of the control IC and starts the game. As shown in Figure 21(c), from time t9 to time t14, the numerical information of the random number stored in the latch register was not updated. Therefore, the numerical information of the random number acquired by the control IC at time t14 is old numerical information of a random number that does not correspond to the current insufficient depression of the start lever 41.

[0229] Thus, when the start command setting process is executed at both the timing when an insufficient pressing operation of the start lever 41 is performed and the timing when noise is mixed into the input terminal of the control IC, in the second slot machine to be compared, a determination of whether a role is successful or not is executed based on the numerical information of an old random number.

[0230] As shown in FIG. 21(f), at the timing of t16, which is the timing after t15, the connection between the start detection sensor and the control-side CPU is disconnected and enters a disconnection state. In the disconnection state, the detection signal output from the start detection sensor is input only to the control IC.

[0231] Thereafter, as shown in FIG. 21(d), the start command setting process is executed at the timing of t17. Here, the game has already ended at the timing of t17, and the second slot machine to be compared is in a state where the game can be started at the timing of t17. As shown in FIG. 21(a), the detection signal input to the control IC at the timing of t17 is in the LOW state.

[0232] When the start lever is pressed down at the timing of t18, which is after the timing of t17, the detection signal input to the control IC rises from the LOW state to the HI state as shown in FIG. 21(a). However, as shown in FIG. 21(f), the connection between the start detection sensor and the control-side CPU has been disconnected since the timing of t16. Therefore, as shown in FIG. 21(b), the detection signal input to the control-side CPU does not rise at the timing of t18.

[0233] As shown in Figure 21(d), at timing t19, the first start command setting process is executed after timing t18. As shown in Figure 21(a), the detection signal input to the control IC at timing t19 is in a HI state. Thereafter, as shown in Figure 21(d), at timing t20, the second start command setting process is executed after timing t18. As shown in Figure 21(a), the detection signal input to the control IC at timing t20 is in a HI state.

[0234] Because the detection signal input to the control IC at times t17, t19, and t20 changed from LOW state to HIGH state and back to HIGH state, the control IC acquires the numerical information of the random number input to the input terminal of the control IC in the lottery process (FIG. 11) executed at time t21, which is after time t20, as shown in FIG. 21(e), and starts the game. As shown in FIG. 21(c), the numerical information of the random number stored in the latch register was not updated between time t18 and time t21. Therefore, the numerical information of the random number acquired by the control IC at time t21 is the old numerical information of the random number that does not correspond to the current depression of the start lever.

[0235] In the second slot machine for comparison, which does not use the latched status 113, the control IC cannot grasp that the numerical information of the random number stored in the random number counter has been written to the latch register. For this reason, it is not possible to set the start command flag to "1" on the condition that the numerical information of the random number stored in the random number counter has been written to the latch register.

[0236] In a slot machine that does not use the latched status 113, when noise, disconnection, etc. cause the detection signal input to the control IC and the detection signal input to the control-side CPU to exhibit different behaviors, there is a problem that the determination of the success or failure of a role is made based on the numerical information of old random numbers. In particular, when the connection between the start detection sensor and the control-side CPU is disconnected, the determination of the success or failure of a role based on the same numerical information of random numbers is repeatedly performed.

[0237] Next, the slot machine 10 of the present embodiment in which the control IC 148 acquires a random number using the latched status 113 will be described with reference to FIG. 22.

[0238] FIG. 22 is a time chart for explaining the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 in the present embodiment. FIG. 22(a) shows the state of the detection signal SG1 input to the control IC 148, FIG. 22(b) shows the state of the signal storage flag 144d (FIG. 5), FIG. 22(c) shows the state of the detection signal SG1 input to the control-side CPU 114, FIG. 22(d) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, FIG. 22(e) shows the state of the latched status 113, FIG. 22(f) shows the timing at which the start command setting process (FIG. 9) is executed in the control IC 148, FIG. 22(g) shows the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, and FIG. 22(h) shows the state of the error counter 144b (FIG. 5).

[0239] As shown in FIG. 22(a), during the game startable period, noise enters the input terminal TA1 of the control IC 148, and the detection signal SG1 input to the control IC 148 rises from the LOW state to the HI state. As shown in FIG. 22(a), the HI state continues until the timing of t3. As shown in FIG. 22(f), the start command setting process is executed at the timing of t2, which is between the timing of t1 and the timing of t3. As shown in FIG. 22(a), since the detection signal SG1 input to the control IC 148 is in the HI state at the timing of t2, as shown in FIG. 22(b), the control IC 148 sets "1" in the signal storage flag 144d at the timing of t2. When the signal storage flag 144d changes from "0" to "1", the control IC 148 detects the rise of the detection signal SG1.

[0240] As shown in FIGS. 22(a) and (c), only the detection signal SG1 input to the control IC 148 rises at the timing of t1, and the detection signal SG1 input to the control side CPU 114 does not rise. For this reason, as shown in FIG. 22(e), the latched status 113 remains "0" at the timing of t2. In the start command setting process performed at the timing of t2, since the condition that "1" is set in the latched status 113 is not satisfied, as shown in FIG. 22(g), the acquisition of the numerical information of the random number by the control IC 148 is not executed. In this case, as shown in FIG. 22(h), the control IC 148 adds "1" to the error counter 144b at the timing of t2.

[0241] In this way, by using the latched status 113, when noise enters only the control IC 148, it is possible to avoid a situation where the control IC 148 acquires the old numerical information of the random number input to the input terminal TA3 of the control IC 148 and a determination of the success or failure of the role based on the old random number is made. Also, when the signal line connecting the start detection sensor 41a and the control side CPU 114 is disconnected, it is possible to avoid a situation where the control IC 148 repeatedly acquires the numerical information of the same random number every time the start lever 41 is operated.

[0242] As shown in FIG. 22(a), after the detection signal SG1 input to the control IC 148 falls at the timing of t3, as shown in FIG. 22(f), the start command setting process is executed at the timing of t4. As shown in FIG. 22(a), at the timing of t4, since the detection signal SG1 input to the control IC 148 is in the LOW state, as shown in FIG. 22(b), the control IC 148 clears the signal storage flag 144d to "0" at the timing of t4.

[0243] Thereafter, when the player operates the start lever 41 within the game startable period, as shown in FIGS. 22(a) and (c), the detection signal SG1 input to the control IC 148 and the control-side CPU 114 rises at the timing of t5. Here, the timing of t7 is the timing when 12.8 μs has elapsed from the timing of t5. As shown in FIG. 22(c), the detection signal SG1 input to the control-side CPU 114 remains in the HI state at the timing of t7 when 12.8 μs has elapsed after the detection signal SG1 input to the control-side CPU 114 rises.

[0244] Therefore, at the timing of t7, the control-side CPU 114 transmits a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register. As a result, as shown in FIG. 22(d), the numerical information of the random number stored in the random number counter 105 is written into the latch register 102 at the timing of t7. Also, as shown in FIG. 22(e), the control-side CPU 114 sets "1" in the latched status 113 at the timing of t7.

[0245] In this case, as shown in FIG. 22(f), at the timing of t6 which is after the timing of t5 and before the timing of t7, the start command setting process is executed. As shown in FIG. 22(a), at the timing of t6, since the detection signal SG1 input to the control IC 148 is in the HI state, as shown in FIG. 22(b), "1" is set in the signal storage flag 144d at the timing of t6. At the timing of t6 when the signal storage flag 144d changes from "0" to "1", the control IC 148 detects the rising edge of the detection signal SG1.

[0246] However, as shown in FIG. 22(e), at the timing of t6, the latched status 113 remains "0". Since the condition that "1" is set in the latched status 113 is not satisfied at the timing of t6, as shown in FIG. 22(g), the acquisition of the numerical information of the random number by the control IC 148 is not executed. In this case, as shown in FIG. 22(h), the control IC 148 adds "1" to the error counter 144b.

[0247] As shown in FIG. 22(f), at the timing of t8 which is after the timing of t7, the start command setting process is executed. As shown in FIG. 22(b), at the timing of t8, "1" has already been set in the signal storage flag 144d, and the control IC 148 does not detect the rising edge of the detection signal SG1 input to the control IC 148 at the timing of t8. Therefore, in the start command setting process performed at the timing of t8, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113. As a result, as shown in FIG. 22(e), the latched status 113 is cleared to "0" at the timing of t8.

[0248] Thus, in this slot machine 10 having the latched status 113, even if the start command setting process is executed before 12.8 μs elapses after the detection signal SG1 input to the control-side CPU 114 rises from the LOW state to the HI state, the control IC 148 can avoid obtaining an old random number and performing a winning / losing determination based on the old random number.

[0249] In such a configuration, even if fraud is committed to raise the detection signal SG1 from the LOW state to the HI state so that the start command setting process is performed before the random number stored in the random number counter 105 is written into the latch register 102, the control IC 148 will not obtain the same random number as the previous time and an error will occur. Then, the number of continuously occurring errors is counted by the error counter 144b. Therefore, it is possible to avoid a situation where a game result advantageous to the player is continuously obtained due to fraud.

[0250] When the condition for the control IC 148 to set "1" in the start command flag 144c is not satisfied at the timing when the player operates the start lever 41, the player needs to operate the start lever 41 again. However, since the start command setting process is executed in the timer interrupt process (FIG. 8) executed at a cycle of 1.49 ms, the frequency of the event that the start command setting process is performed within 12.8 μs after the player operates the start lever 41 is low. Therefore, the player will not frequently re-operate the start lever 41.

[0251] As shown in FIGS. 22(a) and (c), at the timing of t9 after the timing of t8, the detection signal SG1 input to the control IC148 and the control-side CPU114 falls. Then, at the timing of t10 after the timing of t9, as shown in FIG. 22(f), the start command setting process is executed. As shown in FIG. 22(a), at the timing of t10, since the detection signal SG1 input to the control IC148 is in the LOW state, as shown in FIG. 22(b), the control IC148 clears the signal storage flag 144d to "0".

[0252] Thereafter, during the game startable period, when the start lever 41 is operated by the player, as shown in FIGS. 22(a) and (c), at the timing of t11, the detection signal SG1 input to the control IC148 and the control-side CPU114 rises from the LOW state to the HI state. As shown in FIG. 22(c), at the timing of t12 when 12.8 μs has elapsed after the detection signal SG1 input to the control-side CPU114 has risen, the detection signal SG1 maintains the HI state. For this reason, at the timing of t12, the control-side CPU114 transmits a latch signal to the CLK terminals of the latch register D-FFs 102a to 102p. As a result, as shown in FIG. 22(d), the numerical information of the random number stored in the random number counter 105 is written into the latch register 102 at the timing of t12. Also, as shown in FIG. 22(e), the control-side CPU114 sets "1" in the latched status 113 at the timing of t12.

[0253] In this case, as shown in FIG. 22(f), the start command setting process is executed at the timing of t13 after the timing of t12. As shown in FIG. 22(a), at the timing of t13, since the detection signal SG1 input to the control IC 148 is in the HI state, as shown in FIG. 22(b), at the timing of t13, the control IC 148 sets "1" in the signal storage flag 144d. When the signal storage flag 144d changes from "0" to "1", the control IC 148 grasps the rising edge of the detection signal SG1 input to the control IC 148.

[0254] As shown in FIG. 22(e), at the timing of t13 when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, "1" is set in the latched status 113. Since the condition that "1" is set in the latched status 113 is satisfied at the timing when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, the control IC 148 sets "1" in the start command flag 144c. As shown in FIG. 22(g), in the lottery process (FIG. 11) executed at the timing of t14 after the timing of t13, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 and uses it for determining the success or failure of the role.

[0255] Also, at the timing of t13 when the control IC 148 sets "1" in the start command flag 144c, as shown in FIG. 22(h), the control IC 148 clears the error counter 144b to "0".

[0256] It is unlikely that the event of the start command setting process being performed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose is repeated. Even if this event occurs twice in a row, if the control IC 148 subsequently acquires numerical information of a random number corresponding to the operation of the start lever 41, the error counter 144b is cleared to "0." Therefore, the cases in which the value of the error counter 144b becomes "3" and the abnormality notification process (the process of step S311 of the start command setting process (FIG. 9)) is performed can be limited to almost all cases in which fraudulent attempts are made, such as changing the state of the detection signal SG1, and the connection between the start detection sensor 41a and the control-side CPU 114 is cut off.

[0257] Next, a case where noise of 12.8 μs or more occurs only in the control CPU 114 will be described with reference to the time chart of Fig. 23. Note that at the timings t1 to t4, the slot machine 10 is in a state where a game can be started.

[0258] Figure 23(a) shows the state of the detection signal SG1 input to the control IC 148, Figure 23(b) shows the state of the signal memory flag 144d, Figure 23(c) shows the state of the detection signal SG1 input to the control side CPU 114, Figure 23(d) shows the timing when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 23(e) shows the timing when the start command setting process is executed in the control IC 148, Figure 23(f) shows the state of the latched status 113, and Figure 23(g) shows the timing when the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148.

[0259] 23(c), noise enters the input terminal TB1 of the control-side CPU 114, and only the detection signal SG1 input to the control-side CPU 114 rises from a LOW state to a HIGH state from the timing t1 to the timing t3. The timing t3 is later than the timing t2, which is 12.8 μs after the timing t1.

[0260] As shown in FIG. 23(c), the detection signal SG1 input to the control-side CPU 114 rises at the timing of t1 and maintains the HI state from the timing of t1 until the timing of t2, which is 12.8 μs after the timing of t1. For this reason, the control-side CPU 114 transmits a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register at the timing of t2. As a result, as shown in FIG. 23(d), at the timing of t2, the numerical information of the random number stored in the random number counter 105 is written into the latch register 102. Further, as shown in FIG. 23(f), the control-side CPU 114 sets “1” in the latched status 113 at the same timing of t2.

[0261] As shown in FIG. 23(e), the start command setting process is executed at the timing of t4, which is after the timing of t3. As shown in FIG. 23(a), the detection signal SG1 input to the control IC 148 at the timing of t4 is in the LOW state, and the rising edge of the detection signal SG1 is not detected in the control IC 148. In this case, as shown in FIG. 23(f), the control IC 148 raises the signal output to the CLR terminal 113c of the latched status 113 in the start command setting process executed at the timing of t4, and clears the latched status 113 to “0”.

[0262] In this way, even if “1” is set in the latched status 113 at the timing of t2 due to the noise that enters only the input terminal TB1 of the control-side CPU 114, the latched status 113 is cleared to “0” in the start command setting process executed at the timing of t4 immediately after that.

[0263] If the latched status 113 is not cleared to "0" at the timing of t4, three conditions may be met at a later timing: a period in which the game can be started, a rising edge of the detection signal SG1 input to the control IC 148 is detected, and "1" is set to the latched status 113. In contrast, by configuring the control IC 148 to clear the latched status 113 to "0" at the timing of t4, it is possible to reduce the possibility that the control IC 148 will use the random number written to the latch register 102 in response to noise to determine whether the winning combination is correct or not.

[0264] As described above, the control-side CPU 114 is configured to send a latch signal to the CLK terminal of the latch register D-FFs 102a through 102p and set the latched status 113 to "1" when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102. The control IC 148 is also configured to acquire the numerical information of the random number input to the input terminal TA3 of the control IC 148 on the condition that the control IC 148 detects the rising edge of the detection signal SG1 when the game is ready to start and that the latched status 113 is set to "1" when the control IC 148 detects the rising edge of the detection signal SG1. This allows the numerical information of the random number acquired by the control IC 148 to be limited to the random number corresponding to the current operation of the start lever 41. This prevents the control IC 148 from acquiring an old random number and determining whether the winning combination is correct or not based on the old random number. By limiting the random number used to determine whether a winning combination is successful to the random number corresponding to the current operation of the start lever 41, it is possible to provide a gaming machine in which the winning combination is determined based on a random number that accurately reflects the player's actions.

[0265] Further, the control-side CPU 114 is configured to transmit a latch signal to the latch register 102 at the timing when it determines that the detection signal SG1 input to the control-side CPU 114 has become in the HI state and this HI state has continued for 12.8 μs. Therefore, when the rising edge of the detection signal SG1 is due to noise less than 12.8 μs, it is possible to avoid writing random numbers to the latch register 102 due to the noise.

[0266] Also, the main-side RAM 144 includes an error counter 144b. The error counter 144b is a counter that counts the number of times that, in a state where the game can be started, it is continuously determined that "1" is not set in the latched status 113 at the timing when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148. Then, when the value of the error counter 144b reaches "3", the control IC 148 performs an abnormality notification process. As one of the causes of the continuous occurrence of the event that "1" is not set in the latched status 113 at the timing when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, disconnection of the connection between the start detection sensor 41a and the control-side CPU 114 is conceivable. By performing an abnormality notification when the value of the error counter 144b reaches "3", it is possible to notify the game hall administrator that there is a high possibility that disconnection has occurred in the connection between the start detection sensor 41a and the control-side CPU 114.

[0267] Also, if the start command setting process is executed within 12.8 μs after the detection signal SG1 input to the control-side CPU 114 rises, there is a possibility that "1" will be set in the latched status 113 after the start command setting process. Also, even when noise of 12.8 μs or more is mixed only into the input terminal of the control-side CPU 114, "1" will be set in the latched status 113. If the state where "1" is set in the latched status 113 is maintained for a long time, the possibility that the start lever 41 will be operated in the state where "1" is set in the latched status 113 increases. In this case, similar to the case where the latched status 113 is not used, the control IC 148 may acquire an old random number and perform a validity determination of the role based on the old random number. On the other hand, when the rise of the detection signal SG1 input to the control IC 148 is not detected in the start command setting process, by configuring the control IC 148 to clear the latched status 113 to "0", the possibility that the control IC 148 acquires an old random number can be reduced.

[0268] Also, when the start lever 41 is operated during the game, a random number corresponding to the operation of the start lever 41 is written into the latch register 102, and "1" is set in the latched status 113. On the other hand, by configuring to clear the latched status 113 to "0" at the start timing of the period when the game can be started, it is possible to avoid the random number corresponding to the operation of the start lever 41 during the game from being used for the validity determination of the role.

[0269] Furthermore, when the start lever 41 is operated under the condition that the latched status 113 is set to "1", the random number stored in the latch register 102 is rewritten to a random number corresponding to the operation of the start lever 41. Therefore, even if noise enters only the input terminal of the control side CPU 114 and the latched status 113 is set to "1" as a result of the noise, it is possible to reduce the possibility that the random number written to the latch register 102 as a result of the noise will be used to determine whether the winning combination is successful or not.

[0270] Furthermore, in a configuration in which a latch signal is sent when the rising edge of the detection signal SG1 input to the control IC 148 is detected, the random number used to determine whether a winning combination has been achieved varies depending on the timing of the execution of the start command setting process, even if the timing at which the player operates the start lever 41 is the same. In contrast, by configuring the control CPU 114 to output a latch signal to the CLK terminals of the latch register D-FFs 102a-102p when it determines that the detection signal SG1 input to the control CPU 114 rises from a low state to a high state and that the high state has continued for 12.8 μs, the random number 12.8 μs after the rising edge of the detection signal SG1 input to the control CPU 114 is always used to determine whether a winning combination has been achieved. This allows the timing at which the player operates the start lever 41 to be accurately reflected in the game results.

[0271] <Second embodiment> In this embodiment, one of the conditions in the start command setting process is that the control IC 148 determines that the latched status 113 is not set to "1," and the state of the latched status 113 is determined again in the next start command setting process. Also, if the detection signal SG1 input to the control side CPU 114 no longer rises due to a wire break or the like, the control side CPU 114 raises the latch signal in response to receiving a signal from the main side MPU 142. Note that a description of the same configuration as in the first embodiment will basically be omitted.

[0272] FIG. 24 is a block diagram for explaining the configuration of the main control board 141 in the present embodiment. The control IC 148 includes output terminals TA5 (FIG. 24) in addition to input terminals TA1 to TA3 (FIG. 6) and output terminal TA4 (FIG. 6). Further, the control side CPU 114 includes an input terminal TB5 (FIG. 24) in addition to input terminals TB1 and TB2 (FIG. 6) and output terminals TB3 and TB4 (FIG. 6). The output terminal TA5 of the control IC 148 and the input terminal TB5 of the control side CPU 114 are connected by a signal line, and the signal output from the output terminal TA5 of the control IC 148 is input to the input terminal TB5 of the control side CPU 114.

[0273] Also, as shown in FIG. 24, in the main side RAM 144, a startable flag 144a, an error counter 144b, a start command flag 144c, a signal storage flag 144d, a confirmation command flag 144e, and an error status flag 144f are arranged.

[0274] Here, the confirmation command flag 144e is a flag for executing a process of determining the state of the latched status 113 again in the next start command setting process when the start command setting process (FIG. 25) is executed between when the detection signal SG1 rises and when "1" is set in the latched status 113. In this process, when it is determined that "1" is set in the latched status 113, the control IC 148 sets "1" in the start command flag 144c, and the game is started.

[0275] Also, the error status flag 144f is a flag that is set to "1" when "1" is not set in the latched status 113 in both the start command setting process (FIG. 25) in which the control IC 148 detects the rising of the detection signal SG1 input to the control IC 148 and the next start command setting process of the start command setting process.

[0276] Setting "1" to the error state flag 144f changes the content of the process by which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. When the error state flag 144f is set to "0", in the random number acquisition process (Fig. 28) of this embodiment, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 (Fig. 6) of the control IC 148.

[0277] Furthermore, if the error state flag 144f is set to "1," the random number acquisition process (FIG. 28) of this embodiment involves the control IC 148 transmitting a latch instruction signal to the control-side CPU 114. Here, the latch instruction signal is a signal that triggers the control-side CPU 114 to transmit a latch signal to the CLK terminal of the latch register D-FFs 102a to 102p. The latch instruction signal is output from the output terminal TA5 of the control IC 148 and input to the input terminal TB5 of the control-side CPU 114. After transmitting the latch instruction signal, if the latched status 113 is set to "1," the control IC 148 acquires numerical information of the random number input to the input terminal TA3 of the control IC 148. Details of the random number acquisition process will be described later.

[0278] Next, the start command setting process in this embodiment will be described with reference to Fig. 25. The start command setting process is executed in step S206 of the timer interrupt process (Fig. 8).

[0279] First, in step S801, it is determined whether or not the game is ready to start. If the game is ready to start, the start ready flag 144a is set to "1." If the game is not ready to start (step S801: NO), the start command setting process is terminated. Therefore, even if the player operates the start lever 41 during the game, the start command flag 144c will not be set to "1" based on that operation.

[0280] When in a game-startable state (step S801: YES), at step S802, it is determined whether "1" is set in the confirmation command flag 144e. The confirmation command flag 144e is a flag that is set to "1" at step S810 when "1" is not set in the latched status 113 at the timing when the rising edge of the detection signal SG1 input to the control IC 148 is detected in a game-startable state. The confirmation command flag 144e is cleared to "0" at step S812.

[0281] As cases where "1" is set in the confirmation command flag 144e, consider when the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rises, when noise enters only the input terminal of the control IC 148, and when the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected and the detection signal SG1 input to the control-side CPU 114 stops rising. Among these, if it is determined that "1" is not set in the latched status 113 in the start command setting process because the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rises, then "1" is set in the latched status 113 within 12.8 μs from this determination.

[0282] Therefore, when the control IC 148 determines that "1" is not set in the latched status 113, it sets "1" in the confirmation command flag 144e and ends the start command setting process. In the next start command setting process, it is determined again whether "1" is set in the latched status 113 on the condition that "1" is set in the confirmation command flag 144e. Thereby, when the player operates the start lever 41 and the detection signal SG1 rises, no matter at what timing the start command setting process is performed, the control IC 148 can obtain a random number corresponding to this operation of the start lever 41 based on this operation of the start lever 41.

[0283] By adopting a configuration in which the main-side RAM 144 is provided with a confirmation command flag 144e, it is possible to avoid a situation where the game does not start even if the player operates the start lever 41 in a state where the game can be started. In addition, it is possible to avoid a situation where the control IC 148 acquires an old random number that does not correspond to the operation of the current start lever 41.

[0284] When the confirmation command flag 144e is not set to "1" (step S802: NO), it is determined in steps S803 and S804 whether or not the rising edge of the detection signal SG1 input to the control IC 148 is detected. Specifically, in step S803, it is determined whether or not the value of the signal storage flag 144d is "0". When the value of the signal storage flag 144d is "0" (step S803: YES), in step S804, it is determined whether or not the detection signal SG1 input to the control IC 148 is in the HI state. Then, when it is determined in step S804 that the detection signal SG1 is in the HI state (step S804: YES), the signal storage flag 144d is set to "1" in step S805.

[0285] In this way, when the signal storage flag 144d changes from "0" to "1", the control IC 148 enters a state in which it has detected the rising edge of the detection signal SG1 input to the control IC 148.

[0286] In the following step S806, it is determined whether or not "1" is set in the latched status 113 based on the signal output from the Q terminal 113a (FIG. 6) of the latched status 113 and input to the input terminal TB2 of the control IC 148. If "1" is set in the latched status 113 (step S806: YES), this means that numerical information of a random number corresponding to the current operation of the start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, in step S807, the start command flag 144c is set to "1" so that the control IC 148 can obtain the numerical information of the random number input to the input terminal TA3 of the control IC 148 and start the game.

[0287] In the next step S808, the error counter 144b is cleared to "0." In this embodiment, the error counter 144b is a counter that is incremented by "1" when an event occurs in which the latched status 113 is not set to "1" in both the start command setting process in which the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148 and the start command setting process following the start command setting process. The error counter 144b is a counter used to determine whether the event is occurring consecutively.

[0288] Therefore, if it is confirmed that "1" is set in the latched status 113, the error counter 144b is cleared to "0" in step S808. Then, in step S809, a pulse signal is sent to the CLR terminal 113c (FIG. 6) of the latched status 113 to clear the latched status 113 to "0," and this start command setting process ends.

[0289] If it is determined in step S806 that the latched status 113 is not set to "1", then in step S810 the confirmation command flag 144e is set to "1" in order to again determine the state of the latched status 113 in the next start command setting process, and this start command setting process is terminated.

[0290] Furthermore, if it is determined in step S804 that the detection signal SG1 input to the control IC 148 is in a LOW state, this means that the rising edge of the detection signal SG1 has not been detected. In this case, since the signal storage flag 144d has already been set to "0," the latched status 113 is cleared to "0" in step S809, and the start command setting process ends.

[0291] Furthermore, if it is determined in step S803 that the signal storage flag 144d is set to "1," this means that the detection signal SG1 input to the control IC 148 was in a HI state and had already risen at the timing when the previous start command setting process was performed. In this case, in step S811, it is determined whether the detection signal SG1 input to the control IC 148 is in a LOW state. If the detection signal SG1 is in a LOW state (step S811: YES), the signal storage flag 144d is cleared to "0" in step S812.

[0292] After determining in step S811 that the detection signal SG1 input to the control IC 148 is in the HI state (step S811: NO), or after clearing the signal memory flag 144d to "0" in step S812, the latched status 113 is cleared to "0" in step S809, and this start command setting process is terminated.

[0293] Furthermore, if it is determined in step S802 that the confirmation command flag 144e is set to "1," this means that the current start command setting process is the next start command setting process following the start command setting process in which the confirmation command flag 144e was set to "1" in step S810. In this case, the confirmation command flag 144e is cleared to "0" in step S813, and it is determined in step S814 whether or not "1" is set in the latched status 113 based on the numerical information output from the Q terminal 113a of the latched status 113 and input to the input terminal TA2 of the control IC 148.

[0294] If it is determined in step S814 that "1" is set in the latched status 113, it means that the numerical information of the random number corresponding to the operation of the current start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, similar to the case where it is determined in step S806 that "1" is set in the latched status 113, the processes of steps S807 to S809 are executed. Specifically, "1" is set in the start command flag 144c (step S807), the error counter 144b is cleared to "0" (step S808). Then, the latched status 113 is cleared to "0" by sending a pulse signal to the CLR terminal 113c of the latched status 113 (step S809), and this start command setting process is terminated.

[0295] If it is determined in step S814 that "1" is not set in the latched status 113, error handling is performed in step S815 to terminate this start command setting process. The error handling is executed when "1" is not set in the latched status 113 during the period from when the detection signal SG1 input to the control IC 148 rises until the start command setting process is performed twice.

[0296] Next, the error handling executed in step S815 of the start command setting process (Fig. 25) will be described with reference to Fig. 26. Fig. 26 is a flowchart for explaining the error handling executed by the control IC 148.

[0297] First, in step S901, it is determined whether the value of the error counter 144b is "0." If the value of the error counter 144b is "0" (step S901: YES), in step S902, "1" is added to the error counter 144b. If the value of the error counter 144b is not "0" (step S901: NO), this means that the error handling process has been executed twice consecutively. In this case, it is highly likely that the connection between the start detection sensor 41a and the control-side CPU 114 has been cut off. Therefore, in step S903, an abnormality signal is sent to the management computer of the amusement hall to notify the manager of the amusement hall that there is a high possibility of a disconnection.

[0298] Possible cases in which an error handling process is performed include when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, and when noise is mixed into the control IC 148. If the value of the error counter 144b is "0," the possibility that noise has entered the control IC 148 cannot be ruled out, so only a latch instruction signal is sent without sending an abnormality signal. On the other hand, if the value of the error counter 144b is "1," there is a high possibility of a disconnection, so an abnormality signal is sent and a latch instruction signal is also sent.

[0299] When the detection signal SG1 input to the control CPU 114 does not rise even when the start lever 41 is pressed down, such as when the connection between the start detection sensor 41a and the control CPU 114 is cut off, the process of step S903 for transmitting an abnormality signal is continuously executed. The manager of the amusement hall can recognize that a disconnection has occurred by noticing that an abnormality signal is repeatedly being sent to the amusement hall's management computer.

[0300] After adding "1" to the error counter 144b in step S902, or after transmitting an abnormality signal in step S903, in step S904, the control-side CPU 114 transmits a latch instruction signal to the control-side CPU 114. When the control-side CPU 114 receives the latch instruction signal, it transmits a latch signal to the CLK terminal of the latch register D-FFs 102a to 102p (FIG. 6). As a result, the numerical information of the random number stored in the random number counter 105 is written to the latch register 102.

[0301] After transmitting the latch signal in step S904, the start command flag 144c is set to "1" in step S905, and the error state flag 144f is set to "1" in step S906, thereby terminating this error handling process.

[0302] When the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the control-side CPU 114 cannot grasp the timing at which the start lever 41 was operated. Therefore, even if the player operates the start lever 41, the numerical information of the random number stored in the random number counter 105 is not written to the latch register 102. In this state, if the control IC 148 obtains the numerical information of the random number input to the input terminal of the control IC 148, the winning or losing of the winning combination will be determined based on an old random number that does not correspond to the current operation of the start lever 41.

[0303] In response to this, the control IC 148 sends a latch instruction signal to the control side CPU 114, and the control side CPU 114, upon receiving the latch instruction signal, sends a latch signal to the latch register 102, so that the control IC 148 can obtain a random number corresponding to the current operation of the start lever 41. The occurrence of a disconnection is notified to the amusement hall manager, and the control IC 148 obtains a random number based on the operation of the start lever 41 until the amusement hall manager takes action, so that the amusement hall manager can perform maintenance at a timing that will not put players at an unfair disadvantage.

[0304] In this embodiment, there are two timings that trigger the control-side CPU 114 to send a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register. The first timing is when the detection signal SG1 input to the control-side CPU 114 rises from the LOW state to the HI state, and the control-side CPU 114 determines that the HI state of the detection signal SG1 continues for 12.8 μs. This timing is defined as the first timing.

[0305] Since the first timing is the timing after a certain period (12.8 μs) from when the detection signal SG1 input to the control-side CPU 114 rises after the player operates the start lever 41, the timing of the player operating the start lever 41 is strongly reflected.

[0306] The second timing is when the control IC 148 sends a latch instruction signal in step S904 of the error handling process (Fig. 26), and the control-side CPU 114 receives the latch instruction signal. This timing is defined as the second timing.

[0307] The error handling process is a process executed during the start command setting process (Fig. 25). The start command setting process is a process executed during the timer interrupt process (Fig. 8) that is executed at a cycle of 1.49 ms. There is a width of about 1.49 ms in the time from when the player operates the start lever 41 until the first timer interrupt process is executed. Specifically, the timer interrupt process may be executed immediately after the start lever 41 is operated, or the timer interrupt process may be executed about 1.49 ms after the start lever 41 is operated.

[0308] Thus, the second timing reflects the timing of the player operating the start lever 41, but it is not the timing that only reflects the operation timing of the start lever 41 by the player. The second timing also reflects elements that are not dependent on the player's actions.

[0309] Therefore, in this embodiment, in a normal state where the signal line connecting the start detection sensor 41a and the control-side CPU 114 is not disconnected, the numerical information of the random number stored in the random number counter 105 is written into the latch register 102 at the first timing. Accordingly, it is possible to perform a winning or losing determination using the numerical information of the random number strongly reflecting the operation timing of the start lever 41 by the player.

[0310] On the other hand, in an error state where the signal line connecting the start detection sensor 41a and the control-side CPU 114 is disconnected, since the detection signal SG1 input to the control-side CPU 114 does not rise, the control-side CPU 114 cannot grasp the first timing. In this case, the control IC 148 transmits a latch instruction signal to the control-side CPU 114, and the numerical information of the random number stored in the random number counter 105 is written into the latch register 102. Accordingly, even in an error state, it is possible to perform a winning or losing determination using the numerical information of the random number reflecting the operation timing of the start lever 41 by the player.

[0311] Next, the management operation executed by the control-side CPU 114 of this embodiment will be described with reference to FIG. 27. FIG. 27 is a flowchart showing the management operation in this embodiment.

[0312] First, in step S1001, it is determined whether a latch instruction signal has been received from the control IC 148. If the latch instruction signal has not been received in step S1001, then in step S1002, it is determined whether the detection signal SG1 input to the control-side CPU 114 is in the LOW state. If the detection signal SG1 input to the control-side CPU 114 is in the HI state in step S1002, the process returns to step S1001.

[0313] When the detection signal SG1 input to the control-side CPU 114 in step S1002 is in the LOW state, it is determined in step S1003 whether a latch instruction signal has been received. If the latch signal has not been received in step S1003, it is determined in step S1004 whether the detection signal SG1 input to the control-side CPU 114 is in the HI state. And when the detection signal SG1 input to the control-side CPU 114 is in the LOW state (step S1004: NO), the process returns to step S1003.

[0314] When the detection signal SG1 input to the control-side CPU 114 is in the HI state in step S1004, it means that the detection signal SG1 has risen from the LOW state to the HI state. In this case, in step S1005, counting of the time during which the HI state of the detection signal SG1 input to the control-side CPU 114 continues is started. The counting of the time is performed using a timer counter that counts time in units of 0.1 μs.

[0315] In the subsequent step S1006, it is determined whether a latch instruction signal has been received from the control IC 148. When the latch instruction signal has been received in step S1006 (step S1006: YES), a process of invalidating the latch instruction signal received this time is performed in step S1007. Specifically, based on the latch instruction signal received this time, a latch signal is not transmitted to the latch register 102, and the record of receiving the latch instruction signal is erased so that it can be determined that no latch instruction signal has been received until the next latch instruction signal is received.

[0316] After performing a negative determination in step S1006 or after invalidating the latch instruction signal in step S1007, in step S1008, it is determined whether the detection signal SG1 input to the control-side CPU 114 is in the HI state. And when the detection signal SG1 is in the HI state, in step S1009, it is determined whether 12.8 μs has elapsed since the timing when the rising edge of the detection signal SG1 input to the control-side CPU 114 from the LOW state to the HI state was detected. If 12.8 μs has not elapsed since the timing when the rising edge was detected, the process returns to step S1008.

[0317] And when it is determined in step S1009 that 12.8 μs has elapsed since the rising edge of the detection signal SG1 input to the control-side CPU 114 (step S1009: YES), in step S1010, other processing is performed and the process returns to step S1001. In the said other processing, the processing from step S706 to step S708 in the management operation (FIG. 19) of the first embodiment is executed.

[0318] Also, when the detection signal SG1 input to the control-side CPU 114 is in the LOW state in step S1008, that is, when the detection signal SG1 input to the control-side CPU 114 rises from the LOW state to the HI state and the detection signal SG1 returns to the LOW state before 12.8 μs has elapsed since the rising edge, in step S1011, the counting of time by the timer counter is stopped and the process returns to step S1003. In this case, the timer counter is reset.

[0319] Also, if a latch instruction signal is received in step S1001 or step S1003, a latch signal is transmitted to the latch register 102 in step S1012. Specifically, a pulse signal is transmitted to the CLK terminals of the D-FFs 102a to 102p for the latch register. Thereby, the numerical information of the random number stored in the random number counter 105 is written into the latch register 102. In the subsequent step S1013, "1" is set in the latched status 113, and the process returns to step S1001.

[0320] Thus, in step S1001 or step S1003 of this management operation, when a latch instruction signal is received from the control IC 148, a latch signal is transmitted to the CLK terminals of the D-FFs 102a to 102p for the latch register, and "1" is set in the latched status 113. Therefore, even when the connection between the start detection sensor 41a and the control side CPU 114 is disconnected, the control IC 148 can transmit a latch instruction signal to set "1" in the latched status 113 at the timing corresponding to the pressing operation of the start lever 41.

[0321] Also, when a negative determination is made in step S1004, the determination as to whether a latch instruction signal has been received (step S1003) and the determination as to whether the detection signal SG1 input to the control side CPU 114 is in the LOW state (step S1004) are repeated. Therefore, even when a latch instruction signal is received while waiting for the detection signal SG1 to become the HI state in step S1004, the process can proceed to the process of raising the latch signal output to the CLK terminals of the D-FFs 102a to 102p for the latch register (step S1002) and the process of setting "1" in the latched status 113 (step S1003).

[0322] Also, when the negative determination is made in step S1009, the determination as to whether the detection signal SG1 is in the HI state (step S1008) and the determination as to whether 12.8 μs has elapsed since the detection signal SG1 rose to the HI state (step S1009) are repeated.

[0323] As described above, when "1" is not set in the latched status 113 in both the start command setting process (Fig. 25) at the timing when the control IC148 detects the rise of the detection signal SG1 input to the control IC148 and the next start command setting process executed approximately 1.49 ms after the start command setting process, the control IC148 transmits a latch instruction signal to the control side CPU114. Since the start command setting process is executed in the timer interrupt process (Fig. 8) that is executed at a cycle of 1.49 ms, the two start command setting processes are not executed while waiting until 12.8 μs elapses in steps S1008 and S1009.

[0324] The processes of steps S1005 to S1009 of this management operation are processes that are executed until 12.8 μs elapses after the detection signal SG1 input to the input terminal TB1 of the control side CPU114 rises. Therefore, when noise is not considered, the latch instruction signal is not received while waiting until 12.8 μs elapses in steps S1005 to S1009.

[0325] On the other hand, when noise is mixed into the input terminal TA1 of the control IC148 where the detection signal SG1 is input, there is a possibility that it is determined that the latch instruction signal is received in step S1006 of this management operation.

[0326] Specifically, this is the case when noise is mixed only into input terminal TA1 of control IC 148, or when noise of less than 12.8 μs is mixed into both input terminal TA1 of control IC 148 and input terminal TB1 of control side CPU 114, and the start command setting process (Figure 25) is executed in control IC 148 while the signal input to input terminal TA1 of control IC 148 is in a HI state due to the mixed noise.

[0327] In this case, the control IC 148 sets the confirmation command flag 144e to "1" in the start command setting process. If the signal input to the input terminal TB1 of the control side CPU 114 rises from a LOW state to a HIGH state at a timing after the start command setting process and before the next start command setting process, which is executed approximately 1.49 ms after the start command setting process, it may be determined that a latch instruction signal has been received from the control IC 148 in step S1006 of this management operation.

[0328] In this way, if a latch instruction signal is received in step S1006 of this management operation, the latch instruction signal has been affected by noise. For this reason, the control-side CPU 114 is configured to invalidate the latch instruction signal if it is determined in step S1006 that the signal has been received. This reduces the possibility that the control IC 148 will obtain the numerical information of the random number written to the latch register 102 due to noise and use the numerical information of the random number to determine whether the hand has been won or not.

[0329] Next, the random number acquisition process executed in step S501 of the lottery process (FIG. 11) will be described with reference to the flowchart of FIG. 28. The random number acquisition process is executed by the control IC 148.

[0330] First, in step S1101, it is determined whether "1" is set in the error status flag 144f. When "1" is not set in the error status flag 144f (step S1101: NO), it means that the detection signal SG1 input to the control side CPU 114 rises from the LOW state to the HI state, and the control side CPU 114 grasps that the HI state of the detection signal SG1 has continued for 12.8 μs or more. At this timing, the control side CPU 114 sends a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register. Therefore, when a negative determination is made in step S1101, the control IC 148 has already confirmed that "1" is set in the latched status 113.

[0331] On the other hand, when "1" is set in the error status flag 144f (step S1101: YES), it means that the control IC 148 sends a latch instruction signal to the control side CPU 114, and the control side CPU 114 that has received the latch instruction signal sends a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register. In this case, it is necessary to confirm that the numerical information of the random number stored in the random number counter 105 has been written into the latch register 102. Therefore, in step S1102, the error status flag 144f is cleared to "0", and in step S1103, it waits until "1" is set in the latched status 113. Then, when it is determined that "1" is set in the latched status 113 (step S1103: YES), in step S1104, a pulse signal is sent to the CLR terminal of the latched status 113 to clear the latched status 113 to "0".

[0332] After a negative determination is made in step S1101, or after the latched status 113 is cleared to "0" in step S1104, in step S1105, the numerical information of the random number input to the input terminal of the control IC 148 is acquired, and this random number acquisition process is terminated.

[0333] Even when the connection between the start detection sensor 41a and the control side CPU 114 is disconnected, the control IC 148 is configured to acquire the numerical information of the random number input to the input terminal of the control IC 148 on the condition that "1" is set in the latched status 113. Therefore, it is possible to avoid a situation where the control IC 148 acquires the numerical information of the random number written to the latch register 102 before the operation of the start lever 41 this time.

[0334] Next, the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 will be described with reference to the timing charts of FIGS. 29 and 30.

[0335] First, with reference to the timing chart of FIG. 29, a case will be described in which the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control side CPU 114 has risen. Note that at the timings of t1 to t5, the slot machine 10 is in a state where the game can be started.

[0336] FIG. 29(a) shows the state of the detection signal SG1 input to the control IC 148, FIG. 29(b) shows the state of the signal storage flag 144d, FIG. 29(c) shows the state of the detection signal SG1 input to the control side CPU 114, FIG. 29(d) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, FIG. 29(e) shows the timing at which the start command setting process is executed in the control IC 148, FIG. 29(f) shows the state of the latched status 113, FIG. 29(g) shows the state of the confirmation command flag 144e, and FIG. 29(h) shows the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148.

[0337] When the player operates the start lever 41 at the timing of t1, as shown in FIGS. 29(a) and (c), the detection signal SG1 input to the control IC 148 and the control-side CPU 114 rises from the LOW state to the HI state.

[0338] The timing of t3 is the timing when 12.8 μs has elapsed since the timing of t1 when the detection signal SG1 input to the control-side CPU 114 rises. Also, the timing of t2 is the timing after the timing of t1 and before the timing of t3. As shown in FIG. 29(e), the start command setting process is executed at the timing of t2. As shown in FIG. 29(a), at the timing of t2, the detection signal SG1 input to the control IC 148 is in the HI state. Therefore, as shown in FIG. 29(b), at the timing of t2, the control IC 148 sets "1" in the signal storage flag 144d. When the signal storage flag 144d changes from "0" to "1", the control IC 148 detects the rising edge of the detection signal SG1.

[0339] As shown in FIG. 29(f), at the timing of t2 when the control IC 148 detects the rising edge of the detection signal SG1, the value of the latched status 113 is "0". Therefore, as shown in FIG. 29(g), the control IC 148 sets "1" in the confirmation command flag 144e in the start command setting process executed at the timing of t2.

[0340] As shown in FIG. 29(c), the detection signal SG1 input to the control-side CPU 114 rises at the timing of t1 and maintains the HI state until the timing of t3, which is 12.8 μs after the rise. Therefore, at the timing of t3, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register D-FFs 102a to 102p. As a result, as shown in FIG. 29(d), the numerical information of the random number stored in the random number counter 105 is written into the latch register 102 at the timing of t3. Also, as shown in FIG. 29(f), the control-side CPU 114 sets "1" in the latched status 113 at the timing of t3.

[0341] Thereafter, as shown in FIG. 29(e), the start command setting process is executed at the timing of t4, which is after the timing of t3. As shown in FIG. 29(g), "1" is set in the confirmation command flag 144e at the timing of t4, and as shown in FIG. 29(f), "1" is also set in the latched status 113. Therefore, at the timing of t4 as shown in FIG. 29(f), the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0", and as shown in FIG. 29(g), clears the confirmation command flag 144e to "0".

[0342] Also, the control IC 148 sets "1" in the start command flag 144c at the same timing of t4. Therefore, in the lottery process (FIG. 11) executed at the timing of t5, which is after the timing of t4, as shown in FIG. 29(h), the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148.

[0343] Thus, when "1" is not set in the latched status 113 at the timing when the control IC 148 detects the rising edge of the detection signal SG1, the confirmation command flag 144e is set to "1". When "1" is set in the confirmation command flag 144e and "1" is set in the latched status 113 in the start command setting process, the control IC 148 sets "1" in the start command flag 144c and acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Therefore, even if the start command setting process is executed before 12.8 μs elapses after the detection signal SG1 input to the control side CPU 114 rises, the control IC 148 can acquire the numerical information of the random number corresponding to the operation of the start lever 41 this time.

[0344] Next, the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 with the connection between the start detection sensor 41a and the control side CPU 114 disconnected will be described with reference to the time chart of FIG. 30. Note that at the timings of t1 to t5 and t8 to t12, the slot machine 10 is in a state where the game can be started.

[0345] Figure 30(a) shows the state of the detection signal SG1 input to the control IC148, Figure 30(b) shows the state of the signal storage flag 144d, Figure 30(c) shows the state of the detection signal SG1 input to the control-side CPU 114, Figure 30(d) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 30(e) shows the timing at which the start command setting process is executed by the control IC148, Figure 30(f) shows the state of the latched status 113, Figure 30(g) shows the timing at which the control IC148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC148, Figure 30(h) shows the state of the confirmation command flag 144e, Figure 30(i) shows the state of the error counter 144b, and Figure 30(j) shows the timing at which the control IC148 transmits an abnormal signal to the management computer of the game hall.

[0346] As shown in Figure 30(a), when the player operates the start lever 41 at the timing of t1, the detection signal SG1 input to the control IC148 rises from the LOW state to the HI state. As shown in Figure 30(c), since the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected, the detection signal SG1 input to the control-side CPU 114 remains in the LOW state.

[0347] As shown in Figure 30(e), when the start command setting process is executed at the timing of t2, which is after the timing of t1 when the detection signal SG1 rises, as shown in Figure 30(a), since the detection signal SG1 input to the control IC148 is in the HI state at the timing of t2, as shown in Figure 30(b), the control IC148 sets "1" in the signal storage flag 144d. As a result, the control IC148 detects the rising of the detection signal SG1.

[0348] At time t2, a period during which the game can be started is detected, and the rising edge of the detection signal SG1 is detected. However, as shown in FIG. 30(f), the latched status 113 is not set to "1." Therefore, as shown in FIG. 30(g), the control IC 148 does not acquire a random number at time t2. As shown in FIG. 30(h), the control IC 148 sets the confirmation command flag 144e to "1" in the start command setting process performed at time t2, and ends this start command setting process.

[0349] As shown in FIG. 30(e), the next start command setting process following the start command setting process executed at time t2 is executed at time t3, approximately 1.49 ms after time t2. Because the player's operation of the start lever 41 is a human action, it is longer than the interval at which the start command setting process is executed. Therefore, as shown in FIG. 30(a), the detection signal SG1 is in the HI state even at time t3. Also, as shown in FIG. 30(h), the confirmation command flag 144e is set to "1" at time t3. However, because the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the latched status 113 is not set to "1" even at time t3, as shown in FIG. 30(f). Also, as shown in FIG. 30(i), the value of the error counter 144b is "0" at time t3. Therefore, as shown in Fig. 30(h), the control IC 148 clears the confirmation command flag 144e to "0" in the start command setting process executed at timing t3, and performs the error handling process (Fig. 26). Then, as shown in Fig. 30(i), the control IC 148 increments the error counter 144b by "1" in the error handling process executed at timing t3.

[0350] Also, the control IC 148 transmits a latch instruction signal in the error handling process executed at the timing of t3. The control-side CPU 114 that has received the latch instruction signal transmits the latch instruction signal to the CLK terminals of the latch register D-FFs 102a to 102p. As a result, as shown in FIG. 30(d), at the timing of t4 after the timing of t3, the control-side CPU 114 transmits a latch signal to update the numerical information of the random numbers stored in the latch register 102, and as shown in FIG. 30(f), sets "1" in the latched status 113.

[0351] As shown in FIG. 30(g), in the random number acquisition process (FIG. 29) executed at the timing of t5 after the timing of t4, the control IC 148 acquires the numerical information of the random numbers input to the input terminal TA3 of the control IC 148 and starts the game. Also, as shown in FIG. 30(f), at the same timing of t5, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0".

[0352] Thereafter, as shown in FIG. 30(a), the detection signal SG1 input to the control IC 148 falls at the timing of t6. Then, as shown in FIG. 30(e), the start command setting process is executed at the timing of t7 after the timing of t6. As shown in FIG. 30(a), since the detection signal SG1 input to the control IC 148 is in the LOW state at the timing of t7, as shown in FIG. 30(b), the control IC 148 clears the signal storage flag 144d to "0".

[0353] After that, the game started at timing t5 ends, and when the player operates the start lever 41 at timing t8 as shown in FIG. 30(a), the detection signal SG1 input to the control IC148 rises. Then, at timing t9 after timing t8, as shown in FIG. 30(e), a start command setting process is executed. As shown in FIG. 30(a), since the detection signal SG1 input to the control IC148 is in the HI state at timing t9, as shown in FIG. 30(b), the control IC148 sets "1" in the signal storage flag 144d at timing t9. When the signal storage flag 144d changes from "0" to "1", the control IC148 detects the rising edge of the detection signal SG1.

[0354] As shown in FIG. 30(f), since the value of the latched status 113 is "0" at timing t9, as shown in FIG. 30(h), the control IC148 sets "1" in the confirmation command flag 144e and ends the current start command setting process.

[0355] As shown in FIG. 30(e), at timing t10 after timing t9, the next start command setting process after the start command setting process executed at timing t9 is performed. As shown in FIG. 30(h), "1" is set in the confirmation command flag 144e at timing t10. Also, as shown in FIG. 30(f), the value of the latched status 113 is "0" at timing t10. And, as shown in FIG. 30(i), the value of the error counter 144b is "1" at timing t10. Such a situation indicates that, despite the rising edge of the detection signal SG1 being detected by the control IC148, the event that "1" is not set in the latched status 113 has occurred continuously twice triggered by the rising edge of the detection signal SG1. When such an event occurs continuously twice, there is a high possibility that the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected.

[0356] Therefore, as shown in FIG. 30(h), the control IC 148 clears the confirmation command flag 144e to "0" at the timing of t10 and performs error handling. As shown in FIG. 30(j), the control IC 148 transmits an abnormal signal to the management computer of the game hall in the error handling performed at the timing of t10, notifying the administrator of the game hall that there is an abnormality in the behavior of the detection signal SG1 input to the control side CPU 114.

[0357] Also, the control IC 148 transmits a latch instruction signal in the error handling executed at the timing of t10. The control side CPU 114 that has received the latch instruction signal from the control IC 148 transmits a latch signal to the CLK terminals of the latch register D-FFs 102a to 102p. As a result, as shown in FIG. 30(d), the numerical information of the random number stored in the random number counter 105 is written into the latch register 102 at the timing of t11. Also, as shown in FIG. 30(f), the control side CPU 114 sets "1" to the latched status 113 at the same timing of t11.

[0358] Thereafter, in the lottery process (FIG. 11) executed at the timing of t12, as shown in FIG. 30(g), the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Also, as shown in FIG. 30(f), at the same timing of t12, the control IC 148 clears the latched status 113 to "0".

[0359] In this way, when only the detection signal SG1 input to the control IC 148 rises and the detection signal SG1 input to the control-side CPU 114 does not rise, the control IC 148 transmits a latch instruction signal according to the timing at which the rise of the detection signal SG1 is detected in the control IC 148. Then, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register D-FFs 102a to 102p upon receiving the latch instruction signal. As a result, even when the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected, it is possible to perform a winning or losing determination using the numerical information of the random number according to the timing when the player operates the start lever 41.

[0360] Also, when, despite the rise of the detection signal SG1 being detected in the control IC 148, an event occurs two or more times in a row where "1" is not set in the latched status 113 according to the rise of the detection signal SG1, in the error handling after the second time, the control IC 148 transmits an abnormal signal to the management computer of the game hall. Thereby, it is possible to notify the administrator of the game hall that the game is continuing in a state where there is an abnormality in the behavior of the detection signal SG1 input to the input terminal TA3 of the control-side CPU 114.

[0361] As described above, when the start command setting process is executed in a state where the game can be started, the rising edge of the detection signal SG1 input to the control IC 148 is detected, and it is determined that the latched status 113 is not set to "1," the confirmation command flag 144e is set to "1," and the state of the latched status 113 is determined again in the next start command setting process. If the latched status 113 is set to "1" in the next start command setting process after the start command setting process that ended with the confirmation command flag 144e set to "1," the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Therefore, even if the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose, the win / loss determination can be performed using the numerical information of the random number corresponding to the current operation of the start lever 41.

[0362] Furthermore, if the latched status 113 is not set to "1" despite the detection of a rising edge of the detection signal SG1 input to the control IC 148, the control IC 148 transmits a latch instruction signal. The control-side CPU 114 then transmits a latch signal to the CLK terminals of the latch register D-FFs 102a-102p upon receiving the latch instruction signal. If the latched status 113 is not set to "1" despite the detection of a rising edge of the detection signal SG1 input to the control IC 148 two or more consecutive times, the control IC 148 transmits an abnormality signal to the gaming hall's management computer in the error handling process for the second or subsequent occurrences. This allows the control IC 148 to continue acquiring the random number information written to the latch register 102 upon depression of the start lever 41, even if the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected. Furthermore, the gaming hall manager can perform maintenance on the slot machine 10 at a time that does not disadvantage players.

[0363] Also, in the start command setting process executed in a game startable state, when the rising edge of the detection signal SG1 input to the control IC 148 is not detected, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113 in order to clear the latched status 113 to "0". For this reason, even if noise enters only the control side CPU 114 before the player operates the start lever 41 and "1" is set in the latched status 113 due to the noise, if the start command setting process is executed between when the noise enters and when the player operates the start lever 41, the latched status 113 is cleared to "0" in the start command setting process. When the start lever 41 is operated with "1" set in the latched status 113, it is possible to reduce the possibility that the control IC 148 acquires numerical information of an old random number that does not correspond to the current operation of the start lever 41.

[0364] <Another form of the second embodiment> In the error handling process (Fig. 26) of the second embodiment described above, when the value of the error counter 144b is "1" (step S901: NO), the control IC 148 may be configured to directly acquire the numerical information of the random number from the random number counter 105. Here, the direct acquisition of the random number by the control IC 148 means that the control IC 148 acquires the numerical information of the random number output from the Q terminals of the D-FFs 105a to 105p for the random number counter without passing through the latch register 102.

[0365] FIG. 31(a) is a block diagram for explaining the connection mode between the control IC 148 included in the main control board 141 and the random number counter 105. The configuration of the main control board 141 in this configuration will be described using this block diagram. Note that the same configuration as that of the main control board 141 in the second embodiment is omitted. As shown in FIG. 31(a), in the main control board 141 of this configuration, the signal lines coming out from the Q terminals of the D-FFs 105a to 105p for the random number counter are branched and connected to the D terminals of the D-FFs 102a to 102p for the latch register and the input terminal TA6 of the control IC 148. Therefore, the numerical information of the random numbers stored in the random number counter 105 is output to each of the latch register 102 and the input terminal TA6 of the control IC 148. The numerical information of the random numbers output to the latch register 102 is written into the latch register 102 at the timing when a pulse signal is transmitted to the CLK terminals of the D-FFs 102a to 102p for the latch register. Also, the numerical information of the random numbers output to the input terminal TA3 of the control IC 148 is acquired by the control IC 148 when the detection signal SG1 input to the control IC 148 rises and the "1" is not set in the latched status 113.

[0366] Here, the input terminal TA3 (FIG. 6) of the control IC 148 into which the numerical information of the random numbers output from the Q terminals of the D-FFs 102a to 102p for the latch register is input is a different input terminal from the input terminal TA6 (FIG. 31(a)) of the control IC 148 into which the numerical information of the random numbers output from the Q terminals of the D-FFs 105a to 105p for the random number counter is input. Therefore, the control IC 148 can selectively acquire by distinguishing the numerical information of the random numbers output from the latch register 102 and the numerical information of the random numbers output from the random number counter 105.

[0367] When the control IC 148 directly acquires the numerical information of the random numbers output from the Q terminals of the D-FFs 105a to 105p for the random number counter and input to the input terminal TA6 of the control IC 148, the processing of step S904 is omitted in the error handling processing (FIG. 26) in the second embodiment. The error handling processing in this configuration will be specifically described below.

[0368] If the value of the error counter 144b is "0" (step S901: YES), the control IC 148 adds "1" to the error counter 144b (step S902) and then sets the start command flag 144c to "1" (step S905). Then, the control IC 148 sets the error state flag 144f to "1" (step S906) and ends this error handling process. On the other hand, if the value of the error counter 144b is "1" (step S901: NO), the control IC 148 sends an abnormality signal to the gaming hall's management computer (step S903) and then sets the start command flag 144c to "1" (step S905). Then, the control IC 148 sets the error state flag 144f to "1" (step S906) and ends this error handling process.

[0369] As described above, the control IC 148 in this configuration does not transmit a latch instruction signal to the control-side CPU 114. The management operation executed by the control-side CPU 114 in this configuration has the same processing configuration as the management operation executed by the control-side CPU 114 in the first embodiment (FIG. 19).

[0370] Specifically, the control CPU 114 first waits until the detection signal SG1 input to it goes low (step S701), and if it goes low (step S701: YES), it waits until the detection signal SG1 goes high (step S702). If the detection signal SG1 goes high (step S702: YES), it starts counting the time the high state continues using a timer counter (step S703).

[0371] When 12.8 μs has elapsed while the detection signal SG1 remains in the HI state (step S704: YES, step S705: YES), the counting of time using the timer counter is stopped (step S706). Then, a latch signal is transmitted to the CLK terminals of the latch register D-FFs 102a to 102p (step S707), "1" is set in the latched status 113, and the process returns to the first process (step S701) of waiting until the detection signal SG1 becomes LOW again.

[0372] Also, when the HI state of the detection signal SG1 returns to the LOW state in less than 12.8 μs (step S704: NO), the counting of time by the timer counter is stopped (step S709), and the timer counter is reset. Then, the process returns to the second process (step S702) of waiting until the detection signal SG1 becomes HI again.

[0373] Next, the random number acquisition process when the control IC 148 directly acquires the numerical information of the random number stored in the random number counter 105 in this configuration will be described with reference to the flowchart of FIG. 31(b).

[0374] First, in step S1201, it is determined whether "1" is set in the error status flag 144f. In step S1201, the case where "1" is set in the error status flag 144f is the case where the numerical information of the random number corresponding to the operation of the start lever 41 this time is not written to the latch register 102. In this case, in step S1202, the error status flag 144f is cleared to "0", and in step S1203, the numerical information of the random number output from the Q terminals of the random number counter D-FFs 105a to 105p and input to the input terminal TA3 (FIG. 6) of the control IC 148 is acquired, and this random number acquisition process is terminated.

[0375] Also, in step S1201, the case where "1" is not set in the error state flag 144f means that the numerical information of the random number corresponding to the operation of the start lever 41 this time has already been written into the latch register 102. In this case, in step S1204, the numerical information of the random number output from the latch register 102 and input to the input terminal TA6 (FIG. 31(a)) of the control IC148 is acquired, and this random number acquisition process is terminated.

[0376] In this way, the control IC148 of this configuration can acquire random numbers in two ways. Among these, the random number output from the Q terminals of the D-FFs 102a to 102p for the latch register and input to the input terminal TA3 of the control IC148 and acquired by the control IC148 is defined as the indirectly acquired random number. The indirectly acquired random number is the random number stored in the random number counter 105 12.8 μs after the rising edge of the detection signal SG1 input to the control side CPU 114 is detected. The timing at which the indirectly acquired random number is acquired is the random number stored in the random number counter 105 after a certain time from the timing at which the detection signal SG1 rises, and the certain time is a relatively short time of 12.8 μs.

[0377] On the other hand, the random number output from the Q terminals of the D-FFs 105a to 105p for the random number counter and input to the input terminal TA6 of the control IC148 and acquired by the control IC148 is defined as the directly acquired random number. The directly acquired random number is the random number acquired in the timer process (FIG. 8) executed by the control IC148. The timing at which the directly acquired random number is acquired is the random number stored in the random number counter 105 after an indefinite time from the timing at which the detection signal SG1 rises, and the indefinite time is within the time range of 1.49 ms. And the time of 1.49 ms is a long time when compared with 12.8 μs.

[0378] Therefore, the indirectly acquired random number is a random number that more significantly reflects the operation timing of the start lever 41 by the player than the directly acquired random number. This configuration is such that, in a state where the connection between the start detection sensor 41a and the control-side CPU 114 is not disconnected, the determination of the success or failure of a role is executed using the indirectly acquired random number, and in a state where the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected, the random number used for the determination of the success or failure of a role is switched to the directly acquired random number.

[0379] With this configuration, the operation timing of the start lever 41 by the player can be accurately reflected in the game result, and even when the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected, the random number used for the determination of the success or failure of a role can be updated according to the operation timing of the start lever 41.

[0380] <Third Embodiment> In this embodiment, the timing at which the control-side CPU 114 sets "1" in the latched status 113 is limited to the period during which the game can be started. Also, the control IC 148 starts the game when the detection signal SG1 input to the control IC 148 is in the HI state and "1" is set in the latched status 113. Note that the description of the same configuration as that of the first embodiment above is basically omitted.

[0381] FIG. 32 is a block diagram for explaining the configuration of the main control board 141 in this embodiment. As shown in FIG. 32, the main-side MPU 142 of this embodiment includes a control IC 148 and a hardware random number circuit 146. And the hardware random number circuit 146 includes a control circuit 103, an update circuit 101, and a latch register 102.

[0382] The update circuit 101 of this embodiment has the same configuration as the update circuit 101 (Fig. 6) of the first embodiment described above. Therefore, the update circuit 101 includes a clock circuit 104 and a random number counter 105. And the random number counter 105 of this embodiment has the same configuration as the random number counter 105 of the first embodiment described above. Specifically, the random number counter 105 is composed of 16 D-FFs 105a to 105p for random number counters (Fig. 6).

[0383] Also, the latch register 102 of this embodiment has the same configuration as the latch register 102 of the first embodiment described above. Specifically, the latch register 102 is composed of 16 D-FFs 102a to 102p for latch registers (Fig. 6).

[0384] Also, the control circuit 103 of this embodiment has the same configuration as the control circuit 103 (Fig. 6) of the first embodiment described above. Specifically, the control circuit 103 includes a control-side CPU 114 and a latched status 113. The control-side CPU 114 is a CPU that executes processing using a program. A program for executing a management operation (Fig. 35) is stored in the ROM 115 of the control-side CPU 114, and a storage area for temporarily storing information is set in the RAM 116 of the control-side CPU 114.

[0385] Also, as shown in Fig. 32, the main-side RAM 144 in this embodiment includes an error counter 144b and a start command flag 144c. The control IC 148 has an output terminal TA7, and the control-side CPU 114 has an input terminal TB7. The output terminal TA7 of the control IC 148 and the input terminal TB7 of the control-side CPU 114 are connected by a signal line, and the startable signal output from the output terminal TA7 of the control IC 148 is input to the input terminal TB7 of the control-side CPU 114.

[0386] In the normal process (Fig. 34), when the start timing of the game - startable period is reached, the control IC 148 raises the start - enable signal, and when the end timing of the game - startable period is reached, the control IC 148 lowers the start - enable signal. Therefore, the control - side CPU 114 can determine whether it is the game - startable period by grasping the state of the start - enable signal input to the input terminal TB7. The control - side CPU 114 in this embodiment sets "1" to the latched status 113 with the condition that it is the game - startable period. The details of the normal process (Fig. 34) in this embodiment will be described later.

[0387] Also, as shown in Fig. 32, the control - side CPU 114 has an output terminal TB6 connected to the CLR terminal 113c of the latched status 113. Here, the control IC 148 in this embodiment does not have an output terminal connected to the CLR terminal 113c of the latched status 113. In this embodiment, the "0" clearing of the latched status 113 is performed by the control - side CPU 114.

[0388] Specifically, after the control - side CPU 114 sets "1" to the latched status 113, if the start - enable signal falls to the LOW state before a certain time elapses, it means that the timing for the game to start has been reached in the normal process (Fig. 34) executed after the control IC 148 sets "1" to the latched status 113. In this case, at the timing of the fall, a pulse signal is transmitted from the output terminal TB6 to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0".

[0389] Also, after the control-side CPU 114 sets "1" in the latched status 113, if the startable signal does not fall to the LOW state even after a certain period of time has elapsed, it means that noise has entered only the input terminal TB1 of the control-side CPU 114, and based on this noise, the control-side CPU 114 has set "1" in the latched status 113.

[0390] Specifically, when noise enters only the input terminal TB1 of the control-side CPU 114, the signal input to the input terminal TB1 rises from the LOW state to the HI state, and when the HI state is maintained for 12.8 μs, the control-side CPU 114 sends a latch signal to the latch register 102 and sends a pulse signal to the T terminal 113b of the latched status 113 to set "1" in the latched status 113.

[0391] In this case, since the detection signal SG1 input to the input terminal TA1 of the control IC 148 does not rise, the startable signal does not fall. The control-side CPU 114 is configured to determine whether it is in the middle of a game based on the signal output from the output terminal TA7 of the control IC 148 and input to the input terminal TB7 of the control-side CPU 114. When the control-side CPU 114 sets "1" in the latched status 113 due to noise and the state where "1" is set in the latched status 113 is maintained for a long time, the player will operate the start lever 41 in the state where "1" is set in the latched status 113.

[0392] When the start lever 41 is operated while the latched status 113 has "1" set therein, the detection signal SG1 input to the input terminal TA1 of the control IC 148 and the input terminal TB1 of the control-side CPU 114 rises from the LOW state to the HI state. When the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 rises to the HI state and the HI state is maintained for 12.8 μs or more, at the timing when 12.8 μs has elapsed since the rise of the detection signal SG1, the control-side CPU 114 outputs a latch signal to the latch register 102 and transmits a pulse signal to the T terminal 113b of the latched status 113 to set "1" in the latched status 113.

[0393] In this case, when the start command setting process is executed at the timing before 12.8 μs has elapsed since the rise of the detection signal SG1 input to the input terminal TA1 of the control IC 148 and the detection signal SG1 rises, the detection signal SG1 input to the input terminal TA1 of the control IC 148 is in the HI state at the timing when the start command setting process is performed, and since "1" is set in the latched status 113, the control IC 148 sets "1" in the start command flag 144c at this timing. Therefore, in the normal process performed thereafter, there is a possibility that the control IC 148 executes role lottery using the numerical information of the random number written in the latch register 102 due to noise mixing.

[0394] On the other hand, when the startable signal input to the input terminal TB7 of the control-side CPU 114 does not fall from the HI state to the LOW state until a certain time has elapsed since the timing when the control-side CPU 114 set "1" in the latched status 113, by configuring the control-side CPU 114 to clear the latched status 113 to "0", it is possible to reduce the possibility that the control IC 148 executes role success or failure lottery using the numerical information of the random number written in the latch register 102 due to noise mixing.

[0395] Here, the above-mentioned fixed time is a time longer than the maximum time from when the detection signal SG1 rises until the startable signal falls in the slot machine 10, and in this embodiment, it is set to 5 ms. In the slot machine 10, the maximum time from when the detection signal SG1 rises until the startable signal falls is experimentally determined at the design stage.

[0396] Next, the start command setting process executed in step S206 of the timer interrupt process (FIG. 8) will be described with reference to FIG. 33. FIG. 33 is a flowchart showing the start command setting process executed in the control IC 148.

[0397] First, in step S1301, it is determined whether it is a period in which the game can be started. If it is not a period in which the game can be started (step S1301: NO), this start command setting process is terminated as it is. If it is determined that it is a period in which the game can be started (step S1301: YES), the process proceeds to step S1302.

[0398] In step S1302, it is determined whether the detection signal SG1 input to the control IC 148 is in the HI state. If the detection signal SG1 is in the LOW state (step S1302: NO), this start command setting process is terminated as it is. If the detection signal SG1 is in the HI state (step S1302: YES), in step S1303, it is determined whether "1" is set in the latched status 113. If "1" is set in the latched status 113 (step S1303: YES), since it means that the condition for starting the game is satisfied, in step S1304, "1" is set in the start command flag 144c, the error counter 144b is cleared to "0", and this start command setting process is terminated.

[0399] Here, in the present embodiment, the condition for starting the game is that, under the situation where the detection signal SG1 input to the control IC 148 is in the HI state, "1" is set in the latched status 113.

[0400] Also, when "1" is not set in the latched status 113 in step S1303, the same processing as steps S308 to S312 in the start command setting process (FIG. 9) of the first embodiment is executed in steps S1306 to S1309.

[0401] Specifically, after adding "1" to the error counter 144b (step S1306), when the error counter 144b becomes "3" (step S1307: YES), the error counter 144b is cleared to "0" (step S1308), and abnormal notification processing is executed (step S1309). Also, when the error counter 144b after adding "1" is 2 or less (step S1307: NO), this start command setting process is terminated as it is.

[0402] In this way, the control IC 148 is configured to start the game on the condition that the detection signal SG1 input to the control IC 148 is in the HI state and "1" is set in the latched status 113. Therefore, when the start command setting process is executed at the timing before the numerical information of the random number stored in the latch register 102 is updated after 12.8 μs has elapsed since the detection signal SG1 output from the start detection sensor 41a rises to the HI state, compared with the configuration of setting a flag for checking the state of the latched status 113 again in the next start command setting process, the processing load for the control IC 148 to grasp the timing of starting the game can be reduced.

[0403] Next, the normal processing executed in the control IC 148 will be described with reference to Fig. 34. First, in step S1401, the same processing as step S401 in the normal processing (Fig. 10) of the first embodiment is executed. Specifically, an interrupt permission processing is executed to permit the next timer interrupt processing (Fig. 8).

[0404] In the next step S1402, the same process as step S402 in the normal process (FIG. 10) of the first embodiment is executed. Specifically, a start waiting process is executed. Here, when a medal return process is executed in the start waiting process of this embodiment, the control IC 148 clears the start command flag 144c to "0" and lowers the start possible signal at the start timing of the medal return process.

[0405] By clearing the start command flag 144c to "0" at the start timing of the medal return process, it is possible to avoid a situation in which the game starts before the start lever 41 is operated when the number of medals bet reaches the specified number again. Also, by turning off the start enable signal, it is possible to avoid a situation in which the control side CPU 114 sets "1" to the latched status 113 after the medals are returned.

[0406] In the next step S1403, the same process as step S403 in the normal process (FIG. 10) of the first embodiment is executed. Specifically, if the number of bets has not reached the specified number (step S1403: NO), the process returns to step S1402, and if the number of bets has reached the specified number (step S1403: YES), the process proceeds to step S1404.

[0407] In step S1404, it is determined whether the start possible signal output from output terminal TA7 (FIG. 32) of control IC 148 is in a HI state. If the start possible signal is in a LOW state (step S1404: NO), this means that it is time to start the period in which the game can be started, so in step S1405 the start possible signal is raised to a HI state. This allows the control side CPU 114, which has received the start possible signal, to know the start time of the period in which the game can be started.

[0408] Furthermore, if the start enable signal is in a HI state in step S1404, this means that the period in which the game can be started has already begun. After a negative determination is made in step S1404 or after the start enable signal is set to a HI state in step S1405, it is determined in step S1406 whether or not the start command flag 144c is set to "1," and if the start command flag 144c is not set to "1" (step S1406: NO), the process returns to step S1402.

[0409] Furthermore, if the start command flag 144c is set to "1" in step S1406 (step S1406: YES), this means that the random number information corresponding to the current operation of the start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, the start command flag 144c is cleared to "0" in step S1407, and the start possible signal is turned off in step S1408. This allows the control CPU 114, which is receiving the start possible signal, to know that the timing has come to the end of the period in which the game can be started.

[0410] In the following step S1409, other processing is performed, and the process returns to step S1401. In the other processing, the same processing as that in steps S410 to S416 in the normal processing (FIG. 10) of the first embodiment is performed.

[0411] Next, the management operation executed by the control-side CPU 114 will be described with reference to the flowchart of FIG. 35. First, in step S1501, it is determined whether it is a period during which the game can be started. Specifically, if the startable signal output from the output terminal TA7 of the control IC 148 and input to the input terminal TB7 of the control-side CPU 114 is in the LOW state, it is determined that it is outside the period during which the game can be started, and the process waits until the startable signal rises to the HI state. If the startable signal is in the HI state, it is determined that it is a period during which the game can be started, and the process proceeds to step S1502.

[0412] In steps S1502 to S1510, the same processing as steps S701 to S708 of the management operation (FIG. 19) in the above-described first embodiment is executed. Specifically, it waits until the detection signal SG1 input to the control-side CPU 114 becomes the LOW state (step S1502). When the detection signal SG1 input to the control-side CPU 114 becomes the LOW state (step S1502: YES), it waits until the detection signal SG1 becomes the HI state (step S1503).

[0413] When the detection signal SG1 input to the control-side CPU 114 becomes the HI state (step S1503: YES), the counting of the time during which the detection signal SG1 maintains the HI state is started using the timer counter (step S1504). In this embodiment, this count is referred to as the first count. After starting the first count, it is determined whether the HI state of the detection signal SG1 input to the control-side CPU 114 is maintained for at least 12.8 μs (steps S1505, S1506). If the duration of the HI state of the detection signal SG1 is less than 12.8 μs (step S1505: NO), the first count is stopped and the timer counter is reset (step S1507), and the process returns to step S1503.

[0414] Also, when it is determined that the detection signal SG1 has maintained the HI state for 12.8 μs or more (step S1505: YES, step S1506: YES), the first count is stopped and the timer counter is reset (step S1508). Then, a latch signal is transmitted to the CLK terminals of the latch register D-FFs 102a to 102p (step S1509), and "1" is set in the latched status 113 (step S1510).

[0415] After setting "1" in the latched status 113 in step S1510, in step S1511, the timer counter is used to start counting the time during which the state where "1" is set in the latched status 113 continues. This count is referred to as the second count. In the subsequent step S1512, it is determined whether the start enable signal is in the LOW state. If the start enable signal is in the HI state (step S1512: NO), then in step S1513, it is determined whether 5 ms has elapsed since "1" was set in the latched status 113. If 5 ms has not elapsed, the process returns to step S1512.

[0416] If the start enable signal is in the LOW state in step S1512, it means that the period during which the game can be started has ended. Therefore, in step S1514, the second count is stopped and the timer counter is reset. Then, in step S1515, a pulse signal is transmitted to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0", and the process returns to step S1501.

[0417] Also, when an affirmative determination is made in step S1513, it means that "1" was not set in the start command flag 144c in the start command setting process executed by the control IC 148 until 5 ms elapsed since "1" was set in the latched status 113. Such a state occurs when noise is mixed into the input terminal TB1 of the control side CPU 114 and, triggered by the mixing of this noise, "1" is set in the latched status 113.

[0418] In this case, the second count is stopped and the timer counter is reset in step S1516, a pulse signal is sent to the CLR terminal 113c of the latched status 113 in step S1517 to clear the latched status 113 to "0", and the process returns to step S1502.

[0419] In this way, the control-side CPU 114 determines whether it is a period in which the game can be started, and sets "1" in the latched status 113 with the condition that it is a period in which the game can be started. Therefore, the processing load for the control IC 148 to execute the start command setting process can be reduced.

[0420] Also, detecting the rising edge of the detection signal SG1 input to the control-side CPU 114 from the LOW state to the HI state is one of the conditions for setting "1" in the latched status 113. Therefore, when the start lever 41 is pushed down and the push-down operation continues for a long time, the process of setting "1" in the latched status 113 according to the start timing of the push-down operation is performed only once. The process of setting "1" in the latched status 113 is not repeatedly performed in response to the continuation of the push-down operation.

[0421] Also, the fact that it is a period in which the game can be started is one of the conditions for setting "1" in the latched status 113. Therefore, even if the start lever 41 is pushed down outside the period in which the game can be started, "1" will not be set in the latched status 113 due to the push-down operation.

[0422] Here, the process of lowering the startable signal to the LOW state is the process of step S1408 in the normal process (Fig. 34) performed by the control IC 148. Further, the process of step S1408 is performed on the condition that "1" is set in the start command flag 144c. Then, the process of setting "1" in the start command flag 144c (the process of step S1304 in the start command setting process (Fig. 33)) is performed on one condition that "1" is set in the latched status 113.

[0423] Therefore, after it is determined in step S1501 of this management operation that the startable signal is in the HI state, the startable signal will not fall to the LOW state until "1" is set in the latched status 113 in step S1510. For example, while waiting in step S1502 until the detection signal SG1 becomes the LOW state, while waiting in step S1503 until the detection signal SG1 becomes the HI state, and while waiting in steps S1505 and S1506 until it is determined that the HI state of the detection signal SG1 continues for 12.8 μs or more, the startable signal will not fall to the LOW state.

[0424] Also, it is configured to set "1" in the latched status 113 on some conditions that it is a period in which the game can be started and that the detection signal SG1 input to the control-side CPU 114 rises from the LOW state to the HI state. Therefore, when the pressing operation of the start lever 41 is started during the game and it becomes a period in which the game can be started while the pressing operation continues, "1" will not be set in the latched status 113 due to the pressing operation. In this slot machine 10, the game is started on one condition that the start lever 41 is operated in a state where the game can be started.

[0425] Next, timing at which the control IC 148 acquires numerical information of a random number input to the input terminal TA3 of the control IC 148 will be described with reference to the time chart of FIG. 36. FIG. 36(a) shows the state of the detection signal SG1 input to the control IC 148, FIG. 36(b) shows the state of the detection signal SG1 input to the control side CPU 114, FIG. 36(c) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, FIG. 36(d) shows the state of the latched status 113, FIG. 36(e) shows the timing at which the start command setting process is executed in the control IC 148, FIG. 36(f) shows the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, FIG. 36(g) shows the state of the start command flag 144c, FIG. 36(h) shows the period during which the game can be started, and FIG. 36(i) shows the state of the error counter 144b.

[0426] When noise is mixed only into the input terminal TB1 of the control side CPU 114 at the timing of t1, as shown in FIG. 36(a), the detection signal SG1 input to the control side CPU 114 rises from the LOW state to the HI state. The HI state of the detection signal SG1 continues until the timing of t3. At the timing of t2 which is 12.8 μs after the timing of t1 and is the timing before the timing of t3, the control side CPU 114 transmits a latch signal to the CLK terminals of the D-FFs 102a to 102p for the latch register and transmits a pulse signal to the T terminal 113b of the latched status 113. As a result, as shown in FIG. 36(c), the random number stored in the random number counter 105 is written to the latch register 102 at the timing of t2, and as shown in FIG. 36(d), "1" is set in the latched status 113.

[0427] As shown in Fig. 36(e), at the timing t4 after the timing t3, the start command setting process is executed by the control IC 148. As shown in Fig. 36(a), since the detection signal SG1 input to the control IC 148 at the timing t4 is in the LOW state, as shown in Fig. 36(g), the control IC 148 does not set "1" to the start command flag 144c at the timing t4. In this case, as shown in Fig. 36(d), at the timing t5 which is after the timing t4 and 5 ms has elapsed from the timing t3, the control side CPU 114 clears the latched status 113 to "0".

[0428] As shown in Figs. 36(a) and (b), at the timing t6 after the timing t5, the start lever 41 is pushed down, and the detection signal SG1 input to the control IC 148 and the control side CPU 114 rises from the LOW state to the HI state. As shown in Fig. 36(e), at the timing t7 which is after the timing t6 and before the timing t8 at which 12.8 μs has elapsed from the timing t6, the start command setting process is executed.

[0429] At the timing t7, as shown in Fig. 36(a), the detection signal SG1 input to the control IC 148 is in the HI state, but as shown in Fig. 36(d), since "1" is not set to the latched status 113, as shown in Fig. 36(g), the control IC 148 does not set "1" to the start command flag 144c at the timing t7. As shown in Fig. 36(i), the control IC 148 adds "1" to the error counter 144b at the timing t7.

[0430] Thereafter, at the timing of t8, the control-side CPU 114 transmits a latch signal to the CLK terminals of the D-FFs 102a to 102p for the random number counter and transmits a pulse signal to the T terminal 113b of the latched status 113. As a result, as shown in FIG. 36(c), the random number stored in the random number counter 105 is written into the latch register 102, and as shown in FIG. 36(d), "1" is set in the latched status 113.

[0431] Thereafter, as shown in FIG. 36(e), the start command setting process is executed at the timing of t9. At the timing of t9, as shown in FIG. 36(a), the detection signal SG1 input to the control IC 148 is in the HI state, and as shown in FIG. 36(d), "1" is set in the latched status 113. Therefore, as shown in FIG. 36(g), the control IC 148 sets "1" in the start command flag 144c at the timing of t9, and clears the error counter 144b to "0" as shown in FIG. 36(i).

[0432] In the normal process executed at the timing of t10 after the timing of t9, the control IC 148 clears the start command flag 144c to "0" as shown in FIG. 36(g), and lowers the start enable signal to the LOW state to end the game startable period as shown in FIG. 36(h).

[0433] The control-side CPU 114 clears the latched status 113 to "0" as shown in FIG. 36(d) at the timing of t9 when the start enable signal falls. Also, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 in the lottery process executed at the timing of t9.

[0434] Thus, when "1" is set to the latched status 113 triggered by the noise that only enters the control-side CPU 114, the latched status 113 is cleared to "0" after 5 ms. Therefore, it is possible to avoid a situation where the start lever 41 is operated while "1" is set in the latched status 113 and the control IC 148 obtains an old random number.

[0435] Also, when the detection signal SG1 input to the control IC 148 is in the HI state, the control IC 148 is configured to always determine whether "1" is set in the latched status 113. Therefore, even when the start command setting process is executed before 12.8 μs elapses after the rising edge of the detection signal SG1 output from the start detection sensor 41a, the control IC 148 can obtain a random number corresponding to the operation of the start lever 41 this time.

[0436] Next, a case where the start lever 41 is pushed down with the connection between the start detection sensor 41a and the input terminal TB1 of the control-side CPU 114 disconnected will be described with reference to the time chart of FIG. 37. FIG. 37(a) shows the detection signal SG1 input to the control IC 148, FIG. 37(b) shows the timing of the start command setting process executed by the control IC 148, FIG. 37(c) shows the state of the error counter 144b, and FIG. 37(d) shows the timing when the abnormality notification process is executed. Here, the connection between the start detection sensor 41a and the input terminal TB1 of the control-side CPU 114 is disconnected. Also, the timings t1 to t4 are periods during which the game can start.

[0437] As shown in FIG. 37(a), when the start lever 41 is operated at the timing of t1, the detection signal SG1 input to the control IC 148 rises from the LOW state to the HI state. Thereafter, as shown in FIG. 37(b), start command setting processing is executed at the timing of t2 and at the timing of t3 which is about 1.49 ms after the timing of t2. As shown in FIG. 37(a), the detection signal SG1 input to the control IC 148 is in the HI state at the timings of t2 to t4, but since the detection signal SG1 input to the control side CPU 114 does not rise, "1" is not set in the latched status 113.

[0438] Therefore, as shown in FIG. 37(c), "1" is added to the error counter 144b at each of the timings of t2 and t3. In the start command setting process executed at the timing of t4, "1" is added to the error counter 144b, and when the value of the error counter 144b becomes "3", the control IC 148 clears the error counter 144b to "0" at the timing of t4 as shown in FIG. 37(c), and executes abnormal notification processing as shown in FIG. 37(d) to notify the game hall manager that the "1" is not set in the latched status 113.

[0439] In this way, in the start command setting process, when it is determined that the detection signal SG1 input to the control IC 148 is in the HI state and it is determined that "1" is not set in the latched status 113, if this event occurs continuously three times, abnormal notification processing is executed. For this reason, it is possible to avoid a situation where the "1" is not set in the latched status 113 and the determination of the winning or losing of a combination using an old random number that does not correspond to the operation of the start lever 41 is repeated.

[0440] As described above, as conditions for setting "1" in the latched status 113 in the control-side CPU 114, there are set a condition that it is a period during which the game can be started, a condition that a rising edge of the detection signal SG1 input to the control-side CPU 114 is detected, and a condition that the HI state of the detection signal SG1 input to the control-side CPU 114 continues for 12.8 μs or more from the detection of the rising edge. For this reason, the conditions for setting "1" in the start command flag 144c in the start command setting process by the control IC 148 are limited to a condition that the detection signal SG1 input to the control IC 148 is in the HI state and a condition that "1" is set in the latched status 113. Thereby, the processing load for the control IC 148 to set "1" in the start command flag 144c can be reduced.

[0441] Also, the timing for the control-side CPU 114 to set "1" in the latched status 113 is limited only to the period during which the game can be started. The control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 when both the condition that the detection signal SG1 input to the control IC 148 is in the HI state and the condition that "1" is set in the latched status 113 are satisfied. For this reason, even when the start command setting process is executed before the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, the control IC 148 can acquire the random number corresponding to the operation of the start lever 41.

[0442] In the start command setting process, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 on the condition that the detection signal SG1 input to the control IC 148 is in the HI state, and starts the game. At the timing when the control IC 148 starts the game, since the player is in the state of pressing down the start lever 41, even if the timing for the control IC 148 to acquire the numerical information of the random number is delayed due to the deviation of the timing at which each process is performed, the game can be started while the player continues to press down the start lever 41.

[0443] Specifically, if the start command setting process is executed at a timing before "1" is set in the latched status 113 after the player starts pressing down the start lever 41, then in the next start command setting process of the start command setting process, "1" is set in the start command flag 144c, and the game is started.

[0444] Therefore, there are cases where the game starts with "1" set in the start command flag 144c in the first start command setting process executed after the player operates the start lever 41, and cases where the game starts with "1" set in the start command flag 144c in the second start command setting process executed after the player operates the start lever 41. When "1" is set in the start command flag 144c in the second start command setting process, the timing at which the game starts is delayed compared to the case where "1" is set in the start command flag 144c in the first start command setting process.

[0445] However, in any case, at the timing when the game starts, the player is in the state of continuing to press down the start lever 41. Therefore, it is possible to avoid the game starting after the player's operation of pressing down the start lever 41 ends and giving the player a sense of discomfort regarding the game start timing.

[0446] Also, by configuring the control-side CPU 114 to clear the latched status 113 to "0" at the timing when 5 ms has elapsed since "1" was set in the latched status 113, it is possible to avoid a situation where "1" is set in the latched status 113 due to noise and the start lever 41 is operated while this state is maintained, causing the control IC 148 to acquire an old random number.

[0447] The control-side CPU 114 makes it a part of the condition for transmitting a pulse signal to the CLK terminals of the latch register D-FFs 102a to 102p that the game can be started and the rising edge of the detection signal SG1 is detected in the control-side CPU 114. For this reason, even if the player continues to press down the start lever 41 during the game and the start timing of the period when the game can be started is reached while the start lever 41 is being pressed down, the game will not start immediately after this start timing. The game can be configured to start only when the start lever 41 is operated within the period when the game can be started.

[0448] <Fourth Embodiment> The hardware random number circuit 146 in this embodiment includes two latch registers 407 and 408 (FIG. 39). Different numerical information of random numbers is written into the two latch registers 407 and 408 at different timings. The numerical information of the two random numbers written into the two latch registers 407 and 408 is used for different lotteries. Note that the description of the same configuration as in the first embodiment is basically omitted.

[0449] First, while referring to FIG. 38, the differences from the correspondence relationship (FIG. 4) in the first embodiment will be described regarding the correspondence relationship between the combination of symbols that result in a winning in this embodiment and the benefits granted when a winning occurs.

[0450] In this embodiment, there are a first cherry role and a second cherry role as cherry roles. First, the first cherry role will be described. In this embodiment, when the first cherry is won, it becomes the preparation state ST31 (FIG. 47) of the advantageous AT state ST3 (FIG. 47) for the player. In this embodiment, when the first cherry is won and further the first cherry prize is won, a gaming medium is awarded. That is, the first cherry prize is a small winning.

[0451] Specifically, when the stop symbol of the left reel 32L on the main line ML becomes the "cherry" symbol, the first cherry prize is won regardless of whether the stop symbols of the middle reel 32M and the right reel 32R are symbols other than the "cherry" symbol (the "bell" symbol, the "watermelon" symbol, the "replay" symbol, the "red 7" symbol, and the "white 7" symbol). The number of gaming media to be awarded when the first cherry prize is won is "2" in a gaming state other than the BB state. On the other hand, the first cherry prize is excluded from the winning targets in the BB state.

[0452] On the other hand, when the first cherry is won but the first cherry prize is not won, no gaming medium is awarded. In this case, the combination of the stop symbol of the left reel 32L, the stop symbol of the middle reel 32M, and the stop symbol of the right reel 32R on the main line ML is the combination of stop symbols that aligns only in this case. Therefore, the player can grasp that the first cherry has been won and that the first cherry prize has not been won by looking at the combination of the stop symbols.

[0453] Here, the number of games set as the number of games for which the AT state ST3 continues is defined as the number of continuable games. When the first cherry winning occurs in a state other than the AT state ST3, "30" is set as the number of continuable games. Also, when the first cherry winning occurs in the AT state ST3, "30" is added to the set number of continuable games. When shifting to the second RT mode in the preparation state ST31 of the AT state ST3, it becomes the base state ST32 (Fig. 47) of the AT state ST3. The number of continuable games is not subtracted while in the preparation state ST31, and "1" is subtracted each time one game ends when it becomes the base state ST32. Details of the said AT state ST3 will be described later.

[0454] Next, the second cherry role will be described. In the present embodiment, when the second cherry winning occurs, it becomes the preparation state ST31 (Fig. 47) of the advantageous AT state ST3 (Fig. 47) for the player. In the present embodiment, when the second cherry winning occurs and further the second cherry prize winning occurs, game media are awarded. That is, the second cherry prize winning is a small winning.

[0455] Specifically, when the stop symbol of the left reel 32L on the main line ML is the "cherry" symbol, the stop symbol of the middle reel 32M is the "cherry" symbol, and the stop symbol of the right reel 32R is the "cherry" symbol, the second cherry prize winning occurs. The number of game media to be awarded when the second cherry prize winning occurs is "2" if it is a game state other than the BB state. On the other hand, the second cherry prize winning is excluded from the winning target in the BB state.

[0456] On the other hand, when the second cherry winning occurs but the second cherry prize winning does not occur, no game media are awarded. In this case, the combination of the stop symbol of the left reel 32L, the stop symbol of the middle reel 32M, and the stop symbol of the right reel 32R on the main line ML is the combination of stop symbols that aligns only in this case. Therefore, the player can grasp that the second cherry winning has occurred and that the second cherry prize winning has not occurred by looking at the combination of the stop symbols.

[0457] In the state other than the AT state ST3, when the second cherry is won, "300" is set as the number of continuable games. Further, when the first cherry is won in the AT state ST3, "300" is added to the set number of continuable games. The details of the AT state ST3 will be described later.

[0458] Next, while referring to FIG. 39, the configuration of the main control board 141 of the present embodiment will be described in terms of the differences from the main control board 141 (FIG. 6) of the first embodiment. FIG. 39 is a block diagram showing the configuration of the main control board 141 in the present embodiment.

[0459] As shown in FIG. 39, the main MPU 142 includes a control IC 148 and a hardware random number circuit 146. First, the configuration of the control IC 148 will be described. The control IC 148 includes a main ROM 143 that stores various control programs and fixed value data executed by the control IC 148, and a main RAM 144 that is a memory for temporarily storing various data and the like when executing the control programs stored in the main ROM 143. The main RAM 144 in the present embodiment includes a startable flag 144a, a signal storage flag 144d, a first start command flag 144g, and a second start command flag 144h. The main RAM 144 also includes an addition random number counter (not shown). In the addition random number counter, the addition random number used for addition lottery is updated. The addition random number counter of the main RAM 144 is a loop counter in which "1" is added to the previous value each time the update timing is reached, and after reaching the maximum value "65535", it returns to "0". The control IC 148 updates the addition random number in the timer interrupt process (FIG. 8) executed every 1.49 ms. The addition lottery is performed when winning the watermelon role in the game performed in the base state ST32 of the AT state ST3, and when winning in the addition lottery, the number of continuable games is added.

[0460] As shown in FIG. 39, the start detection sensor 41a and the control IC 148 are connected by a single signal line. A detection signal SG2 is output from the start detection sensor 41a. The detection signal SG2 is a signal that is in the LOW state when the start lever 41 is not operated, and becomes the HI state when the start lever 41 is pushed down.

[0461] The first start command flag 144g is a flag in which "1" is set on the condition that the rising edge of the detection signal SG2 input to the control IC 148 is detected. The control IC 148 acquires the numerical information of the first random number, which is the first random number, on the condition that "1" is set in the first start command flag 144g. The second start command flag 144h is a flag in which "1" is set on the condition that the falling edge of the detection signal SG2 input to the control IC 148 is detected. The control IC 148 acquires the numerical information of the second random number, which is the second random number, when "1" is set in the second start command flag 144h.

[0462] Note that the main-side RAM 144 of the present embodiment does not include the error counter 144b (FIG. 5) and the start command flag 144c (FIG. 5), which are different from the main-side RAM 144 of the first embodiment.

[0463] Next, the configuration of the hardware random number circuit 146 will be described. As shown in FIG. 39, the hardware random number circuit 146 of the present embodiment includes an update circuit 101 including a random number counter 105, latch registers 407 and 408 in which the numerical information of the random number stored in the random number counter 105 is temporarily written, and management circuits 403 and 404 that transmit a latch signal to the latch registers 407 and 408 when the input signal rises to the HI state and the HI state continues for 12.8 μs. Specifically, the hardware random number circuit 146 of the present embodiment includes a first latch register 407 and a second latch register 408 as latch registers, and a first management circuit 403 and a second management circuit 404 as management circuits.

[0464] As shown in FIG. 39, one signal line output from the start detection sensor 41a branches at two branch points 171 and 172 on the main control board 141. Specifically, the signal line output from the start detection sensor 41a branches into two at the first branch point 171 on the main control board 141. One of the signal lines branched at the first branch point 171 is connected to the input terminal TA1 of the control IC 148. Therefore, the detection signal SG2 output from the start detection sensor 41a is input to the input terminal TA1 of the control IC 148.

[0465] Also, the other of the signal lines branched at the first branch point 171 branches into two at the second branch point 172 on the main control board 141. One of the signal lines branched at the second branch point 172 is connected to the first management circuit 403, and the other of the signal lines branched at the second branch point 172 is connected to the second management circuit 404 via an inversion circuit 431 arranged on the main control board 141. Therefore, the detection signal SG2 is input to the first management circuit 403, and the inverted detection signal SG3 generated by inverting the detection signal SG2 is input to the second management circuit 404.

[0466] The first management circuit 403 is a hardware circuit equipped with a timer counter in which "1" is subtracted from the set value in units of 0.1 μs. The value "128" is set in advance in the timer counter. In the first management circuit 403, when the signal input to the first management circuit 403 rises from the LOW state to the HI state, the countdown by the timer counter starts. The countdown by the timer counter continues until the value of the timer counter becomes "0" while the detection signal SG2 input to the first management circuit 403 maintains the HI state. Then, when the value of the timer counter becomes "0", a latch signal is transmitted from the first management circuit 403 to the first latch register 407. In this case, the timer counter is reset and enters a state in which the initial value "128" is set. When the timer counter is reset, the state in which the initial value is set is maintained until the detection signal SG2 input to the first management circuit 403 rises again. Also, when the detection signal SG2 input to the first management circuit 403 rises from the LOW state to the HI state, the countdown by the timer counter starts, and if the detection signal SG2 falls to the LOW state before the value of the timer counter becomes "0", the countdown by the timer counter stops. In this case, the timer counter is reset and enters a state in which the initial value is set.

[0467] The second management circuit 404 has the same configuration as the first management circuit 403 described above. An inverted detection signal SG3 is input to the second management circuit 404. Therefore, when the inverted detection signal SG3 rises to the HI state and this HI state is maintained for 12.8 μs, a latch signal is output from the second management circuit 404 to the second latch register 408.

[0468] Also, the update circuit 101 in this embodiment has the same configuration as the update circuit 101 in the first embodiment. Specifically, the update circuit 101 includes a clock circuit 104 and a random number counter 105. The clock circuit 104 outputs a clock signal of 16 MHz. Then, the numerical information of the random numbers stored in the random number counter 105 is updated at the timing when the clock signal rises. Also, the random number counter 105 is composed of 16 D-FFs 105a to 105p for random number counters (FIG. 6) and has a storage area of 2 bytes. The random numbers stored in the random number counter 105 are 16-bit binary numbers.

[0469] Also, each of the first latch register 407 and the second latch register 408 has the same configuration as the latch register 102 in the first embodiment. Specifically, the first latch register 407 and the second latch register 408 are each composed of 16 D-FFs and have a storage area of 2 bytes. If the D-FFs constituting the first latch register 407 are the D-FFs 407a to 407p for the first latch, and the D-FFs constituting the second latch register 408 are the D-FFs 408a to 408p for the second latch. 16-bit binary numbers are stored in each of the first latch register 407 and the second latch register 408.

[0470] One signal line coming out from the Q terminals of the D-FFs 105a to 105p for random number counters branches into two in the middle. One of the signal lines after branching is connected to the D terminals of the D-FFs 407a to 407p for the first latch register, and the other signal line after branching is connected to the D terminals of the D-FFs 408a to 408p for the second latch register. Specifically, one signal line coming out from the Q terminals of the D-FFs 105a to 105p for random number counters that store the nth digit numerical information in the random number counter 105 is connected to the D terminals of the D-FFs 407a to 407p for the first latch that store the nth digit numerical information in the first latch register 407 and the D terminals of the D-FFs 408a to 408p for the second latch that store the nth digit numerical information in the second latch register 408. Here, n is a natural number from 1 to 16.

[0471] The CLK terminals of the first latch D-FFs 407a to 407p are connected to the first management circuit 403, and the CLK terminals of the second latch D-FFs 408a to 408p are connected to the second management circuit 404. More specifically, one signal line output from the first management circuit 403 branches into 16 lines which are connected to the CLK terminals of the first latch D-FFs 407a to 407p, and one signal line output from the second management circuit 404 branches into 16 lines which are connected to the CLK terminals of the second latch D-FFs 408a to 408p. Also, as shown in Fig. 39, the Q terminals of the first latch D-FFs 407a to 407p are connected to input terminal TA8 of the control IC 148, and the Q terminals of the second latch D-FFs 408a to 408p are connected to input terminal TA9 of the control IC 148.

[0472] Therefore, when the first management circuit 403 transmits a latch signal to the CLK terminals of the first latch D-FFs 407a to 407p, the numerical information of the random numbers stored in the random number counter 105 is written into the first latch register 407 and output to the input terminal TA8 of the control IC 148. When the second management circuit 404 transmits a latch signal to the CLK terminals of the second latch D-FFs 408a to 408p, the numerical information of the random numbers stored in the random number counter 105 is written into the second latch register 408 and output to the input terminal TA9 of the control IC 148.

[0473] Regarding the relationship between the state of the detection signal SG2 output from the start detection sensor 41a and the timing at which the latch signal is output from the first management circuit 403 and the second management circuit 404, it will be described with reference to the time chart of FIG. 40. FIG. 40(a) shows the state of the start lever 41, FIG. 40(b) shows the state of the detection signal SG2 input to the first management circuit 403, FIG. 40(c) shows the state of the timer counter in the first management circuit 403, FIG. 40(d) shows the timing at which the first management circuit 403 transmits the latch signal to the first latch register 407, FIG. 40(e) shows the state of the inverted detection signal SG3 input to the second management circuit 404, FIG. 40(f) shows the state of the timer counter in the second management circuit 404, and FIG. 40(g) shows the timing at which the second management circuit 404 transmits the latch signal to the second latch register 408.

[0474] As shown in FIG. 40(a), when the start lever 41 is pushed down at the timing of t1, as shown in FIG. 40(b), the detection signal SG2 input to the first management circuit 403 rises from the LOW state to the HI state. Then, as shown in FIG. 40(c), at the timing of t1, the time counting by the timer counter in the first management circuit 403 is started. In this timer counter, the value is subtracted from the initial value of "128" to "1" every 0.1 μs. Also, as shown in FIG. 40(e), at the timing of t1, the inverted detection signal SG3 input to the second management circuit 404 falls from the HI state to the LOW state.

[0475] As shown in FIG. 40(b), the HI state of the detection signal SG2 input to the first management circuit 403 continues from time t1 to time t3. Here, time t3 is later than time t2, which is 12.8 μs after time t1. Therefore, as shown in FIG. 40(c), the timer counter in the first management circuit 403 continues counting from time t1, and the value of the timer counter in the first management circuit 403 becomes "0" at time t2, which is 12.8 μs after time t1. At time t2, when the value of the first management circuit 403 becomes "0," the first management circuit 403 sends a latch signal to the first latch register 407, as shown in FIG. 40(d). As a result, the numerical information of the random number stored in the random number counter 105 at time t2 is written to the first latch register 407 as the numerical information of the first random number.

[0476] As shown in Figure 40(a), when the depression of the start lever 41 is completed at timing t3, the detection signal SG2 input to the first management circuit 403 falls from a HI state to a LOW state as shown in Figure 40(b). Then, as shown in Figure 40(e), at timing t3, the inversion detection signal SG3 input to the second management circuit 404 rises from a LOW state to a HI state. This causes the timer counter in the second management circuit 404 to start counting time as shown in Figure 40(f).

[0477] As shown in FIG. 40(e), the HI state of the inversion detection signal SG3 input to the second management circuit 404 continues even at the timing of t4. Here, the timing of t4 is the timing when 12.8 μs has elapsed from the timing of t3. Therefore, as shown in FIG. 40(f), the time counting by the timer counter in the second management circuit 404 continues from the timing of t3, and the value of the timer counter in the second management circuit 404 becomes "0" at the timing of t4 when 12.8 μs has elapsed from the timing of t3. At the timing of t4 when the value of the second management circuit 404 becomes "0", as shown in FIG. 40(g), the second management circuit 404 transmits a latch signal to the second latch register 408. As a result, the numerical information of the random number stored in the random number counter 105 at the timing of t4 is written into the second latch register 408 as the numerical information of the second random number.

[0478] When the player presses the start lever 41 down once, the detection signal SG2 output from the start detection sensor 41a rises from the LOW state to the HI state, and the operations from t1 to t4 are performed, where the HI state is maintained for 12.8 μs or more and then returns to the LOW state. By the operations from t1 to t4, the first random number is written into the first latch register 407, and the second random number is written into the second latch register 。

[0479] Thus, the numerical information of the first random number is the numerical information of the random number written into the first latch register 407 on the condition that the detection signal SG2 input to the first management circuit 403 rises. In other words, the first random number is the random number corresponding to the timing when the player starts pressing the start lever 41. On the other hand, the numerical information of the second random number is the numerical information of the random number written into the second latch register 408 on the condition that the inversion detection signal SG3 input to the second management circuit 404 rises. In other words, the second random number is the random number corresponding to the timing when the player finishes pressing the start lever 41.

[0480] The control IC 148 acquires the numerical information of the first random number input to the input terminal of the control IC 148 at the rising timing of the detection signal SG2 input to the control IC 148, and acquires the numerical information of the second random number input to the input terminal of the control IC 148 at the falling timing of the detection signal SG2 input to the control IC 148. Thereby, during the period when the player operates the start lever 41 once, the control IC 148 can acquire two different random numbers.

[0481] Since the pressing operation of the start lever 41 by the player is a human operation, the time during which the state where the start lever 41 is pressed continues is different each time. For this reason, in one game, the control IC 148 can perform a lottery using the numerical information of the second random number that is asynchronous with the first random number in addition to the lottery using the numerical information of the first random number.

[0482] Next, the start command setting process of the present embodiment will be described with reference to FIG. 41. The start command setting process is a process executed in step S206 of the timer interrupt process (FIG. 8).

[0483] First, in step S1601, it is determined whether or not "1" is set in the start enable flag 144a, thereby determining whether or not it is a period in which the game can be started. If it is a period in which the game can be started (step S1601: YES), then in step S1602, it is determined whether or not "1" is set in the signal storage flag 144d. If "1" is not set in the signal storage flag 144d in step S1602, then in step S1603, it is determined whether or not the detection signal SG2 input to the control IC 148 is in the HI state.

[0484] The fact that the detection signal SG2 is in the LOW state in step S1603 means that the rising edge of the detection signal SG2 that was in the LOW state in the previous start command setting process was not detected. In this case, since the signal storage flag 144d is already "0", this start command setting process is terminated as it is.

[0485] The fact that the detection signal SG2 is in the HI state in step S1603 means that the rising edge of the detection signal SG2, which was in the LOW state in the previous start command setting process, has been detected, and the conditions for the control IC 148 to acquire the numerical information of the first random number are met. In this case, the signal storage flag 144d is set to "1" in step S1604, an...

Claims

1. numerical value updating means for updating numerical value information; storage execution means for causing acquisition and storage means to store the numerical value information updated by the numerical value updating means based on the occurrence of a first trigger; control means for executing special processing using the numerical value information stored in the acquisition and storage means based on the occurrence of a second trigger; In a gaming machine comprising: The storage execution means: information setting means for setting acquired information when the first trigger occurs and the acquisition and storage means stores the numerical value information; rewriting means for rewriting the numerical value information stored in the acquisition and storage means with the numerical value information updated by the numerical value updating means at that time when the first trigger occurs again in a situation where the acquired information is already set; comprising: The control means: determination means for determining whether or not the second trigger has occurred each time a monitoring timing is reached; control execution means for executing the special processing on at least one condition that the acquired information is set when it is determined by the determination means that the second trigger has occurred; comprising: The update cycle of the numerical value information in the numerical value updating means is configured to be shorter than the period required from the occurrence of one monitoring timing in the determination means to the occurrence of the next monitoring timing; A gaming machine, characterized in that control for setting the acquired information is executed even when the numerical value information is rewritten by the rewriting means.

2. The gaming machine according to claim 1, characterized in that the first trigger and the second trigger are based on the establishment of a start condition.

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