Analog circuit design

Abstract

Disclosed herein is an analog circuit design apparatus configured to receive information representing technical requirements for an analog circuit, including (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a particular set of manufacturing process-related rules. The analog circuit design apparatus is configured to identify a plurality of candidate analog circuit design architectures that satisfy the at least one manufacturing requirement for satisfying the circuit performance requirement, and select an initial analog circuit design architecture from the plurality of candidate analog circuit design architectures as a current analog circuit design architecture in dependence on the set of manufacturing process-related rules.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for analog circuit design, and more particularly, to methods and systems for automating the design process of analog circuits.

Background Art

[0002] Analog components account for the largest number of defects in chip manufacturing tests and account for up to 95% of field defects. In recent years, although the circuit design of digital circuits has been automated to some extent, the automation of analog circuit design has been difficult so far due to problems such as parasitic effects. In conventional analog circuit design, designers often make estimates and specification guard banding by manual "best guess" based on past knowledge and experience. As a result, the circuit is often oversized, inefficient, and prone to failure. Therefore, in the design of analog circuits, it is desirable to construct a more efficient and reliable process.

Summary of the Invention

Means for Solving the Problems

[0003] Aspects of the present invention are as described in the independent claims, and any features are as described in the dependent claims. Aspects of the present invention may be provided in relation to each other, and features of one aspect may be applied to other aspects.

[0004] In a first aspect, an analog circuit design device is provided. The device includes at least one design unit having a processor and a communication interface, The processor, (a) controls the communication interface to receive information representing the technical requirements of an analog circuit, including (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules, (b) Based on the information received, identify several candidate analog circuit design architectures that satisfy at least one manufacturing requirement in order to meet the circuit performance requirements, (c) As the current analog circuit design architecture, an initial analog circuit design architecture is selected from among several candidate analog circuit design architectures, depending on the set of manufacturing process-related rules. (d) Generate a current design of an analog circuit that satisfies the current analog circuit design architecture, (e) Regarding the current design of the analog circuit, determine whether the current design satisfies at least one circuit performance requirement. If the current design of the analog circuit is determined not to meet the circuit performance requirements, (f) Select a further analog circuit design architecture as the current analog circuit design architecture, and the selection of the further analog circuit design architecture depends on the set of manufacturing process-related rules. (g) Repeat steps (d) and (e), (h) If the current design of the analog circuit design architecture is determined to meet the circuit performance requirements, output the analog circuit design. It is structured in this way.

[0005] The processor further, (i) For each current design of an analog circuit, determine to what extent the current design satisfies at least one circuit performance requirement and a set of manufacturing process-related rules, (j) As the current analog circuit design architecture, select a further analog circuit design architecture depending on the set of manufacturing process-related rules. (k) Repeat steps (d) and (e) to generate multiple generated analog circuit designs. (l) From the multiple analog circuit designs generated, select and output the analog circuit design that best satisfies at least one circuit performance requirement and a set of manufacturing process-related rules. It may be configured as follows.

[0006] The selection of the analog circuit design architecture in step (c) and / or step (f) may be based on prioritizing multiple architecture candidates, which creates a prioritized list of candidate analog circuit design architectures that are determined to satisfy the set of manufacturing process-related rules. The prioritized list of candidate analog circuit design architectures can be determined using a machine learning model.

[0007] In some examples, the device includes a primary design unit and a secondary design unit. The primary design unit is, (m) Based on the received information, identify multiple candidate analog circuit design architectures that meet the manufacturing requirements and satisfy the circuit performance requirements. (n) From among several candidate analog circuit design architectures, each comprising multiple circuit components, select the initial analog circuit design architecture as the current analog circuit design architecture. (o) For each of the multiple circuit components, determine the respective circuit performance requirements for the circuit component based on a specific set of manufacturing process-related rules. (p) Provide the respective circuit performance requirements for each circuit component to at least one of a plurality of secondary design units. It is configured in such a way, Each of the multiple secondary design units of the analog circuit design device is (q) Based on the circuit performance requirements for each circuit component provided by the primary design unit, design each circuit component of the multiple circuit components, (r) Output the results of the initial design of each circuit section. It is configured in such a way, The primary design unit further, (s) Receive the design of each circuit part from each of the multiple secondary design units, (t) Based on the design of each circuit component, generate the current analog circuit design of the analog circuit that satisfies the current analog circuit design architecture. It is structured in this way.

[0008] The primary design unit further, (u) Simulate the analog circuit based on the current analog circuit design and generate at least one simulation output, (v) Verify whether the analog circuit meets the circuit performance requirements, If the analog circuit meets the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, As for current analog circuit design architectures, further analog circuit design architectures are selected depending on the set of manufacturing process-related rules. Repeat steps (d) through (e) and (m) through (v). It is configured in this way.

[0009] The primary design unit further, (w) Simulate the analog circuit based on the current analog circuit design and generate at least one simulation output. (x) Verify whether the analog circuit meets the circuit performance requirements for analog circuits. If the analog circuit meets the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, For at least one of the multiple circuit components that is affected, a modified circuit performance requirement for the affected circuit component is determined based on the simulation output and the circuit performance requirements. Provide at least one corresponding secondary design unit with modified circuit performance requirements for each affected circuit portion. Receive the updated design for each affected circuit section from at least one corresponding secondary design unit. The current design of the analog circuit will be updated with the updated design of each affected circuit component. Repeat step (w) to step (x) for the updated design set. It may be configured as follows.

[0010] Each of the plurality of secondary design units may be configured to adapt the design of each part based on the simulated behavior by adapting the design of each part based on the difference between the simulated behavior and the circuit performance requirements.

[0011] In some examples, after at least an initial design of a given circuit part is completed by at least another one of the secondary design units, at least one of the secondary design units is configured to adapt the current analog circuit design based on the context of the corresponding circuit part, where the context includes circuit performance requirements generated based on the completed design of a given circuit part completed by at least another one of the secondary design units.

[0012] In some examples, after at least an initial design of a given circuit part is completed by at least another one of the secondary design units, at least one of the secondary design units is configured to adapt the output initial design based on the context of the corresponding circuit part, where the context includes circuit performance requirements generated based on the completed design of a given circuit part completed by at least another one of the secondary design units.

[0013] Each of the secondary design units may be configured to repeat the step of adapting the design of a further circuit part when a change in the design of another circuit part among the plurality of circuit parts causes a change in the context of the further circuit part.

[0014] Additionally or alternatively, each of the secondary design units may be configured to repeat the step of adapting the design of a further circuit part only when the change in context is greater than a selected threshold level.

[0015] In some examples, it is configured to obtain the context by simulating the performance of a given circuit part.

[0016] In another embodiment, a method for designing analog circuits is provided. The method includes a design unit comprising a processor and a communication interface, (a) a step of controlling a communication interface to receive information representing the technical requirements of an analog circuit, including (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules, (b) Based on the information received, the step of identifying several candidate analog circuit design architectures that satisfy at least one manufacturing requirement in order to meet the circuit performance requirements, (c) As the current analog circuit design architecture, the step of selecting an initial analog circuit design architecture from among several candidate analog circuit design architectures, depending on the set of manufacturing process-related rules, (d) A step of generating a current design of an analog circuit that satisfies the current analog circuit design architecture, (e) A step of determining whether the current design for the analog circuit design architecture satisfies at least one circuit performance requirement, If the current design of the analog circuit design architecture is determined not to meet the circuit performance requirements, (f) The current analog circuit design architecture is a step of selecting a further analog circuit design architecture depending on the set of manufacturing process-related rules, (g) A step of repeating steps (d) and (e), (h) If the current design of the analog circuit design architecture is determined to meet the circuit performance requirements, the step of outputting the analog circuit design, It is equipped with.

[0017] The method is further, (i) A step of determining the extent to which the current design of the analog circuit satisfies at least one circuit performance requirement and a set of manufacturing process-related rules, (j) As the current analog circuit design architecture, the step of selecting a further analog circuit design architecture depending on the set of manufacturing process-related rules, (k) A step of repeating steps (d) and (e) to generate multiple generated analog circuit designs, (l) A step of selecting and outputting from multiple generated analog circuit designs the analog circuit design that best satisfies at least one circuit performance requirement and a set of manufacturing process-related rules, It may be provided.

[0018] The selection of the analog circuit design architecture in step (c) and / or step (f) may be based on prioritizing multiple architecture candidates, which results in a prioritized list of analog circuit design architecture candidates that are determined to satisfy the set of manufacturing process-related rules.

[0019] The method is further, In the primary design unit, (m) Based on the received information, the step of identifying multiple candidate analog circuit design architectures that meet the manufacturing requirements and satisfy the circuit performance requirements, (n) A step of selecting an initial analog circuit design architecture as the current analog circuit design architecture from among several candidate analog circuit design architectures, each having multiple circuit components, (o) For each of the multiple circuit parts, the step of determining the respective circuit performance requirements for the circuit part based on a specific set of manufacturing process-related rules, (p) The step of providing the respective circuit performance requirements for each circuit component to at least one of a plurality of secondary design units, They may be provided, In each of the multiple secondary design units, (q) A step of designing each circuit component of multiple circuit components based on the circuit performance requirements for each circuit component provided by the primary design unit, (r) A step of outputting the results of the initial design of each circuit part, Equipped with, In the primary design unit, (s) A step of receiving the design of each circuit part from each of the multiple secondary design units, (t) A step of generating a current analog circuit design of an analog circuit that satisfies the current analog circuit design architecture based on the design of each circuit part, It may be provided.

[0020] The method is further, In the primary design unit, further, (u) A step of simulating an analog circuit based on the current analog circuit design and generating at least one simulation output, (v) A step to verify whether the analog circuit meets the circuit performance requirements, If the analog circuit meets the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, The current analog circuit design architecture involves a step of selecting a further analog circuit design architecture based on prioritizing multiple candidate architectures that depend on a set of manufacturing process-related rules, A step that repeats from step (d) to step (e) and from step (m) to step (v), It may be provided.

[0021] The method is further, In the primary design unit, further, (w) A step of simulating an analog circuit based on the current analog circuit design and generating at least one simulated output, (x) A step to verify whether the analog circuit meets the circuit performance requirements for the analog circuit, If the analog circuit meets the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, A step of determining a modified circuit performance requirement for at least one affected circuit part among multiple circuit parts, based on the simulation output and the circuit performance requirement, The steps include providing at least one corresponding secondary design unit with modified circuit performance requirements for each affected circuit portion, The steps include receiving the updated design of each affected circuit portion from at least one corresponding secondary design unit, The steps include updating the design set with the updated design for each affected circuit part, The steps from step (w) to step (x) are repeated for the updated design set, It may be provided.

[0022] The method is further, In each of the multiple secondary design units, The process may include a step of adapting the design of each part based on simulated behavior, by adapting the design of each part based on the difference between the simulated behavior and the circuit performance requirements.

[0023] The method is further, The process may further include a step of adapting an outputted initial design of at least one of the secondary design units based on the context of the corresponding circuit portion, after at least an initial design of a given circuit portion has been completed by at least one other of the secondary design units.

[0024] The method is further, The process may further include, after at least the initial design of a given circuit portion has been completed by at least one other secondary design unit, adapting at least one output initial design of a secondary design unit based on the context of the corresponding circuit portion. The context includes circuit performance requirements generated based on the completed design of a given circuit portion completed by at least one other secondary design unit.

[0025] The method is further, If a modification to the design of one of several circuit components causes a change in the context of further circuit components, the process may further include repeating the step of adapting the design of the further circuit components in each of the secondary design units.

[0026] The method is further, The process may further include repeating the step of adapting the design of further circuit components only if the change in context is greater than a selected threshold level. In some examples, the context is obtained by simulating the performance of a given circuit component.

[0027] It will be understood that the method may further include fabricating analog circuits to match the output design.

[0028] In another embodiment, a computer-readable non-temporary storage medium is provided, which includes a computer program configured to cause a processor to perform one of the methods described above. [Brief explanation of the drawing]

[0029] [Figure 1A] A schematic diagram illustrating the functionality of an example analog circuit is shown. [Figure 1B] Figure 1B is a conceptual block representation of the functional schematic diagram in Figure 1A. [Figure 2] Figure 2 is a schematic diagram of the functionality of the computer implementation hierarchy model for analog circuit design. [Figure 3] Figure 3 is a schematic flowchart illustrating the functional design method for analog circuits used in the modes shown in Figure 2 or Figure 4. [Figure 4] Figure 4 is a schematic diagram illustrating the functionality of another embodiment of the computer implementation model for analog circuit design. [Figure 5] Figure 5 is a schematic flowchart illustrating the functionality of an analog circuit design method using, for example, the computer implementation model shown in Figure 2 or Figure 4. [Figure 6A] Figure 6A shows a portion of an analog circuit designed by a computer implementation hierarchy model, such as the model described with reference to either Figure 1A-2 or Figure 4-5. [Figure 6B] Figure 6B shows an example of a designed analog circuit incorporating the circuit portion shown in Figure 6A. [Figure 7] Figure 7 is a schematic diagram illustrating an example of how a machine learning model is trained to rank architectures. [Modes for carrying out the invention]

[0030] Figure 1A is a simplified functional schematic of an example analog electronic circuit, which in this example is an AD converter (ADC) 1000. The analog circuit may comprise multiple parts or components, such as a comparator 1001, a DAC 1002, a level shifter 1003, and an operational amplifier 1004. Each part or component may initially be considered separately, but the context or environment in which that part or component operates when applied in situ to the entire circuit can influence how that component / block behaves, including, for example, the parasitic effects experienced by the circuit part and the circuit as a whole. The design of analog circuits has been difficult to automate until now due to complex feedback loops and the mathematical relationships between the various parts / components of the analog circuit.

[0031] Embodiments of the claims relate to a method and system for automating the design of analog circuits so that more efficient circuits can be designed. In particular, embodiments of the claims relate to a method and system for automating the design of analog circuits that take into account both circuit performance requirements (e.g., those required by the customer) and manufacturing requirements (e.g., the manufacturing capabilities of the foundry where the circuit is manufactured). As described above, conventional approaches to analog circuit design often involve estimates based on "best guesses" and manual specification guard-banding by engineering teams relying on prior knowledge and experience, resulting in circuits that are over-designed, inefficient, and prone to failure. When it is necessary to develop different circuit architectures to suit different manufacturing requirements, such as those of a foundry or process design kit (PDK), if an analog circuit design suitable for use in multiple different foundries / PDKs is designed, this "compatible" circuit design may be selected by all foundries / PDKs even if it is not the most efficient circuit design for the other foundries. This results in an inefficient circuit design. In contrast, the inventors of this invention have surprisingly developed a counterintuitive circuit design method in which they select the architecture best suited for analog circuit design for a specific foundry / PDK (and potentially many other foundries / PDKs), rather than selecting a circuit design suitable for use in the foundry / PDK (and potentially many other foundries / PDKs). This approach is counterintuitive because selecting the most appropriate architecture requires choosing the most efficient circuit design that is technically complex but optimized to meet manufacturing requirements such as the requirements of the foundry / PDK. In contrast, conventional analog circuit design approaches tend to select the design that is technically simplest and meets manufacturing requirements.

[0032] To implement this solution, the inventors developed a computer implementation model that delegates the design responsibility for parts or components of an analog circuit to its respective units or "blocks." An example of this model is shown in Figure 2. Such a hierarchical model involves the use of a primary design unit called a "parent block" 900, which functions as a control entity, and a number of secondary design units called "child blocks" 950a-950d, which receive instructions from the primary design unit or parent block on what needs to be designed.

[0033] As a control entity, the parent block 900 is configured to receive and process technical requirements and obtain at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules. The manufacturing process-related rules may be based on the foundry or process design kit (PDK) requirements 350, as described above. This process performed by the parent block 900 is summarized in Figure 3 and will be described in more detail below.

[0034] Based on technical requirements, parent block 900 identifies several candidate analog circuit design architectures that meet manufacturing lease requirements and satisfy circuit performance requirements. As described later, parent block 900 can do this by employing machine learning algorithms. Next, parent block 900 selects an initial analog circuit design architecture from the several candidate analog circuit design architectures as the current analog circuit design architecture, and the selection of the initial analog circuit design depends on a set of manufacturing process-related rules.

[0035] Next, the model generates a current design of the analog circuit that satisfies the current analog design architecture. This is done by the parent block 900 instructing each secondary design unit or child blocks 950a-950d to design their respective components or parts of the analog circuit based on instructions received from the parent block 900. The instructions may include circuit performance requirements (e.g., functional requirements) that the component or part must satisfy.

[0036] The parent block 900 can do this by identifying, based on the received information, several candidate analog circuit design architectures that satisfy the manufacturing requirements and meet the circuit performance requirements. Next, the parent block 900 selects an initial analog circuit design architecture from the several candidate analog circuit design architectures as the current analog circuit design architecture, each circuit design architecture consisting of several circuit parts, and for each of the multiple circuit parts, the respective circuit performance requirements for that part are determined, and these respective circuit performance requirements for each circuit part are determined based on a specific set of manufacturing process-related rules. Next, the parent block 900 provides each of the child blocks 950a to 950d with instructions that may include, for example, the respective circuit performance requirements for each circuit part. Next, each child block 950a to 950d designs each of the multiple circuit parts based on the circuit performance requirements for each circuit part provided by the parent block 900, and outputs the resulting initial design of each circuit part. The parent block 900 receives the respective designs of each circuit component from each of the multiple child blocks 950a to 950d, and based on the respective designs of each circuit component, generates the current analog circuit design of the analog circuit that satisfies the current analog circuit design architecture.

[0037] In addition to the respective circuit performance requirements for each circuit part, the instructions provided by the parent block 900 may also include information relating to the context of each component or part of the circuit, in other words, information relating to what that part or component of the circuit will experience when placed in place in the completed circuit (in some examples, the context may be provided as part of the circuit performance requirements, while in other examples, it may be provided as something in addition to the circuit performance requirements). The context may include parameters and variables that the part or component of the circuit will experience during use. The context of any given circuit part or component may be generated based on simulating the performance of the circuit part or component that interacts with that given circuit part or component, or by simulating the completed circuit with that given circuit part or component. For example, the parent block 900 may be configured to assemble a completed circuit from the parts or components designed by each child block 950a to 950d and to simulate the operation of the assembled circuit. The context of any given circuit part or component may, additionally or alternatively, be generated based on mathematical calculation or extraction.

[0038] Once an analog circuit design that satisfies the current analog circuit design architecture is created, the completed analog circuit design is tested to determine whether the current design meets at least one circuit performance requirement. This test may be performed by the parent block 900. The parent block 900 can do this by simulating the analog circuit based on the current analog circuit design to generate at least one simulation output, and then verifying whether the analog circuit meets the circuit performance requirement.

[0039] If the current design for an analog circuit is determined not to meet the circuit performance requirements, the parent block selects a further analog circuit design architecture from a pool of candidate analog circuit design architectures as the current analog circuit design architecture, and the selection of the further analog circuit design architecture depends on a set of manufacturing process-related rules. The model then repeats the steps of creating a current design for an analog circuit that satisfies the current analog circuit design architecture, and testing the completed analog circuit design to determine whether the current design satisfies at least one circuit performance requirement. If the current design does not satisfy at least one circuit performance requirement, this process is repeated. However, if the current design satisfies at least one circuit performance requirement, the parent block 900 outputs the analog circuit design.

[0040] When testing the design of an analog circuit design architecture, in some embodiments, the parent block 900 determines, for the current design of the analog circuit, to what extent the current design satisfies at least one set of circuit performance requirements and manufacturing process-related rules, if it is determined that it satisfies at least one circuit performance requirement. The parent block 900 may then select a further analog circuit design architecture as the current analog circuit design architecture, the selection of the further analog circuit design architecture depends on the set of manufacturing process-related rules, and, if it is determined that it satisfies at least one set of circuit performance requirements, to what extent the current design satisfies at least one set of circuit performance requirements and manufacturing process-related rules. This process may be repeated to generate multiple generated analog circuit designs, all of which satisfy the circuit performance requirements, but some designs may be better suited than others to at least one set of circuit performance requirements and manufacturing process-related rules. The parent block 900 can then select and output from the multiple generated analog circuit designs the analog circuit design that best satisfies at least one set of circuit performance requirements and manufacturing process-related rules.

[0041] When parent block 900 selects an analog circuit design architecture, this may be based on prioritizing multiple architecture candidates. For example, there may be a prioritized list of analog circuit design architecture candidates that are determined to satisfy, or likely to satisfy, a set of manufacturing process-related rules. This list may be input by parent block 900 based on previous iterations of the design process, or it may be supplied to parent block 900 from elsewhere. For example, as will be described in more detail below, a machine learning algorithm may determine a prioritized list of analog circuit design architectures based on at least one of (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a particular set of manufacturing process-related rules.

[0042] Hierarchical models implemented in computers may be iterative. When parent block 900 instructs each child block 950a-950d to design their respective parts, some degree of redesign of the circuit and each part may be necessary to account for characteristics such as parasitic elements and / or context arising from the respective circuit parts designed by the other child blocks 950a-950d. This may occur before parent block 900 determines whether the current design meets at least one circuit performance requirement. For example, certain parts of the circuit may need to be adapted due to context provided by other designed circuit parts and / or assumed parasitic elements that may be experienced by a particular circuit part or the completed analog circuit. Therefore, the circuit part design process by each child block 950a-950d may be repeated to adapt the design of one or more circuit parts to mitigate and reduce them, for example, taking into account context and / or assumed parasitic elements. This process of adapting the circuit part design may be iteratively repeated by child blocks 950a-950d until changes in assumed parasitic rates resulting from adjustments to other parts or components of the analog circuit are taken into account. For example, this process can be repeated until the change in the estimated parasitism rate falls below a threshold level for the change in the selected parasitism rate.

[0043] The context and / or parasitic properties of any given circuit portion can be generated by simulating the performance of the circuit portions that interact with that given circuit portion, or by simulating a complete circuit comprising that given circuit portion. For example, parent block 900 may be configured to assemble a complete circuit from the portions designed by each child block 950a to 950d and to simulate the operation of the assembled circuit. Parasitism of any circuit portion can be generated additionally or alternatively based on mathematical calculation or extraction. Additionally or alternatively, the parasitic properties of any given circuit portion may be obtained by performing a lookup of a database of circuit designs and parasitic properties, and / or by prediction using a machine learning model. Parent block 900 may then verify whether the analog circuit meets the circuit performance requirements. If the analog circuit meets the circuit performance requirements, parent block 900 can output the generated design. If the analog circuit fails to meet the circuit performance requirements, the parent block 900 may determine a modified circuit performance requirement for at least one affected circuit part among several circuit parts, based on the simulation output and the circuit performance requirements, and provide the modified circuit performance requirement for each affected circuit part to at least one corresponding child block 950a-950d. Alternatively, the parent block 900 may receive the updated design for each affected circuit part from at least one corresponding child block 950a-950d and update the current design of the analog circuit with the updated design for each affected circuit part. The parent block 900 can then determine, with respect to the updated current design of the analog circuit, whether the current design meets at least one circuit performance requirement, and optionally, to what extent the current design meets at least one set of circuit performance requirements and / or manufacturing process-related rules.

[0044] Such a process is schematically illustrated in Figure 3. As shown in Figure 3, information representing the technical requirements of the analog circuit 350 is received. The technical requirements 350 include (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules. In this case, the at least one manufacturing requirement includes information related to the PDK. The technical requirements 350 is a process, and important device physics are captured (301). This step may include identifying a plurality of candidate analog circuit design architectures that satisfy the circuit performance requirement and at least one manufacturing requirement based on the received information. Next, a current analog circuit design architecture is selected from the plurality of candidate analog circuit design architectures (303), where the selection of the initial analog circuit design depends on the set of manufacturing process-related rules. Next, an analog circuit design that satisfies the current analog circuit design architecture is generated (305). Next, the designed circuit is analyzed for the current design of the analog circuit to determine whether the current design satisfies at least one circuit performance requirement (307). If previous iterations of the analog circuit have been designed, the process compares the new (current) design to the previous design to determine whether the current analog circuit design is an improvement (309). If step 309 determines that the current analog circuit design meets the circuit performance requirements, the previous analog circuit design that meets the circuit performance requirements is output. Conversely, if the current analog circuit design represents an improvement, the circuit is checked to determine whether there are any improvements to the circuit performance requirements that can be achieved (311). If improvements are determined to be possible, the process redesigns the analog circuit according to the current design architecture. If improvements to the circuit performance requirements are not determined to be possible, the process then determines whether another architecture could represent an improved architecture. If there is another architecture available, the design process is repeated. If there is no other architecture available, the current analog circuit design is output.

[0045] The inventors of this application have found that, advantageously, the use of such a process and iterative hierarchical model allows for the automation of analog circuit design. As a result, advantageously, this means that over-engineered analog circuits and / or circuits with unacceptable parasites can be avoided, and instead, more efficient circuits can be designed and created. Furthermore, the inventors recognize that designing and selecting analog circuits in this manner means that the design of analog circuits that are optimal not only for circuit performance requirements but also for manufacturing requirements can be achieved. This means that instead of using a generic architecture that may meet the requirements of a foundry / PDK but is not the best design (due to inefficiencies, over-engineering, etc.), it is possible to create a more efficient circuit architecture tailored to the requirements of each foundry / PDK, for example.

[0046] As described above, Figure 1A shows an exemplary analog circuit architecture 1000, which in this example is an analog-to-digital converter (ADC). Conceptually, a circuit architecture can be divided into functional blocks corresponding to different parts or components of the circuit, for example, based on their respective functionalities. The layout of these functional blocks or components can be said to represent the architecture. For example, an ADC may consist of a comparator 1001, a digital-to-analog converter (DAC) 1002, a number of level shifters 1003, and one or more operational amplifiers 1004. In the example shown in Figure 1A, the circuit can be conceptually divided into blocks corresponding to these different parts or components that constitute the architecture. For example, as shown in Figure 1B, the comparator can be conceptually divided into a first “child block” 950a, the DAC into a second child block 950b, the level shifters into a third child block 950c, and the operational amplifiers into a fourth child block 950d. The ADC as a whole can be conceptually classified into its own block (labeled “parent” 900 in Figure 1B). It will be understood that the ADC itself may form a conceptual block within a larger analog circuit.

[0047] For example, in a certain architecture, operational amplifier 1004 may be replaced with two smaller operational amplifiers with lower gain to satisfy certain manufacturing process-related regulations. This is because manufacturing process-related regulations stipulated by a single foundry / PDK may not support the gain of operational amplifier 1004 shown in Figure 1A, and therefore, to achieve the same circuit performance requirements, the single operational amplifier 1004 in Figure 1A is replaced with two operational amplifiers, each with lower gain, to achieve the desired gain.

[0048] In another example, one PDK (e.g., PDK180) might support a voltage of 1.8V, while a second PDK (e.g., PDK28) might support a voltage of 0.9V. The analog circuit design architecture for the PDK supporting the lower voltage (i.e., PDK28) might consist of an OTA-based amplifier with a source follower. While this architecture might also work with the higher voltage of the PDK180, such an architecture is not the optimal architecture to use for that PDK, and a folded cascode is more appropriate and efficient instead. The folded cascode architecture is more complex, and it would be counterintuitive not to use the model and process described in this specification. Thus, this application can be said to involve a counterintuitive approach to analog circuit design.

[0049] As mentioned above, when used in the field, there are interactions between the different blocks of an analog circuit. These interactions between blocks in the field (which may include the parasitic effects each part experiences when placed in the completed circuit), and the resulting parameters and variables that each block experiences when placed in that circuit, affect the performance of the circuit. For example, the specifications of the operational amplifiers used in the circuit may depend on many parameters and variables arising from the selection and design of comparators, DACs, level shifters, and the connections between them.

[0050] A non-exhaustive list of examples of parameters and variables that may influence the selection and design of these different blocks include: silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, supply voltage, available transistor types, output common-mode range, output swing, settling time, noise immunity, supply voltage rejection ratio (PSRR), common-mode range-input (input CMR), common-mode range-output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandpass range, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter-ptp, jitter-RMS, output ripple-ptp, total harmonic distortion, startup time, channel isolation, reference voltage, gain error, offset error, and gain drift. These parameters and variables are sometimes referred to as the "context" or "environment" in which the block is placed. Understanding the context can improve the circuit design in order to create an optimal analog circuit. It will also be understood that some of these parameters and variables constitute part of the circuit performance requirements.

[0051] As mentioned above, the manufacturing requirements for analog circuits may consist of or be specified by a set of specific manufacturing process-related rules. Manufacturing requirements may be defined by a process design kit (PDK) created by the foundry. A PDK may include one or a combination of physical constraints, SPICE models (simulation models), PCELLS and technical files, rule decks, and schematic symbols.

[0052] However, it is understood that analog circuit design is an iterative process, and the selection and adjustment of one block may affect the context of another block. Therefore, when components of one block are selected / adjusted to form a circuit part, it may become necessary to adjust or re-select components of another block, taking into account the parasitic and / or context experienced by the completed circuit / circuit part that includes that block. Such an iterative process is not practical to perform manually, is prone to errors, and can only be detected through communication.

[0053] As described above, Figure 2 shows an example of a computer implementation model used to automate the design of analog circuits. Figure 2 schematically shows the blocks described above in Figure 1B and the interactions between the blocks.

[0054] In the example in Figure 2, each block of the model is responsible for designing the component / function represented by that block. In Figure 2, child 1 (950a) is responsible for designing comparator 1001, child 2 (950b) for designing DAC 1002, child 3 (950c) for designing level shifter 1003, and child 4 (950d) for designing operational amplifier 1004. Parent block 900 is responsible for the overall design of ADC 1000, delegating the design responsibility for parts / components / functions of the ADC to child blocks 950a-950d. In some examples, parent block 900 can select how many child blocks 950a-950d are needed and the responsibilities assigned to each block. Although child blocks 950a-950d are shown in order, it should be understood that this order does not necessarily represent the order in which the circuit parts are designed. For example, parent block 900 can instruct child block 950d, which is responsible for the operational amplifier, to design that part of the circuit first. In some examples, child blocks 950a to 950d may be configured to design the output first and then work backward from there.

[0055] Each circuit part may initially be designed separately by its corresponding block, but the context in which each circuit part operates when applied in place to the entire circuit may influence how both the individual circuit parts operate, as well as the entire circuit. Therefore, while a parent block can instruct each child block to design its respective part, when the initial version of the circuit designed from the parts or components designed by each child block 950a-950d is assembled by the parent 900, it is highly likely that some degree of adaptation or even redesign of the circuit 1000 and its parts or components will be necessary to account for the resulting parasitic and / or context created by the parts designed by the other child blocks 950a-950d. As mentioned above, this becomes an iterative process.

[0056] Therefore, the parent block 900 is configured to function as a controller that handles and processes the design process performed by each child block. To perform this function, the parent block 900 may have a number of different modules, each configured to perform a different function as part of the design process, as shown in Figure 2. The parent block in Figure 2 includes an instructor module 901, an assembly module 902, and a verification / simulator module 903.

[0057] The instructor module 901 is configured to receive the technical requirements of the circuit to be designed, including at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules, and to translate these into a set of instructions / criteria that each child block 950a-950d must satisfy when designing each component of the circuit. It is also configured to create instructions on what each child block 950a-950d must design and what criteria it must satisfy in doing so, and to send these instructions to each child block 950a-950d. The instructions may also include the context of other designed parts of the circuit designed by other child blocks and the broader context of the circuit on which the component or part of the circuit is intended to operate. For example, the circuit performance requirement may be adjusted to take the context into consideration.

[0058] The assembly module 902 is configured to receive and match all of the designed parts or components of the analog circuits provided by each of the child blocks 950a to 950d, and to assemble the complete analog circuit based on the respective designed parts or components. The completed analog circuit is tested by the verification / simulator module 903.

[0059] The verification / simulator module 903 is configured to receive designed components from each of its child blocks and compare them to a set of technical requirements to determine whether the designed part or component is satisfactory. This can be done by simulating the function of the assembled components of an analog circuit. The verification / simulator module 903 may determine whether the designed component / finished circuit design satisfies the technical requirements by, for example, verifying whether each designed circuit part or component satisfies the corresponding circuit performance requirements and / or whether the designed analog circuit satisfies a particular set of manufacturing process-related rules. In this case, the degree to which these requirements are met may be determined, for example, by assigning a score based on how closely the requirements are met and / or whether the requirements are exceeded. Additional or alternative verification checks may also be included to determine whether the designed circuit is valid in the sense that it can operate within certain technical limitations.

[0060] The verification and simulator module 903 may function as a “testbed” and be configured to simulate the functionality of assembled components of a circuit. Such simulations can provide information, for example, about parasitic information and / or contextual information, and the extent to which the components / finished circuit design meet technical requirements such as a specific set of circuit performance requirements and / or manufacturing process-related rules. For example, the verification and simulator module 903 may be configured to obtain, for example, contextual and parasitic performance information experienced in an analog circuit when the analog circuit includes its designed circuit portion, by mathematically simulating the performance of at least one of (i) a designed circuit portion and (ii) a complete analog circuit comprising the designed circuit portion in a virtual testbench. Additionally or alternatively, the verification and simulator module 903 may be configured to obtain, for example, parasitic performance information experienced in an analog circuit when the analog circuit includes its designed circuit portion, by performing a lookup for similar generated designs in a database of circuit designs and parasitic elements. Additionally or alternatively, the verification / simulator module 903 may be configured to perform lookups in a database of circuit designs and parasitic elements for at least one of each circuit component and for each similar circuit component, and to obtain performance information related to parasitic elements that the generated design will experience, based on the parasitic element values ​​obtained through the lookups for at least one of each circuit component. In another example, the verification / simulator module 903 may be configured to obtain performance information related to parasites that the generated design will experience, for example, by predicting the performance of the circuit using a machine learning model.

[0061] The verification / simulator module 903 may be configured to input a database of circuit designs, for example, if the instructor module 901 instructs child blocks 950a-950d to repeat the process of designing circuit parts based on corresponding (new or adapted) circuit performance requirements multiple times. The database of circuit designs may also include information relating to the extent to which the circuit designs meet the technical requirements.

[0062] Furthermore, each child block 950a-950d comprises a number of different modules, each configured to perform a different function as part of the design process. In the example shown in Figure 2, each child block 950a-950d comprises converter modules 951a-951d, assembly modules 952a-952d, and simulator modules 953a-953d. In some embodiments, it will be understood that each child block 950a-950d may further comprise additional modules for directing tertiary design units or "grandchild" blocks, as will be further described below with reference to Figures 4-6, similar to how the parent block 900 in Figure 2 is composed of modules such as an instructor module and a verification module for directing and verifying the design process from the child blocks 950a-950d.

[0063] Each child block 950a-950d's converter modules 951a-951d are configured to receive circuit performance requirements from the parent block 900, and optionally the context of the entire circuit and the context of other components of the circuit, and to translate these into a set of requirements for designing parts or components of the analog circuit to meet those criteria. It will be understood that in some examples, context information may be provided and received as part of the circuit performance requirements, while in other examples, it may be provided in addition to (e.g., separately from) the circuit performance requirements.

[0064] Assembly modules 952a to 952d are configured to select and / or design electronic components that meet the required requirements, satisfying the instructions / criteria indicated by the parent block, the context of the entire circuit, and / or the context of other components of the circuit.

[0065] Simulator modules 953a-953d may be configured to simulate how the design parts or components designed by the assembly module would behave in place in order to check / verify whether those components are technically feasible. In some examples, simulator modules 953a-953d may also obtain information related to the parasites of each circuit part designed by the parent block 900 in a similar manner to the verification / simulator module 903 of the parent block 900 described above (in such examples, it will be understood that the verification / simulator module 903 of the parent block 900 may not need to obtain information related to parasites because this may have already been done by the simulator modules 953a-953d of each child block 950a-950d).

[0066] When in use, the parent block 900 receives a set of technical requirements for the analog circuit 1000 to be designed. The technical requirements include at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules. In the example shown in Figure 2, the parent block 900 receives a set of technical requirements for the ADC to be designed, which has specific characteristics, including, for example, characteristics (i.e., manufacturing requirements) instructed by the foundry that manufactures the ADC.

[0067] The parent block 900 receives these requirements, and the instructor module 901 translates them into a set of instructions / references. As part of this process, the instructor module 901 selects an initial analog circuit design architecture from among several candidate analog circuit design architectures as the current analog circuit design architecture, and the selection of the initial analog circuit design depends on a set of manufacturing process-related rules.

[0068] These instructions / criteria are then sent to each of the child blocks 950a-950d. The instructor module 901 may send these instructions / criteria to each of the child blocks 950a-950d in parallel (i.e., all simultaneously) or in series (for example, the criteria are sent to child 1, then to child 2, then to child 3, and so on). In some examples, the instructor module 901 may wait until it receives the designed circuit from the first child before sending the set of circuit performance requirements to the next child, and in some examples, the instructor module may be configured to adjust the circuit performance requirements sent to the next child based on the designed circuit received from the preceding child, in other words, based on the context of the designed circuit received from the preceding child.

[0069] In an example where instructions / references are sent in series to child blocks 950a-950d, the instructions / references may include means for distinguishing which part of the circuit performance requirements is relevant to which child blocks 950a-950d—for example, the instructions / references may include headers or flags that identify whether a particular part of the instructions / references is relevant to child blocks 950a-950d. These headers or flags are determined by the parent block 900, and the instructions / references may be adjusted as appropriate to incorporate them.

[0070] Each child block 950a-950d receives these instructions / criteria from the parent block 900, and each respective converter module 951a-951d translates these into a set of requirements for designing a portion or component of the analog circuit to meet these circuit performance requirements. Assembly modules 952a-952d receive these requirements and design the circuit component / portion that meets these requirements. It will be understood that this design process may include looking up a database of known circuit designs (or portions thereof) to find the circuit design that best fits the instructions / criteria.

[0071] Next, simulator modules 953a-953d simulate how these components / parts of the circuit would operate in the field to check whether the designed components / parts of the circuit designed by the assembly module are technically feasible and / or verify whether each corresponding designed circuit part meets the instructions / criteria. If the designed circuit part meets its corresponding instructions / criteria, child blocks 950a-950d are then configured to send the designed circuit part or component back to or output it to the parent 900. If the designed circuit part does not meet its corresponding instructions / criteria, child blocks 950a-950d are configured to adapt the design of that circuit part and repeat the process.

[0072] Once the parent 900 has received all the designed parts or components of the circuit from all the child blocks 950a-950d, the assembly module 902 of the parent 900 then assembles the completed circuit (in this case, an ADC) from the designed parts or components of each child block and verifies, via the verification / simulator module 903, whether the designed circuit meets the technical requirements. This may be done by simulating how the assembled circuit will operate and comparing this simulated performance to the circuit performance requirements and / or manufacturing requirements. For example, the verification / simulator module 903 may determine whether the designed component / completed circuit design meets the technical requirements by, for example, verifying whether each designed circuit part or component meets the corresponding circuit performance requirements and / or whether the designed analog circuit meets a particular set of manufacturing process-related rules. In this case, the degree to which these requirements are met may also be determined by assigning a score based on how closely the requirements are met and / or whether the requirements are exceeded. Additionally or alternatively, verification checks may be included to determine whether the designed circuit is valid in the sense that it can operate within certain technical limitations. In some examples, this simulated performance of the completed analog circuit design may be used to obtain parasitic and / or optional contextual information (e.g., for another design unit), and it will be understood that the parent 900 may adjust the circuit performance requirements based on the parasitic and / or optional contextual information obtained through the simulation of the completed analog circuit design.

[0073] If the simulated performance of the designed circuit does not meet at least one circuit performance requirement (for example, if the parameters of the simulated circuit are above a different threshold level than the parameters determined by the circuit performance requirement, such as parasitic elements being above the parasitic element threshold level), the verification module 903 communicates this to the instructor module 901. The instructor module 901 can then select a further analog circuit design architecture as the current analog circuit design architecture, and the selection of a further analog circuit design architecture depends on a set of manufacturing process-related rules.

[0074] In some examples, the parent block 900 (e.g., verification module 903 / instructor module 901) may determine which part or component of the circuit is causing the circuit to fail to meet the circuit performance requirements (e.g., which part accounts for a large proportion of parasitic elements) before further analog circuit design architectures are selected. If the child blocks 950a-950d can be identified, the parent block 900 may be configured to send the modified circuit performance requirements only to the child block responsible for the problematic part or component of the circuit. However, in other examples, the modified criteria may be sent back to all child blocks 950a-950d. It will also be understood that in some examples, the parent module 900 may determine that additional and / or alternative child blocks 950a-950d and / or grandchild blocks are needed to design the relevant part or component of the circuit, for example, to meet the modified circuit performance requirements.

[0075] The process then continues iteratively, with the converter modules 951a-951d of each child block 950a-950d receiving these modified or adapted circuit performance requirements from the parent block 900 and translating them into a new set of instructions / criteria for designing parts or components of the analog circuit to meet these adapted circuit performance requirements. The assembly modules 952a-952d receive these new instructions / criteria and design the circuit components / parts to meet these requirements. Next, the simulator modules 953a-953d can simulate how the redesigned circuit components / parts would function in place to check whether the designed components / parts of the circuit designed by the assembly modules are technically feasible. The child blocks 950a-950d are then configured to send the (redesigned) components / parts of the circuit back to the parent 900.

[0076] When parent block 900 receives all (redesigned) components / parts of the circuit from all child blocks 950a-950d, parent block 900 then assembles the completed circuit (in this case, an ADC) from the components / parts designed by each child block, simulates how the assembled circuit operates, and verifies whether the designed circuit meets the circuit performance requirements via a verification / simulator module 903 that can compare this simulated performance to the circuit performance requirements. If the analog circuit meets the circuit performance requirements, parent block 900 can output the generated design. If the analog circuit does not meet the circuit performance requirements, parent block 900 may determine correction instructions / criteria for at least one affected circuit part among several circuit parts, based on the simulation output and the circuit performance requirements, and provide correction instructions / criteria for each affected circuit part to at least one corresponding child block 950a-950d. The parent block 900 can, instead, receive the updated design of each affected circuit section from at least one corresponding child block 950a-950d, and update the current design of the analog circuit with the updated design of each affected circuit section.

[0077] As shown in Figure 3 above, the parent block 900 can then optionally determine whether the current design of the updated analog circuit meets at least one circuit performance requirement, and optionally to what extent the current design meets at least one set of circuit performance requirements and / or manufacturing process-related rules (step 307). This process may be repeated to generate multiple manufacturing analog circuit designs, all of which meet the circuit performance requirements, but some designs may be better suited than others to at least one set of circuit performance requirements and manufacturing process-related rules. The parent block 900 can then select and output from the multiple generated analog circuit designs the analog circuit design that best meets at least one set of circuit performance requirements and manufacturing process-related rules.

[0078] It will be understood that child blocks 950a-950d and / or parent block 900 may also include loop relaxation modules to prevent the occurrence of endless redesign loops. For example, the loop relaxation module may have a record of previously designed circuits and be configured to output a loop indication when a component / part of the redesigned circuit, or the completed circuit, is identical to a component / part of the previously designed circuit, or the completed circuit, or when the difference between the components / part of the previously designed circuit, or the completed circuit, is less than a selected threshold level. For example, parent block 900 may include a loop relaxation module and be configured to terminate the design process when the loop relaxation module provides a loop indication, accepting the last designed circuit as the completed circuit. Furthermore or alternatively, parent block 900 may be configured to reduce the difference at a selected threshold level when the design process has been repeated a selected number of times, for example. This may result in finding a “best compromise” functional circuit that satisfies technical requirements.

[0079] Figure 4 is a schematic diagram of the functionality of another embodiment of a computer implementation model for designing analog circuits. The implementation of this model is similar in many respects to the model shown in Figure 2, and the functions described above for the parent block 900 and child blocks 950a to 950d in Figure 2 can be attributed to the parent and child blocks in Figure 4. Furthermore, some of the functions described in Figure 2 for the primary design unit or parent block 900 can be attributed to the secondary design unit or child blocks 950a to 950d in Figure 4, if its child block has a tertiary design unit or "grandchild" block below it.

[0080] More specifically, as shown in Figure 4, the model hierarchy comprises a core design layer containing a main design unit or parent block. While only one parent block 900 is shown in the core design layer of Figure 4, it will be understood that in some examples, there may be multiple parent blocks 900, such as when each parent block 900 operates in parallel. For example, each parent block 900 may be configured to design different aspects of an analog circuit (e.g., functionally and / or structurally different from each other).

[0081] Below the core design layer is the first design layer. The first design layer comprises a second design unit or child block 950 coupled to the parent block 900 of the layer above (in this case, the core design layer). In this example, there are six child blocks, all coupled to the parent block of the core design layer. The child blocks 950 are divided into two distinct groups: a first group consisting of child blocks 1, 2, and 3, and a second group consisting of child blocks 4, 5, and 6. Each child block 950 is coupled to the parent block 900. The two groups can represent different functional areas or regions of analog circuitry that the parent block 900 instructs to design in parallel.

[0082] In the illustrated example, the first group of child blocks 950 are coupled in parallel to the parent block 900 of the core design layer, and the second group of child blocks 950 are coupled in parallel to the parent block 900 of the core design layer. Child blocks 950 can be grouped in this way to design different areas or aspects of an analog circuit (e.g., functionally and / or structurally different from each other). However, it will be understood that in some examples, it is not necessary for all child blocks 950 of the first design layer to be coupled in parallel to the parent block of the core design layer. For example, child blocks 1 and 3 of the first design layer may be coupled to the parent block 900 of the core design layer, and child block 2 of the first design layer may be coupled in series to child blocks 1 and 3, respectively.

[0083] The grouping of child blocks 950 may be determined by the parent block 900 of the core design layer. For example, the parent block 900 may be configured to group child blocks of the first design layer to design different aspects of an analog circuit (e.g., functionally and / or structurally different from each other). The parent block 900 of the core design layer may be configured to do this based on the determination of requirements from customer specifications.

[0084] Below the first design layer is the second design layer. The second design layer comprises tertiary design units or grandchild blocks 1, 2, 3, 4, 5, 6, 7, 8 (960). Grandchild block 960 is coupled to the child block of the layer above it (the first design layer). Not all child blocks of the first design layer are coupled to the grandchild blocks of the second design layer. In the illustrated example, grandchild blocks 1, 2, and 3 of the second design layer are coupled in parallel to child block 2 of the first design layer. However, as described above for child block 950 of the first design layer, it will be understood that in some examples, not all grandchild blocks of the second design layer need to be coupled in parallel to the child blocks of the first design layer. For example, grandchild blocks 1 and 3 of the second design layer may be coupled to child block 2 of the first design layer, and grandchild block 2 of the second design layer may be coupled in series to grandchild blocks 1 and 3 of the second design layer, respectively.

[0085] Below the second design layer is another (Nth) design layer. The Nth design layer comprises great-grandchild blocks 1, 2, 3, and 4 (970). Great-grandchild block 970 is coupled to the grandchild block 960 of the layer above it (the second design layer) in much the same way that the grandchild block 960 of the second design layer is coupled to the child block 950 of the first design layer. Thus, it can be seen that below the second design layer there may be multiple design layers, each containing its own blocks coupled to the blocks of the layer above it.

[0086] The block hierarchy structure shown in Figure 4 is configured such that blocks at different hierarchical levels of the model design aspects or parts of an analog circuit at different levels of complexity. For example, the parent block 900 may be configured to design a complete analog circuit, the child block 950 may be configured to design functional components of an analog circuit (such as operational amplifiers, AC / DC converters, level shifters, comparators, voltage regulators, and power switches), and the grandchild block 960 may be configured to design components of that functional component (for example, the arrangement of resistors, transistors, capacitors, diodes, inductors, etc. of that component).

[0087] The parent block 900 (of the core design layer) may be configured to determine the level of complexity to which the blocks of a selected layer are configured to design, and / or, a block in a certain layer may be configured to determine the level of complexity to which the blocks in the layer below are configured to design.

[0088] Alternatively, the block hierarchy structure shown in Figure 4 is configured such that blocks in different layers of the model design aspects or parts of an analog circuit based on different functional or structural requirements. For example, one layer may consist of blocks configured to design aspects or parts of an analog circuit based on one functional requirement (e.g., size), while another layer may consist of blocks configured to design for another functional requirement (e.g., current or voltage).

[0089] Figure 5 is a functional flowchart illustrating an example of an analog circuit design method using, for example, the computer implementation hierarchy model shown in Figure 2 or Figure 4. The method in Figure 5 shares many features with the method described above with respect to Figure 2.

[0090] In step 500, the parent block 900 receives the technical requirements for the circuit to be designed, including at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules. The parent block 900 is configured to translate the technical requirements into a set of instructions / criteria. As part of this process, the instructor module 901 selects an initial analog circuit design architecture from among several candidate analog circuit design architectures as the current analog circuit design architecture (502), the selection of the initial analog circuit design depends on a set of manufacturing process-related rules.

[0091] The parent block 900 may be configured to additionally or alternatively determine whether to send these instructions / criteria to the child blocks 950 in parallel or in series, and / or send a different set of instructions / criteria to the child blocks 950 in the lower layers.

[0092] At this stage, the parent block 900 may be configured to determine the number of layers in the model, for example, based on the selected current analog circuit design architecture, or it may be configured to determine whether the lower layer blocks are necessary when designing the part of the circuit that is left to the upper layer blocks to design.

[0093] The parent block 900 converts the technical requirements into instructions / criteria (502) and sends them to child block 1 of the first design layer. These instructions / criteria can specify how many child blocks 950 of this layer to use and which child block 950 will be responsible for designing each part of the analog circuit.

[0094] Upon receiving a criterion, child 1 designs the first part of the analog circuit based on the received instructions / criterion, in accordance with the current analog circuit design architecture (506). It will be understood that child 1 may be configured to design the first part of the analog circuit based on a subset / first part of instructions / criteria applicable to it, as determined by the parent block.

[0095] When child 1 designs the first part of an analog circuit, the instruction / reference received from parent block 900 can instruct child 1 to send the designed first part of the circuit and the reference to a second child (child 2) on the same layer (508). Child 2 can then design the second part of the analog circuit based on the received instruction / reference according to the current analog circuit design architecture (510), and in some examples, the second part of the analog circuit can be designed based on only a subset of the instruction / reference (e.g., only the parts applicable to it) or on all of the instruction / reference.

[0096] Child 2 also adapts the design of the second part of the analog circuit based on the context created by the first part of the analog circuit designed by Child 1. In some examples, this context may be expressed in the form of a set of adjusted criteria, for example, Child 1 and / or the parent block may be configured to adjust the criteria based on the context and / or parasites provided by the first part of the circuit designed by Child 1, but in other examples, it will be understood that the context and / or parasites may be provided in addition to / separate from the criteria. For example, in an example where the parent block consists of a verification / simulator module, the verification / simulator module can simulate the performance of the designed part or component of the circuit in order to obtain context and / or parasite information. Furthermore or alternatively, in an example where each child block consists of a verification / simulator module, the verification / simulator module can simulate the performance of the designed part or component of the circuit in order to obtain context and / or parasite information.

[0097] In some examples, child 2 may decide that, according to the current analog circuit design architecture, it is necessary to employ the underlying blocks to design the portion of the circuit that child 2 is tasked with designing, and / or decide whether to employ these underlying blocks in series and / or parallel. Furthermore or alternatively, criteria received by child 2 may instruct child 2 to employ the underlying blocks to design the portion of the circuit that child 2 is tasked with designing (and whether to employ these blocks in series or parallel) (as determined, for example, by the parent block). For example, as shown in Figure 6, child 2 may optionally instruct 512 grandchildren 1 and 2 to design a subset of the second portion of the analog circuit. In such an example, child 2 may optionally verify whether the portion of the circuit designed by the underlying blocks (grandchildren 1 and 2 in the illustrated example) meets the instructions / criteria required of them (513).

[0098] Next, child 2 transmits the designed first part, the designed second part, and the instructions / criteria to child 3 (514). In some examples, the instructions / criteria may be modified by a preceding child. For example, the instructions / criteria may be modified by child 1 and / or child 2 before being transmitted to the next child. For example, child 2 may be configured to modify the instructions / criteria it transmits to child 3 based on the designed first part and / or the designed second part of the circuit.

[0099] Next, child 3 designs a third part of the analog circuit according to the current analog circuit design architecture, based on the received instructions / criteria and, additionally or alternatively, the first and / or second parts that were designed (516).

[0100] Next, child block 3 sends the completed circuit to the parent block, which generates an initial design of the analog circuit based on the set of circuit subdesigns and determines whether the completed circuit currently being designed meets the circuit performance requirements (520). As described above, the parent block can do this by employing a verification and simulation module to simulate the performance of the completed circuit.

[0101] If the designed and completed circuit does not meet the circuit performance requirements, the parent block selects a further analog circuit design architecture, the selection of which depends on a set of manufacturing process-related rules. The process is then repeated, with the parent resending instructions / criteria to child 1 (522) and redesigning the new analog circuit according to the new analog circuit design architecture. As part of this process, the parent may determine that it is necessary to adopt an additional or alternative child (and / or grandchild) block.

[0102] In the above example, it will be understood that the first, second, third, and fourth parts of the analog circuit may be independent parts of the circuit and / or functionally dependent on one another. In other examples, the first, second, third, and fourth parts of the analog circuit may be selected subsets of the analog circuit. For example, the second part may consist of a part of the first part, the third part may consist of parts of the first and second parts, and the fourth part may comprise parts of the first, second, and third parts.

[0103] Figure 6A shows the input buffer, level shifter, DAC, and comparator. Each of these may form part of a complete analog circuit, such as the completed ADC shown in Figure 6B.

[0104] The examples shown in Figures 6A and 6B are designed using a computer-implemented hierarchical model as described above. The parent block (or primary design unit) is responsible for the overall design of the ADC, while the child blocks (or secondary design units) are responsible for the input buffer, level shifter, DAC, and comparator, respectively. The parent block receives technical requirements from the user, translates them into circuit performance requirements, and each child block uses them to design its respective part of the circuit. The context of other parts of the circuit is taken into consideration and used by the child blocks when designing their respective parts. This model is also iterative in that when the parent block 900 instructs each child block 950a-950d to design their respective parts or components, some degree of redesign of the circuit and its parts is performed so that the context provided by other parts of the circuit is used when designing each circuit part and the circuit as a whole. As described above, each child block and / or parent block can also perform verification / checking to determine whether the designed part / complete circuit meets the required technical requirements.

[0105] The reason there are two DACs in the designed circuit shown in Figure 6B is that this circuit operates as a differential ADC. There are multiple input buffers (three in the example shown) because two are used to buffer the two inputs, and the reference is also buffered as an input.

[0106] As described above, analog circuit design equipment can use machine learning models to identify, select, and / or prioritize candidate analog circuit design architectures.

[0107] The machine learning model may include a neural network. The neural network may include at least one of the following: a deep residual network, a highway network, a tightly coupled network, and a capsule network.

[0108] In this type of network, the network may consist of multiple different neurons organized into different layers. Each neuron is configured to receive input data, process this input data, and provide output data. Each neuron can be configured to perform specific operations on its input, which may include mathematical processing of the input data. The input data of each neuron can include outputs from several other preceding neurons. As part of the neuron's operation on the input data, each stream of input data (for example, each preceding neuron has one stream of input data that provides the neuron's output) is assigned a weight. In other words, the neuron's processing of the input data involves applying weights to different streams of the input data, so that different items of the input data have a greater or lesser impact on the neuron's overall output. If the input values ​​of a neuron are adjusted, such as as a result of a change in the input weighting, the output values ​​of that neuron may change. The output data from each neuron can be sent to several subsequent neurons.

[0109] Neurons are organized in layers. Each layer contains multiple neurons that process data supplied from the outputs of neurons in the preceding layer. Each layer may contain many different neurons, each applying different weights to the input data and performing different operations on the input data. The input data for all neurons in a layer may be the same, and the output from a neuron is passed to the neurons in the subsequent layer.

[0110] Precise routing between neurons in different layers is a major difference between capsule networks and deep residual networks (including variations such as highway networks and tightly coupled networks).

[0111] In residual networks, layers are organized into blocks, and a network can have multiple blocks, each block containing at least one layer. In residual networks, output data from a neuron in a single layer may follow multiple different paths. In conventional neural networks (such as convolutional neural networks), output data from one layer is passed to the next layer, continuing to the end of the network, with each layer receiving input from the layer immediately preceding it and providing output to the layer immediately following it. However, in residual networks, different routing may occur between layers. For example, the output from one layer may be passed to multiple different subsequent layers, and the input to one layer may be received from multiple different preceding layers.

[0112] In a residual network, layers of neurons can be organized into different blocks, each block containing at least one layer of neurons. The blocks can be arranged with layers stacked on top of each other, such that the output of the preceding layer (or layers) becomes the input to the layer of the next block. The structure of a residual network may be such that the output from one block (or layer) is passed to both the immediately following block (or layer) and at least one other subsequent block (or layer). Shortcuts may be introduced into the neural network that pass data from one layer (or block) to another while bypassing other layers (or blocks) in between. This allows for more efficient network training, for example, by addressing degradation-related issues when training very deep networks (this will be discussed in more detail below). The arrangement of a residual neural network may allow for branching so that the same input provided to one layer or block of layers is provided to at least one other layer or block of layers (for example, so that other layers operate on both input and output data from one layer or block of layers). This arrangement allows for deeper penetration into the network when training it using backpropagation algorithms. For example, during training, a layer or block of layers can receive the inputs and outputs of the previous layer / block as inputs, and shortcuts can be used to provide deeper penetration when updating the network's weights.

[0113] In a capsule network, layers can be nested inside other layers to provide "capsules." Different capsules can be adapted to be more proficient in performing different tasks than other capsules. A capsule network can provide dynamic routing between capsules so that for a given task, the task is assigned to the capsule most capable of handling that task. For example, a capsule network can avoid routing the outputs of all neurons in one layer to all neurons in the next layer. Lower-level capsules are configured to send their input to the higher-level (successor) capsule that is judged to be most likely to process their input. Capsules can predict the activity of capsules in higher layers. For example, a capsule may output a vector whose direction represents the properties of the object in question. In response, each subsequent capsule may output the probability that the object it is trained to identify is present in the input data. This information (e.g., probability) can be fed back to the capsule, which can dynamically determine routing weights and forward the input data to the subsequent capsule that is most likely to be the relevant capsule to process the data.

[0114] Any type of neural network may include multiple different layers with different functions. A neural network may include at least one convolutional layer configured to convolve the input data horizontally and vertically. A neural network may also have multiple filtering layers, each filtering layer comprising multiple neurons configured to focus on different parts of the input data and apply filters. Other layers for processing the input data may include pooling layers (to introduce nonlinearity), such as maximum pooling or global average pooling, rectified linear unit layers (ReLU), loss layers, etc. The final block of layers can receive input from the last output layer (or more layers if there are branches). The final block may comprise at least one fully connected layer.

[0115] The final output layer may include classifiers such as softmax, sigmoid, and tan. Different classifiers may be suitable for different types of outputs; for example, a sigmoid classifier may be suitable when the output is a binary classifier. The neural network of this disclosure may be configured to predict which analog circuit design architecture is most likely to function based on at least one of the circuit performance requirements and the manufacturing requirements of the analog circuit, and to specify a particular set of manufacturing process-related rules. The output of the neural network may provide an index of the probability that an analog circuit design architecture satisfies both at least one manufacturing requirement and at least one circuit performance requirement. For example, the output of the neural network may provide an index of the probability that an analog circuit design architecture satisfies at least one circuit performance requirement, using the knowledge that an analog circuit design architecture definitely satisfies at least one manufacturing requirement. The circuit design architectures may be prioritized or ranked according to the determined probabilities, for example, when the parent block described above selects a circuit design architecture from among several circuit design architectures that satisfy at least one manufacturing requirement, the one determined to have the highest probability of satisfying at least one circuit performance requirement may be selected first.

[0116] Figure 7 is a schematic diagram of an exemplary method for training a machine learning model to estimate the probability that an analog circuit design architecture satisfies at least one manufacturing requirement and at least one circuit performance requirement. The neural network 700 is configured to take designed circuit parts and / or analog circuits as input (710). The designed circuit parts and / or analog circuits may be stored in a database and may be designed using a hierarchical model of primary and secondary design units, using the computer implementation model described above with reference to Figures 1A to 6B. The circuit parts and / or analog circuits may be vectorized and / or encoded, for example, by using one-hot encoding to provide a binary format. This input is fed into the 3D layer of the neural network. The network has several features that can be changed as the network is trained. Each neuron may have multiple weights, each weight applied to its respective input stream with respect to output data from neurons in preceding layers. These weights are modifiable variables to change the output of the neural network. These weights can be changed during training to obtain more accurate data. The modified weights, as they have been trained, are called "trained." Furthermore, while layer size and connectivity may depend on the network's typical input data, these too may be variables that are modified and learned during training, including connectivity enhancements.

[0117] To train a network, for example, to learn the values ​​of the weights, these weights are assigned initial values. These initial values ​​can be basically random, but to improve network learning, appropriate initialization of the values, such as Xavier / Glorot initialization, can be applied. Such initialization can prevent situations where the initial random weights are too large or too small, preventing the neural network from being properly trained to overcome these initial biases. This type of initialization may include assigning weights using a distribution with a mean of zero but a fixed variance.

[0118] Once weights are assigned, the training data can be supplied to or input to the neural network 700 (710). This may involve operating the neural network against known design circuits (and / or circuit parts) and their corresponding circuit performance. Based on this information, a backpropagation optimization method using, for example, gradient descent (e.g., stochastic gradient descent) and a loss function may be run on the network to compare the predicted circuit performance (720) with the expected or known circuit performance for that circuit part / analog circuit (730). The expected or known circuit performance may be obtained, for example, using a virtual testbench. Algorithms such as minibatch gradient descent, RMSprop, Adam, Adadelta, and Nesterov may be used during this process. This allows for the identification of how much each different point (neuron) or path (between neurons in subsequent layers) in the network contributes to the determination of an inaccurate score, and as a result, the determination of the weight adjustments that need to be made (740). The weights can be adjusted according to the calculated error (750). For example, minimizing or eliminating contributions from neurons that contribute to, or most contribute to, inaccurate decisions.

[0119] After iteratively training the network with different pairs of designed circuits (and / or circuit parts) and corresponding circuit performance, the weights may be updated (750), and this process may be repeated many times. To mitigate the possibility of network overtraining, training variables such as learning rate and momentum may be varied and / or controlled to selected values. Furthermore, regularization techniques such as L2 and dropout can be used to reduce the possibility that different layers are overtrained by becoming too specialized for the training data without being generally applicable to other similar data. Similarly, batch normalization is also used to aid training and improve accuracy. Generally, weights are adjusted so that the expected results are obtained when the network is run again on the same training data. However, the degree to which this is correct depends on training variables such as the learning rate.

[0120] It should be understood that increasing the depth of a neural network can cause problems during training, such as the vanishing gradient problem, and can also slow down the network. However, this disclosure makes it possible to provide a network with improved depth and accuracy without sacrificing the ability to properly train the network.

[0121] The network depth used can be chosen to balance accuracy and the time it takes to produce an output. Increasing the network depth can potentially improve accuracy, but it can also increase the time it takes to produce an output. Using a branched structure (in contrast to convolutional neural networks) allows the network to learn more as the network depth increases, thus improving the network's accuracy.

[0122] In the context of this disclosure, it will be understood that a non-exhaustive list of exemplary analog parameters that may form the basis of a reference includes noise immunity, power supply rejection ratio (PSRR), common-mode range-input (input CMR), common-mode range-output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandpass range, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter-ptp, jitter-RMS, output ripple-ptp, total harmonic distortion, startup time, channel isolation, reference voltage, gain error, offset error, and gain drift.

[0123] Furthermore, it will be understood that design units (primary, secondary, tertiary design units, etc.) may be implemented in software or hardware, for example, as dedicated circuits. For example, design units may be implemented as part of a computer system. The computer system may include buses or other communication mechanisms for communicating information data, signals, and information between various components of the computer system. Components may include input / output (I / O) components that process user (i.e., sender, receiver, service provider) actions, such as selecting a key from a keypad / keyboard or selecting one or more buttons or links, and send corresponding signals to the bus. I / O components may include output components such as displays and cursor controls (keyboard, keypad, mouse, etc.). Transceivers or network interfaces may send and receive signals between the computer system and other devices such as other user devices, merchant servers, or service provider servers via a network. In one embodiment, the transmission is wireless, but other transmission media and methods may also be preferred. A processor, which may be a microcontroller, digital signal processor (DSP), or other processing component, processes these various signals, such as for display on the computer system or for transmission to other devices via a communication link. The processor may also control the transmission of information such as cookies and IP addresses to other devices.

[0124] The components of a computer system may include system memory components (e.g., RAM), static storage components (e.g., ROM), and / or disk drives (e.g., solid-state drives, hard drives). The computer system performs specific operations by the processor and other components by executing one or more instruction sequences contained in the system memory components.

[0125] Logic may be encoded within a computer-readable medium, which may refer to any medium that participates in providing instructions to the processor for execution. Such a medium can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. In various embodiments, non-volatile media include optical or magnetic disks, volatile media include dynamic memory such as system memory components, and transmission media include coaxial cables, copper wires, and optical fibers. In one embodiment, the logic is encoded in a non-transient computer-readable medium. In one example, the transmission medium may take the form of radio waves, light, and acoustic or optical waves, such as those generated during infrared data communication.

[0126] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes, other magnetic media, CD-ROMs, other optical media, punch cards, paper tapes, other physical media with hole patterns, RAM, PROMs, EPROMs, Flash-EPROMs, other memory chips or cartridges, or other media designed to be read by a computer.

[0127] In various embodiments of the Disclosure, the execution of instruction sequences for implementing the Disclosure may be performed by a computer system. In various other embodiments of the Disclosure, a plurality of computer systems 600 connected by communication links to a network (e.g., LAN, WLAN, PTSN, and / or various other wired or wireless networks including telecommunications, mobile, and cell phone networks) may work together to execute instruction sequences for implementing the Disclosure.

[0128] Furthermore, it will be understood that aspects of this disclosure may be implemented using hardware, software, or a combination of hardware and software. Also, where applicable, the various hardware and / or software components specified herein may be combined into composite components consisting of software, hardware, and / or both, without departing from the spirit of this disclosure. Also, where applicable, the various hardware and / or software components described herein may be separated into subcomponents consisting of software, hardware, or both, without departing from the scope of this disclosure. Furthermore, where applicable, software components may be implemented as hardware components, and vice versa.

[0129] The software described herein, such as program code and / or data, may be stored in one or more computer-readable media. Furthermore, the software identified herein may be implemented using networked and / or other general-purpose or specific-purpose computers and / or computer systems. Where applicable, the order of the various steps described herein may be modified, combined into composite steps, and / or separated into substeps, in order to provide the features described herein.

[0130] The various features and steps described herein may be implemented as a system comprising one or more memories for storing the various information described herein, and one or more processors coupled to one or more memories and a network, wherein the one or more processors are operable to perform the steps described herein in a non-temporary machine-readable medium containing a plurality of machine-readable instructions adapted to cause the one or more processors to perform the methods including the steps described herein, and the methods performed by one or more devices such as hardware processors, user devices, servers, and other devices described herein.

[0131] In the context of this disclosure, other examples and variations of the apparatus and methods described herein will be obvious to those skilled in the art.

Claims

1. It comprises at least one design unit equipped with a processor and a communication interface, The aforementioned processor, (a) Controlling the communication interface to receive information representing the technical requirements of an analog circuit, including (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules. (b) Based on the information received, identify a plurality of candidate analog circuit design architectures that satisfy at least one manufacturing requirement in order to satisfy the circuit performance requirements, (c) As the current analog circuit design architecture, an initial analog circuit design architecture is selected from among the multiple candidate analog circuit design architectures, depending on the set of manufacturing process-related rules. (d) Generate a current design of an analog circuit that satisfies the current analog circuit design architecture, (e) With respect to the current design of the analog circuit, determine whether the current design satisfies at least one of the circuit performance requirements. If it is determined that the current design of the analog circuit does not meet the circuit performance requirements, (f) As the current analog circuit design architecture, a further analog circuit design architecture is selected depending on the set of manufacturing process-related rules: (g) Repeat step (d) and step (e), (h) If it is determined that the current design of the analog circuit design architecture satisfies the circuit performance requirements, the design of the analog circuit is output. It is structured in such a way. Analog circuit design equipment.

2. In the analog circuit design apparatus according to claim 1, The aforementioned processor further, (i) For each current design of the analog circuit, determine to what extent the current design satisfies at least one of the circuit performance requirements and the set of manufacturing process-related rules, (j) As the current analog circuit design architecture, a further analog circuit design architecture is selected depending on the set of manufacturing process-related rules: (k) Repeat steps (d) and (e) above to generate a plurality of generated analog circuit designs, (l) Select and output from the multiple generated analog circuit designs the analog circuit design that best satisfies at least one of the circuit performance requirements and the set of manufacturing process-related rules, It is structured in such a way. Analog circuit design equipment.

3. In the analog circuit design apparatus according to claim 1 or 2, The selection of the analog circuit design architecture in step (c) and / or step (f) is based on prioritizing the candidates of the multiple architectures, which results in a prioritized list of candidate analog circuit design architectures that are determined to satisfy the set of manufacturing process-related rules. Analog circuit design equipment.

4. In the analog circuit design apparatus according to any one of claims 1 to 3, It comprises a primary design unit and a secondary design unit. The aforementioned primary design unit is (m) Based on the received information, identify a number of candidate analog circuit design architectures that satisfy the manufacturing requirements and satisfy the circuit performance requirements, (n) From among the candidate analog circuit design architectures, each comprising multiple circuit components, the initial analog circuit design architecture is selected as the current analog circuit design architecture. (o) For each of the plurality of circuit parts, the respective circuit performance requirements for the circuit part are determined based on a specific set of manufacturing process-related rules, (p) Provide the respective circuit performance requirements for each circuit component to at least one of the plurality of secondary design units. It is configured in such a way, Each of the plurality of secondary design units of the analog circuit design apparatus is (q) Based on the circuit performance requirements for each circuit part provided by the primary design unit, design each circuit part of the plurality of circuit parts, (r) Output the results of the initial design of each circuit part. It is configured in such a way, The aforementioned primary design unit further, (s) The design of each circuit part is received from each of the multiple secondary design units, (t) Based on the respective designs of each circuit component, generate a current analog circuit design of the analog circuit that satisfies the current analog circuit design architecture. It is structured in such a way. Analog circuit design equipment.

5. In the analog circuit design apparatus according to claim 4, The aforementioned primary design unit further, (u) Simulate the analog circuit based on the current analog circuit design and generate at least one simulation output, (v) Verify whether the analog circuit satisfies the circuit performance requirements, If the analog circuit satisfies the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, As the current analog circuit design architecture, a further analog circuit design architecture is selected depending on the set of manufacturing process-related rules. Repeat steps (d) through (e) and steps (m) through (v). It is configured in such a way. Analog circuit design equipment.

6. In the analog circuit design apparatus according to claim 4 or 5, The aforementioned primary design unit further, (w) Simulate the analog circuit based on the current analog circuit design and generate at least one simulation output, (x) Verify whether the analog circuit satisfies the circuit performance requirements of the analog circuit, If the analog circuit satisfies the circuit performance requirements, the generated design is output. If the analog circuit does not meet the circuit performance requirements, For at least one affected circuit portion among multiple circuit portions, a modified circuit performance requirement for the affected circuit portion is determined based on the simulation output and the circuit performance requirement. Provide at least one corresponding secondary design unit with the modified circuit performance requirements for each affected circuit portion, From at least one corresponding secondary design unit, the updated design of each affected circuit portion is received. The current design of the aforementioned analog circuit is updated with the updated design of each affected circuit component. Repeat steps (w) through (x) for the updated design set. It is configured in such a way. Analog circuit design equipment.

7. In the analog circuit design apparatus according to claim 6, Each of the plurality of secondary design units is configured to adapt the design of each part based on the simulated behavior by adapting the design of each part based on the difference between the simulated behavior and the circuit performance requirements. Analog circuit design equipment.

8. In the analog circuit design apparatus according to any one of claims 5 to 7, After at least the initial design of a given circuit portion is completed by at least one of the secondary design units, at least one of the secondary design units is configured to adapt the current analog circuit design based on the context of the corresponding circuit portion, the context includes circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the secondary design units. Analog circuit design equipment.

9. In the analog circuit design apparatus according to any one of claims 4 to 8, After at least the initial design of a given circuit portion is completed by at least one of the secondary design units, at least one of the secondary design units is configured to adapt an initial output design based on the context of the corresponding circuit portion, the context includes circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the secondary design units. Analog circuit design equipment.

10. In the analog circuit design apparatus according to claim 8, Each of the secondary design units is configured to repeat the step of adapting the design of further circuit parts when a change in the design of another circuit part among the plurality of circuit parts causes a change in the context of further circuit parts. Analog circuit design equipment.

11. In the analog circuit design apparatus according to claim 9 or 10, Each of the secondary design units is configured to repeat the step of adapting the design of further circuit components only if the change in the context is greater than a selected threshold level. Analog circuit design equipment.

12. In the analog circuit design apparatus according to any one of claims 8 to 10, The system is configured to obtain the context by simulating the performance of the predetermined circuit portion. Analog circuit design equipment.

13. In a design unit equipped with a processor and a communication interface, (a) controlling the communication interface to receive information representing the technical requirements of an analog circuit, including (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to satisfy a specific set of manufacturing process-related rules; (b) Based on the information received, identify a plurality of candidate analog circuit design architectures that satisfy at least one manufacturing requirement in order to satisfy the circuit performance requirement, (c) The step of selecting an initial analog circuit design architecture from among several candidate analog circuit design architectures, depending on the set of manufacturing process-related rules, as the current analog circuit design architecture, (d) A step of generating a current design of an analog circuit that satisfies the current analog circuit design architecture, (e) A step of determining whether the current design for the analog circuit design architecture satisfies at least one circuit performance requirement, If it is determined that the current design of the analog circuit design architecture does not meet the circuit performance requirements, (f) The step of selecting a further analog circuit design architecture as the current analog circuit design architecture, depending on the set of manufacturing process-related rules, (g) A step of repeating steps (d) and (e), (h) If it is determined that the current design of the analog circuit design architecture satisfies the circuit performance requirements, the step of outputting the design of the analog circuit, Equipped with, Analog circuit design methods.

14. In the analog circuit design method according to claim 13, (i) A step of determining to what extent the current design of the analog circuit satisfies at least one of the circuit performance requirements and the set of manufacturing process-related rules, (j) The step of selecting a further analog circuit design architecture as the current analog circuit design architecture, depending on the set of manufacturing process-related rules, (k) A step of repeating steps (d) and (e) to generate a plurality of generated analog circuit designs, (l) A step of selecting and outputting from a plurality of generated analog circuit designs the analog circuit design that best satisfies at least one of the circuit performance requirements and the set of manufacturing process-related rules, It is equipped with Analog circuit design methods.

15. In the analog circuit design method according to claim 13 or 14, The selection of the analog circuit design architecture in step (c) and / or step (f) is based on prioritizing multiple architecture candidates to create a prioritized list of analog circuit design architecture candidates that are determined to satisfy the set of manufacturing process-related rules. Analog circuit design methods.

16. In the analog circuit design method according to claim 15, In the primary design unit, (m) Based on the received information, the step of identifying a plurality of candidate analog circuit design architectures that satisfy the manufacturing requirements and satisfy the circuit performance requirements, (n) A step of selecting the initial analog circuit design architecture as the current analog circuit design architecture from among the candidate analog circuit design architectures, each having multiple circuit components, (o) For each of the plurality of circuit parts, the step of determining the respective circuit performance requirements for the circuit part based on a specific set of manufacturing process-related rules, (p) The step of providing the respective circuit performance requirements for each circuit component to at least one of a plurality of secondary design units, Equipped with, In each of the above-mentioned secondary design units, (q) A step of designing each of the multiple circuit components based on the circuit performance requirements for each circuit component provided by the primary design unit, (r) A step of outputting the results of the initial design of each circuit part, Equipped with, In the aforementioned primary design unit, (s) The step of receiving the design of each circuit part from each of the multiple secondary design units, (t) A step of generating a current analog circuit design of the analog circuit that satisfies the current analog circuit design architecture based on the respective design of each circuit part, It is equipped with Analog circuit design methods.

17. In the analog circuit design method according to claim 16, In the aforementioned primary design unit, further, (u) The steps of simulating an analog circuit based on the current analog circuit design and generating at least one simulation output, (v) A step of verifying whether the analog circuit satisfies the circuit performance requirements, If the analog circuit satisfies the circuit performance requirements, the step is to output the generated design. If the analog circuit does not meet the circuit performance requirements, The steps include selecting a further analog circuit design architecture based on prioritizing a number of candidate architectures that depend on the set of manufacturing process-related rules, as the current analog circuit design architecture; A step of repeating steps (d) through (e) and steps (m) through (v), It is equipped with Analog circuit design methods.

18. In the analog circuit design method according to claim 16 or 17, In the aforementioned primary design unit, further, (w) A step of simulating an analog circuit based on the current analog circuit design and generating at least one simulation output, (x) A step of verifying whether the analog circuit satisfies the circuit performance requirements of the analog circuit, If the analog circuit satisfies the circuit performance requirements, the step is to output the generated design. If the analog circuit does not meet the circuit performance requirements, A step of determining a modified circuit performance requirement for at least one affected circuit portion among multiple circuit portions, based on the simulation output and the circuit performance requirement, The steps include providing at least one corresponding secondary design unit with the modified circuit performance requirements for each affected circuit portion, The steps include receiving the updated design of each affected circuit portion from at least one corresponding secondary design unit, The steps include updating the design set with the updated design for each affected circuit part, A step of repeating steps (w) through (x) for the updated design set, It is equipped with Analog circuit design methods.

19. In the analog circuit design method according to claim 16, In each of the above-mentioned secondary design units, The method includes a step of adapting the design of each part based on the simulated behavior, by adapting the design of each part based on the difference between the simulated behavior and the circuit performance requirements. Analog circuit design methods.

20. In the analog circuit design method according to any one of claims 16 to 18, The process further includes the step of adapting the initial design output by at least one of the secondary design units, after at least the initial design of a given circuit portion has been completed by at least one of the secondary design units, based on the context of the corresponding circuit portion, wherein the context includes circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the secondary design units. Analog circuit design methods.

21. In the analog circuit design method according to any one of claims 16 to 20, The process further includes, after at least the initial design of a given circuit portion has been completed by at least one of the secondary design units, adapting at least one output initial design of the secondary design unit based on the context of the corresponding circuit portion. The context includes circuit performance requirements generated based on the completed design of the predetermined circuit portion completed by at least one of the secondary design units, Analog circuit design methods.

22. In the analog circuit design method according to claim 21, If a modification to the design of another circuit component among the plurality of circuit components causes a further change in the context of a further circuit component, the step of adapting the design of the further circuit component is further repeated in each of the secondary design units, Analog circuit design methods.

23. In the analog circuit design method according to claim 21 or 22, The process further includes repeating the step of adapting the design of further circuit components only if the change in the context is greater than a selected threshold level. Analog circuit design methods.

24. In the analog circuit design method according to any one of claims 21, 22, or 23, The aforementioned context is obtained by simulating the performance of the predetermined circuit portion. Analog circuit design methods.

25. In the analog circuit design method according to any one of claims 13 to 24, This further includes the step of fabricating analog circuits according to the output design. Analog circuit design methods.

26. A computer-readable non-temporary storage medium comprising a computer program configured to cause a processor to perform the method described in any one of claims 13 to 24.

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