Method for manufacturing photonic packages

Abstract

To provide a photonic interposer that enables low-power and high-bandwidth inter-chip and intra-chip communication.SOLUTION: Some embodiments provide a photonic interposer that uses photonic tiles, each of which contains programmable photonic circuitry that can be programmed based on needs of a particular computer architecture. Some tiles are instantiated common template tiles that are stitched together in 1D or 2D arrangements. A programmable physical network is constituted designed to connect pairs of tiles with each other using photonic links.SELECTED DRAWING: Figure 1-1

Description

【Background Art】 【0001】 A computer system includes random access memory (RAM) for storing data and machine code. RAM is typically volatile memory, such that the stored information is lost when power is removed. In recent implementations, the memory is in the form of an integrated circuit. Each integrated circuit includes a plurality of memory cells. To enable access to the stored data and machine code, the memory is arranged in electrical communication with a processor. Typically, these electrical communications are implemented as metal traces formed on a substrate on which the memory and processor are provided. 【Summary of the Invention】 【0002】 Some embodiments relate to a photonic interposer comprising a plurality of photonic tiles instantiating template photonic tiles, each of the plurality of photonic tiles comprising a transceiver comprising a transmitter and a receiver, an electrical connection configured to enable electrical communication between the transceiver and an electronic chip when the electronic chip is attached to the photonic interposer corresponding to the photonic tile, a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides, and an optical distribution network comprising a plurality of programmable interconnects, each programmable interconnect configured to selectively optically communicate a bus waveguide of the first set of bus waveguides with a bus waveguide of the second set of bus waveguides, each programmable interconnect comprising a waveguide intersection and an active coupler. 【0003】 In some embodiments, the transceiver comprises a plurality of modulators coupled to a first bus waveguide of the first set of bus waveguides and tuned to different wavelengths relative to each other, and a plurality of drop filters coupled to a second bus waveguide of the first set of bus waveguides and tuned to different wavelengths relative to each other. 【0004】 In some embodiments, the multiple modulators are resonant modulators, and the multiple drop filters are resonant drop filters. In some embodiments, the transmitter is configured to transmit data in either a first or second direction along a first bus waveguide of a first set of bus waveguides. 【0005】 In some embodiments, each of the multiple photonic tiles further comprises a 2x2 coupler that couples a transceiver to a first bus waveguide of a first set of bus waveguides. In some embodiments, the 2x2 coupler comprises first, second, third, and fourth terminals, the first terminal being coupled to the output of the transmitter, the second terminal being coupled to the input of the receiver, and the third and fourth terminals being coupled to the first bus waveguide of a first set of bus waveguides. 【0006】 In some embodiments, each of the multiple photonic tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter. The transmitter is coupled to the input of the interferometer, the first and second outputs of the interferometer are coupled to a resonant filter, and the resonant filter is coupled to the first bus waveguide of a first set of bus waveguides. 【0007】 In some embodiments, each of a plurality of photonic tiles further comprises an interferometer having an output and first and second inputs, and a resonant filter, the resonant filter being coupled to a first bus waveguide of a first set of bus waveguides, the first and second inputs of the interferometer being coupled to the resonant filter, and a receiver being coupled to the output of the interferometer. 【0008】 In some embodiments, the waveguide crossover comprises a first waveguide patterned on a first waveguide layer, a second waveguide patterned on a second waveguide layer, and a third waveguide layer patterned on a third waveguide layer, the second waveguide layer being located between the first and third waveguide layers, the first waveguide being evanescently coupled to the second waveguide, and the second waveguide being evanescently coupled to the third waveguide. 【0009】 In some embodiments, the first waveguide layer is made of silicon, and both the second and third waveguide layers are made of silicon nitride. In some embodiments, the active coupler includes a first terminal coupled to a first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide crossover. 【0010】 In some embodiments, the active coupler includes first and second Mach-Zehnder interferometers (MZI), where the first terminal corresponds to the first output of the first MZI, the second terminal corresponds to the second output of the first MZI, and the third terminal corresponds to the output of the second MZI. 【0011】 In some embodiments, a second set of bus waveguides traverses multiple photonic tiles. Some embodiments relate to a photonic interposer, the photonic interposer comprising a plurality of photonic tiles instantiating a template photonic tile, the plurality of photonic tiles including a first, second, third, and fourth photonic tile, each of the plurality of photonic tiles comprising a first transceiver and an electrical connection coupled to the first transceiver, configured to enable electrical communication between the first transceiver and the electronic chip when an electronic chip is mounted on the photonic interposer corresponding to the photonic tile. The system comprises: first and second bus waveguides, each traversing a first and second photonic tile; third and fourth bus waveguides, each traversing a third and fourth photonic tile; and first and second fibers, wherein the first fiber, the first bus waveguide, and the fourth bus waveguide enable optical communication between a first transceiver of the first photonic tile and a first transceiver of the fourth photonic tile; and the second fiber, the second bus waveguide, and the third bus waveguide enable optical communication between a first transceiver of the second photonic tile and a first transceiver of the third photonic tile. 【0012】 In some embodiments, each of a plurality of photonic tiles further comprises a second transceiver, and the second transceiver of the first photonic tile communicates optically with the second transceiver of the second photonic tile. 【0013】 In some embodiments, the second transceiver of the third photonic tile communicates optically with the second transceiver of the fourth photonic tile. In some embodiments, the photonic interposer further comprises a third fiber, and the third fiber, a first bus waveguide, and a fourth bus waveguide further optically communicate the first transceiver of the first photonic tile with the first transceiver of the fourth photonic tile. 【0014】 In some embodiments, the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile form a closed loop. 【0015】 In some embodiments, the photonic interposer further comprises a fourth fiber, and the fourth fiber, a second bus waveguide, and a third bus waveguide further optically communicate the first transceiver of the second photonic tile with the first transceiver of the third photonic tile. 【0016】 In some embodiments, the second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile form a closed loop. 【0017】 Some embodiments relate to a computing system comprising a photonic interposer having multiple photonic tiles instantiating template photonic tiles, and first and second application-specific integrated circuits implemented on the photonic interposer. A first ASIC is coupled to a first photonic tile among a plurality of photonic tiles, and the second ASIC is coupled to a second photonic tile among a plurality of photonic tiles, comprising a data path for the first ASIC to communicate with the second ASIC, comprising: a first die-to-die (D2D) interface incorporated in the first ASIC and having a plurality of wires; a plurality of first SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to the plurality of SerDes and formed in the first photonic tile; a plurality of photodetectors coupled to the plurality of optical modulators and formed in the second photonic tile; a plurality of second SerDes coupled to the plurality of photodetectors; and a second D2D interface incorporated in the second ASIC, comprising a data path. 【0018】 In some embodiments, multiple photodetectors are coupled to multiple optical modulators via waveguides formed on a photonic interposer. In some embodiments, multiple photodetectors are coupled to multiple optical modulators via a fiber. 【0019】 In some embodiments, the first and second D2D interfaces include an Advanced Interface Bus (AIB) interface. 【0020】 In some embodiments, the first and second D2D interfaces include a Universal Chiplet Interconnect Express (UCIe) interface. 【0021】 In some embodiments, the data path extends a length greater than 2.5 cm from the first D2D interface to the second D2D interface. Some embodiments relate to a method for manufacturing a photonic package, the method comprising obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer, attaching an electronic chip to the first surface of the photonic interposer, encapsulating the electronic chip with an encapsulation material, disposing a protective material on the first surface of the photonic interposer so as to cover the grating coupler, following the disposing of the protective material, forming an electrical connection on a second surface of the photonic interposer opposite the first surface, following the forming of the electrical connection, removing the protective material from the first surface of the photonic interposer so as to expose the grating coupler to air. 【0022】 In some embodiments, the method further comprises cleaning the first surface of the photonic interposer following the removal of the protective material from the first surface of the photonic interposer. 【0023】 In some embodiments, the method further comprises attaching a fiber to the first surface of the photonic interposer following the removal of the protective material, whereby the fiber is optically coupled to the grating coupler when attached. 【0024】 In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber is at a non-zero angle with respect to the first surface of the photonic interposer. In some embodiments, attaching the electronic chip to the first surface of the photonic interposer is performed following the disposing of the protective material on the first surface of the photonic interposer. 【0025】 In some embodiments, the protective material includes a photoimageable dielectric. In some embodiments, disposing the protective material on the first surface of the photonic interposer is performed following attaching the electronic chip to the first surface of the photonic interposer. 【0026】 In some embodiments, disposing the protective material on the first surface of the photonic interposer is performed following encapsulating the electronic chip with an encapsulation material. In some embodiments, the protective material comprises a glass lid having a removable adhesive. 【0027】 Some embodiments relate to a method for manufacturing a photonic package, the method comprising obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer, attaching an electronic chip to the first surface of the photonic interposer, encapsulating the electronic chip with an encapsulation material such that the grating coupler remains exposed to air, disposing the photonic interposer on a carrier mount so as to cover the grating coupler, forming electrical connections on a second surface of the photonic interposer opposite the first surface following disposing the photonic interposer on the carrier mount, and removing the carrier mount following forming the electrical connections. 【0028】 In some embodiments, encapsulating the electronic chip is performed following attaching the electronic chip to the first surface of the photonic interposer. In some embodiments, the method further comprises separating the photonic interposer into a plurality of systems each comprising an electronic chip and a grating coupler following removing the carrier mount. 【0029】 In some embodiments, the method further includes, following the removal of protective material, attaching a fiber to a first surface of a photonic interposer, thereby optically coupling the fiber to a grating coupler when attached. 【0030】 In some embodiments, when the fiber is optically coupled to the lattice coupler, the fiber is at a non-zero angle with respect to the first surface of the photonic interposer. Some embodiments relate to a photonic package, the photonic package comprising: a photonic interposer; a first electronic chip disposed on the photonic interposer; a circuit board having a first surface and a second surface opposite to the first surface, the photonic interposer being coupled to the first surface of the circuit board; a voltage regulator module (VRM) coupled to the second surface of the circuit board; and a connection portion configured to provide the output voltage of the VRM to the first electronic chip, the connection portion traversing the circuit board and the photonic interposer. 【0031】 In some embodiments, the photonic package further comprises a substrate and a socket, where the photonic interposer is placed on the substrate and the substrate is placed on the socket. In some embodiments, the connection further extends across the substrate and the socket. 【0032】 In some embodiments, the photonic package further comprises a power bus configured to provide an input voltage to a voltage regulator module. In some embodiments, a voltage regulator module receives an input voltage from a power bus and adjusts the output voltage to a first electronic chip. 【0033】 In some embodiments, the first electronic chip is in contact with a photonic interposer. In some embodiments, the photonic package further comprises a lid covering a photonic interposer and a cooling plate covering the lid, the lid being in thermal contact with the first electronic chip. 【0034】 Some embodiments relate to a photonic device, the photonic device comprising: a photonic circuit; a plurality of optical channels having a plurality of chip-fiber couplers and a plurality of waveguides coupled to each chip-fiber coupler; an optical switch coupled between the plurality of optical channels and the optical circuit; and a controller configured to determine performance information associated with each of the plurality of optical channels, to use the performance information associated with each of the plurality of optical channels to identify a subset of the plurality of optical channels, and to control the optical switch to selectively couple the subset of the plurality of optical channels to the photonic circuit. 【0035】 In some embodiments, the multiple optical channels further comprise multiple photodetectors coupled to each waveguide, and determining performance-related information associated with each of the multiple optical channels includes determining the output of each of the multiple photodetectors. 【0036】 In some embodiments, multiple photodetectors are coupled to their respective waveguides via tap couplers. In some embodiments, determining performance information associated with each of the multiple optical channels includes determining the bit error rate (BER) associated with each of the multiple optical channels. 【0037】 In some embodiments, the photonic circuit comprises a plurality of tiles patterned according to a template tile, each tile comprising a transmitter, a receiver, a network of programmable optical connections, and an electrical connection configured for vertical die-to-die connections with an electronic chip, the electrical connection being coupled to the transmitter, receiver, and network of programmable optical connections. 【0038】 In some embodiments, using information to identify a subset of multiple optical channels includes identifying a subset of multiple optical channels that exhibit the best performance among the optical channels. 【0039】 In some embodiments, the tip-fiber coupler comprises an edge coupler or a grid coupler. In some embodiments, the controller is further configured to control the photonic circuit to transmit data to the outside of the photonic device using a subset of multiple optical channels selected by an optical switch. 【0040】 Some embodiments relate to a method for transmitting data using a photonic device comprising an optical switch and a plurality of optical channels having a plurality of chip-fiber couplers and a plurality of waveguides coupled to each chip-fiber coupler, the method comprising determining performance-indicating information associated with each of the plurality of optical channels, identifying a subset of the plurality of optical channels using the performance-indicating information associated with each of the plurality of optical channels, controlling the optical switch to select a subset of the plurality of optical channels, and transmitting data to the outside of the photonic device using the subset of the plurality of optical channels selected by the optical switch. 【0041】 In some embodiments, the multiple optical channels further comprise multiple photodetectors coupled to each waveguide, and determining performance-related information associated with each of the multiple optical channels includes determining the output of each of the multiple photodetectors. 【0042】 In some embodiments, determining performance information associated with each of the multiple optical channels includes determining the bit error rate (BER) associated with each of the multiple optical channels. 【0043】 In some embodiments, using information to identify a subset of multiple optical channels includes identifying a subset of multiple optical channels that exhibit the best performance among the optical channels. 【0044】 Some embodiments relate to a photonic interposer, the photonic interposer comprising a plurality of photonic tiles, including redundant tiles, each photonic tile comprising a transmitter, a receiver, an electrical connection unit configured for vertical die-to-die connection to a programmable optical connection network and an electronic chip, coupled to the transmitter, receiver and programmable optical connection network, and a monitoring photodetector; and a controller configured to use the output of each monitoring photodetector to determine information indicating the performance of each of the plurality of photonic tiles, to use the information indicating the performance of each of the plurality of photonic tiles to identify a defective tile from among the plurality of tiles, and to functionally swap the defective tile with a redundant tile. 【0045】 In some embodiments, functionally swapping a defective tile with a redundant tile includes redirecting data directed to the defective tile to the redundant tile. In some embodiments, redirecting data involves programming a network of programmable photonic connections. 【0046】 Some embodiments relate to a photonic interposer, the photonic interposer comprising: a bus waveguide; a plurality of photonic transmitters coupled to the bus waveguide; a plurality of photonic receivers coupled to the bus waveguide; and a controller configured to lock a first photonic transmitter among the plurality of photonic transmitters to a first photonic receiver among the plurality of photonic receivers by dithering the photonic components of a first photonic transmitter at a first frequency and dithering the photonic components of a first photonic receiver at a first frequency. 【0047】 In some embodiments, each of a plurality of photonic transmitters comprises a resonant modulator, and each of a plurality of photonic receivers comprises a resonant drop filter coupled to a bus waveguide, and dithering the photonic component of the first photonic transmitter includes dithering the resonant modulator of the first photonic transmitter, and dithering the photonic component of the first photonic receiver includes dithering the resonant drop filter of the first photonic receiver. 【0048】 In some embodiments, each of a plurality of photonic transmitters comprises a resonant additional filter coupled to a bus waveguide, and each of a plurality of photonic receivers comprises a resonant drop filter coupled to a bus waveguide, and dithering the photonic component of the first photonic transmitter includes dithering the resonant additional filter of the first photonic transmitter, and dithering the photonic component of the first photonic receiver includes dithering the resonant drop filter of the first photonic receiver. 【0049】 In some embodiments, the first frequency is 1 kHz to 1000 kHz. In some embodiments, the photonic interposer further comprises a plurality of photonic tiles instantiated from a template photonic tile, each of which comprises a photonic transmitter from a plurality of photonic transmitters and a photonic receiver from a plurality of photonic receivers, and the bus waveguide traverses two or more photonic tiles. 【0050】 Some embodiments relate to a photonic transmitter, the photonic transmitter comprising: a resonant modulator configured to modulate light received from a laser using input data; a Mach-Zehnder interferometer (MZI) coupled to the resonant modulator, the MZI having a first output and a second output; a resonant additional filter coupled to a bus waveguide; and a controller configured to transmit the modulated light along the bus waveguide in either a first or second direction by selectively coupling either the first output or the second output of the MZI to the resonant additional filter. 【0051】 In some embodiments, the photonic transmitter further comprises a heater thermally coupled to a resonant modulator and a first monitoring detector coupled to a first output of the MZI, and the controller is further configured to lock the resonant modulator to the laser by applying a first ramp signal to the heater and maximizing the output generated by the first monitoring detector. 【0052】 In some embodiments, selectively coupling either the first or second output of the MZI to a resonant additional filter includes applying a second ramp signal to the MZI and minimizing the output generated by the first monitoring detector. 【0053】 In some embodiments, selectively coupling either the first or second output of the MZI to a resonant additional filter further includes applying a third ramp signal to the resonant additional filter and minimizing the output generated by a second monitoring detector coupled to the second output of the MZI. 【0054】 In some embodiments, the resonant additional filter includes a second-order filter. Some embodiments relate to a photonic interposer, the photonic interposer comprising: first and second photonic tiles instantiating a template photonic tile, each of which comprises a transceiver and a receiver; an optical channel coupling the transmitter of the first photonic tile to the receiver of the second photonic tile; an encoder coupled to the transmitter of the first photonic tile and configured to perform an Xb / Yb coding scheme; a decoder coupled to the receiver of the second photonic tile and configured to perform an Xb / Yb decoding scheme; and a clock recovery circuit configured to time the receiver of the second photonic tile using the output of the decoder. 【0055】 In some embodiments, the photonic interposer further comprises a first local oscillator coupled to an encoder and a second local oscillator coupled to a decoder. In some embodiments, the photonic interposer further comprises an equalizer coupled to the receiver of a second photonic tile, the equalizer configured to perform a linear combination of the outputs of the receivers of the second photonic tile. 【0056】 In some embodiments, the equalizer is further configured to determine the characteristics of the optical channel during runtime and to adjust the number of taps associated with the equalizer based on the characteristics of the optical channel determined by the equalizer. 【0057】 In some embodiments, the equalizer is further configured to determine the characteristics of the optical channel during runtime and to adjust coefficients associated with the equalizer based on the characteristics of the optical channel determined by the equalizer. 【0058】 Various aspects and embodiments of this application will be described with reference to the following drawings. Please note that these drawings are not necessarily drawn to a fixed scale. Items appearing in multiple drawings are indicated by the same reference numeral in the drawings in which they appear. [Brief explanation of the drawing] 【0059】 [Figure 1-1] A computing system based on a photonic interposer, according to several embodiments, is illustrated. [Figure 1-2A] A semiconductor wafer according to several embodiments is shown. [Figure 1-2B] A set of photomasks according to several embodiments is illustrated. [Figure 1-2C] An example of a photomask for forming an optical waveguide, according to several embodiments, is illustrated. [Figure 1-2D] A wafer from Figure 1-2A, patterned according to the photomask set of Figure 1-2B, is shown according to several embodiments. [Figure 1-2E] This identifies photonic circuits formed on a patterned wafer according to several embodiments, as shown in Figure 1-2D. [Figure 1-3A] An example of a patterned wafer tile according to several embodiments is shown in Figure 1-2E. [Figure 1-3B] A group of tiles of the type shown in Figure 1-3A, according to several embodiments, are illustrated. [Figure 1-4A] A group of tiles sharing the same pattern of metal traces, according to several embodiments, is illustrated. [Figure 1-4B] The diagram illustrates a group of tiles that share the same pattern of metal traces and form a moisture barrier, according to several embodiments. [Figure 2-1A] This document describes an architecture in which photonic interposer tiles are interconnected using static connections, according to several embodiments. [Figure 2-1B]This document presents another architecture in which photonic interposer tiles are interconnected using static connections, according to several embodiments. [Figure 2-1C] This document presents yet another architecture in which the tiles of a photonic interposer are interconnected using static connections, according to several embodiments. [Figure 2-1D] This document describes an architecture in which photonic interposer tiles are interconnected using static connections and fiber, according to several embodiments. [Figure 2-1E] This document describes an architecture in which tiles of a photonic interposer are interconnected using static connections and two fibers, according to several embodiments. [Figure 2-1F] This document describes an architecture in which photonic interposer tiles are interconnected using static connections and three fibers, according to several embodiments. [Figure 2-1G] This document presents another architecture in which tiles of a photonic interposer are interconnected using static connections and two fibers, according to several embodiments. [Figure 2-1H] This document presents another architecture in which photonic interposer tiles are interconnected using static connections and four fibers, according to several embodiments. [Figure 2-1I] We present yet another architecture in which the tiles of the photonic interposer are interconnected using static connections and four fibers, according to several embodiments. [Figure 2-2A] This document describes an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to several embodiments. [Figure 2-2B] This document presents another architecture in which photonic interposer tiles are interconnected using programmable connections, according to several embodiments. [Figure 2-2C] Here is yet another architecture in which tiles of optical interposers are interconnected using programmable connections, according to some embodiments. [Figure 2-2D] The tiling of the photonic interposer shown in Figure 2-2C, according to several embodiments, is shown in more detail. [Figure 2-2E] Examples of programmable photonic interconnects according to several embodiments are shown. [Figure 2-2F] An example of an active coupler according to several embodiments is shown. [Figure 2-3A] This document describes an architecture with a bidirectional bus according to several embodiments. [Figure 2-3B] This document presents another architecture with a bidirectional bus, based on several embodiments. [Figure 2-4A] Several embodiments of photonic circuits for coupling a transmitter to a bidirectional bus are shown. [Figure 2-4B] Several embodiments of photonic circuits for coupling a receiver to a bidirectional bus are shown. [Figure 2-5] An example of waveguide crossing according to several embodiments is shown. [Figure 2-6A] This document presents yet another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to several embodiments. [Figure 2-6B] An example of a coupler used in the example shown in Figure 2-6A, according to several embodiments, is shown. [Figure 2-6C] This document describes an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to several embodiments. [Figure 2-6D] This document presents another architecture in which photonic interposer tiles are interconnected using programmable connections and fibers, according to several embodiments. [Figure 2-7A] This document describes architectures that use wavelength-based tile identification in several embodiments. [Figure 2-7B] This document presents another architecture using wavelength-based tile identification, based on several embodiments. [Figure 2-7B-1]This document presents another architecture using wavelength-based tile identification, based on several embodiments. [Figure 2-7C] We present yet another architecture using wavelength-based tile identification in several embodiments. [Figure 2-7D] An example of a programmable optical loopback used in the example shown in Figure 2-7C, according to several embodiments, is presented. [Figure 2-8A] Several embodiments of an ASIC having an Advanced Interface Bus (AIB) interface are shown. [Figure 2-8B] This document describes ASIC-ASIC connectivity using AIB interfaces and optical links in several embodiments. [Figure 2-8C] The following describes a photonic interposer that hosts multiple ASICs communicating with each other via an AIB interface, according to several embodiments. [Figure 2-9A] This block diagram shows a pair of ASICs interconnected using a wire bundle (WoR) interface, according to one embodiment. [Figure 2-9B] This block diagram shows another pair of ASICs interconnected using a wire bundle (WoR) interface, according to one embodiment. [Figure 2-10A] This is a schematic diagram illustrating a computing network architecture using a photonic interposer, according to several embodiments. [Figure 2-10B] This is a schematic diagram illustrating another computing network architecture using a photonic interposer, according to several embodiments. [Figure 2-10C] This is a schematic diagram illustrating yet another computing network architecture using a photonic interposer, according to some embodiments. [Figure 2-10D] This is a schematic diagram illustrating yet another computing network architecture using a photonic interposer, according to some embodiments. [Figure 3-1] This is a block diagram showing a plesiocronous clock distribution method according to several embodiments. [Figure 3-2] This is a block diagram showing several embodiments of a mesochronous clock distribution scheme. [Figure 3-3A] This block diagram shows some of the photonic interposers configured to perform equalization according to several embodiments. [Figure 3-3B] This block diagram shows examples of adaptive equalizers according to several embodiments. [Figure 3-4A] The following shows a sequence for tuning the transmitter according to several embodiments. [Figure 3-4B] The following shows a sequence for tuning the transmitter according to several embodiments. [Figure 3-4C] The following shows a sequence for tuning the transmitter according to several embodiments. [Figure 3-5A] The following shows a sequence for tuning the receiver according to several embodiments. [Figure 3-5B] The following shows a sequence for tuning the receiver according to several embodiments. [Figure 3-6A] This paper describes techniques for using dithering to lock a receiver to a specific transmitter, according to several embodiments. [Figure 3-6B] This document illustrates optical channels that support communication between multiple transmitter-receiver pairs, according to several embodiments. [Figure 4-1A] Several embodiments of a photonic integrated circuit (PIC) having a photonic circuit and multiple fiber attachment points are shown. [Figure 4-1B] This is a block diagram showing a pair of PICs interconnected using k fibers, according to several embodiments, some of which are provided solely for redundancy. [Figure 4-1C]The overall system yield (%) of a system having 16 fiber attachment sites, according to several embodiments, is shown as a function of the number of attachments at each site. [Figure 4-2] Several embodiments of a photonic interposer having multiple tiles are shown, one of which is provided for redundancy. [Figure 4-3] This is a schematic diagram showing a power monitoring grid embedded in a photonic interposer according to several embodiments. [Figure 5-1] This is a schematic diagram showing fibers coupled to a grid coupler according to several embodiments. [Figure 5-2A] This is a schematic diagram showing a wafer on which multiple photonic circuits are patterned according to several embodiments. [Figure 5-2B] This is a cross-sectional view of the wafer shown in Figure 5-2A, according to several embodiments. [Figure 5-3A] This is a side view of a photonic interposer according to several embodiments. [Figure 5-3B] This is a side view of a packaged photonic interposer according to several embodiments. [Figure 5-4] A flowchart shows a process for manufacturing a packaged photonic interposer according to several embodiments. [Figure 5-5] A flowchart shows another process for manufacturing a packaged photonic interposer according to several embodiments. [Figure 5-6] A flowchart shows yet another process for manufacturing a packaged photonic interposer according to several embodiments. [Figure 5-7] This is a schematic diagram showing a packaged photonic interposer including a voltage regulator module (VRM) according to several embodiments. [Figure 5-8A] This is a block diagram of a VRM according to several embodiments. [Figure 5-8B]This is a schematic diagram showing a package in which power supply to an electronic chip is performed using a VRM, according to several embodiments. [Modes for carrying out the invention] 【0060】 I. Overview The inventors recognize and understand several challenges that limit the scalability of modern digital computing. First, current designs are power-constrained. The trend in modern computing leads to a constant increase in power consumption, which limits its scalability. In addition, the power-hungry nature of modern chips often results in hot spots exceeding 1000°C. High temperatures substantially limit the performance of the computer. Second, modern computing architectures are bandwidth-constrained. These architectures rely on multiple memory chips to provide the hundreds of gigabytes or terabytes of capacity required by modern applications. Unfortunately, providing connectivity between several memory chips is difficult. The physical space available on the board or rack to accommodate the interconnects is limited, and therefore the overall bandwidth is limited. In addition, maintaining coherence and consistency across several memory chips (e.g., memory-to-memory and processor-to-memory) is difficult to achieve. Some architectures rely on Peripheral Component Interconnect (PCI), Compute Express Link (CXL), or Ethernet® for inter-chip communication. However, these interfaces involve board-level or rack-level communication, which increases power consumption and reduces bandwidth. Wafer-scale telecommunications have also been considered, but this approach suffers from reliability issues and power inefficiencies. 【0061】 The inventors have developed a photonic interposer that enables low-power, high-bandwidth inter-chip (e.g., board-level and / or rack-level) and intra-chip communication. This specification describes techniques, architectures, and processes that improve the performance of conventional multi-chip computers. Some embodiments provide a photonic interposer that uses “photonic modules” (also referred herein as “photonic tiles” or simply “tiles”). Each tile contains a programmable photonic circuit that can be programmed based on the needs of a particular computer architecture. Some photonic interposers are arranged according to a one-dimensional scheme such as a 3x1 tile block, a 5x1 tile block, a 10x1 module block, or a 20x1 block. Some photonic interposers are arranged according to a two-dimensional scheme such as a 3x3 tile block, a 5x3 tile block, a 5x5 tile block, or a 10x10 tile block. More generally, a photonic interposer enables any block of NxM tiles where N≧1 and M≧1, and any topology such as T-topology, L-topology, or X-topology. Each tile can function as a node in a computing system. Each node may have one or more digital processor chips, one or more analog accelerators, one or more photonic accelerators, one or more memory chips, one or more networking chips, or other devices. 【0062】 The photonic interposers described herein are engineered to limit manufacturing costs. These platforms may rely on the use of a common set of photomasks (or at least one common photomask) to manufacture multiple tiles. This approach reduces costs in two ways. First, it reduces the additional costs that would have been incurred when procuring multiple different sets of photomasks. Second, it enables the manufacture of tiles using standard semiconductor foundries that require the use of the same set of photomasks (or at least one photomask) across the entire wafer. By designing tiles that share at least one photomask, it becomes possible to manufacture many tiles on the same semiconductor wafer while leveraging standard, low-cost step-and-repeat manufacturing processes. Thus, in some embodiments, the tiles are instantiations (copies) of a common template tile that are stitched together in a 1D or 2D arrangement. Some embodiments include two template tiles such that each tile of the interposer is formed as either an instantiation of a first template tile or an instantiation of a second template tile. Tiles of different templates may alternate, for example, in a checkerboard pattern, such that each tile of the first type is adjacent to a tile of the second type. Other arrangements are also possible. 【0063】 In one example, a photonic interposer includes a 6x8 array of tiles, each tile being an instance of a reticle shot in a step-and-repeat manufacturing process. Each tile measures 24.8mm x 32mm and can support heterogeneous technologies (e.g., general-purpose processors, GPUs, DRAM / HBM stacks, or custom accelerators). With a waveguide pitch of 3μm, the photonic interposer can support well over 10,000 optical links emanating from each tile. 【0064】 Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles to each other using photonic links. The communicating tiles do not need to be adjacent. For example, the physical network can be programmed so that a tile located in the upper left corner can communicate directly with a tile in the lower right corner without retransmission in an intermediate tile. Network configuration time can be less than 10 μs, and communication between any two tiles, whether adjacent or not, can have a transition latency of less than 5 ns. The photonic interposers described herein offer flexibility in forming various logical network topologies (e.g., from low-cardinality large-diameter mesh topologies to high-cardinality small-diameter bus topologies). For example, a 4x4 photonic interposer can map an all-to-all logical network with dedicated channels between each pair of tiles, which can provide bandwidth of up to 14.4 Tbps per channel (between any two tiles) with a total bipartite bandwidth of up to 1851 Tbps. As another example, a photonic interposer can provide up to 231 Tbps of bandwidth per channel for a 2-ary, 4-fly butterfly network. 【0065】 The photonic interposer described herein enables efficient heterogeneous architectural solutions, thereby allowing chips designed from different technology nodes and performing different functions to be housed together on a single wafer, while providing high bandwidth and low latency between chips via photonic links. Furthermore, the photonic interposer described herein allows for slicing large chips into multiple smaller chiplets, thereby addressing the thermal constraints associated with high-power consumption chips. The photonic interposer can host these smaller chiplets and provide energy-efficient communication (similar to on-chip communication) between them. 【0066】 In a multi-chip system, each chip is typically connected to its own dedicated main memory. Data is usually shared among multiple chips using Remote Direct Memory Access (RDMA) (e.g., via a Last Level Cache (LLC) or L2). The photonic interposer described herein can aggregate the main memories of all chips to form a shared global main memory. This global shared main memory is accessible to all chips via a photonic link. For example, the LLC can be obtained by slicing from each chip, and the LLC can be moved next to the common global shared main memory while enabling low-latency and high-bandwidth communication between each chip's L2 and LLC pair. Holding all LLCs together allows for low-overhead coherency management across the LLCs. In some embodiments, the photonic interposers described herein can reduce the overhead of using standard cache coherence protocols across the chip (e.g., IV, MESI, and MOESI) by enabling the efficient design of, for example, cache-coherent non-uniform memory access (NUMA) architectures. 【0067】 In conventional architectures, processor chips communicate with memory chips (e.g., DRAM and HBM) using high-speed electrical links. However, the capacitance associated with electrical links limits the available bandwidth and leads to power consumption. Recently, co-packaged optics (CPOs) have emerged as a potential alternative to electrical links. CPOs provide communication between processors and memory using fiber optic-based communication links. Unfortunately, CPOs are not a scalable solution in that it is still difficult to use fiber links to support communication between one processor chip and multiple memory chips and vice versa. In contrast, the photonic interposers described herein can host processor and memory chips on the same substrate, enabling high-bandwidth density communication. Taking advantage of their wafer-scale nature, photonic interposers can spread processors across multiple tiles so that there is sufficient area for processor components and many memory controllers. This enables architectures that require multiple memory controllers on each processor chip, such as from one processor chip to multiple memory chips and from one memory chip to multiple processor chips. 【0068】 The photonic interposers described herein can be used in a wide variety of applications, including machine learning, privacy protection, and graph applications. Photonic interposers can be used to support communication between analog computing chips (e.g., photonic, memristor) and memory chips, communication between digital computing chips (e.g., processor FPGA GPU) and memory chips, networking chips, digital switch chips, and communication between digital computing chips and analog computing chips. 【0069】 Current machine learning models involve massive amounts of data (e.g., often hundreds of GB to tens of TB). Therefore, a large amount of memory is required to store the models and data. Current technology does not provide sufficient memory within a single chip. The photonic interposer described herein provides a solution for integrating multiple memory chips onto a single board while providing high-bandwidth, low-latency communication between memory chips and computing chips. As a result, execution time is reduced both during training and inference. 【0070】 Since data privacy has become the primary concern when designing systems, various privacy-preserving computing techniques have been proposed. One of these techniques is homomorphic encryption (HE). Memory bandwidth and latency are major bottlenecks in HE-based applications. The photonic interposer described herein can mitigate this problem by providing high-bandwidth and low-latency access to memory. 【0071】 Graph applications involve irregular access to memory. Furthermore, graph applications typically use small data granularity because they do not utilize all the data present in the cache lines. The photonic interposers described herein can overcome this bottleneck by enabling efficient access to memory through high-bandwidth, low-latency photonic links. 【0072】 Architectures, systems, and processes including tile-based photonic interposers are described herein. II. Tile-like photonic interposer Figure 1-1 illustrates an example of a computing system based on a photonic interposer, where nine tiles are arranged in a 3x3 topology, following an example. The computing system 10 includes a photonic interposer 20 patterned with nine tiles 22. This photonic interposer supports one processor die (30) positioned in the center of the photonic interposer 20, and eight memory nodes surrounding the processor die. Some of the memory nodes contain a single memory chip (see, for example, memory die 32). Other memory nodes contain stacked memory, which includes multiple vertically stacked memory dies (see, for example, stacked memory 34). The dies are stacked on a wafer defining the tiles. The dies can communicate electronically (using, for example, through-silicon vias, copper columns, microbumps, ball grid arrays, or other electrical interconnects) and / or optically (using, for example, grating couplers, prisms, lenses, or other optical couplers). 【0073】 As will be described in detail later, the tiles may be patterned with optical waveguides and optical distribution networks. The optical distribution network of a tile can selectively bring the die of a particular node into optical communication with any other die in the computing system. For example, the optical distribution network of a tile positioned beneath the processor die 30 may be reconfigured according to the needs of the processor. At the start of a routine, the processor may need to access data stored in a first memory node. This read operation involves configuring the respective optical distribution network so that the processor is in optical communication with the first memory node. Later in the routine, the processor may need to write data to a second memory node. This write operation involves reconfiguring the optical distribution network so that the processor is in optical communication with the second memory node. 【0074】 Manufacturing tiles on a large scale can be costly. The photonic interposers described herein are engineered to limit manufacturing costs. These platforms rely on the use of a common set (subset) of photomasks to manufacture multiple tiles. This approach reduces costs in two ways. First, it reduces the additional costs incurred when sourcing multiple different photomask sets. Second, while some standard semiconductor contract manufacturers require the use of the same photomask set (or at least one photomask) across the entire wafer, this approach makes it possible to manufacture tiles using those manufacturers. Designing tiles that share at least one photomask makes it possible to manufacture a large number of tiles on the same semiconductor wafer while leveraging standard, low-cost step-and-repeat manufacturing processes. 【0075】 The tiles described herein may be manufactured using microfabrication techniques, for example, complementary metal-oxide-semiconductor (CMOS) microfabrication techniques. Therefore, some embodiments relate to silicon photonic-based photonic interposers. Some specific microfabrication techniques involve a step-and-repeat approach, which uses a stepper machine to pattern a semiconductor wafer with multiple copies of a template layout (e.g., a reticle). Each tile resulting from the step-and-repeat approach may correspond to a reticle. Figures 1-2A to 1-2E illustrate microfabrication techniques for manufacturing tiles. Figures 1-3A to 1-3B show examples of tiles patterned using these microfabrication techniques. 【0076】 Referring first to Figure 1-2A, this figure illustrates a semiconductor wafer 11. The wafer 11 may be made of any material. For example, the wafer 11 may be made of silicon (or otherwise containing silicon). In one example, the wafer 11 is a silicon-on-insulator (SOI) wafer. In another example, the wafer 11 is a bulk silicon wafer. The wafer 11 may have any size. For example, the diameter of the wafer 11 can be 150 mm, 300 nm, or 450 mm, but other values ​​are also possible. However, not all wafers need to have a circular shape. 【0077】 Figure 1-2B illustrates a set of photomasks that may be used to pattern a wafer 11 using photolithography techniques. Photomask set 200 includes three photomasks (201, 202, and 203), but other sets may include more or fewer photomasks. Each photomask has a specific pattern consisting of opaque and transparent areas. When a photomask is exposed, the opaque areas block light, thereby preventing it from illuminating the wafer, while allowing light to pass through the transparent areas. As a result, the pattern of the photomask is transferred to the wafer. 【0078】 Each photomask may define a specific layer of tiles. A single photomask may be used to define an optical waveguide. When the wafer undergoes an etching process, only the exposed areas (or only the unexposed areas) are etched away, while other areas remain unetched. This photomask may be patterned to form a network of optical waveguides when the wafer is exposed through this photomask. Figure 1-2C illustrates a portion of a photomask that may be used to form waveguides on a wafer 11. The lines in photomask 201 represent opaque areas. The background of photomask 201 is transparent. When photomask 201 is exposed so that the image of the photomask is projected onto the wafer 11, it becomes possible to pattern the waveguides with the shape of the opaque areas. In this particular example, the pattern of lines in the photomask becomes the grid of waveguides. 【0079】 Some tiles involve the use of different levels of optical waveguides. In some such embodiments, the photomask set 200 may include a dedicated photomask for each waveguide level. Another photomask may be used to define n-doped regions. When a wafer undergoes an ion implantation or dopant diffusion process, only the exposed regions (or only the unexposed regions) are doped, while other regions remain undoped. A different photomask may be used to define p-doped regions using a similar process. Some tiles involve the use of different doping concentrations. In some such embodiments, the photomask set 200 may include a dedicated photomask for each doping concentration. In other embodiments, the photomask set 200 may include photomasks used to define the deposition of semiconductor materials other than silicon, such as germanium, and / or other materials of the periodic table, such as Group III or Group V. Another photomask may be used to define metal contacts. Another photomask may be used to define metal traces. Some tiles involve the use of different levels of metal traces. In some such embodiments, the photomask set 200 may include a dedicated photomask for each metal trace level. 【0080】 In some embodiments, the wafer 11 is patterned in a step-and-repeat manner. As the wafer 11 is processed by the stepper machine, the pattern of the photomask is repeatedly exposed in a grid pattern across the entire surface of the wafer. This process involves stepping the wafer back and forth and side to side under the lens of the stepper, exposing the photomask at each step. As a result, the wafer 11 is patterned with multiple copies of the pattern defined by the photomask. This operation may be repeated for each photomask in the set (or for at least some photomasks). Thus, in some embodiments, the tiles are copies of a common template tile that are stitched together in a 1D or 2D array. Other embodiments include two template tiles such that each tile of the interposer is formed as either an instantiation of a first template tile or an instantiation of a second template tile. The tiles of the different templates may be arranged alternately in a checkerboard pattern, for example, such that each tile of the first type is adjacent only to a tile of the second type. Other arrays are also possible. 【0081】 In the example shown in Figure 1-2D, the wafer 11 is patterned with a grid of tiles 22. The tiles may share the patterns of one or more photomasks in set 200. For example, the tiles may share the patterns of the same waveguide photomask and / or the same metal trace photomask. In other embodiments, the tiles share the patterns of all photomasks in set 200. For example, the tiles may share the same optical waveguide pattern, the same n-doped pattern, the same p-doped pattern, the same contact pattern, the same metal trace pattern, and so on. 【0082】 In some embodiments, the entire surface of the wafer 11 is patterned using a photomask set 200. However, not all embodiments are limited to this, for a portion of the wafer 11 may be patterned using a first photomask set and the other portion of the wafer 11 may be patterned using a second photomask set. The first photomask set may correspond to a first reticle, and the second photomask set may correspond to a second reticle. The first and second types of reticles may be arranged alternately in a checkerboard pattern. 【0083】 Once patterned, wafer 11 may contain multiple photonic circuits. In one example, the wafer in Figure 1-2E is marked to obtain six photonic circuits from wafer 11. The photonic circuits are monolithically integrated with the wafer. This figure identifies a 1x1 photonic circuit having only one tile 22, a 2x2 photonic circuit having four tiles 22, a 2x3 photonic circuit having six tiles 22, and three 3x3 photonic circuits, each having nine tiles 22. Isolating the photonic circuits from the wafer involves dicing the wafer along the periphery of the desired photonic circuits. In this respect, the photonic circuits described herein can be considered as wafer-level architectures. Once diced, each optical photonic circuit forms an independent photonic interposer. One of the 3x3 photonic circuits of wafer 11 may be used as a photonic interposer in the example computing system in Figure 1-1. (See photonic interposer 20.) Figure 1-3A shows an exemplary tile 22. In this example, tile 22 is shaped as a rectangle (however, other shapes such as squares or other polygons are also possible). Thus, tile 22 borders four boundaries (boundaries 1, 2, 3, and 4). Boundary 1 is opposite boundary 2, and boundary 3 is opposite boundary 4. Boundary 1 is adjacent to boundaries 3 and 4, and boundary 2 is also adjacent to boundaries 3 and 4. Tile 22 includes an optical distribution network 104 coupled to waveguides 111, 112, 113, and 114. Waveguide 111 optically couples the optical distribution network 104 to boundary 1. Thus, optical signals coupled from the optical distribution network 104 to waveguide 111 can be transferred outside the tile by crossing boundary 111. Similarly, waveguide 112 optically couples the optical distribution network 104 to boundary line 2, waveguide 113 optically couples the optical distribution network 104 to boundary line 3, and waveguide 114 optically couples the optical distribution network 104 to boundary line 4. In some embodiments, the tile boundaries are defined based on photolithography shots (for example, the boundaries are defined by the boundaries of the photomasks used to manufacture the tiles). However, in other embodiments, one photolithography shot may define two or more tiles. For example, the photomask may be patterned with multiple adjacent instances of a template tile. In some such embodiments, the tile boundaries are defined where adjacent instances of the template tile intersect. 【0084】 An example in Figure 1-3A illustrates waveguides connecting the optical distribution network to each boundary line, but not all embodiments are arranged in this manner. In other embodiments, tile 22 may include two of these four waveguides, for example, waveguides 111 and 112, or waveguides 111 and 113. In yet another embodiment, tile 22 may include three of these four waveguides, for example, waveguides 111, 112, and 113. The optical distribution network 104 includes photonic components (e.g., photonic switches) for routing optical signals inside and outside tile 22. Furthermore, the optical distribution network 104 may include transmitters (providing an electrical-optical interface with electronic chips mounted on the tiles) and receivers (providing an optical-electrical interface with electronic chips mounted on the tiles). Examples of optical distribution networks are described in detail in the following sections. 【0085】 In some embodiments, the tile may include a photonic waveguide consisting of multiple layers. Just as a conductive trace consisting of multiple layers enhances the electrical signal routing capability of an electronic circuit, a waveguide consisting of multiple layers enhances the optical signal routing capability of the tile. In one example, one layer may consist of a silicon waveguide, and one or an additional layer may consist of a silicon nitride waveguide. The choice of material for each waveguide layer may be determined by the wavelength of light to be routed by the waveguide. For example, the silicon layer and the silicon nitride layer may be used to route infrared light in the telecommunications band at wavelengths around 1.3 μm or 1.5 μm. In some examples, the waveguide consisting of multiple layers may also include an aluminum nitride waveguide usable for routing visible light down to UV wavelengths, or an aluminum oxide waveguide usable for routing UV light. Each layer may be arranged in a configuration having an optical distribution network for routing signals between the waveguides of the layers, similar to the configuration illustrated in Figure 1-3A. 【0086】 The tile 22 may further include one or more out-of-plane couplers (not shown in Figure 1-3A). The out-of-plane couplers may be configured to emit light outside the xy-plane, for example, in a direction parallel to the Z-axis or at an angle to the Z-axis. The out-of-plane couplers may be further configured to capture light incident from outside the xy-plane. In some embodiments, the out-of-plane couplers enable optical communication between the tile 22 and a die located above and / or below the tile. The out-of-plane couplers may be implemented using any suitable optical components, such as optical gratings, lenses, and prisms. In some embodiments, the optical distribution network may be configured such that the same out-of-plane coupler enables optical communication both from the optical distribution network 104 to the die and from the die to the optical distribution network 104. In some embodiments, the out-of-plane couplers enable optical communication between the tile 22 and a fiber. 【0087】 The optical distribution network 104 may selectively couple any component of tile 22 to any other component of tile 22, as will be described in detail in the following section. For example, the optical distribution network 104 may allow light to pass between waveguide 111 and waveguide 112, and / or between waveguide 111 and waveguide 113, and / or between waveguide 113 and waveguide 114, and so on. This can be achieved by equipping the optical distribution network with controllable optical switches. 【0088】 The tile 22 may further include electrical connections 117 that can be positioned to provide electrical access from electronic chips mounted on the tile to the tile. For example, the electrical connections 117 may be in the form of bonds, bumps, vias, or contact pads that provide a landing surface for other types of vertical chip-to-chip interconnects. The electrical connections 117 can be coupled to transmitters, receivers, and switches of an optical distribution network, thereby providing electronic chips with electrical access to their photonic components. 【0089】 A photonic circuit may include multiple tiles connected together to form an optical network. Figure 1-3B illustrates an example of a 2x3 photonic circuit containing six tiles 22. This photonic circuit is obtained by dicing and separating a group of 2x3 tiles from a wafer 11 (see Figure 1-2E). The tiles 22 are arranged such that the waveguide 111 of one optical module aligns with the waveguide 112 of the optical module to its left, the waveguide 112 of one optical module aligns with the waveguide 111 of the optical module to its right, the waveguide 113 of one optical module aligns with the waveguide 114 of the optical module above it, and the waveguide 114 of one optical module aligns with the waveguide 113 of the optical module below it. As a result, the optical modules form an optical network. The optical distribution network 104 may route optical signals anywhere inside or outside the network. For example, suppose a processor is mounted on a tile located at the northwest corner of the photonic circuit, and memory is mounted on a tile located at the southeast corner of the photonic circuit. A read operation may involve reconfiguring the optical distribution network (e.g., by controlling an optical switch) to bring the processor into optical communication with the memory. For example, the optical communication path may be configured such that 1) the processor is coupled to an out-of-plane coupler on the tile on which the processor is mounted, 2) the out-of-plane coupler on that tile is coupled to a waveguide 112 on the same tile, 3) the waveguide 112 on that tile is coupled to a waveguide 111 on an adjacent tile (the top-center tile), 4) the waveguide 112 on the top-center tile is coupled to a waveguide 111 on the next adjacent tile (the northeast corner of the circuit), 5) the waveguide 114 on the tile located at the northeast corner is coupled to a waveguide 113 on the tile on which the memory is mounted, and 6) the waveguide 113 on the tile on which the memory is mounted is coupled to an out-of-plane coupler on the same photonic module. 【0090】 As described above, the waveguides of adjacent tiles are optically coupled to each other, allowing light to pass from one tile to the next photonic module. In some embodiments (although not all embodiments are limited to this particular embodiment, as will be detailed below), the ends of the waveguides may be physically connected. In other embodiments, there may be gaps between the waveguides. In this example, each waveguide has an end located at a distance from the boundary line. Thus, a gap is formed in the boundary region. Despite the gaps, the waveguides of adjacent tiles are still optically coupled to each other. In this case, light emitted from one end of one waveguide actually reaches the other end of the waveguide by free-space propagation. 【0091】 In some embodiments, the tiles 22 may be patterned according to a common metal trace photomask. As a result, the tiles share the same pattern of metal trace. In some embodiments, the tiles 22 are patterned according to multiple common photomasks. As a result, multiple levels of metal traces share the same pattern across different tiles. Some of the metal traces may be used to deliver power across the photonic circuit. For example, some of the metal traces may be arranged to form a power grid, as will be further detailed below. Figure 1-4A illustrates a 2x3 photonic circuit where each tile 22 shares the same pattern of metal trace. For illustrative purposes, only the metal traces are shown in this figure, but each tile further includes waveguides, one or more out-of-plane couplers, and an optical distribution network. In this example, there are two levels of metal traces. The metal traces at each level are fabricated using the same photomask across different tiles. The metal traces at metal trace level 1 extend horizontally, thereby electrically coupling tiles adjacent to each other in the horizontal direction. The metal traces at metal trace level 2 extend vertically, thereby electrically coupling tiles adjacent to each other in the vertical direction. Naturally, other arrangements are also possible. For example, in another embodiment, the metal traces at the same level may electrically couple one tile to all tiles adjacent to that tile. 【0092】 Metal traces are arranged to transmit electricity (e.g., signals and / or power) across tile boundaries. This may be achieved by patterning the metal traces to be continuous across tile boundaries. In this example, Level 1 metal traces are continuous across vertical boundaries, and Level 2 metal traces are continuous across horizontal boundaries. Metal traces of different levels may be connected to each other using vias. In some embodiments, tiles may share the same pattern of vias. In other words, the same via photomask may be used for each tile. In some embodiments, tiles may have a much larger number (tens to hundreds) of metal traces. Some of these metal traces may be arranged to be continuous across tiles, but in some embodiments, the majority of metal traces do not need to be patterned to be continuous across modules. In one example, some metal traces may be patterned so that they do not reach the edge of a group of tiles, as shown in Figure 1-4B. This creates a moisture barrier between the die lane and the metal. Furthermore, these metal traces for transmitting signals and / or power may be connected to through-silicon vias (TSVs) that connect to other chips located on the substrate and / or tiles. In some embodiments, the metal traces may also be connected to transistor elements that can act as electronic switches, amplifiers, or TX / RX components. 【0093】 Vita. Optical Distribution Network This section describes an architecture for interconnecting photonic interposer tiles to enable high bandwidth, low latency, and high resource utilization. The interconnection may be static or programmable. 【0094】 A. Static connection Figure 2-1A shows an example where tiles of a photonic interposer are interconnected using static connections. This example shows an interposer having four tiles arranged in one dimension. Each tile has a transmitter (TX) and a receiver (RX). The transmitter may include (or be coupled to) a light source and an optical modulator. The optical modulator may be configured to encode light using information provided by the electronic chip to which the tile is connected. Each receiver may include a photodetector that converts the signal provided by the transmitter into electricity. In this arrangement, waveguides couple the TX of one tile to the RX of the adjacent tile. This arrangement is called "one hop right" in that each waveguide reaches the RX immediately to the right of the TX. 【0095】 Figure 2-1B shows another example where photonic interposer tiles are interconnected using static connections. In this example, waveguides connect the TX of one tile to the RX of a second adjacent tile. This arrangement is called "two-hop right," in that each waveguide reaches the RX two steps to the right of the TX. 【0096】 Figure 2-1C shows yet another example where photonic interposer tiles are interconnected using static connections. In this example, waveguides connect the TX of one tile to the RX of a third adjacent tile. This arrangement is called "three hops right," in that each waveguide reaches the RX three steps to the right of the TX. 【0097】 The configurations in Figures 2-1D, 2-1E, and 2-1F are similar to those in Figures 2-1A, 2-1B, and 2-1C, respectively, but with the addition of optical fibers to close the loops. The use of fibers increases flexibility by allowing information to flow in a closed-loop manner. In Figure 2-1D, the fibers loop around the photonic interposer by coupling the TX of tile 4 with the RX of tile 1. In Figure 2-1E, the first fiber couples the TX of tile 4 with the RX of tile 2, and the second fiber couples the TX of tile 3 with the RX of tile 1. In Figure 2-1F, the first fiber couples the TX of tile 4 with the RX of tile 3, the second fiber couples the TX of tile 3 with the RX of tile 2, and the third fiber couples the TX of tile 2 with the RX of tile 1. 【0098】 The configurations in Figures 2-1D, 2-1E, and 2-1F have one drawback: TX can only transmit data in one direction (to the right in these examples), and RX can only receive data in the opposite direction (to the left in these examples). Therefore, such networks cannot maintain a bidirectional link between two pairs of TX and RX modules. To implement a bidirectional link, a complementary network with waveguides cascaded in opposite directions can be included. Examples are shown in Figures 2-1G and 2-1H (implementing a one-hop and two-hop configuration, respectively). In each configuration, bidirectional links are provided. TX1, TX2, TX3, and TX4 transmit data in one direction, and TX5, TX6, TX7, and TX8 transmit data in the opposite direction. Similarly, RX1, RX2, RX3, and RX4 receive data from one direction, and RX5, RX6, RX7, and RX8 receive data from the opposite direction. Tile 1 includes TX1, RX1, TX5, and RX5. Tile 2 includes TX2, RX2, TX6, and RX6. Tile 3 includes TX3, RX3, TX7, and RX7. Tile 4 includes TX4, RX4, TX8, and RX8. 【0099】 However, such an arrangement does not provide a bidirectional link between two pairs of adjacent TX and RX. In practice, it is desirable for the first tile to transmit to the second tile and the second tile to reply to the first tile. To implement a bidirectional link between two pairs of TX and RX modules, it is proposed to implement a "swap" between the TX modules. This is shown in Figure 2-1I. The swap allows a TX module to transmit to an RX connected in a complementary loop. This example shows a two-hop double-loop architecture with swapped TX modules. As a result, TX1 can transmit to RX7, and TX7 can reply to RX1, closing the bidirectional link. 【0100】 B. Programmable connections The static connections described above do not allow for reconfiguration based on network needs, and the network topology is fixed. However, allowing the network to dynamically reconfigure itself according to user needs can be useful in certain applications. Therefore, some embodiments relate to programmable connections between tiles of a photonic interposer. The arrangement in Figure 2-2A is similar to the arrangement in Figure 2-1F in that both arrangements implement a three-hop architecture. However, instead of having static connections, the arrangement in Figure 2-2A includes waveguide buses (four in this example, equal to the number of tiles). Each bus can couple any TX to any RX. Each transmitter and each receiver can selectively connect to the bus via switches. The connection points are identified as “nodes” in Figure 2-2A. When a transmitter activates a switch, the transmitter can transmit data using the bus waveguide. Similarly, when a receiver activates a switch, the receiver can listen for data from the bus waveguide. Three fibers are used to close the loop. In this example, the first bus connects TX1 to RX4, the second bus connects TX2 to RX1 (along with the first fiber), the third bus connects TX3 to RX2 (along with the second fiber), and the fourth bus connects TX4 to RX3 (along with the third fiber). The network can be reconfigured using switches to change the number of hops from 3 to 1 or 2. 【0101】 To implement bidirectional links, a dual-loop architecture with swapped TXs (similar to the architecture in Figure 2-1I) can be used, as shown in Figure 2-2B. However, unlike the architecture in Figure 2-1I, this architecture includes buses and nodes, allowing for dynamic network reconfiguration. 【0102】 Figure 2-2C shows another photonic interposer with programmable connections according to several embodiments. This example includes four tiles, but any number of tiles are possible and arranged in 1D or 2D. Each tile includes a transceiver 100 and a programmable photonic interconnect 120. Each transceiver includes one or more instances of a transceiver cell 110. The transceiver cell shown in Figure 2-2C includes a laser 101, which may be mounted on the same package as the photonic interposer or outside the package. In this example, the laser 101 emits light at eight distinct wavelengths, but a different number of wavelengths is also possible. Thus, the architecture of Figure 2-2C can increase data throughput using wavelength division multiplexing (WDM). The TX bus 102 receives light from the laser and is optically coupled to a plurality of modulators 104. Each modulator is coupled to its own TX module, which may include a digital-to-analog converter and a modulator driver. The PLL synchronizes the operation of the TX module. The TX module can then be coupled to an electronic chip mounted on the photonic interposer corresponding to the tiles. In this example, each modulator 104, implemented as a ring (or disk) resonator, is tuned to a different emission wavelength (λ0...λ7) of the laser 101. Thus, each modulator is configured to provide data to a different WDM channel. On the receiver side, the RX module is coupled to a drop filter 108, implemented as a ring (or disk) resonator in this example. Each drop filter is tuned to a different emission wavelength (λ0...λ7) of the laser 101. As a result, each drop filter captures data from the RX bus 106 on a specific WDM channel. The RX module may also be coupled to an electronic chip that includes a photodetector, a transimpedance amplifier, and an analog-to-digital converter. 【0103】 The programmable photonic interconnects enable programmable communication between tiles (and consequently between electronic chips mounted on the photonic interposer). The programmable interconnects form a grid of switchable intersections connected to each other by waveguides, as shown in Figure 2-2D, with the waveguides arranged to form row buses and column buses. The tiles may further include electrical connections 117, which can be arranged to provide electrical access from electronic chips mounted on the tiles to the tiles. For example, the electrical connections 117 may be in the form of bonds, bumps, vias, or contact pads providing landing surfaces for other types of vertical chip-to-chip interconnects. The electrical connections 117 can be coupled to a transceiver 100. 【0104】 In the example shown in Figure 2-2C, the programmable interconnect is programmed to enable communication between each tile and all other tiles. In this figure, a first optical path is formed between tile 1 and tile 4, a second optical path is formed between tile 1 and tile 3, and a third optical path is formed between tile 1 and tile 2. Each optical path can support multiple wavelengths. 【0105】 Figure 2-2E shows exemplary implementations of the programmable photonic interconnect 120 according to several embodiments. This programmable photonic interconnect includes active couplers 126 coupled to one another via waveguides. As further shown in Figure 2-2F (an example of an active coupler is shown), each active coupler may provide a one-to-multi-waveguide coupling configuration. The active couplers can operate in both directions. When light propagates from a single waveguide, the active coupler may select one of several waveguides for the propagation of the light, thereby performing a switching operation. Possible implementations of the active coupler 126 include cascaded Mach-Zehnder interferometers (MZI), as further shown in Figure 2-2F (see MZI127 and MZI128). 【0106】 Referring again to Figure 2-2E, the central waveguides of the active couplers are coupled to each other to form a waveguide crossover 127. The waveguide crossover 127 presents a system-level challenge in that it introduces insertion loss and crosstalk. Below is an example of a waveguide crossover developed by the inventors that results in low insertion loss and low crosstalk. 【0107】 The waveguide bus shown in Figure 2-2D may be bidirectional in some embodiments. In some such embodiments, instead of having a transmit-only bus and a receive-only bus, tiles may transmit and receive using the same bus waveguide. Additionally or alternatively, the transmitter may determine which direction of the bus data should be transmitted, and the receiver may determine which direction of the bus data should be received. An example of such an implementation by some embodiments is shown in Figure 2-3A. On the TX side, the tile includes coupler 131 arranged to form an optical tree. The coupler may be controllable (similar to the active coupler in Figure 2-2F). Each output branch of the tree is coupled to the bus via couplers 133, 134, and 135. Coupler 133 selects one input and one output. Selecting the waveguide provided by the TX as the input allows coupler 133 to put the tile into transmit mode. By selecting one of the outputs, the TX can communicate along the bus from right to left or left to right, thus enabling bidirectional communication. Couplers 134 and 135 determine whether the bus is in append / drop mode (append when transmitting, drop when receiving) or through mode (bypass tile 1). 【0108】 On the RX side, the tile also includes coupler 132, which is arranged to form an optical tree. Each output branch of the tree is coupled to the bus via couplers 133, 134, and 135, allowing selection of right-to-left or left-to-right direction during transmission. In this example, couplers 134 and 135 are implemented as 1x2 couplers and coupler 133 is implemented as a 2x2 coupler, but other configurations are possible. The architecture in Figure 2-3B is similar to the architecture in Figure 2-3A in that both architectures use coupler 133. However, the architecture in Figure 2-3B replaces couplers 133 and 135 with a 2x2 coupler (137). 【0109】 Figures 2-4A and 2-4B illustrate additional mechanisms that enable bidirectional propagation along the bus. On the TX side (Figure 2-4A), TX is coupled to the MZI, which is then coupled to a resonant add-on filter. Depending on which output of the MZI is selected, either the clockwise or counterclockwise mode of the resonant filter is excited. As a result, transmission on the bus occurs from left to right or right to left. On the RX side (Figure 2-4B), RX is coupled to the MZI, which is coupled to a resonant drop-off filter. Depending on which input of the MZI is selected, either the clockwise or counterclockwise mode of the resonant filter is selected. As a result, RX selects either a left-to-right or right-to-left bus mode. 【0110】 Figure 2-5 shows an example of a waveguide crossover that may be used in several embodiments (e.g., Figure 2-2E). This implementation includes three waveguide layers (140, 141, and 142). The waveguide layers may be made of, for example, silicon or silicon nitride. In one example, waveguide layer 140 is made of silicon, and waveguide layers 141 and 142 are made of silicon nitride. The waveguide crossover is designed to couple mode A from layer 140 to layer 141, then to layer 142, then back from layer 142 to layer 141, and back to layer 140 again. A taper can be used to expand and contract mode A vertically. By pushing mode A out of the plane of layer 140, the overlap between mode A and mode B is limited, and therefore crosstalk is reduced. The inventors understand that having a three-layer configuration as described herein is advantageous over a two-layer configuration in that it can provide the same low insertion loss performance, but allows for negligible crosstalk between layers 140 and 142. 【0111】 Therefore, some embodiments relate to a photonic interposer comprising a plurality of photonic tiles (e.g., tiles 1-4 in Figure 2-2C) which are instances of a template photonic tile. Each of the plurality of photonic tiles comprises a transceiver (100) comprising a transmitter and a receiver. An electrical connection (117) coupled to the transceiver is configured to enable electrical communication between the transceiver and the electronic chip when the electronic chip is mounted on the photonic interposer corresponding to the photonic tile (e.g., as shown in Figure 1-1). The optical distribution network comprises a first set of bus waveguides optically coupled to the transceiver (e.g., row bus in Figure 2-2D), a second set of bus waveguides (e.g., column bus in Figure 2-2D), and a plurality of programmable interconnects (120). Each programmable interconnect is configured to selectively optically communicate one bus waveguide of the first set of bus waveguides with one bus waveguide of the second set of bus waveguides. Each programmable interconnect includes a waveguide crossover (127) and an active coupler (126). 【0112】 In some embodiments, the transceiver comprises a plurality of modulators (104) coupled to a first bus waveguide of a first set of bus waveguides and tuned to different wavelengths relative to one another, as shown, for example, in Figure 2-2C. In addition, a plurality of drop filters (108) coupled to a second bus waveguide of the first set of bus waveguides are tuned to different wavelengths relative to one another. In some embodiments, the plurality of modulators are resonant modulators, and the plurality of drop filters are resonant drop filters. 【0113】 In some embodiments, the transmitter is configured to transmit data in either a first or second direction along a first bus waveguide of a first set of bus waveguides, for example, as shown in Figures 2-3A, 2-3B, and 2-4A. 【0114】 In some embodiments, each of the photonic tiles further comprises a 2x2 coupler (133) that couples a transceiver to a first bus waveguide of a first set of bus waveguides. The 2x2 coupler may have first, second, third, and fourth terminals. The first terminal is coupled to the output of the transmitter. The second terminal is coupled to the input of the receiver. The third and fourth terminals are coupled to the first bus waveguide of the first set of bus waveguides. 【0115】 In some embodiments, each of the multiple photonic tiles further comprises an interferometer (e.g., MZI in Figure 2-4A) having an input and first and second outputs, and a resonant filter. A transmitter is coupled to the input of the interferometer, and the first and second outputs of the interferometer are coupled to the resonant filter. The resonant filter is coupled to the first bus waveguide of a first set of bus waveguides. In addition, in some embodiments, each of the multiple photonic tiles further comprises an interferometer (e.g., MZI in Figure 2-4B) having an output and first and second inputs, and a resonant filter. The resonant filter is coupled to the first bus waveguide of a first set of bus waveguides. The first and second inputs of the interferometer are coupled to the resonant filter. A receiver is coupled to the output of the interferometer. 【0116】 In some embodiments, the waveguide crossover comprises a first waveguide patterned on a first waveguide layer (140), a second waveguide patterned on a second waveguide layer (141), and a third waveguide layer patterned on a third waveguide layer (142). The second waveguide layer lies between the first and third waveguide layers, with the first waveguide evanescently coupled to the second waveguide, and the second waveguide evanescently coupled to the third waveguide. In some embodiments, the first waveguide layer is made of silicon, and both the second and third waveguide layers are made of silicon nitride. 【0117】 In some embodiments, the active coupler comprises a first terminal coupled to a first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide crossover, as shown, for example, in Figure 2-2E. 【0118】 In some embodiments, the active coupler comprises first and second Mach-Zehnder interferometers (MZI), as shown, for example, in Figure 2-2F. The first terminal corresponds to the first output of the first MZI (128), the second terminal corresponds to the second output of the first MZI, and the third terminal corresponds to the output of the second MZI (127). 【0119】 In some embodiments, the bus waveguides of a second set of bus waveguides traverse multiple photonic tiles (e.g., tiles 1-4 in Figure 2-2C). Figure 2-6A shows another interconnection architecture. The advantage of this architecture over the architecture in Figure 2-2C is that waveguide crossings are eliminated. The disadvantage is that transceiver utilization is insufficient. In this architecture, each tile contains multiple transceivers 100. Each transceiver is coupled to one of the buses (151, 152, 153, 154, and 155). These buses cross the boundaries between tiles and do not intersect with each other. In this figure, bus 151 enables communication between tile 1 and tile 2, and between tile 3 and tile 4. Bus 152 enables communication between tile 1 and tile 3. Bus 153 enables communication between tile 2 and tile 4. Bus 154 enables communication between tile 1 and tile 4. Bus 155 enables communication between tile 2 and tile 3. Transceiver-bus connections can be programmed according to the network requirements. Coupler 156 is used to selectively couple a transceiver to or from a bus. An exemplary implementation of coupler 156 shown in Figure 2-6B includes an MZI arranged in a closed-loop configuration. The MZI enables communication in two directions, whether transmitting or receiving. 【0120】 The utilization rate in the architecture of Figure 2-6A can be increased by including additional buses. For each row of transceivers spanning tiles 1-4, there are two buses (e.g., 151A and 151B) to which the transceivers are switchably coupled. One bus can support left-to-right communication, and the other can support right-to-left communication, thereby closing the loop. However, in some embodiments, both buses may support communication in the same direction. In this figure, bus 151A causes tile 1 to communicate with tile 4, and bus 151B causes tile 1 to communicate with tile 2, tile 2 to communicate with tile 3, and tile 3 to communicate with tile 4. Coupler 156 can be implemented, for example, as shown in Figure 2-6B. One drawback of this configuration is that the links between tiles at both ends of a row (e.g., tile 1 and tile 4) are longer than the other links, resulting in greater optical loss. 【0121】 The architecture in Figure 2-6D addresses this problem by connecting remote tiles using optical fiber. In this architecture, the tiles are arranged in two 1x2 tile blocks. The first block contains tiles 1 and 2, and the second block contains tiles 3 and 4. Each tile contains multiple transceivers 100. Tiles 1 and 2 communicate with each other using buses 161A and 161B. Having two buses enables bidirectional communication. For example, the TX of tile 1 can send data to the RX of tile 2 using bus 161A, and the TX of tile 2 can send data to the RX of tile 1 using bus 161B. Similarly, tiles 3 and 4 communicate with each other using buses 164A and 164B. In one example, the TX of tile 3 can send data to the RX of tile 4 using bus 164A, and the TX of tile 4 can send data to the RX of tile 3 using bus 164B. Therefore, buses 161A, 161B, 164A, and 164B can be considered intrablock buses. Alternatively, buses 162A, 162B, 163A, and 164B may be considered interblock buses. Bus 162A connects to bus 163B via fibers 166A and 168A. Similarly, bus 162B connects to bus 163A via fibers 166B and 168B. 【0122】 Compared to the architecture in Figure 2-6C, the architecture in Figure 2-6D shortens the on-chip path connecting tile 1 and tile 4. Part of the on-chip path connecting tile 1 and tile 4 is replaced with fiber. The losses introduced by the fiber can be lower than the losses introduced by the integrated waveguide, thus reducing the overall loss. 【0123】 Accordingly, some embodiments relate to a photonic interposer comprising a plurality of photonic tiles (e.g., tiles 1-4 in Figure 2-6D) which are instances of a template photonic tile. Each of the plurality of photonic tiles comprises a first transceiver (100). An electrical connection (not shown in Figure 2-6D) coupled to the first transceiver is configured to enable electrical communication between the first transceiver and the electronic chip when the electronic chip is mounted on the photonic interposer corresponding to the photonic tile, for example, as shown in Figure 1-1. First and second bus waveguides (162A and 162B) traverse the first and second photonic tiles, respectively, and third and fourth bus waveguides (163A and 163B) traverse the third and fourth photonic tiles, respectively. The first fiber (166A), the first bus waveguide (162A), and the fourth bus waveguide (163B) enable optical communication between the first transceiver of the first photonic tile and the first transceiver of the fourth photonic tile. The second fiber (166B), the second bus waveguide (162B), and the third bus waveguide (163A) enable optical communication between the first transceiver of the second photonic tile and the first transceiver of the third photonic tile. 【0124】 In some embodiments, each of a plurality of photonic tiles further comprises a second transceiver. The second transceiver of the first photonic tile communicates optically with the second transceiver of the second photonic tile (e.g., via buses 161A and / or 161B). Similarly, the second transceiver of the third photonic tile can communicate optically with the second transceiver of the fourth photonic tile (e.g., via buses 164A and / or 164B). 【0125】 In some embodiments, the interposer further comprises a third fiber (168A). The third fiber (168A), the first bus waveguide (162A), and the fourth bus waveguide (163B) further enable the first transceiver of the first photonic tile to communicate optically with the first transceiver of the fourth photonic tile. The first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile can form a closed loop. The interposer may further comprise a fourth fiber (168B). The fourth fiber (168B), the second bus waveguide (162B), and the third bus waveguide (163A) further enable the first transceiver of the second photonic tile to communicate optically with the first transceiver of the third photonic tile. The second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile can also form a closed loop. 【0126】 C. Wavelength-based tile identification The architecture described in relation to Figures 2-1A to 2-6D utilizes WDM to increase the total bandwidth of each tile-to-tile optical link. In other embodiments, wavelengths can be used to uniquely identify each tile. In a 4-tile architecture, for example, wavelength λ0 can uniquely identify tile 1, wavelength λ1 can uniquely identify tile 2, wavelength λ2 can uniquely identify tile 3, and wavelength λ3 can uniquely identify tile 4. Thus, the receiver can identify the source of data collected from the bus simply by determining the wavelength supporting the data. An example is shown in Figure 2-7A. This architecture includes four tiles. A first set of transceivers 100 is connected by bus 171, a second set of transceivers 100 is connected by bus 172, and a third set of transceivers 100 is connected by bus 173. Each transceiver is assigned a pair of digits (x and y). The first digit (x) identifies the transmit wavelength of the transceiver's transmitter. The second digit (2) identifies the wavelength that the transceiver's receiver is configured to read. Note that the x-number for all transceivers on a given tile is the same. This allows the system to uniquely identify the transmitter by wavelength. 【0127】 In the example in Figure 2-7B, each tile in a row has a unique transmission wavelength. However, wavelengths are reused across different rows. The first row includes rows 1-4, and the second row includes tiles 5-8. In this example, wavelength λ0 can uniquely identify tiles 1 and 5, wavelength λ1 can uniquely identify tiles 2 and 6, wavelength λ2 can uniquely identify tiles 3 and 7, and wavelength λ3 can uniquely identify tiles 4 and 8. Bus set 181 (containing three buses) enables communication between tiles in the first row (tiles 1-4). Bus set 183 (containing three buses) enables communication between tiles in the second row (tiles 5-8). Bus set 182 (containing eight buses) enables communication between each tile in the first row and each tile in the second row. Each tile includes transmitters and receivers, which are represented herein in the form of resonant modulators (TX) and resonant drop filters (RX). The wavelengths in parentheses indicate the transmission wavelength (for TX) and the drop wavelength of the resonant drop filter (for RX). 【0128】 The architecture in Figure 2-7C is similar to the architecture in Figure 2-7A, but further includes a programmable optical loopback 190 that enables a unidirectional traffic lane. The exemplary programmable optical loopback shown in Figure 2-7D is implemented using MZI. 【0129】 IV. D2D Interface The photonic interposers described herein can be used to interconnect application-specific integrated circuits (ASICs) in ways that were impractical with conventional interfaces (e.g., too expensive or energy-inefficient). In recent years, new die-to-die (D2D) interface standards have emerged that enable chiplets from different sources to communicate with each other. D2D interfaces utilize very short channels to connect two dies within a common package to achieve power efficiency and extremely high bandwidth efficiency, beyond what conventional inter-chip interfaces can achieve. A D2D interface can be seen as being divided into a physical layer (PHY), a link layer, and a transaction layer. The PHY layer can be implemented using a high-speed SerDes architecture for parallel-to-serial and serial-to-parallel data conversion. The main role of SerDes is to minimize the number of I / O interconnects. 【0130】 With electronic interposers and silicon bridges now becoming mainstream products, the industry is focusing heavily on advanced packaging. Examples of D2D interfaces include, among others, the Advanced Interface Bus (AIB), Universal Chiplet Interconnect Express (UCIe), and Low-voltage-In-Package-INterCONnect (LIPINCON). Bunch of Wires (BoW) is a relatively new D2D interface designed to standardize some of the interconnects that are expected to become more important in future generations of chips. These interfaces are designed for high-bandwidth communication between electronic ASICs located relatively close together, for example, a few millimeters apart. 【0131】 The inventors recognize and understand that the relatively close proximity set by D2D interfaces imposes practical limitations on the types of computing architectures that can be achieved using these interfaces. The maximum D2D distance set by these interfaces (at most a few millimeters) ensures high bandwidth and reliability, given the constraints of electrical interconnects. The photonic interposers described herein can extend the applicability of conventional D2D interfaces to ASIC distances greater than those possible with conventional electronic interposers. For example, the use of a photonic interposer may enable AIB-based communication between a pair of ASICs separated by, for example, more than 1 cm, 1.5 cm, 2.5 cm, 3 cm, 5 cm, and 10 cm. Similarly, the use of a photonic interposer may enable UCIe-based communication between a pair of ASICs separated by, for example, more than 1 cm, 1.5 cm, 2.5 cm, 3 cm, 5 cm, and 10 cm. A SerDes interface connected to a photonic interposer can multiplex wires into a single photonic link using a single photonic channel, whether it be a spatial channel (waveguide or fiber), a wavelength channel, or a polarization channel. In some embodiments, the photonic channel can support speeds from 56 Gbps using non-return to zero (NRZ) to 112 Gbps using PAM4 modulation. 【0132】 Figure 2-8A shows an ASIC with an AIB interface. More specifically, the ASIC includes a “Northwest” AIB unit, a “Southwest” AIB unit, a “Southeast” AIB unit, and a “Northeast” AIB unit. Each AIB contains 24 channels (although other numbers of channels are also possible). Figure 2-8B shows how the AIB interface can enable connection between two ASICs (ASIC0 and ASIC1) using a photonic interposer of the type described herein. The transmitter port in ASIC0 supports 128 wires, each wire supporting 1.5 Gbps to 2.5 Gbps (e.g., 2 Gbps). In an 8:1 SerDes, signals from eight wires can be multiplexed to produce 12 Gbps to 20 Gbps (e.g., 16 Gbps). In some embodiments, the SerDes may be formed directly on the photonic interposer (e.g., using transistors in an SOI wafer hosting the photonic interposer). A modulator formed within the photonic interposer converts the data obtained from SerDes into an optical signal that is transmitted using a waveguide formed on the interposer or fiber. On the receiver side, a photodetector receives the signal, SerDes performs demultiplexing, and the wire provides the data to ASIC1 via the AIB receiver port. 【0133】 Figure 2-8C shows a photonic interposer 20 hosting 16 ASICs having an AIB interface. Each ASIC may be mounted on a tile of the photonic interposer, for example, in an arrangement similar to that shown in Figure 1-1. An external laser module couples light to the interposer using a lattice coupler, although edge coupling is also possible. Waveguides formed in the interposer and / or fiber support communication between ASICs via the AIB interface. To support communication between ASICs, either static or programmable photonic interconnects described herein can be used. Note that the AIB interface described in relation to Figures 2-8A to 2-8C may be replaced with other D2D interfaces, including, for example, UCIe. 【0134】 Figure 2-9A shows a pair of ASICs (ASIC0 and ASIC1) communicating with each of the interposer's tiles (tile 0 and tile 1). In this example, a BoW interface is used. Communication takes place via waveguides formed within the photonic interposer, although in other embodiments, fibers may be used. In some embodiments, to reduce the number of waveguides crossing the tile boundaries, signals may be multiplexed within a single waveguide or fiber using WDM and / or polarization diversity. In the example in Figure 2-9B, one polarization is used in one transmission direction and the other polarization is used in the opposite direction. 【0135】 The photonic interposers described herein enable several types of computer architectures, including those shown in Figures 2-10A, 2-10B, 2-10C, and 2-10D. In the example of Figure 2-10A, the photonic interposer 20 hosts 16 ASICs. Of these, only one (ASIC0) interfaces with components outside the interposer 20 using optical fiber. The ASICs communicate with each other using one of the interconnects described herein. In the example of Figure 2-10B, fiber is used to close a loop. As a result, a ring network architecture can be formed. This architecture is particularly suitable for applications involving pipeline operation using multiple ASICs. In the example of Figure 2-10C, each ASIC communicates with its neighbors, and further links are formed to enable communication between ASICs located at opposite ends of a column or row. This enables a 2D hypertroid architecture. Finally, in the example of Figure 2-10D, all ASICs communicate with all other ASICs to form an all-to-all architecture. This architecture is particularly well-suited for smaller layer sizes, parallel batch processing, sequential graph processing, and HPC / AI clusters where multi-tenancy is desired. 【0136】 The inventors understand that a greater number of hops (with respect to photonic tiles) requires longer photonic paths and / or more photonic switches / crossovers. This can lead to greater optical loss and crosstalk. The topology in Figure 2-10A, i.e., the all-to-all topology, represents the baseline topology. The topologies in Figures 2-10B to 2-10D are achieved by reducing the number of hops a particular optical link takes compared to the topology in Figure 2-10A. Therefore, the optical loss of links in the topologies of Figures 2-10B to 2-10D is lower than the optical loss of links shown in Figure 2-10A. For efficiency reasons, the laser power / current can be reduced to reduce the amount of redundant light used for each optical link. 【0137】 Additional topologies are possible where the hop count of a particular TX / RX link is higher in the reconfigured topology than in the baseline topology. In this case, that particular optical link may require higher laser power (to compensate for higher loss or crosstalk) to achieve the same performance (e.g., baud and BER). Higher laser power can be achieved without increasing the overall system laser power by routing additional power to that link from an optical link with a reduced hop count, for example. Otherwise, it may be necessary to add an additional laser module or increase the output of a laser module. Another solution is to use a different communication protocol that is slower, has fewer bits (e.g., going from PAM-4 to NRZ, or from QAM-16 to QAM-4), or accepts a higher bit / symbol error rate, which can be improved by using error correction codes. 【0138】 VI. Clock Distribution The inventors recognize and understand that using a single global clock to synchronize the entire photonic interposer and the electronic chips connected to it is impractical. This is partly because the global clock distribution scheme is complex and requires considerable power to operate. 【0139】 In some embodiments, clock and data recovery (CDR) may be performed by generating a local clock within each tile. CDR recovery may be implemented for each TX / RX pair, where the optical communication channel traverses the boundary between one tile and another. CDR may be performed in some embodiments using a plesiochronous method. Alternatively, CDR may be performed using a mesochronous method in some embodiments. Both methods are described below. 【0140】 A. Plesiochronous method In a plesiochronous scheme, the clock may be transmitted within the same optical channel on which the data is transmitted. Therefore, the same TX and RX circuits are used to transmit / receive both data and clock. This can be achieved by operating at a bandwidth slightly higher than what would be needed to transmit data alone, taking into account CDR overhead. Several protocols can be used, including 8b / 10b, 64b / 66b, 128b / 130b, or 256b / 257b protocols. Generally, the Xb / Yb protocol achieves DC balancing by converting X bits of data into a Y-bit string, providing sufficient state changes for clock recovery and data alignment. An example of a DC-balanced data string is that the difference between the count of 1s and the count of 0s in a string of at least 20 bits must not exceed 2, and / or the number of consecutive 1s or 0s (in a row) must be 5 or less. DC balancing can be implemented in some embodiments using a linear feedback shift register. Clock recovery implemented according to these methods depends on data transitions (e.g., rising and / or falling edges). 【0141】 The plesiochronous scheme described herein relies on separate local oscillators (LOs), one LO located on the transmitting side of the channel and the other on the receiving side. Having separate LOs can result in clock drift. In some embodiments, clock drift may be compensated for using an elastic first-input first-output (FIFO) scheme, where the FIFO depth is established by the packet length in parts per million (PPM). 【0142】 Figure 3-1 is a block diagram showing a plesiochronous clock distribution scheme according to several embodiments. In this example, the data path includes communication from a photonic transmitter (TX) 301 located on tile 1 to a photonic receiver (RX) 203 located on tile 2. Inter-tile routing can be performed using any of the architectures described above. The optical communication channel 303 (implemented as a bus waveguide of the photonic interposer or as a fiber) supports data using the Xb / Yb protocol. The system includes a local oscillator (LO) 310 on the RX side and an LO 316 on the RX side. Each LO may include a dedicated crystal, or alternatively, the LOs may be supplied by a common crystal. Optionally, a PLL can be used to multiply the frequency of LO 310 by a predetermined coefficient, thereby achieving a higher clock frequency. The system further includes a transmitting Xb / Yb encoder 312 and a corresponding receiving Xb / Yb decoder 314. 【0143】 B. Mesochronous method In a mesochronous system, the clock is transmitted using a separate optical channel for the data. Having a separate optical channel may involve a separate propagation medium (e.g., a separate waveguide or fiber), or the same propagation medium but with a different wavelength or polarization. 【0144】 Figure 3-2 is a block diagram showing a mesochronous clock distribution scheme according to several embodiments. As in the previous example, the data path includes communication from a photonic transmitter (TX) 301 located on tile 1 to a photonic receiver (RX) 203 located on tile 2. However, the clock is transmitted using channel 352 and the data is transmitted using channel 350. The channels can represent distinct wavelengths or distinct polarizations in the physical propagation medium or common medium. In this scheme, the transmitter includes an LO 310, but the receiver does not have a separate LO. Instead, a PLL 354 recovers the clock based on the signal transmitted via clock channel 352. Optionally, a PLL 311 can be used to multiply the frequency of LO 310 by a predetermined coefficient, thereby achieving a higher clock frequency. 【0145】 VII. Equalization The inventors have developed techniques for improving the data throughput of photonic interposers with analog and / or digital equalization. Equalization improves data throughput by reducing inter-symbol interference (ISI), and consequently by reducing the bit error rate (BER). Equalization can be performed on the transmitter side of a channel, on the receiver side of a channel (or both). Equalization can amplify high-frequency components, enabling lower BER operation. Several types of equalization techniques can be used, including pre-emphasis feedforward equalization (FFE), continuous-time linear equalization (CTLE), and discrete feedback equalization (DFE). Photonic interposers utilizing the equalization techniques described herein can be fast enough to support clock frequencies exceeding 10 GHz, 15 GHz, or even 25 GHz, representing a substantial improvement over conventional processors. 【0146】 Figure 3-3A is a block diagram showing a portion of a photonic interposer configured to perform equalization. On the transmitting side, FFE unit 360 performs pre-emphasis and / or de-emphasis. On the receiving side, unit 362 performs DFE and / or CTLE. In some embodiments, the system may decide whether to perform equalization (FFE, DFE, or CTLE) depending on whether the communication between tile 1 and tile 2 occurs within a common photonic interposer or extends to two separate photonic interposers. Alternatively, the system may decide whether to perform equalization depending on whether the communication between tile 1 and tile 2 is performed using a bus waveguide or using fiber. 【0147】 In addition to deciding whether to apply equalization, in some embodiments, the characteristics of the equalizer may be adaptively modified depending on the nature of the channel. For example, the system may modify the S of the channel. 11 and / or S 21 The parameters can be determined, and based on that information, the number of taps in the DFE / CTLE unit 362 can be adjusted. Figure 3-3B is a block diagram showing an example of an adaptive equalizer. The ADC 370, located at the ends of the channel, digitizes the channel output by generating state samples y[n], y[n-1], y[n-2], etc. The DFE / CTLE unit 362 generates the output w[n] by calculating a linear combination of the state samples y[n], y[n-1], y[n-2], etc. The linear combination can be expressed as follows: 【0148】 【number】 【0149】 Here, c iis a coefficient (real or complex) representing the channel response. Here, M determines how many previous state samples y[n] are used to perform the equalization. M is the number of taps in the equalizer. If M is a finite number, the digital equalizer 400 implements a finite impulse response (FIR) filter. However, in other embodiments, the digital equalizer 400 may implement an infinite impulse response (IIR) filter. Each state sample y[ni] corresponds to a digitization of the amplitude of the analog signal in the past (if i>0) or present (if i=0), and w[n] corresponds to the calculated steady-state output value for the current set of digital inputs. In the example in Figure 3-3B, the DFE / CTLE unit 362 includes multiple registers 372, multiple digital multipliers 374, and a digital adder 376. Each register 372 records a state sample (y) at a different time. For example, one register may record y[n-1], and another register may record y[n-2], and so on. The registers allow the equalizer to store historical state samples. Digital multiplier 374 multiplies the state samples by the corresponding coefficients. One of the digital multipliers may, for example, multiply the coefficient c1 by the state sample y[n-1]. Digital adder 376 adds the results of the digital multiplications together. As a result, the output w[n] represents a linear combination of the historical state samples. 【0150】 The number M, representing the number of taps, can be dynamically adjusted during runtime. This means that instead of transmitting known signals to analyze the channel characteristics, the system adjusts the number of taps based on the payload itself (the data transmitted from TX to RX that carries the actual information). Adjusting the number of taps involves changing the number of registers and digital multipliers involved in equalization. Furthermore, the coefficient c i The value of can be determined based on the characteristics of the channel. 【0151】 VIII. Channel Tuning Some embodiments relate to ring or disk modulators and optical interconnects that rely on resonant devices such as ring or disk filters. The high refractive index contrast of silicon over silicon oxide results in very high mode confinement, enabling the use of resonant devices with a very small footprint while keeping optical losses low. In one example, the ring modulator is 10 5 They can have a diameter of less than 5 μm with a quality factor (Q) exceeding . Since resonant devices can be made small without sacrificing optical loss, these devices are preferred over other types of modulators and filters when device density is of paramount importance (as in the case of the photonic interposers described herein). 【0152】 However, the use of resonant devices presents challenges. A prerequisite for resonance-based operation is that the relationship between the laser output wavelength and the resonator's resonant wavelength remains constant over time. Unfortunately, both the laser output wavelength and the resonator's resonant wavelength are affected by thermal drift, i.e., a phenomenon in which the wavelength can change due to unpredictable changes in local temperature. Furthermore, the resonator's resonant wavelength can also be affected by nonlinear effects, such as two-photon absorption in silicon, especially when the resonator confines light and increases the luminous flux density. When the laser output wavelength and the resonator's resonant wavelength drift relative to each other, the operation of the photonic interposer can deteriorate significantly. 【0153】 The inventors have developed a technique for locking a resonant device despite the presence of thermal drift. Figures 3-4A to 3-4C show the sequence for locking the wavelength of the transmitter. As shown in Figure 3-4A, the transmitter in this example can transmit data either in one direction or in opposite directions along the bus waveguide 410. The transmitter includes a resonant modulator 400, a modulator driver 402, a heater 404, an MZI 406, monitoring detectors 411, 412, 413 and 414, and a resonant additional filter 408 coupled to the bus waveguide 410. The modulator driver 402 drives the modulator 400 with data. As a result, the light provided by the laser is modulated with data. Depending on which output of the MZI is selected, the modulated light is coupled to the bus waveguide in either one direction (e.g., right to left) or opposite direction (e.g., left to right). The additional filter ensures that the data added to the bus waveguide is of the desired wavelength, thus enabling the bus waveguide 410 to support WDM. In this example, the additional filter is a second-order filter designed to flatten the frequency response across the passband in question. 【0154】 The first tuning step is shown in Figure 3-4A. Here, a signal in the form of a linear ramp controls the heater 404, thereby causing a shift in the resonant frequency of the modulator 400. While the modulator is ramped, a controller (not shown in Figure 3-4A) monitors the outputs (e.g., the sum of the outputs) of detectors 414 and 412. By determining the point where the detector outputs are maximized, it is possible to determine what value of the ramp will lock the modulator to the laser. Sweeping the modulator in this way ensures that the resonant wavelength of the modulator is tuned (or slightly out of tune) to the wavelength of the laser. In the following steps, the heater is driven to a value that maximizes the outputs of detectors 414 and 412. 【0155】 The steps shown in Figure 3-4B include tuning the MZI 406. This step ensures that 100% (or nearly 100%) of the modulator's output optical power is transmitted in either one or the other direction of the bus waveguide. This is to avoid transmitting data in the wrong direction of the bus waveguide. In this step, a signal in the form of a linear ramp controls the MZI 406, thereby causing a shift in the proportion of power appearing from the MZI's output. When the MZI is ramped, the controller monitors the output of either detector 414 or detector 412, depending on the desired transmission direction. For example, if the desired direction is right to left, the controller monitors the output of detector 414. By determining the point where the output of detector 414 is minimized, it can be inferred that all power is transmitted in the desired direction. In contrast, if the desired direction is left to right, the controller monitors the output of detector 412. 【0156】 The steps shown in Figure 3-4C include tuning the additional filter 408. With respect to the modulator 400, a heater (not shown in Figure 3-4C) can be placed near the additional filter to cause a wavelength shift when a signal is applied. Tuning the filter ensures that the desired wavelength is transmitted over the bus waveguide. In this step, a signal in the form of a linear ramp controls the heater near the additional filter 408, thereby causing a shift in the filter's resonant frequency. When the filter is ramped, the controller monitors the output of either detector 413 or detector 411, depending on the desired transmission direction. For example, if the desired direction is right to left, the controller monitors the output of detector 411. By determining the point where the output of detector 411 is minimized, it can be inferred that all the power is transmitted over the bus waveguide at the desired wavelength. In contrast, if the desired direction is left to right, the controller monitors the output of detector 413. If, after the steps in Figure 3-4C, it is determined that the MZI406 is no longer properly tuned, the controller may repeat the steps in Figure 3-4C and / or Figure 3-4B. 【0157】 Figures 3-5A and 3-5B show the sequence for tuning the receiver. As shown in Figure 3-5A, the receiver in this example can receive data transmitted along the bus waveguide 410 from either one direction or the other. The resonant drop filter 420 is the counterpart to the resonant add-on filter 408 in that it selects which wavelengths to transmit to the receiver and thus enables the bus waveguide to support WDM. In this example, the drop filter is a second-order filter designed to flatten the frequency response across the passband in question. Monitoring detectors 424 and 425 monitor the state of the drop filter. The MZI 426 determines the direction from which the data is received, whether from the left or the right. Monitoring detectors 434 and 435 monitor the state of the MZI. The receiver 440 includes a photodetector and an electronic receiver circuit (e.g., a transimpedance amplifier and an ADC). 【0158】 The steps shown in Figure 3-5A include tuning the drop filter 420. With respect to the modulator 400, a heater (not shown in Figure 3-5A) can be placed near the drop filter to cause a wavelength shift when a signal is applied. Tuning the filter ensures that the desired wavelength is received from the bus waveguide. In this step, a signal in the form of a linear ramp controls the heater near the drop filter 420, thereby causing a shift in the filter's resonant frequency. When the filter is ramped, the controller monitors the output of detector 413 or detector 411 depending on the desired transmission direction. For example, if the desired direction is left to right, the controller monitors the output of detector 425 and / or detector 424. By determining the point where the output of detector 425 is maximized and / or the output of detector 424 is minimized, it can be inferred that all power received from the bus waveguide is the desired wavelength. In contrast, if the desired direction is right to left, the controller monitors that the output of detector 424 is maximized and / or the output of detector 425 is minimized. 【0159】 The steps shown in Figure 3-5B include tuning the MZI426. This step ensures that 100% (or nearly 100%) of the optical power supplied to the receiver is received from one direction or the other. This is to avoid receiving data from the wrong direction in the bus waveguide. In this step, a signal in the form of a linear ramp controls the MZI426, thereby causing a shift in the percentage of power accepted from the input of the MZI, which is ultimately transferred to the RX440. While the MZI is ramped, the controller monitors the output of detector 434 or detector 435. By determining the point where the output of detector 435 is maximized and / or the output of detector 434 is minimized, it can be inferred that all power is received from the desired direction. 【0160】 Utilizing the resonant characteristics of wavelength division multiplexing transmission described above, the inventors have further developed a technique including dithering that enables a receiver to uniquely identify a particular transmitter. Dithering involves modulating a resonant component at a relatively slow frequency (e.g., 1 kHz to 1000 kHz) to uniquely identify the signal propagated through that component. The slow frequency should be supported in some embodiments by a modulation element such as a thermo-optic heater. Essentially, a component marks its signal with a signature in the form of a specific dithering frequency. Each component may be dithered at a slightly different frequency. Component identification becomes particularly important in architectures having several components in series. In some embodiments, a detector can identify which transmitter transmitted particular data depending on the dithering frequency. In one example, the dithered signal is used to lock a receiver's drop filter to a specific modulator. It is important to note that the dithered signal may be applied to a non-resonant element associated with the transmission of a specific wavelength (e.g., an MZI, such as in component 406). 【0161】 Figure 3-6A illustrates a technique for locking a receiver to a specific transmitter using dithering, according to several embodiments. In this example, multiple transmitters and multiple receivers are coupled in series along the length of a bus waveguide 410. The transmitters are coupled to the bus waveguide via an additional filter 408, and the receivers are coupled to the bus waveguide via a drop filter 420. The transmitter architecture is similar to that shown in Figure 3-4A, and the receiver architecture is similar to that shown in Figure 3-5A. In this case, the signal, which is maximized / minimized by detectors (424 and 425) in the RX device, is dithered. The analog circuit can be constructed to capture the signal at a specific dither frequency, for example, using homodyne or heterodyne circuits, and the local oscillator can be generated locally by the RX device. Other TX-RX transmitter pairs in series use different dither frequencies. Care must be taken to ensure that different dither frequencies are not rational numbers of each other, for example, that f1 / f2 is not a rational number a / b (where a and b are integers). Thus, by using a signal of a specific dither frequency associated with a particular TX-RX transmit pair, components within and between TX-RX transmit pairs can be locked to the correct pair (not confused by signals from other TX-RX pairs). In some embodiments, a receiver drop filter can be locked to the modulator of a particular transmitter by having (main and tap) detectors within the RX device to dither the modulator at a certain frequency and then maximize / minimize the signal at that particular frequency. Furthermore, in some embodiments, multiple components within the same TX-RX transmission link can be dithered using the same dither frequency such that all detectors within the TX-RX transmission link only need to generate a single dither frequency to lock. In other embodiments, different components within the same TX-RX transmission link can be dithered at different frequencies such that detectors within the TX-RX link can distinguish error signals of different components along the link.The dither frequency may be slower than the frequency of the crystal oscillator (in the MHz regime) typically used to construct the PLL. 【0162】 In some embodiments, an FIR digital bandpass filter (not shown in Figure 3-6A) programmed to identify a specific dithering frequency may be coupled to the detector. In these embodiments, locking between the transmitter and receiver may involve programming the FIR digital bandpass filter to accept only signals that are dithered at a specific frequency. 【0163】 Figure 3-6B shows an optical channel supporting communication between multiple transmitter-receiver pairs. Transmitter TX1 and receiver RX1 form a pair, and data transmitted by TX1 is directed to RX1. Transmitter TX2 and receiver RX2 form another pair, and data transmitted by TX2 is directed to RX2. Transmitter TX3 and receiver RX3 form yet another pair, and data transmitted by TX3 is directed to RX3. Transmitter TX4 and receiver RX4 form yet another pair, and data transmitted by TX4 is directed to RX4. Each TX-RX pair uses a unique dither frequency (f1 for TX1-RX1, f2 for TX2-RX2, f3 for TX3-RX3, and f4 for TX4-RX4). Each pair can use unique wavelengths λ1, λ2, λ3, and λ4 within the optical channel. 【0164】 IX. Redundancy The inventors recognized and understood that the finite yield associated with microscale manufacturing processes can adversely affect the scalability of photonic interposers. Yield associated with a manufacturing process represents the percentage of defect-free components divided by the total number of components manufactured. Manufacturing process yields are generally less than 100% and are attributed to various factors, including, for example, equipment performance, system complexity, and manufacturer capability. 【0165】 Some types of defects can impair the function of photonic circuits. When light encounters one of these defects, a partial or complete loss of optical power may occur. Other types of defects can impair the function of electronic circuits and / or wiring that are part of the tile (e.g., modulator drivers or transimpedance amplifiers). When an electrical signal encounters one of these defects, signal attenuation or complete loss may occur. 【0166】 A. Redundancy of the fiber optic attachment point The impact of limited yield in fiber optic attachments can be particularly serious. Fiber optic attachments enable photonic integrated circuits (photonic interposers being one example) to communicate with the outside world using optical fibers. Fiber optic attachments can be performed using passive or active processes. In passive processes, the fiber is attached to the chip without feedback on whether and to what extent the light is coupled. In active processes, the chip provides feedback, which can be used to improve optical alignment before the fiber is fixed to the chip. Active processes offer higher coupling efficiency than passive processes but are more expensive. Unfortunately, both types of processes have finite yields. Furthermore, chip manufacturers cannot determine the quality of the fiber optic attachments until the package is completely (or nearly completely) assembled. This is because fiber optic attachment is one of the final process steps in the packaging of photonic integrated circuits. 【0167】 Whether via edge coupling, vertical coupling, or the use of V-grooves, the yield in industry environments for mounting multiple (16 or 32) fibers at once remains around 95%. The types of fiber mounting described herein refer to mounting either a single fiber (e.g., single-mode fiber, polarization-retaining fiber, or multi-core fiber) or an array of fibers (e.g., a V-groove fiber array or fiber ribbon). Applications requiring many fibers, such as optically interconnected servers, demand higher fiber mounting yields. If a particular system requires N parts to be good, the system's yield rate is (p) N Here, p is the probability that the mounting site is a good product. Even when p is approximately 90%, the yield rate rapidly drops to approximately 20% for N=16. A more fault-tolerant mounting strategy is needed to increase the system's yield rate. The current focus is on improving the yield of the fiber mounting itself by introducing new packaging processes such as better refractive index-matched epoxy / adhesive or better active alignment during the mounting process. However, these methods are often insufficient. 【0168】 The inventors have developed a method for increasing the yield of fiber attachments with fiber redundancy. This can be achieved by having more fiber attachments than are required to operate the photonic integrated circuit. The controller identifies which fiber attachments or subsets of fiber attachments provide better performance from among all the fiber attachments. These fibers are utilized during chip operation, while the others remain unused. This process can be performed in real time, thus allowing the controller to continuously monitor the quality of the fiber attachments during operation. 【0169】 Figure 4-1A shows a photonic integrated circuit (PIC) 900 having a photonic circuit 902 and multiple fiber attachment points. The PIC 900 may represent, for example, one of the photonic interposers described herein. In these embodiments, the photonic circuit 902 may include tiles, transceivers, and photonic interconnects, as described above. However, fiber redundancy can be used in relation to any type of PIC. At each attachment point, the fiber 908 is coupled to the waveguide 907 of the PIC via an optical chip-fiber coupler 906 (e.g., an edge coupler, v-groove, or grid). As shown, instead of having only a single fiber attachment point, an additional k-1 fiber attachment points (a total of k fiber attachment points) are provided. An optical switch 904 on the PIC selects which of the k fiber attachment points should be used for the operation of the PIC. A controller 903 monitors the performance of each fiber attachment point and controls the operation of the optical switch 904. 【0170】 Different methods may be used to monitor the performance of the fiber optic attachments. In one example, a photodetector 909 coupled to waveguide 907 using a tap coupler monitors the optical power present in the waveguide (only one photodetector 909 is shown in Figure 4-1A). The photodetector 909 provides information to the controller 909 indicating the optical power present in various waveguides 907. Based on this information, the controller 909 can determine which subset (which may be one or more fiber optic attachments) of the k fiber optic attachments provides the best performance. The controller 909 can then control the optical switch 904 to select the waveguide(s) corresponding to the best-performing fiber optic attachment subset. In another example, the photonic integrated circuit 902 may include a system for monitoring the quality of channels corresponding to various fiber optic attachments. For example, the photonic integrated circuit 902 may monitor the bit error rate (BER), eye diagram quality coefficient, power, and / or signal-to-noise ratio (SNR) associated with each channel. In this example, the controller 909 can control the optical switch 904 to sequentially select waveguides one after another, thus allowing the photonic circuit 902 to individually monitor the quality of each channel. The photonic circuit 902 provides the controller 909 with information indicating the quality of various channels. Based on this information, the controller 909 can determine which subset (which may be one or more fiber attachments) of the k fiber attachments provides the best performance. The controller 909 can then control the optical switch 904 to select the waveguide(s) corresponding to the best-performing fiber attachment subset. In some embodiments, where fiber attachment performance can be measured before final system assembly, it is not necessary to connect the less-performing fiber attachment subset to other optical devices or connectors. In other embodiments, where fiber attachment performance cannot be measured before final assembly, all fiber attachments can be performed, and then subset selection can be performed. 【0171】 The redundancy scheme described in relation to Figure 4-1A can be used regardless of whether the PIC900 is used as a transmitter or receiver. Figure 4-1B is a block diagram showing a pair of PIC900s connected to each other using k fibers, some of which are simply provided for redundancy. One PIC operates as a transmitter, in which the photonic circuit 902 operates as the TX photonic circuit. The other PIC operates as a receiver, in which the photonic circuit 902 operates as the RX photonic circuit. Each controller 909 monitors the quality of the fiber attachments and controls each optical switch 904 to select the waveguide(s) corresponding to the best-performing fiber attachment subset. 【0172】 If the probability that each individual fiber attachment works correctly is p, then the overall probability that at least one of the k fiber attachments works correctly using fiber redundancy is 1 - (1 - p). k This is equal to p. Since this quantity is always greater than p, the yield improves. For example, consider a system that requires 16 functional fiber attachment points to be good. By using redundant fiber attachment points at each attachment point, the system yield can be increased to nearly 100%, even when the probability of successful fiber attachment is low. The results are shown in Figure 4-1C. Figure 4-1C shows the overall system yield (in %) for a system with 16 fiber attachment points as a function of the number of attachment points on each point. Having a single attachment point (one on the x-axis) means that no redundant fiber attachment points are used. Having N attachment points (N on the x-axis) means that N-1 redundant fiber attachment points are used. As can be seen from this figure, regardless of the initial probability that the fiber attachment points will work properly, the overall system yield approaches 100% as the number of attachment points increases. 【0173】 B. Tile redundancy The inventors further understand that not all tiles of a photonic interposer are good. Some tiles may have, for example, defective transmitters, receivers, interconnects, and / or switches. This can negatively impact network performance, as electronic chips mounted on defective tiles may become unusable. In addition, not all electronic chips mounted on a photonic interposer are good. To avoid these problems, the inventors have developed a system with tile redundancy. 【0174】 Figure 4-2 shows a photonic interposer having multiple tiles, one of which is provided for redundancy. Electronic chips 911, 912, 913, 914, 915, and 916 are mounted on the photonic interposer 20 corresponding to their respective tiles. Optionally, an additional electronic chip 917 may be placed on the redundant tile. Chip 917 may also be provided for redundancy in case one of the other electronic chips fails to function properly. For example, chip 917 may be a copy of one of the other chips. In this example, the tile corresponding to chip 914 is defective. In response, the photonic interposer may be reconfigured to functionally swap the defective tile with the redundant tile. Using the programmable interconnect described above, the optical signal directed to the defective tile can be redirected to the redundant tile. Optionally, the redundant chip 917 may be used in place of chip 914. 【0175】 In some embodiments, wafer-level testing can be used to determine the quality of tiles on a photonic wafer. This method allows manufacturers to determine wafer quality without having to test separate parts of the wafer individually. The drawback of this method is that once a particular part of the wafer is designed for a specific application, the tiles of that wafer part, regardless of their quality, are ultimately packaged as part of a photonic interposer. 【0176】 In some embodiments, tile performance can be monitored in real time during operation. This can be achieved using a power monitoring grid, an example of which is shown in Figure 4-3. The power monitoring grid includes multiple photodetectors (e.g., photodetector 909 in Figure 4-1A) positioned at various locations on the photonic interposer. The photodetectors can be coupled to various photonic components via tap couplers. The power monitoring grid can be used, for example, to determine if a particular tile is not operating as expected. Using this information, the system can decide to reconfigure itself to functionally swap that tile with one of the redundant tiles. This operation can be performed while the photonic interposer is operating. 【0177】 X. Manufacturing of grid-based packages The photonic interposers described herein require light to operate, whether the light is supplied by a laser or another type of light source. Unfortunately, monolithically integrating a laser with a photonic interposer is difficult due to the low luminescence of silicon. Instead, it is often more practical to use an external laser (located on the same package or substrate as the interposer) and direct the light emitted by the external laser into the chip. This can be done via edge coupling or surface coupling. Edge coupling involves coupling optical modes from a fiber to a waveguide through one of the sides of the chip. In contrast, surface coupling involves coupling optical modes from a fiber to a waveguide through the top surface of the chip. Lattice couplers are often used to guide light coming from outside the top surface plane to a waveguide extending parallel to the top surface of the chip. A lattice coupler is a planar structure formed on or just below the top surface of the photonic chip. 【0178】 The inventors recognize and understand that the presence of particles or other types of debris on the top surface of the chip can adversely affect fiber lattice coupling efficiency. This is because particles can cause scattering. Unfortunately, due to various manufacturing steps performed after lattice formation but before the fibers are attached to the top surface of the chip, achieving particle-free operation is difficult. 【0179】 The inventors have developed a manufacturing process that limits the accumulation of particles or other debris on the upper surface of a photonic chip, thereby resulting in improved fiber lattice efficiency. In some embodiments, this can be achieved by forming a temporary protective layer positioned to protect the lattice during process steps that are more likely to generate undesirable particles. Once these process steps are complete, the temporary protective layer can be removed, exposing the lattice to air for subsequent fiber mounting. The temporary protective layer may be formed before or after the electronic chip (e.g., ASIC) is bonded to the photonic interposer. Examples of protective layers include photoimageable dielectrics (e.g., polyimide or resist) and glass (e.g., with UV-peelable adhesive). Other materials are also possible. Furthermore, in some embodiments, particle-free processing can be achieved by using a custom molding process designed to seal the electronic chip without ever contacting the lattice coupler. 【0180】 Figure 5-1 is a schematic diagram showing a fiber coupled to a grating coupler formed on a photonic interposer, according to several embodiments. The fiber 1120 is positioned above the grating coupler 1110 formed on the upper surface of the photonic interposer 1130. The fiber 1120 is at a non-zero angle with respect to the surface of the photonic interposer 1130. In this example, the fiber is also at a non-zero angle with respect to an axis perpendicular to the upper surface of the interposer, but in some embodiments, the fiber may be parallel to the vertical axis. Light emanating from the fiber core 1122 of the fiber 1120 is coupled to the grating coupler 1110. The grating then transmits the light to the waveguide 1121. 【0181】 Figure 5-2A is a top view of wafer 1130 patterned to form a photonic circuit, which can be used as a photonic interposer once diced from the wafer. An electronic chip 1210 is mounted on the photonic interposer(s). The electronic chip is sealed by a sealing material 1220 which may be formed using a molding compound. Regions 1230 include a grid coupler formed on the top surface of the wafer. These regions are not covered by the sealing material to allow for subsequent fiber attachment. 【0182】 Figure 5-2B is a side cross-sectional view showing a portion of the wafer of Figure 5-2A as seen from the y-axis in the xz-plane. This figure shows multiple electronic chips mounted on the top surface of a photonic interposer. The electronic chips are sealed by the sealing material 1220. Region 1230 is exposed to air. 【0183】 Figure 5-3A shows the photonic interposer of Figure 5-2B after dicing. Region 1230 remains exposed to air, allowing for fiber attachment in subsequent steps. A connector 1310 formed on the bottom surface of the photonic interposer enables connection between the photonic interposer and the circuit board 1340. Examples of connectors 1310 include ball grid arrays (BGAs), copper pillars, C4 bumps, and pins. 【0184】 Figure 5-3B is a side cross-sectional view of the package after the fiber 1120 has been mounted on the top surface of the interposer 1130. Once the fiber is mounted, the fiber core is optically coupled to the grating coupler. In this figure, the interposer 1130 is mounted on a printed circuit board (PCB) 1340 via a connector 1310 that passes through the underfill 1330. A cap 1320, such as a heat spreader, is positioned on top of the electronic chip. The fiber 1120 is coupled to the grating coupler on one side of the package via a steering optical component 1350 that steers the light propagating through the fiber in a direction that is a non-zero angle with respect to the top surface of the photonic interposer, thereby enabling the fiber modes to be coupled to the grating. 【0185】 Figures 5-4, 5-5, and 5-6 are flowcharts illustrating various processes for manufacturing packaged photonic interposers. These manufacturing processes are designed to prevent (or at least limit) the accumulation of particles or debris corresponding to the fiber grid, thereby enabling low-loss, high-efficiency fiber grid coupling. As will be described in more detail below, the processes in Figures 5-4 and 5-5 include a temporary protective layer. The process in Figure 5-6 includes a custom molding process. 【0186】 Referring first to Figure 5-4, the manufacturing process begins in step 4A in a packaging facility, which includes obtaining a photonic interposer 1130 (e.g., the photonic interposer in Figure 1-3B or any of the photonic interposers described herein) patterned with one or more grid couplers, and covering the area 1230 (where the grid is patterned) with a protective material 1438. As a result, the grid couplers are covered. The photonic interposer may be received from a semiconductor foundry to a packaging facility, where the wafer is patterned with photonic and electronic circuits including grid couplers. Examples of materials that may be used for the protective material 1438 include a photo-imageable film (PIF) (e.g., polyimide or photoresist). In step 4B, an electronic chip 1210 (e.g., an ASIC, processor, memory, etc.) is placed on the photonic interposer. In step 4C, the electronic chip 1210 is sealed with sealing material 1220 by a process such as mass reflow and wafer-level mold underfill (WL MUF). Note that the protective film applied in step 4A does not allow the coating of the mold compound on the grid coupler in step 4C and further maintains the cleanliness of the grid coupler from all contaminants and particulate matter released during the subsequent back grinding and CMP process step 4D. The sealing provides protection for the chip and enables the formation of the subsequent TSV exposure process step. In step 4D, the sealing material is removed from the top of the electronic chip via planarization (e.g., CMP) or back grinding to allow the carrier mount 1638 to be attached, which is done in step 4E (after the flip step). In step 4F, after the TSV exposure process, the connector 1310 (e.g., BGA) is attached to the bottom surface of the photonic interposer. Note that the attachment of the connector 1310 to the interposer may generate particles or other debris. However, this installation step is performed when the grating coupler is covered with protective material 1438.As a result, particles or fragments generated during the adhesion step do not affect the cleanliness of the upper surface on which the grating couplers are patterned. In step 4G, the carrier mount 1638 is removed from the top of the electronic chips. In step 4H, UV peelable adhesive tape 1330 (e.g., dicing tape) is applied. In step 4I, the protective material 1438 is removed from the upper surface of the photonic interposer, leaving the grating couplers exposed to the air. Optionally, a cleaning step can be performed using a plasma process to ensure surface cleanliness for fiber mounting and optical coupling. In step 4J, the photonic interposer is separated into multiple systems, each comprising one or more electronic chips and one or more grating couplers, by, for example, stealth dicing or mechanical sawing. In step 4K, the photonic interposer is mounted to the circuit board 1340 by a process such as mass reflow, capillary underfill (CUF), and urea-formaldehyde (UF) resin curing. Furthermore, cap 1320 is attached to the electronic chip, and the cap can function as a heat spreader. In addition, an open / short (O / S) test is performed to ensure good electrical connection between the photonic interposer and the circuit board. Finally, fiber 1120 is attached to the top surface of the interposer. As a result, the fiber is optically coupled to the lattice coupler. 【0187】 Figure 5-5 is a flowchart showing alternative methods for manufacturing a photonic package according to several embodiments. The method in Figure 5-5 is similar in some respects to the method in Figure 5-4. The main difference is that the protective material 1538 is formed after the chip is mounted on the photonic interposer and after the sealing step. Step 5A includes obtaining a photonic interposer 1130 patterned with one or more grating couplers and placing the chip 1210 on the interposer. In step 5B, the electronic chip 1210 is sealed with sealing material 1220 via a process such as mass reflow and wafer-level molded underfill (WL MUF). As described above, the sealing provides protection for the chip and allows for the formation of the subsequent TSV exposure process step. In step 5C, the protective material 1538 (e.g., a glass lid with UV peelable adhesive) is placed over the area of ​​the interposer where the grating couplers are formed. The mounting of the protective glass maintains the cleanliness of the grating couplers from all contaminants and particulate matter released during the subsequent back grinding and CMP process step 5D. In step 5D, the top surface is flattened or the back surface is ground. In step 5E, after the TSV exposure process, the interposer is flipped over and the connector 1310 (e.g., BGA) is attached to the bottom surface of the photonic interposer. As described above, the attachment of the connector 1310 to the interposer may generate particles or other debris. However, this attachment step is performed when the grid coupler is covered with protective material 1538, thereby maintaining the cleanliness of the top surface on which the grid coupler is patterned. In step 5F, the protective material 1538 is removed, and the grid coupler is thus exposed to the air. Optionally, plasma cleaning is performed on the top surface of the photonic interposer. Subsequent steps are similar to those shown in Figure 5-4, including fiber attachment. 【0188】 Figure 5-6 is a flowchart showing another alternative method for manufacturing a photonic package according to several embodiments. The method in Figure 5-6 differs from the methods in Figures 5-4 and 5-5 in that no protective material is used to cover the grid coupler. Instead, a custom-designed molding process is performed to encapsulate the electronic chip, while simultaneously covering and contaminating the grid coupler with debris caused by the encapsulation step. Subsequent steps are similar to those described in Figure 5-4. 【0189】 In step 6A, the chip 1210 is mounted on the interposer 1130. In step 6B, the encapsulation material 1120 is formed using a custom molding process in a manner that avoids covering area 1230. As a result, contamination generated by the molding step, which would have affected the cleanliness of the grid coupler, is prevented (or at least limited). Thus, this process avoids leaving impurities on top of the grid coupler. In step 6C, the top surface of the package is planarized or back-ground. In step 6D, the package is mounted on the carrier mount 1638. In step 6E, the device is flipped over, and after the TSV exposure process, the connector 1310 is attached to the bottom surface of the interposer. In step 6F, the carrier mount 1638 is removed. In step 6G, the interposer is diced. In step 6H, the fiber is attached to the top surface of the interposer to couple with the grid coupler. 【0190】 XI.Power distribution Figure 5-7 is a side cross-sectional view of a photonic package mounted on a circuit board including a power supply system, according to several embodiments. The package in Figure 5-7 includes a circuit board 1740, a socket 1730, a substrate 1720, a photonic interposer 1714, an electronic chip 1712, a lid 1732, a cooling plate 1734, a voltage regulator module (VRM) 1750, a connector 1752, and a power bus 1754. The photonic interposer 1714 and the electronic chip 1712 mounted on the photonic interposer have similar characteristics to the interposer and chip described in detail above. The lid 1732 covers the electronic chip and is positioned in thermal contact with the electronic chip. The lid 1732 and the cooling plate 1734 located on top of the lid transfer the heat generated by the electronic chip to the outside of the package. As shown in Figure 5-7, the photonic interposer 1714 is placed on a substrate 1720 (for example, an organic substrate), and the substrate 1720 is placed on a socket 1730. The socket 1730 is further placed on the upper surface of the circuit board 1740. 【0191】 The package in Figure 5-7 relies on a power bus 1754, a VRM 1750, and a connector 1752 to transmit power to the photonic interposer and electronic chip. The VRM receives power from the power bus and provides a regulated power output to the electronic components to avoid voltage fluctuations exceeding acceptable limits caused by loads from the electronic chip, as shown in Figures 5-8A. The inventors understand that by mounting the VRM 1750 and power bus 1754 on the bottom surface of the circuit board 1740 (opposite the circuit board to the interposer) compared to an implementation where the VRM and power bus are located on the circuit board near the interposer, the lateral spread of the circuit board 1740 can be reduced, thereby reducing power losses that would have resulted from longer lateral paths for power supply. As a result, the design becomes more compact and easier to integrate with other electronic systems. In this configuration, the connector 1752 interconnects the VRM and the corresponding electronic chip by traversing multiple layers: the interposer 1714, the substrate 1720, the socket 1730, and the circuit board 1740. The connector 1752 includes a series of different types of vias, the properties of which depend on the substrate being traversed. 【0192】 Figures 5-8B are side cross-sectional views illustrating how power can be delivered from the VRM to the electronic chips. In some embodiments, the VRM delivers power to one electronic chip. In other embodiments, the VRM delivers power to multiple electronic chips. In Figures 5-8B, one VRM is shown delivering power to four electronic chips via the connector 1752. 【0193】 XII. Additional comments While several aspects and embodiments of the technology of this application have been described herein, it should be recognized that those skilled in the art will readily conceive of various modifications, alterations, and improvements. Such modifications, alterations, and improvements are intended to fall within the spirit and scope of the technology described herein. Therefore, it should be understood that the embodiments described herein are presented only as examples, and embodiments of the present invention may be practiced in ways other than those specifically described, within the scope of the appended claims and equivalents. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is included within the scope of this disclosure, provided that such features, systems, articles, materials, and / or methods are not contradictory to each other. 【0194】 Similarly, as described, some embodiments can be embodied as one or more methods. The actions performed as part of the method can be ordered in any suitable manner. Thus, even if shown as a sequence of actions in exemplary embodiments, embodiments can be constructed in which the actions are performed in a different order than described, which may include performing several actions simultaneously. 【0195】 It should be understood that all definitions defined and used herein refer to dictionary definitions, definitions in documents referenced by reference, and / or the ordinary meanings of the terms defined. As used in the specification and claims herein, the indefinite articles “a” and “an” should be understood to mean “at least one” unless explicitly indicated otherwise. 【0196】 As used in the specification and claims herein, the phrase "and / or" should be understood to mean "either or both" of the combined elements, that is, elements that may exist conjugately or disjunctly. 【0197】 As used in the specification and claims herein, the phrase “at least one” relating to an enumeration of one or more elements means at least one element selected from any one or more of the enumerated elements, and does not require that at least one of all elements specifically enumerated in the enumeration be included, nor does it exclude any combination of elements in the enumeration. Furthermore, this definition allows for the presence of elements other than those specifically identified in the enumeration of elements referred to by the phrase “at least one,” regardless of whether they relate to the specifically identified elements. 【0198】 The terms “approximately” and “about” may be used in some embodiments to mean within ±20% of the target value, within ±10% of the target value, within ±5% of the target value, and further, within ±2% of the target value. The terms “approximately” and “about” may include the target value.

Claims

[Claim 1] A method for manufacturing a photonic package, To obtain a photonic interposer having a lattice coupler formed on the first surface of the photonic interposer, The electronic chip is attached to the first surface of the photonic interposer, The aforementioned electronic chip is sealed with a sealing material, A protective material is placed on the first surface of the photonic interposer so as to cover the grid coupler, After the protective material is placed and the electronic chip is attached to the first surface of the photonic interposer, an electronic connection portion is formed on the second surface of the photonic interposer opposite to the first surface. After forming the electronic connection portion, the entire protective material is removed from the first surface of the photonic interposer in order to expose the first surface including the grid coupler to air. A method that includes this. [Claim 2] The method according to claim 1, further comprising removing the protective material from the first surface of the photonic interposer and then cleaning the first surface of the photonic interposer. [Claim 3] The method according to claim 1 further comprises, after removing the protective material, attaching a fiber to the first surface of the photonic interposer, wherein the fiber is optically coupled to the grating coupler when attached. [Claim 4] The method according to claim 3, wherein when the fiber is optically coupled to the lattice coupler, the fiber is at a non-zero angle with respect to the first surface of the photonic interposer. [Claim 5] The method according to claim 1, wherein the attachment of the electronic chip to the first surface of the photonic interposer is performed after the protective material is placed on the first surface of the photonic interposer. [Claim 6] The method according to claim 5, wherein the protective material includes a photoimageable dielectric. [Claim 7] The method according to claim 1, wherein the placement of the protective material on the first surface of the photonic interposer is performed after the electronic chip is mounted on the first surface of the photonic interposer. [Claim 8] The method according to claim 7, wherein placing the protective material on the first surface of the photonic interposer is performed after sealing the electronic chip with the sealing material. [Claim 9] The method according to claim 8, wherein the protective material comprises a glass lid having a peelable adhesive.

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