Switch circuits and power supply circuits

Abstract

Provided are a switch circuit and a power supply circuit capable of reducing power consumption.　A switch circuit (25) comprises: an electric field effect switch element (M1) that can switch between an ON state and an OFF state according to the potential (VC1) of a control terminal (TP1); and a control circuit (18a) which, when maintaining one among the ON state and the OFF state of the switch element (M1), supplies the control terminal (TC1) with a first level potential that causes the switch element (M1) to be in the one state, and when changing the switch element (M1) from the one state to the other state among the ON state and the OFF state, charges or discharges and then floats the control terminal (node N1) via resistors (M2, M3), and supplies a second level potential that causes the switch element (M1) to be in the other state.

Description

Technical Field

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[0001] The present invention relates to a switch circuit and a power supply circuit.

Background Art

[0002] There is known a power supply circuit that stores power in a capacitor or the like while converting the voltage of the power generated by a power generation element such as an environmental power generation element. In such a power supply circuit, switching for converting the voltage of the power is realized by a FET (Field Effect Transistor) and a control circuit that controls its gate voltage (for example, Patent Document 1). (For example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, a gate voltage for turning on the MOSFET (M1) is generated by resistively dividing the voltage between the node between the power generation element and the MOSFET (M1) and the ground by resistors R2 and R3 (see FIG. 1 of Patent Document 1). However, current continues to flow through the resistors R2 and R3 during the period when the MOSFET (M1) is in the on state, resulting in increased power consumption. Therefore, the power supply circuit of Patent Document 1 affects the power consumption of a circuit that requires low power consumption, for example, a circuit using a so-called environmental power generation element as a power supply element. This influence is not limited to the circuit of Patent Document 1, but also occurs similarly in circuits having a similar switching function.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a switch circuit and a power supply circuit capable of reducing power consumption.

Means for Solving the Problems

[0013] Another invention's switch circuit includes a first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, wherein the on state and off state are switched according to the potential of the gate. A second FET having a source connected to the first node, a drain connected to the first terminal, and a gate. In order to maintain the off state of the first FET, a first level potential that causes the first FET to be in the off state is supplied to the first node. The first FET is turned from the off state to the on state. When The connection between the source and drain of the second FET is turned off, and the first node is 、 Connected to a reference potential via a resistor After charging or discharging the first node, The first node is disconnected from the first terminal and the reference potential. The first node is made floating, And the first control terminal , to turn on the aforementioned 1FET Supplying the second level of potential Equipped with a control circuit, .

[0014] In the above configuration, a third FET is provided, having a source connected to the reference potential, a drain connected to the first node, and a gate, wherein the resistor is the resistance between the source and drain of the third FET, and a saturation current flows through the third FET when the first node is connected to the reference potential via the second FET.

[0015] In the above configuration, the rectifier element is provided such that the direction of the second node, which capacitively couples the first node to the second control terminal, is forward, the second FET is of type N, the gate of the second FET is connected to the second node, the first FET is of type P, and the first node is connected to the reference potential via the rectifier element, the second node, and the resistor.

[0016] In the above configuration, the rectifier element is provided such that the direction from the second node capacitively coupled to the second control terminal to the first node is forward, the second FET is of type P and connected to the second node capacitively coupled to the second control terminal, the first FET is of type N and the first node is connected to the reference potential via the rectifier element, the second node and the resistor.

[0017] In the above configuration, the control circuit may be configured to supply the second level potential to the first control terminal and the third level potential to the second control terminal to turn off the second FET when the first FET remains in the ON state, to supply the second control terminal with a fourth level potential to turn on the second FET when the first FET is turned off from the ON state, and thereafter supply the first level potential to the first control terminal and the third level potential to the second control terminal.

[0018] In the above configuration, the control circuit may be configured to supply the third level potential to the second control terminal and then supply the first level potential to the first control terminal when switching the first FET from the ON state to the OFF state.

[0019] In the above configuration, when the first FET remains in the off state, a determination circuit is provided to determine that the input voltage input to the first terminal has changed by a certain voltage from the input voltage when the first FET last switched from the on state to the off state. The control circuit may be configured to supply the second level to the first control terminal and the fourth level to the second control terminal when it determines that the input voltage has changed by a certain voltage, and then supply the first level to the first control terminal and the third level to the second control terminal.

[0020] In the above configuration, the determination circuit may be configured to include a comparator that compares the voltage of a third node capacitively coupled to the first terminal with a constant voltage and outputs the comparison result to the control circuit.

[0021] In the above configuration, the input voltage input to the first terminal is higher than the reference potential, and the first FET can be a PFET.

[0022] In the above configuration, the input voltage to the first terminal is lower than the reference potential, and the first FET can be an NFET.

[0023] In the above configuration, the power generation element can be configured as a vibration power generation element. Furthermore, another switching circuit of the invention comprises a first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, and which can be switched between an on state and an off state depending on the potential of the gate; a second FET having a source connected to the first node, a drain connected to the first terminal, and a gate connected to a second node capacitively coupled to a second control terminal; and a control circuit that controls the first FET and the second FET, wherein the control circuit causes the first FET to be turned on from the first control terminal to the first node when maintaining the on state of the first FET. When supplying a first level potential to turn the first FET from an ON state to an OFF state, the first and second nodes are connected to the first terminal via a resistor to charge or discharge, and then the first and second nodes are disconnected from the first terminal and made floating by supplying a potential from the second control terminal to the second node to turn off the source and drain of the second FET. After they are made floating, a second level potential is supplied to the first control terminal to turn off the first FET.

[0024] The present invention is a power supply circuit including the above switch circuit.

Effects of the Invention

[0025] According to the present invention, it is possible to provide a switch circuit and a power supply circuit capable of reducing power consumption.

Brief Description of the Drawings

[0026] [Figure 1] FIG. 1 is a circuit diagram showing a first embodiment of a power supply circuit in which a switch circuit whose details are shown in FIG. 3 is used. [Figure 2] FIG. 2 is a timing chart showing the on / off of the switch constituting the voltage conversion circuit shown in FIG. 1 and the current IL flowing through the inductor. [Figure 3] FIG. 3 is a detailed circuit diagram of the switch circuit constituting the power supply circuit of the first embodiment, and shows the details of the switch shown as HSW in FIG. 1 and its control circuit. [Figure 4] FIG. 4 is a timing chart showing the time change of each voltage and on / off of the switch circuit shown in FIG. 3. [Figure 5] FIG. 5 is a detailed circuit diagram of the switch circuit constituting the power supply circuit of the second embodiment, and shows the details of the switch shown as HSW in FIG. 1 and its control circuit. [Figure 6] FIG. 6 is a timing chart showing the time change of each voltage and on / off of the switch circuit shown in FIG. 5. [Figure 7] FIG. 7 is a detailed circuit diagram of the switch circuit constituting the power supply circuit of the third embodiment, and shows the details of the switch shown as HSW in FIG. 1 and its control circuit. [Figure 8]Figure 8 is a timing chart showing the time variations of each voltage, current, and on / off state of the switch circuit shown in Figure 7. [Figure 9] Figure 9 is a detailed circuit diagram of the switch circuit that constitutes the power supply circuit of Embodiment 4, and is a circuit diagram showing the details of the switch shown as HSW in Figure 1 and its control circuit. [Figure 10] Figure 10(a) is a block diagram showing an embodiment of the power supply circuit of the present invention, in which a switch circuit of any of Embodiments 1 to 4 or its modified form is used in the voltage conversion circuit 64. Figure 10(b) is a block diagram showing a sensor circuit system in which a switch circuit of any of Embodiments 1 to 4 or its modified form is used. [Modes for carrying out the invention]

[0027] The following describes an embodiment with reference to the drawings. [Examples]

[0028] Figure 1 is a circuit diagram showing one embodiment of a power supply circuit using a switch circuit, the details of which are shown in Figure 3. The output current of the power generation element 10 is input to the input terminal Tin of the voltage conversion circuit 12 in Figure 1. When an AC power generation element is used as the power generation element 10, the output current of the power generation element 10 is rectified by the rectifier circuit 11 and input to the input terminal Tin.

[0029] The power generation element 10 is, for example, an energy harvesting element such as a vibration power generation element. The vibration power generation element is, for example, a piezoelectric element using a piezoelectric material or a MEMS (Micro Electro Mechanical Systems) element using MEMS. The vibration power generation element is installed, for example, on a road or bridge, and generates electricity from vibrations caused by pedestrians or vehicles passing by. When a vibration power generation element is used as the power generation element 10, the generated power is a small amount of AC power and changes with the state of vibration. When a piezoelectric element is used, the output voltage is generally relatively higher than the several volts required for the operation of an electronic circuit. In Example 1, the input to the input terminal Tin is positive relative to ground by the rectifier circuit 11.

[0030] Nodes N01 to N04 are provided between the input terminal Tin and the output terminal Tout of the voltage conversion circuit 12. In this embodiment, the voltage conversion circuit 12 steps down the relatively high voltage from the power generation element 10 and outputs it to the output terminal Tout. Switch HSW is a high-side switch provided on the high-voltage side (referred to as the high-side) of the voltage conversion circuit 12. One end of switch HSW, terminal Tsw1, is connected to node N01, and the other end, terminal Tsw2, is connected to node N02. One end of inductor L1 is connected to node N02, and the other end is connected to node N03. One end of switch SW3 is connected to node N03, and the other end is connected to node N04. One end of the primary side capacitor C01 of the voltage conversion circuit 12 is connected to node N01, and the other end is connected to ground (reference potential). One end of the secondary side capacitor C02 of the voltage conversion circuit 12 is connected to node N04, and the other end is connected to ground. One end of switch SW1 is connected to node N02, and the other end is connected to ground. One end of switch SW2 is connected to node N03, and the other end is connected to ground.

[0031] The control unit 14 outputs control signals Sh and S1 to S3 to switches HSW and SW1 to SW3, respectively. Switches HSW and SW1 to SW3 are turned on or off based on the control signals Sh and S1 to S3, respectively. In this embodiment, the control unit 14 generates the control signal Sh at a constant frequency. Its frequency is sufficiently higher than the frequency of the AC component included in the electromotive force output from the power generation element 10 and the rectifier circuit 11. The frequency of the control signal Sh is set so that impedance matching is performed to efficiently transmit the electromotive force output from the power generation element 10 and the rectifier circuit 11 to the voltage conversion circuit 12. The control unit 14 may also detect voltages Vin and Vout and output control signals Sh and S1 to S3 based on voltages Vin and Vout.

[0032] When a positive current is input from the power generation element 10 to the input terminal Tin relative to ground via the rectifier circuit 11, capacitor C01 is charged. The potential of capacitor C01 relative to ground on the node N01 side is referred to as the input voltage Vin of input terminal Tin. Due to the operation of the voltage conversion circuit 12, that is, the operation of switches HSW, SW1, SW2, and SW3 within the voltage conversion circuit 12 as described below, the charge from capacitor C01 is transferred to capacitor C02. The potential of capacitor C02 relative to ground on the node N04 side is referred to as the voltage Vout of output terminal Tout.

[0033] Figure 2 is a timing chart showing the on / off states of the switches constituting the voltage conversion circuit shown in Figure 1 and the current IL flowing through the inductor. Figure 2 shows the value of the input voltage Vin, the on and off states of each switch in Figure 1, the current IL flowing through the inductor L1, and the value of the output voltage Vout. Time t00 in Figure 2 is a timing when the power supply circuit is operating, and at that time, the current from the power generation element 10 is stored in the capacitor C01, and its voltage Vin is voltage Vin1. Charge is also stored in the capacitor C02 due to the voltage conversion operation described later, and its voltage Vout is voltage Vout1. At time t00, the control unit 14 keeps switches HSW and SW1~SW3 in the off state.

[0034] The charge stored in capacitor C01 increases due to the generated current from power generation element 10, and after the voltage Vin exceeds a predetermined threshold voltage, at time t01, the control unit 14 turns on switches HSW and SW2 while keeping switches SW1 and SW3 off. As a result, current IL begins to flow from capacitor C01 to ground through node N01, switch HSW, inductor L1, and switch SW2. The control unit 14 may detect the voltage Vin at input terminal Tin and turn on switches HSW and SW2 when the voltage Vin exceeds a predetermined threshold voltage, or it may turn on switches HSW and SW2 at predetermined intervals. Between times t01 and t02, the current IL gradually increases, and as the charge in capacitor C01 is discharged, the voltage Vin gradually decreases. Magnetic field energy is stored in inductor L1.

[0035] At time t02, voltage Vin becomes voltage Vin2. Voltage Vout is voltage Vout1. At time t02, when current IL becomes IL1, the control unit 14 turns off switches HSW and SW2 and turns on switches SW1 and SW3. The control unit 14 may detect the voltage Vin at input terminal Tin and turn off switches HSW and SW2 and turn on switches SW1 and SW3 when voltage Vin becomes Vin2, or it may turn off switches HSW and SW2 and turn on switches SW1 and SW3 at predetermined intervals. Between times t02 and t03, current IL flows from ground through switch SW1, inductor L1 and switch SW3 due to the magnetic field energy stored in inductor L1, and as capacitor C02 is charged, voltage Vout rises.

[0036] At time t03, the control unit 14 turns off switches SW1 and SW3 and maintains the off state of switches HSW and SW2. The control unit 14 detects the voltage Vout at the output terminal Tout and may turn off switches SW1 and SW3 when the voltage Vout reaches a predetermined threshold voltage, or it may turn off switches SW1 and SW3 at predetermined intervals. After time t03, the current IL is 0, the voltage Vin is voltage Vin2, and the voltage Vout is voltage Vout2. Voltages Vout1 and Vout2 may be lower or higher than voltages Vin1 and Vin2. Voltages Vout1 and Vout2 can be set by appropriately setting the capacitance values ​​of capacitors C01 and C02, and the on / off timing of switches HSW and SW1 to SW3.

[0037] Figure 3 is a detailed circuit diagram of the switch circuit that constitutes the power supply circuit of Embodiment 1, and shows the details of the switch shown as HSW in Figure 1 and its control circuit. Hereinafter, an FET with a channel conductivity of type P will be referred to as a PFET, and an FET with a channel conductivity of type N will be referred to as an NFET. The on / off state of PFETM1 corresponds to the on / off state of switch HSW. As shown in Figure 3, in the switch circuit 25 of Embodiment 1, the source of PFETM1 (first FET) is connected to terminal Tsw1 (first terminal), the drain is connected to terminal Tsw2 (second terminal), and the gate is connected to node N1 (first node). Capacitor C1 (first capacitor) has a control signal VC1 (first control signal) input to one end and the other end is connected to node N1. That is, the gate is capacitively coupled to the control terminal TC1 (first control terminal). The source of NFETM2 (second FET) is connected to node N1, the drain is connected to terminal Tsw1, and the gate is connected to control terminal TC2, which receives the control signal VC2 via capacitor C2 (second capacitor). The source of NFETM3 (third FET) is connected to ground (reference potential), the drain is connected to node N1, and the gate is connected to control terminal TC3, which receives the control signal VC3. The control circuit 18a receives the control signal Sh output by the control unit 14 in Figure 1. The control circuit 18a controls the states of PFETM1, NFETM2, and NFETM3 by changing the levels of control signals VC1, VC2, and VC3 at timings based on the control signal Sh.

[0038] Figure 4 is a timing chart showing the time changes of each voltage and on / off state of the switch circuit shown in Figure 3. As shown in Figure 4, between times t10 and t11, which is the period during which switch HSW remains in the off state, the control circuit 18a sets control signal VC1 to a high level H (voltage X), control signal VC2 to a high level H, and control signal VC3 to a low level L. Since NFETM2 is in the on state, voltage G1 is voltage Vin, and PFETM1 is in the off state.

[0039] The control unit 14 in Figure 1 detects the voltage Vin at the input terminal Tin, and at time t01 in Figure 2, if it determines that the voltage Vin exceeds a predetermined threshold voltage, it outputs a control signal Sh instructing the switch HSW to switch from the off state to the on state. The control unit 14 may also output a control signal Sh to switch the switch HSW from the off state to the on state at a predetermined period. When the control signal Sh instructs the switch HSW to switch from the off state to the on state, between times t11 and t13, the control circuit 18a performs an operation to switch PFETM1 from the off state to the on state. At time t11, the control circuit 18a sets the control signal VC2 to a low level L, the control signal VC3 to a high level H, and maintains the control signal VC1 at a high level H. As a result, NFETM2 is turned off and NFETM3 is turned on. Current Im3 flows from node N1 to ground. When the voltage difference between node N1 and ground is in the saturation region of NFETM3 (the region where the drain current saturates), the current Im3 is almost constant regardless of the voltage difference between node N1 and ground. As a result, the voltage G1 at node N1 gradually decreases due to the current Im3 between times t11 and t12 in Figure 4.

[0040] When control circuit 18a determines that a predetermined period has elapsed from time t11, at time t12, it sets control signal VC3 to a low level L, maintains control signal VC1 at a high level H, and maintains control signal VC2 at a low level L. NFETM3 is turned off. Between times t12 and t13, voltage G1 is approximately constant. When control circuit 18a determines that a predetermined period has elapsed from time t12, at time t13, it sets control signal VC1 to a low level L, maintains control signal VC3 at a low level L, and maintains control signal VC2 at a low level L. As a result, voltage G1 becomes lower than voltage Vin by a voltage difference X (the difference between the high level H and low level L of control signal VC1), becoming voltage Vin-X. PFETM1 is turned on. Current IP flows through inductor L1 in Figure 1 and gradually increases from time t12 onwards. Thus, NFETM2 is off when PFETM1 remains on. Although node N1 becomes floating after time t12, if the interval between time t12 and t13 is short, for example, a few microseconds, the fluctuation of voltage G1 will not be a practical problem. In order to set voltage G1 to voltage Vin-X, it is preferable that the timing of setting control signal VC1 to a low level L is after the timing of setting control signal VC3 to a low level L.

[0041] As described above, according to Embodiment 1, when the control circuit 18a turns the PFETM1 from the off state to the on state, it charges or discharges node N1 through the resistor (NFETM3) (between times t11 and t12). After that, node N1 is made floating (time t12), and after a predetermined time, the control signal VC1 is set to a low level L (second level that turns the PFETM1 on) (time t13). As a result, the PFETM1 turns on. Although current flows through NFETM3 between times t11 and t12, NFETM3 is in the off state from time t13 onwards, so the potential of node N1 is floating. Therefore, no current flows between terminal Tsw1 and ground. Thus, compared to the case in Patent Document 1, where current continues to flow through resistors R2 and R3 during the period when the MOSFET (M1) (see Figure 1 of Patent Document 1) is on, power consumption can be suppressed.

[0042] Furthermore, when the control circuit 18a switches PFETM1 from the off state to the on state, it switches NFETM2 to the off state, disconnects node N1 from terminal Tsw1 (time t11), and then connects node N1 to ground via NFETM3 (between times t11 and t12). Subsequently, the control circuit 18a disconnects node N1 from ground (time t12) and supplies a low level L to control terminal TC1 (time t13). As a result, the voltage G1 can be stably set to voltage Vin-X due to the decrease in voltage G1 due to the capacitive coupling of capacitor C1 and the decrease in voltage G1 due to the current Im3 of NFETM3. Therefore, PFETM1 can be stably switched from the off state to the on state. As a result, the voltage conversion circuit 12 operates stably when it should operate, and the conversion efficiency can be improved.

[0043] In this embodiment, a PFET may be used for the third FET corresponding to NFETM3. To use a PFET for the third FET, the control signal VC3 that turns the first switch ON will be a voltage G1-X. Since the voltage G1 fluctuates as shown in the graph in Figure 4, a generation circuit should be provided to generate the control signal VC3 in accordance with the fluctuation of voltage G1. On the other hand, if an NFET is used for the third FET corresponding to NFETM3, the control signal VC3 only needs to be a constant voltage (high level H) relative to ground when turning the third FET ON, making the generation of the control signal VC3 easy. Therefore, the first switch can be stably turned ON at a predetermined timing. When an NFET is used for the first switch, the aforementioned generation circuit is not necessary compared to when a PFET is used, and the power consumption of that generation circuit does not increase the power consumption of the entire power supply circuit. Furthermore, when an NFET is used for the third FET, the control circuit 18a is configured to output a control signal VC3 that is a voltage value set so that a saturation current flows between the source and drain of NFETM3 when the control signal VC3 is high level H (first level). This allows the current Im3 to be kept constant regardless of the voltage difference between node N1 and ground. Therefore, by setting the interval between times t11 and t12, the decrease in voltage G1 from time t11 to time t12 can be kept almost constant, regardless of the voltage value of voltage Vin. Therefore, the voltage G1 at time t13 can be made approximately equal to voltage Vin-X, regardless of the voltage value of voltage Vin. Therefore, PFETM1 can be stably switched from the off state to the on state. As a result, the voltage conversion circuit 12 operates when it should operate, improving the conversion efficiency.

[0044] In this embodiment, a PFET may be used for the second FET corresponding to NFETM2. To use a PFET for the second FET, a generation circuit is required to generate a voltage Vin-X as the control signal VC2 that turns on the second FET. On the other hand, if an NFET is used for the second switch corresponding to NFETM2, the control signal VC2 only needs to be a constant voltage (high level H) relative to voltage G1 or ground when turning on the second FET, making the generation of the control signal VC2 easy. Therefore, the second FET can be stably turned on at a predetermined timing. When an NFET is used for the second FET, the aforementioned generation circuit is not necessary compared to when a PFET is used, and the power consumption of that generation circuit does not increase the power consumption of the entire power supply circuit.

[0045] In the above embodiment 1, the first FET, PFETM1 in Figure 3, has a first terminal Tsw1 connected to the power generation element 10, a second terminal Tsw2, a source connected to the first terminal Tsw1, a drain connected to the second terminal Tsw2, and a gate connected to a first node N1 that is capacitively coupled to the first control terminal TC2.

[0046] When the first FETM1 maintains either the off state or the on state, a first level is supplied to the first control terminal TC1 that causes the first FETM1 to be in either of the aforementioned states. When the first FETM1 is changed from either of the aforementioned states to the other state of the off state or the on state, the first node N1 is charged or discharged via a resistor, and then the first node N1 is made floating. The control circuit 18a that supplies the first FETM1 to the first control terminal TC1 that causes the first FETM1 to be in the other state is composed of the control circuit 18a that supplies NFETM2, NFETM3, and VC1, VC2, VC3.

[0047] In this embodiment, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component included in the electromotive force output from the power generation element 10 and the rectifier circuit 11. However, the power consumption of FETM1 to M3 increases in proportion to the increase in the frequency of the control signal Sh. Therefore, in order to transmit the power generated in the power generation element 10 to the subsequent capacitor C02 as efficiently as possible, it is preferable that the frequency of the control signal Sh be low.

[0048] Furthermore, as described above, in this embodiment 1, the control signal Sh is generated at a constant period. However, instead of a constant period, the control signal Sh may be generated when the comparator detects that the voltage of the secondary capacitor C02 (node ​​N04) has reached a predetermined voltage necessary to drive the load. Alternatively, the control signal Sh may be generated when the comparator detects that the voltage of the primary capacitor C01 (node ​​N01) has reached a predetermined voltage. In Figure 4, the control signal VC3 may become high level H after the switch SW5 is turned off.

[0049] In Modification 1 of Example 1, the control terminal TC2 and the gate of NFETM2 are capacitively coupled. As a result, when the control circuit 18a switches the control signal VC2 from a low level L to a high level H, the voltage G2 at the gate of NFETM2 becomes high level H. This turns NFETM2 on. However, because the gate of NFETM2 is floating, the voltage G2 is unstable. [Examples]

[0050] In Example 1, depending on the period during which the control signal VC1 is set to high and low levels, or the circuit constants such as the saturation current value between the source and drain of NFETM3, the voltage G2 may not be stable during the period when the gate of NFETM2 is floating. In this case, the operation of switch HSW(PFETM1) may not be stable, and the power supply circuit as a whole may not perform as desired. Example 2 describes a switch circuit that performs as desired as a power supply circuit even in such a case.

[0051] Figure 5 is a detailed circuit diagram of the switch circuit constituting the power supply circuit of Embodiment 2, and is a circuit diagram showing the details of the switch shown as HSW in Figure 1 and its control circuit. As shown in Figure 5, in the switch circuit 26 of Embodiment 2, the control signal VC2 is input to one end of the capacitor C2 (second capacitor), and the other end is connected to node N2 (second node). The diode D (rectifier element) has an anode connected to node N1 and a cathode connected to node N2 between NFETM2 and capacitor C2. The direction from node N1 to N2 is the forward direction. The drain of NFETM3 is connected to node N1 via node N2 and diode D. NFETM2 (second FET) has a source connected to node N1, a drain connected to terminal Tsw1, and a gate connected to node N2 which is capacitively coupled to the control terminal TC2 (second control terminal). The other configurations as a power supply circuit are the same as in Embodiment 1 and are omitted from the description.

[0052] Figure 6 is a timing chart showing the time changes of each voltage and on / off state of the switch circuit shown in Figure 5. As shown in Figure 6, between times t10 and t11, when the switch HSW is in the off state, the control circuit 18b sets the control signal VC1 to a high level H (voltage X), the control signal VC2 to a low level L, and the control signal VC3 to a low level L. In the same state as from time t16 onward, voltage G1 is set to voltage Vin. Voltage G2 becomes voltage Vin - ΔV. ΔV is the forward voltage drop across diode D.

[0053] When the control signal Sh instructs switch HSW to switch from the off state to the on state, between times t11 and t13, the control circuit 18b switches PFETM1 from the off state to the on state. At time t11, the control circuit 18b raises the control signal VC3 to a high level H, while maintaining the control signals VC1 and VC2 at a high level H and a low level L, respectively. As a result, NFETM3 turns on, and current Im3 flows from nodes N2 and N1 to ground. Between times t11 and t12, the voltage G2 decreases due to the current Im3, and the voltage G1 decreases as current flows from node N1 to N2 through diode D.

[0054] At time t12, control circuit 18b sets control signal VC3 to a low level L, and maintains control signals VC1 and VC2 at high level H and low level L, respectively. NFETM3 is turned off. Voltage G2 becomes VG2. Voltage G1 becomes VG2 + ΔV. Between times t12 and t13, voltage G1 is approximately constant. At time t13, control circuit 18b sets control signal VC1 to a low level L, and maintains control signals VC2 and VC3 at low levels L. As a result, voltage G1 becomes voltage Vin - X. PFETM1 is turned on, and current IP flows. Between times t13 and t14, while switch HSW remains in the ON state, control circuit 18b sets control signals VC1 to VC3 to a low level L.

[0055] The control unit 14 in Figure 1 detects the voltage Vin at the input terminal Tin, and at time t02 in Figure 2, when it determines that the voltage Vin has reached a predetermined threshold voltage, it outputs a control signal Sh instructing the switch HSW to switch from the ON state to the OFF state. The control unit 14 may also output a control signal Sh that switches the switch HSW from the ON state to the OFF state at a predetermined period. When the control signal Sh instructs the switch HSW to switch from the ON state to the OFF state, between times t14 and t16, the control circuit 18b executes the operation to switch PFETM1 from the ON state to the OFF state. At time t14, the control circuit 18b sets the control signal VC2 to a high level H, and maintains the control signals VC1 and VC3 at a low level L. Between times t14 and t15, the voltage G2 at node N2 capacitively coupled to the control terminal TC2 rises. As NFETM2 turns ON, the voltage G1 gradually rises. When voltage G1 rises above the threshold voltage of PFETM1, PFETM1 turns off and current IP becomes 0. If the time at which voltage G1 rises above the threshold voltage of PFETM1 is later than time t14, PFETM1 turns on at a time later than time t14.

[0056] At time t15, control circuit 18b sets control signal VC2 to a low level L and maintains control signals VC1 and VC3 at low levels L. Voltage G2 decreases. When voltage G2 falls below voltage G1-ΔV, current flows from node N1 to N2 through diode D. As a result, voltage G1 decreases slightly, voltage G2 increases slightly, and voltages G1 and G2 reach a balanced voltage state.

[0057] At time t16, control circuit 18b sets control signal VC1 to a high level H and maintains control signals VC2 and VC3 at a low level L. The voltage G1 at node N1, which is capacitively coupled to control terminal TC1, rises. Current flows from node N1 to N2 through diode D, and the voltage G2 rises. Voltage G1 becomes voltage Vin to fully turn on NFETM2. Voltage G2 becomes voltage Vin-ΔV. As voltage G2 stabilizes, voltage G1 stabilizes, and PFETM1 stabilizes in the off state.

[0058] According to Embodiment 2, in addition to when PFETM1 is turned on from the off state, the control circuit 18b charges or discharges node N2 through the resistor (i.e., the resistor between the source and drain of NFETM2) when PFETM1 is turned off from the on state (between time t14 and time t15). After that, the control circuit 18b makes node N2 floating ( At time t15, a low level L is supplied to the control terminal TC2 (at time t16). In this way, In Embodiment 2, when PFETM1 maintains either the off state or the on state, the control circuit 18b supplies a first level potential (a level that causes PFETM1 to be in either the off state or the on state) to the control terminal TC1. When changing PFETM1 from either the off state or the on state to the other off state or on state, the control circuit 18b charges or discharges node N1 through the resistor (between times t11 and t12 and between t14 and t15). Subsequently, the control circuit 18b makes node N1 floating (between times t12 and t15) and supplies a second level potential (a level that causes PFETM1 to be in either the off state or the on state) to the control terminal TC1 (between times t13 and t16).

[0059] Thus, the PFETM1 (switch element) is an electric field controlled switch element whose on and off states are switched according to the potential (voltage G1) of the gate, which is the control terminal. The control circuit 18a supplies a first level of potential to the gate to cause the PFETM1 to be in either the off or on state when maintaining the state of the PFETM1. When changing the PFETM1 from one of the above states to the other state of the off or on state, the gate is charged or discharged through a resistor and then made floating, and a second level of potential is supplied to cause the PFETM1 to be in the other state. As a result, when the PFETM1 is maintained in either the on or off state, node N1 is floating, and therefore power consumption can be suppressed.

[0060] Furthermore, in Embodiment 2, a capacitor C2, a diode D, and an NFETM2 are provided as a maintenance circuit to maintain voltage G1 within a predetermined range. As a result, when PFETM1 is switched from the off state to the on state, if NFETM3 is switched on between time t11 and t12, current flows from node N1 to ground through diode D and node N2, causing voltages G1 and G2 to decrease. Therefore, NFETM2 can be switched from the on state to the off state, and PFETM1 can be switched from the off state to the on state, regardless of the voltage value of voltage Vin.

[0061] The control circuit 18b supplies a low level L (second level) to control terminal TC1 and a low level L (third level that turns NFETM3 off) potential to control terminal TC2 when PFETM1 remains in the ON state, such as at times t13 and t14. Path 18b supplies a high-level H (the fourth level that turns NFETM3 on) potential to control terminal TC2 when turning PFETM1 from the ON state to the OFF state, as in the case of time t14 to t16. Subsequently, it supplies a low-level L (the third level) to control terminal TC2, and then supplies a high-level H (the first level) to control terminal TC1. When the control signal VC2 becomes high-level H, the voltage G2 rises, turning NFETM2 on and increasing voltages G1 and G2. Subsequently, by setting the control signal VC1 to high-level H, the voltage G1 can be further increased. This allows voltage G1 to be stabilized at voltage Vin and voltage G2 at voltage Vin + ΔV.

[0062] When the control circuit 18b switches the PFETM1 from the ON state to the OFF state, it first supplies a low level L (third level) to the control terminal TC2 at time t15, and then supplies a high level H (first level) to the control terminal TC1 at time t16, after a predetermined time has elapsed. This allows the high level H (second level) to be supplied to the control terminal TC1 after the transient response of the voltage G2 across the capacitor C2 has stabilized. As a result, voltages G1 and G2 become more stable. This allows the PFETM1 to be switched off stably when switching it from the ON state to the OFF state. Therefore, unintended current flow in the voltage conversion circuit 12 can be suppressed, and the conversion efficiency of the voltage conversion circuit 12 can be improved.

[0063] The high level H of the control signal VC2 is, for example, 2V, and the high level H of the control signal VC1 is, for example, 1V. Thus, it is preferable that the high level H of the control signal VC2 is higher than the high level H of the control signal VC1. This allows the voltage G2 to be increased further between times t14 and t15. This allows the PFETM1 to be turned off more stably, thereby improving the conversion efficiency of the voltage conversion circuit 12. [Examples]

[0064] Figure 7 is a detailed circuit diagram of the switch circuit constituting the power supply circuit of Embodiment 3, and is a circuit diagram showing the details of the switch shown as HSW in Figure 1 and its control circuit. In Embodiments 1 and 2, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component included in the electromotive force output from the power generation element 10 and the rectifier circuit 11. The power consumption of FETM1 to M3 increases in proportion to the increase in the frequency of the control signal Sh. For this reason, in order to transmit the power generated in the power generation element 10 to the downstream capacitor C02 as efficiently as possible, it is preferable that the frequency of the control signal Sh be low. However, if the electromotive force of the power generation element 10 is large, and the switch HSW is off during the intervals between the high and low levels of the control signal Sh, that is, during the period when node N1 is set to provide a floating voltage such that no current flows between the source and drain of FETM1, then if the voltage Vin rises significantly (for example, to 0.3V or more), and becomes a voltage at which a minute current flows between the source and drain of FETM1, then the charge of capacitor C01 will not contribute to voltage conversion by the amount of that minute current, and there is a risk that the voltage conversion efficiency will decrease.

[0065] In view of such concerns, and in order to further improve the voltage conversion efficiency, as shown in Figure 7, the switch circuit 27 of Example 3, the determination circuit 15, comprises a comparator 16, an NFETM4, and a capacitor C3, and outputs a reset signal Vr to the control circuit 18c when the voltage Vin fluctuates above Vref. This reset signal Vr resets the gate potential of the PFETM1 to the same potential as the voltage Vin, similar to the control signal Sh of Example 2. In Figure 7, one end of the capacitor C3 is connected to node N4 between the source of the PFETM1 and terminal Tsw1, and the other end is connected to node N3 (third node). That is, node N3 is capacitively coupled to terminal Tsw1. The NFETM4 has a source connected to ground, a drain connected to node N3, and a gate connected to control terminal TC4 to which the control signal VC4 is input. The comparator 16 has a positive input terminal connected to node N3, a negative input terminal to which the reference voltage Vref is input, and an output terminal to which the reset signal Vr is output. Comparator 16 outputs a high-level H as a reset signal Vr when the voltage Vm at node N3 is greater than or equal to the reference voltage Vref, and outputs a low-level L as a reset signal Vr when the voltage Vm is less than the reference voltage Vref. The reference voltage Vref is, for example, 0.3V.

[0066] The control circuit 18c receives the control signal Sh output by the control unit 14 and the reset signal Vr output by the comparator 16. Based on the control signal Sh and the reset signal Vr, the control circuit 18c outputs control signals VC1 to VC4. The other configurations are the same as in Embodiment 2 and will not be described.

[0067] Figure 8 is a timing chart showing the time changes of each voltage, current, and on / off state of the switch circuit shown in Figure 7. As shown in Figure 8, the input current Iin input from the rectifier circuit 11 to terminal Tsw1 changes depending on the amount of power generated by the power generation element 10, but here it is set to a very small Iin1 until time t20, and to Iin2 from time t20 onward. Current Iin1 has almost no effect on voltage Vin etc. in this timing chart. Therefore, the voltage Vin from time t10 to t13 and from t14 to t20 is almost constant. Between time t13 and t14, the voltage Vin decreases slightly because charge moves from capacitor C1 to C2. The changes in other control signals VC1~VC3, voltages G1, G2, and current IP between time t10 to t16 are the same as in Figure 6 of Example 2, so the explanation is omitted. As will be described later, NFETM4 turns on at a predetermined timing, so the voltage Vm at time t10 is 0. Between times t10 and t16, the control signal VC4 is at a low level L, and the reset signal Vr remains at a low level L.

[0068] After time t20, as the current Iin from the power generation element 10 increases to Iin2 and the voltage Vin gradually rises from voltage Vin0, the voltage at node N4 gradually increases. The voltage Vm at node N3, which is capacitively coupled to node N4, gradually rises from 0.

[0069] At time t21, the control circuit 18c detects the voltage Vin at terminal Tsw1. When voltage Vin exceeds voltage Vin0 + Vref, voltage Vm exceeds the reference voltage Vref, and comparator 16 outputs a high level H as a reset signal Vr. When the reset signal Vr becomes high level H, the control circuit 18c sets control signal VC1 to a low level L and control signal VC2 to a high level H, while maintaining low levels L for control signals VC3 and VC4. The voltage G1 at node N1 capacitively coupled to control terminal TC1 decreases. The voltage G2 at node N2 capacitively coupled to control terminal TC2 increases. Note that the timing of setting control signal VC1 to a low level L and the timing of setting control signal VC2 to a high level H may differ slightly within the range in which the above operation is possible.

[0070] Between times t21 and t22, current flows from node N1 to N2 through diode D, causing voltages G1 and G2 to rise slightly. At time t22, control circuit 18c sets control signal VC2 to a low level L and maintains low levels L for control signals VC1, VC3, and VC4. Voltage G2 at node N2, which is capacitively coupled to control terminal TC2, decreases. Current flows from node N1 to N2 through diode D, causing voltage G1 to decrease slightly. At time t23, control circuit 18c sets control signals VC1 and VC4 to a high level H and maintains low levels L for control signals VC2 and VC3. Just as voltage G1 became voltage Vin0 at time t16, voltage G1 becomes Vin0+Vref, which is the voltage of voltage Vin. NFETM4 turns on, and the voltage Vm at node N3 becomes 0V. Note that the timing at which the control signal VC1 is set to a high level H and the timing at which the control signal VC4 is set to a high level H may differ slightly, as long as the voltage Vm at node N3 can be appropriately set to 0V. At time t24, the control circuit 18c sets the control signal VC4 to a low level L, maintains the high level H of the control signal VC1, and maintains the low levels L of the control signals VC2 and VC3.

[0071] In the switch circuit of Embodiment 2 described in Figure 5, at time t16, when voltage Vin is voltage Vin0, if PFETM1 switches from the on state to the off state, voltage G1 is voltage Vin0, the voltage difference between the source and gate of PFETM1 is approximately 0, and PFETM1 is in the off state. Subsequently, even if voltage Vin is not high after time t20, voltage G1 remains at voltage Vin0. As a result, the gate voltage becomes lower than the source voltage of PFETM1. This can cause PFETM1 to turn on. When PFETM1 turns on, current flows through PFETM1, reducing the conversion efficiency of the voltage conversion circuit 12.

[0072] The comparator 16 compares the voltage Vm at node N3 with the reference voltage Vref and outputs the comparison result to the control circuit 18c. This allows the determination circuit 15 to determine whether the voltage Vin has changed by a constant voltage corresponding to the reference voltage Vref to a higher voltage (further from the reference potential 0V) than the voltage Vin0.

[0073] According to Embodiment 3, the determination circuit 15 determines that when the PFETM1 is in the off state, the voltage Vin has changed by a certain voltage (Vref) to a higher voltage (further from the reference potential 0V) than the voltage Vin0 (the voltage when the PFETM1 last switched from the on state to the off state). When the control circuit 18c determines that the voltage Vin has changed by a certain voltage (Vref), it supplies a low level L (second level) to the control terminal TC1 and a high level H (fourth level) to the control terminal TC2, and then supplies a high level H (first level) to the control terminal TC1 and a low level L (third level) to the control terminal TC2. As a result, when the voltage Vin becomes higher than or equal to the reference voltage Vref from the voltage Vin0, the gate voltage G1 of the PFETM1 can be set back to the voltage Vin. Therefore, when the voltage Vin rises above voltage Vin0, it is possible to suppress the flow of a small current between the source and drain of FETM1 during the period when FETM1 is normally controlled to be in the off state, thereby suppressing the outflow of charge from the primary capacitor. This prevents a decrease in the conversion efficiency of the voltage conversion circuit 12.

[0074] In Example 3, the control signal Sh has a constant period, and as mentioned above, a lower frequency is preferable. However, when the control signal SH and the reset signal Vr occur almost simultaneously, the operation according to the control signal Sh takes precedence. [Examples]

[0075] Example 4 is an example where the input voltage Vin from the power generation element 10 is low relative to the ground potential. Figure 9 is a detailed circuit diagram of the switch circuit that constitutes the power supply circuit of Example 4, and is a circuit diagram showing the details of the switch and its control circuit, which are shown as HSW in Figure 1. As shown in Figure 9, in the switch circuit 28 of Example 4, NFETM1a, PFETM2a, M3a, and M4a are used instead of PFETM1, NFETM2, M3, and M4 of Figure 7 of Example 3, respectively. The cathode of diode D is connected to node N1 and the anode is connected to node N2, and the direction from node N2 to N1 is the forward direction. The negative input terminal of comparator 16a is connected to node N3, and the reference voltage Vref is input to the positive input terminal. The control circuit is 18d. The other configurations are the same as in Figure 7 of Example 3 and are omitted from the explanation. The high level H and low level L of the control signals VC1~VC4 are the opposite of those in Figure 8. Voltage X, voltage Vin0, and reference voltage Vref are negative.

[0076] As in Examples 1 to 3, when the input voltage Vin is higher than ground (reference potential), the first FET is PFETM1, and the second and third FETs are NFETM2 and M3, respectively. The first and fourth levels are high levels (H), and the second and third levels are low levels (L). On the other hand, when the input voltage Vin is lower than ground (reference potential), the first FET is NFETM1a, and the second and third FETs are PFETM2a and M3a, respectively. The first and fourth levels are low levels (L), and the second and third levels are high levels (H). Thus, the second and third FETs are NFETs and PFETs, respectively, with channel conductivity types opposite to that of the first FET.

[0077] In Examples 1 to 4, the PFET is in the off state when the gate voltage (voltage at the gate relative to the source) is 0V, and turns on when the gate voltage falls below a negative threshold voltage. The NFET is in the off state when the gate voltage is 0V, and turns on when the gate voltage rises above a positive threshold voltage. The PFET and NFET are, for example, MOS (Metal Oxide Semiconductor) FETs using silicon. Diode D is, for example, a diode for the FET. This is a connected diode. Although an FET was used as an example of a switching element in the explanation, any field-effect element in which the potential of its control terminal (gate) operates in a floating state can be applied to Examples 1 to 4. The switching element should be a field-effect switching element in which the on and off states of the conductive channel are switched according to the electric field formed in the conductive channel by the potential applied to the control terminal. For example, a bipolar transistor or IGBT (Insulated Gate Bipolar Transistor) combined with an FET may also be used. .

[0078] For control signals VC1 to VC4, the high level and low level only need to be a higher voltage than the low level for the same control signal. The high level voltages of different control signals may be different from each other, and the low levels may also be different from each other.

[0079] By using the switches from Examples 1 to 4 in the voltage conversion circuit 12 shown in Figure 1, the switches in the voltage conversion circuit 12 can be stably controlled. In Figure 1, an example of a step-down / step-up voltage conversion circuit is shown as the power supply circuit, but the power supply circuit may also be a step-down voltage conversion circuit, a step-up voltage conversion circuit, or an inverting voltage conversion circuit. Furthermore, the power supply circuit may also be a power conversion circuit that converts AC to DC, etc.

[0080] Figure 10(a) is a block diagram showing an embodiment of the power supply circuit of the present invention, in which a switch circuit from any of Embodiments 1 to 4 or a modified version thereof is used in the voltage conversion circuit 64. As shown in Figure 10(a), the system comprises a power generation element 60, rectifier circuits 61 and 62, matching circuit 63, voltage conversion circuit 64, charge management circuit 65, capacitor 66, cold start circuit 67, and boost circuit 68.

[0081] The power generation element 60 is, for example, the power generation element 10 in Figure 1, and generates alternating current power with a small current. The rectifier circuit 61 is, for example, a diode bridge, and the rectifier circuit 62 is, for example, a synchronous rectifier circuit. The matching circuit 63 matches the output impedance of the rectifier circuits 61 and 62 with the input impedance of the voltage conversion circuit 64. The voltage conversion circuit 64 is, for example, the voltage conversion circuit 12 in Figure 1, and is a DC-DC converter. The charge management circuit 65 stores power in an appropriate capacitor 66 from among several capacitors 66. A capacitor 66 is, for example, a capacitor. The charge management circuit 65 monitors the voltage across the multiple capacitors and charges the appropriate capacitor with the generated power. The cold start circuit 67 charges the capacitor 66 with the output current of the rectifier circuit 61 when the capacitor 66 is almost empty. The boost circuit 68 is, for example, a charge pump, and generates the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64, etc.

[0082] The system operation will now be described. When the power generation element 60 generates a small amount of power when the capacitor 66 is almost empty, the rectifier circuit 61 rectifies the small amount of power. The rectifier circuit 61 can perform rectification without an external power source, like a diode bridge. The current rectified by the rectifier circuit 61 goes through the cold start circuit 67 to the charge management circuit 65 and is stored in the capacitor 66. When the capacitor 66 is charged to a sufficient voltage, the boost circuit 68 boosts the voltage from the capacitor 66 to the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64. The voltage of the capacitor 66 is, for example, 1V, and the output voltage of the boost circuit 68 is, for example, 2V. If the rectifier circuit 62 and the voltage conversion circuit 64 operate using the voltage of the capacitor 66, the boost circuit 68 may not be necessary.

[0083] The matching circuit 63 increases the input power when the power generation of the power generation element 60 is large and the generated current is large, and increases the input power when the power generation of the power generation element 60 is small and the generated current is small. This matches the output impedance of the power generation element 60 with the input impedance of the rectifier circuits 61 and 62. The matching circuit 63 switches between the rectifier circuits 61 and 62 depending on the input voltage. For example, if the rectifier circuits 61 and 62 are a diode bridge and a synchronous rectifier circuit, respectively, the loss due to the on-voltage of the diode becomes large when the input voltage is 1V or less. For this reason, the rectifier circuit 62 is used. When the input voltage is 1V or more, the rectifier circuit 61 is used.

[0084] The voltage conversion circuit 64 converts the input voltage set by the matching circuit 63 into a voltage that the capacitor 66 charges. The voltage of the capacitor 66 is, for example, 1V or 3.3V. The charge management circuit 65 monitors the voltages of multiple capacitors 66 and charges the appropriate capacitor 66 with the generated power.

[0085] In a system using a power generation element 60 that generates such minute amounts of power, the input voltage of the voltage conversion circuit 64 changes. As a result, the high-side switch HSW (see Figure 1) of the voltage conversion circuit 64 may not operate stably, and the conversion efficiency of the voltage conversion circuit 64 may decrease. By using the switch circuits of Examples 1 to 4 as the switch HSW of the voltage conversion circuit, the switch HSW can be controlled stably, and the decrease in the conversion efficiency of the voltage conversion circuit 64 can be suppressed.

[0086] Figure 10(b) is a block diagram showing a sensor circuit system in which any of the switch circuits of Examples 1 to 4 or their modified versions are used. As shown in Figure 10(b), the switch element of the switch circuit 71 in Examples 1 to 4 switches the power supply from the power source 70 to the sensor circuit 72 on and off. Thus, the switch element of the switch circuit in Examples 1 to 4 is not limited to an element that switches the electromotive force supplied from the power generation element on and off. The switch circuits in Examples 1 to 4 may also be used in circuits other than power supply circuits, such as low-power IoT (Internet of Things) devices or edge devices.

[0087] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of symbols]

[0088] 10 Power generation element 12 Voltage conversion circuit 14 Control Unit 16 Comparator 18a~18d Control circuits

Claims

1. A first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, wherein the on state and off state are switched according to the potential of the gate, A second FET having a source connected to the first node, a drain connected to the first terminal, and a gate, A control circuit that, when maintaining the off state of the first FET, supplies a first level potential to the first node to turn off the first FET, and when turning the first FET from the off state to the on state, turns off the connection between the source and drain of the second FET, connects the first node to a reference potential via a resistor to charge or discharge the first node, then disconnects the first node from the first terminal and the reference potential to make the first node floating, and supplies a second level potential to the first control terminal to turn on the first FET, A switch circuit equipped with this feature.

2. The third FET comprises a source connected to the reference potential, a drain connected to the first node, and a gate. The switch circuit according to claim 1, wherein the resistor is the resistance between the source and drain of the third FET, and a saturation current flows through the third FET when the first node is connected to the reference potential via the second FET.

3. The device includes a rectifier element whose direction is forward when the second node capacitively couples from the first node to the second control terminal, The second FET is of type N, and the gate of the second FET is connected to the second node. The first FET is of type P, The switch circuit according to claim 1, wherein the first node is connected to the reference potential via the rectifier element, the second node, and the resistor.

4. The device includes a rectifier element whose direction from the second node, which is capacitively coupled to the second control terminal, to the first node is forward. The second FET is of type P, and the gate of the second FET is connected to the second node. The first FET is of type N, The switch circuit according to claim 1, wherein the first node is connected to the reference potential via the rectifier element, the second node, and the resistor.

5. The switch circuit according to claim 3, wherein the control circuit supplies the second level potential to the first control terminal and the second level potential to the second control terminal to turn off the second FET when the first FET is kept in the ON state, supplies the second level potential to the second control terminal to turn on the second FET when the first FET is turned off from the ON state, and thereafter supplies the first level potential to the first control terminal and the third level potential to the second control terminal.

6. The switch circuit according to claim 5, wherein the control circuit supplies the third level potential to the second control terminal and then supplies the first level potential to the first control terminal when switching the first FET from an ON state to an OFF state.

7. The circuit includes a determination circuit that determines whether the input voltage input to the first terminal has changed by a certain voltage from the input voltage when the first FET last switched from the ON state to the OFF state, while the first FET remains in the OFF state. The switch circuit according to claim 5, wherein the control circuit determines that the input voltage has changed to a constant voltage, supplies the second level to the first control terminal and the fourth level to the second control terminal, and thereafter supplies the first level to the first control terminal and the third level to the second control terminal.

8. The aforementioned determination circuit is The switch circuit according to claim 7, further comprising a comparator that compares the voltage of a third node capacitively coupled to the first terminal with a constant voltage and outputs the comparison result to the control circuit.

9. The switch circuit according to claim 1, wherein the input voltage input to the first terminal is higher than the reference potential, and the first FET is a PFET.

10. The switch circuit according to claim 1, wherein the input voltage input to the first terminal is lower than the reference potential, and the first FET is an NFET.

11. The switch circuit according to claim 1, further comprising a diode connected to the first node to maintain the potential of the first node within a predetermined range.

12. A first FET having a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively coupled to a first control terminal, wherein the on state and off state are switched according to the potential of the gate, A second FET having a source connected to the first node, a drain connected to the first terminal, and a gate connected to a second node capacitively coupled to a second control terminal, The system comprises a control circuit for controlling the first FET and the second FET, The aforementioned control circuit is When maintaining the ON state of the first FET, a first level potential is supplied from the first control terminal to the first node to turn on the first FET. When switching the first FET from an ON state to an OFF state, the first node and the second node are connected to the first terminal via a resistor to charge or discharge by supplying a potential to switch the source and drain of the second FET ON state, and then the first node and the second node are disconnected from the first terminal and made floating by supplying a potential to switch the source and drain of the second FET OFF state by supplying a potential to the second node via a resistor, and after being made floating, a second level potential is supplied to the first control terminal to switch the first FET OFF state. Switch circuit.

13. The first FET switches the electromotive force supplied from the power generation element on and off. The switch circuit according to claim 1 or 12.

14. The aforementioned power generation element is a vibration power generation element. The switch circuit according to claim 13.

15. The first FET switches the power supply to the sensor circuit on and off. The switch circuit according to claim 1 or 12.

16. A power supply circuit comprising the switch circuit according to claim 1 or 12.

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