Semiconductor device, time measurement method, and time measurement program

Abstract

To provide a semiconductor device, a time measurement method, and a time measurement program capable of reducing current consumption.SOLUTION: According to one embodiment, a semiconductor device 1 comprises a processor 10, a plurality of peripheral circuits 41 controlled by the processor 10, and a timing management circuit 50 for outputting, to the peripheral circuits 41, results of time measurement performed in response to a time measurement request from the peripheral circuits 41. The timing management circuit 50 performs time measurement in response to each time measurement request.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device, a time measurement method, and a time measurement program. [Background technology]

[0002] <000000> Non-patent document 1 contains a block diagram of hardware in a microcomputer. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] "RX660 Group User's Manual Hardware Edition," [online], March 2022, [Accessed February 24, 2023], Internet <https: / / www.renesas.com / jp / ja / document / mah / rx660-group-users-manual-hardware?r=<1618106> [Overview of the project] [Problems that the invention aims to solve]

[0004] The MCU (Microcontroller Unit) includes a clock generation circuit, timers, and communication IP (Intellectual Property), among other components. The clock generation circuit has an oscillation stabilization waiting circuit that waits until the oscillator's oscillation stabilizes. The oscillation stabilization waiting circuit has a function to measure the time it takes for the oscillator's oscillation to stabilize. Multiple peripheral circuits, such as timers and communication IP, each have a function to measure time. Each circuit can measure time simultaneously through its respective time measurement function.

[0005] When multiple circuits in an MCU perform time measurement simultaneously, current consumption increases. Furthermore, when many circuits are supplied with a clock signal for time measurement, the current consumption associated with the clock operation also increases.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] According to one embodiment, the semiconductor device comprises a processing unit, a plurality of peripheral circuits controlled by the processing unit, and a timing management circuit that outputs the results of time measurements performed in response to time measurement requests from the peripheral circuits to the peripheral circuits, wherein the timing management circuit performs time measurements in response to each of the time measurement requests.

[0008] According to one embodiment, the time measurement method is a time measurement method in a semiconductor device comprising a processing unit, a plurality of peripheral circuits controlled by the processing unit, and a timing management circuit that outputs the results of the time measurement performed in response to a time measurement request from the peripheral circuits to the peripheral circuits, wherein the method includes the step of causing the timing management circuit to perform the time measurement in response to each of the time measurement requests.

[0009] According to one embodiment, the time measurement program is a time measurement program for a semiconductor device comprising a processing unit, a plurality of peripheral circuits controlled by the processing unit, and a timing management circuit that outputs the results of the time measurement performed in response to a time measurement request from the peripheral circuits to the peripheral circuits, wherein the program causes a computer to perform the step of causing the timing management circuit to perform the time measurement in response to each of the time measurement requests. [Effects of the Invention]

[0010] According to the above embodiment, it is possible to provide a semiconductor device, a time measurement method, and a time measurement program that can reduce current consumption. [Brief explanation of the drawing]

[0011] [Figure 1]This is a block diagram illustrating a semiconductor device related to a comparative example. [Figure 2] This is a block diagram illustrating a semiconductor device related to a comparative example. [Figure 3] This is a block diagram illustrating the arithmetic processing unit, clock generation circuit, timer, and communication IP in a comparative example semiconductor device. [Figure 4] This is a block diagram illustrating a semiconductor device according to Embodiment 1. [Figure 5] This is a block diagram illustrating an oscillation stabilization waiting circuit in a semiconductor device according to a comparative example. [Figure 6] This is a block diagram illustrating an oscillation stabilization waiting circuit in a semiconductor device according to a comparative example. [Figure 7] This is a block diagram illustrating an oscillation stabilization waiting circuit and a timing management circuit in a semiconductor device according to Embodiment 1. [Figure 8] This is a block diagram illustrating the configuration of an oscillation stabilization waiting circuit in a semiconductor device relating to a comparative example. [Figure 9] This is a block diagram illustrating the configuration of the oscillation stabilization waiting circuit and the timing management circuit in the semiconductor device according to Embodiment 1. [Figure 10] This is a block diagram illustrating the arithmetic processing unit, memory device, timer, and timing management circuit in the semiconductor device according to Embodiment 1. [Figure 11] This is a block diagram illustrating a clock generation circuit, timer, peripheral circuit, and timing management circuit in a semiconductor device according to Embodiment 1. [Figure 12] This is a block diagram illustrating a timer in a semiconductor device relating to a comparative example. [Figure 13] This is a block diagram illustrating the relationship between a timer and a timing management circuit in a semiconductor device according to Embodiment 1. [Figure 14] This flowchart illustrates the procedure for setting the compare match timer operation in a semiconductor device relating to a comparative example. [Figure 15]It is a flowchart diagram illustrating the setting procedure of the compare match timer operation in the semiconductor device according to Embodiment 1. [Figure 16] It is a block diagram illustrating the semiconductor device according to Embodiment 1. [Figure 17] It is a block diagram illustrating the relationship between the clock generation circuit and the timing management circuit, and the relationship between the timing management circuit and the peripheral circuits in the semiconductor device according to Embodiment 1. [Figure 18] It is a block diagram illustrating the timing management circuit of the semiconductor device according to Embodiment 1. [Figure 19] It is a diagram illustrating the count operation of the timing management circuit in the case of a single request in which a time measurement request is received from one peripheral circuit in the semiconductor device according to Embodiment 1. [Figure 20] It is a diagram illustrating the count operation of the timing management circuit in the case of a multiple request in which time measurement requests are received from a plurality of peripheral circuits in the semiconductor device according to Embodiment 1. [Figure 21] It is a block diagram illustrating the clock generation circuit and the timing management circuit in the semiconductor device according to Embodiment 1. [Figure 22] It is a block diagram illustrating the connection relationship between the timing generation circuit and the peripheral circuits in the timing management circuit in the semiconductor device according to Embodiment 1. [Figure 23] It is a flowchart diagram illustrating the operation of the timing generation circuit in the semiconductor device according to Embodiment 1. [Figure 24] It is a diagram illustrating the count operation of the timing management circuit in the case of a single request in which a time measurement request is received from one peripheral circuit in the semiconductor device according to Embodiment 1. [Figure 25] It is a diagram illustrating the count operation of the timing management circuit in the case of a multiple request in which overlapping time measurement requests are received from a plurality of peripheral circuits in the semiconductor device according to Embodiment1. [Figure 26]This figure illustrates the counting operation of a timing management circuit involving clock signal switching in the case of multiple requests for time measurement, in a semiconductor device according to Embodiment 1, where multiple peripheral circuits simultaneously request time measurement. [Figure 27] This graph illustrates the current consumption during time measurement in a semiconductor device relating to a comparative example. The horizontal axis shows the configuration in which current-consuming components are stacked, and the vertical axis shows the current consumption. [Figure 28] This graph illustrates the current consumption during time measurement in the semiconductor device according to Embodiment 1. The horizontal axis shows a configuration in which current-consuming components are stacked, and the vertical axis shows the current consumption. [Figure 29] This is a block diagram illustrating a semiconductor device according to Embodiment 2. [Figure 30] This is a block diagram illustrating the arithmetic processing unit, clock generation circuit, timer, peripheral circuit, and timing management circuit in the semiconductor device according to Embodiment 3. [Modes for carrying out the invention]

[0012] For clarity, the following descriptions and drawings have been omitted and simplified as appropriate. Furthermore, the same elements are denoted by the same reference numerals in each drawing, and redundant explanations have been omitted where necessary.

[0013] First, in the <Comparative Example> section, the semiconductor device relating to the comparative example will be described. Then, in the <Problems Newly Identified by the Inventor> section, the problems newly identified by the inventor with respect to the semiconductor device of the comparative example will be described. Finally, in the <Embodiment 1> section, the semiconductor device relating to Embodiment 1 will be described. In addition, in <Embodiment 1>, the semiconductor device relating to Embodiment 1 will be compared with the semiconductor device of the comparative example as appropriate in order to clarify the features of the semiconductor device relating to Embodiment 1.

[0014] <Comparative Example> A semiconductor device relating to a comparative example will be described. Figures 1 and 2 are block diagrams illustrating a semiconductor device relating to a comparative example. Figure 1 is a block diagram extracted as an example of a part of the main components of Figure 2. As shown in Figure 1, the semiconductor device 101 of the comparative example comprises an arithmetic processing unit 110, an internal peripheral bus 111, a clock generation circuit 120, and a plurality of timers 130. The timer 130 has a register 131, a counter circuit 132, and a clock selection circuit 133. Note that the names "CPU," "INTERNAL PERIPHERAL BUS," "TIMER," "CLOCK GENERATION CIRCUIT," etc. shown in the drawings are examples and are not limited to these.

[0015] The arithmetic processing unit 110 is, for example, a CPU (Central Processing Unit). However, the arithmetic processing unit 110 is not limited to a CPU; it may also be an MPU (Micro Processor Unit) or other device, as long as it performs processing such as controlling other devices and circuits within the semiconductor device 101 and performing data calculations. The arithmetic processing unit 110 is connected to the internal peripheral bus 111 in a manner that allows for information transmission.

[0016] The clock generation circuit 120 generates a clock signal CLK. The clock signal CLK may include, for example, a signal that periodically repeats between a high-voltage state and a low-voltage state. The clock generation circuit 120 supplies the generated clock signal CLK to a plurality of timers 130.

[0017] The timer 130 is connected to the internal peripheral bus 111 in a state where it can transmit information. For example, each register 131 of multiple timers 130 is connected to the internal peripheral bus 111 in a state where it can transmit information. The register 131 controls the counter circuit 132 and the clock selection circuit 133.

[0018] The counter circuit 132 performs time measurement using the clock signal CLK. For example, the counter circuit 132 performs time measurement by counting the number of high-voltage and low-voltage states of the clock signal CLK. The counter circuit 132 outputs the counted number to the register 131 as the result of the time measurement.

[0019] The clock selection circuit 133 receives a clock signal CLK from the clock generation circuit 120. The clock selection circuit 133 selects a predetermined clock signal CLK from the received clock signal CLK. The clock selection circuit 133 selects the predetermined clock signal CLK through control by register 131. The clock selection circuit 133 supplies the selected clock signal CLK to the counter circuit 132. The clock selection circuit 133 may also control the generation of the clock signal CLK in the clock generation circuit 120.

[0020] As shown in Figure 2, the semiconductor device 101 may include an arithmetic processing unit CPU, an arithmetic processing unit MPU, a clock generation circuit 120, a storage device ROM, a storage device RAM, a trigonometric function unit TFU, an interrupt controller ICU, a data transfer controller DTC, a DMA controller DMAC, and a bus controller BSC. The semiconductor device 101 may also include circuits such as a timer TMR, a compare match timer CMTW, a temperature sensor, a comparator, and a D / A converter. Each circuit may be connected to a bus such as an instruction bus, an operant bus, an internal main bus (INTERNAL MAIN BUS1 and BUS2), and an internal peripheral bus (INTERNAL OERIPHERAL BUS) in a manner that enables information exchange.

[0021] Figure 3 is a block diagram illustrating a semiconductor device 101 according to a comparative example, showing an arithmetic processing unit 110, a clock generation circuit 120, a timer 130, and a communication IP 140. As shown in Figure 3, the semiconductor device 101 may include a plurality of communication IPs 140 in addition to the arithmetic processing unit 110, the clock generation circuit 120, and a plurality of timers 130. Furthermore, the semiconductor device 101 may include, for example, an MCU.

[0022] The clock generation circuit 120 may include oscillator A121a, oscillator B121b, and oscillation stabilization waiting circuit 123. The oscillation stabilization waiting circuit 123 has the function of waiting until the oscillations of oscillators A121a and B121b stabilize. The oscillation stabilization waiting circuit 123 has the function of measuring the time until the oscillations of oscillators A121a and B121b stabilize.

[0023] <New challenges identified by the inventor> Multiple peripheral circuits, such as the timer 130 and the communication IP 140, each have a time measurement function. Therefore, each circuit, such as the oscillation stabilization waiting circuit 123, the timer 130, and the communication IP 140, can simultaneously measure time using their respective time measurement functions. This configuration allows the semiconductor device 101 to improve the degree of freedom for parallel operation. However, operating the time measurement of each circuit in the semiconductor device 101 simultaneously increases current consumption. Furthermore, if the number of circuits supplied with the clock signal CLK for time measurement increases, the current consumption associated with clock operation also increases.

[0024] In recent years, with the demand for long-term operation using batteries and the addition of functions to MCUs, there has been a need for further reduction in power consumption of the semiconductor device 101. In the following embodiment, the current consumption is reduced by optimizing the redundant time measurement circuit.

[0025] <Embodiment 1> Next, a semiconductor device according to Embodiment 1 will be described. The semiconductor device of this embodiment has, for example, a circuit within the MCU that centrally performs time measurement. Furthermore, the semiconductor device of this embodiment has an interface that receives time measurement requests from peripheral circuits such as timers and communication IPs, and responds to the peripheral circuits with the results of the time measurement. In the following embodiments, such a circuit will be referred to as a timing management circuit.

[0026] Figure 4 is a block diagram illustrating a semiconductor device 1 according to Embodiment 1. As shown in Figure 4, the semiconductor device 1 includes an arithmetic processing unit 10, a clock generation circuit 20, a timer 30, a communication IP 40, and a timing management circuit 50. The clock generation circuit 20 may include an oscillator A21a, an oscillator B21b, and an oscillation stabilization waiting circuit 23. The timing management circuit 50 has a function to perform time measurement. The semiconductor device 1 may also include a plurality of peripheral circuits other than the timer 30 and the communication IP 40. The plurality of peripheral circuits are controlled by the arithmetic processing unit 10.

[0027] The clock generation circuit 20 generates a clock signal CLK, which serves as the reference for time measurement in the timing management circuit 50. The clock signal CLK generated from oscillator A21a in the clock generation circuit 20 may be supplied to the arithmetic processing unit 10 via the oscillation stabilization waiting circuit 23. The clock signal CLK generated from oscillator B21b may be supplied to the timing management circuit 50.

[0028] The timing management circuit 50 is connected to the clock generation circuit 20 in a manner that enables information transmission. Specifically, the timing management circuit 50 is connected to the oscillation stabilization waiting circuit 23 in a manner that enables information transmission. The timing management circuit 50 may also be connected to peripheral circuits including multiple timers 30 and multiple communication IPs 40 in a manner that enables information transmission.

[0029] The timing management circuit 50 controls the oscillation stabilization waiting circuit 23, while the oscillation stabilization waiting circuit 23 controls the timing management circuit 50. For example, the oscillation stabilization waiting circuit 23 requests the timing management circuit 50 to perform a time measurement. On the other hand, the timing management circuit 50 outputs the result of the time measurement to the oscillation stabilization waiting circuit 23.

[0030] Furthermore, the timing management circuit 50 controls multiple peripheral circuits, including multiple timers 30 and multiple communication IPs 40, while the multiple peripheral circuits control the timing management circuit 50. For example, peripheral circuits such as timers 30 and communication IPs 40 request time measurement from the timing management circuit 50. On the other hand, the timing management circuit 50 outputs the results of the time measurement performed in response to the time measurement requests from the peripheral circuits to the peripheral circuits.

[0031] Thus, the timing management circuit 50 is connected to various circuits that require time measurement. The timing management circuit 50 has the function of measuring time using the supplied clock signal CLK. When a peripheral circuit that requires time measurement requests the timing management circuit 50 to start time measurement, the timing management circuit 50 notifies the completion of time measurement after a certain period of time has elapsed. The timing management circuit 50 may also output the result of the time measurement.

[0032] When the timing management circuit 50 receives time measurement requests from multiple peripheral circuits, it performs time measurement according to each time measurement request. Specifically, when the timing management circuit 50 receives a first time measurement request from any of the multiple peripheral circuits, it starts the first time measurement. If the timing management circuit 50 receives a second time measurement request while performing the first time measurement, it starts the second time measurement while continuing the first time measurement. The timing management circuit 50 may receive the second request from a peripheral circuit different from the one that received the first request. In some cases, the timing management circuit 50 may receive the second request from the peripheral circuit that received the first request.

[0033] Furthermore, the time measurement method in the semiconductor device 1 of this embodiment includes a step of causing the timing management circuit 50 to perform time measurement in response to each time measurement request. The step of causing time measurement to perform includes a step of starting the first time measurement when a first request for the first time measurement is received from any of the plurality of peripheral circuits, and a step of starting the second time measurement while continuing the first time measurement when a second request for the second time measurement is received while the first time measurement is being performed.

[0034] During periods when time measurement is not required, the timing management circuit 50 disables its built-in time measurement function. Therefore, the timing management circuit 50 performs time measurement only when it receives a request for time measurement from a peripheral circuit. Thus, after outputting the results of all requested time measurements, the timing management circuit 50 disables time measurement until it receives the next request for time measurement.

[0035] Figures 5 and 6 are block diagrams illustrating the oscillation stabilization standby circuits 123a to 123e in a comparative example semiconductor device 101. Figure 6 is a block diagram extracted as an example of a part of the main components of Figure 5. Figure 7 is a block diagram illustrating the oscillation stabilization standby circuits 23a to 23c and the timing management circuit 50 in a semiconductor device 1 according to Embodiment 1.

[0036] As shown in Figures 5 and 6, the semiconductor device 101 in the comparative example has oscillators A121a and B121b, as well as multiple oscillators 121c to 121e and oscillation stabilization waiting circuits 123a to 123e for each of the multiple on-chip oscillators. As shown in Figure 6, each of the multiple oscillation stabilization waiting circuits 123a to 123c has a time measurement function. The time measurement function may be performed by, for example, a counter.

[0037] On the other hand, as shown in Figure 7, in this embodiment, the semiconductor device 1 has a timing management circuit 50 that performs the function of a counter for measuring time. The semiconductor device 1 according to this embodiment has oscillation stabilization waiting circuits 23a to 23c for each of the multiple oscillators A21a and B21b, and each of the multiple on-chip oscillators. When oscillators A21a, B21b, and 21c start oscillating, the oscillation stabilization waiting circuits 23a to 23c output a time measurement request (REQUEST) to the timing management circuit 50. The timing management circuit 50 then performs the function of measuring time. The timing management circuit 50 outputs the result of the time measurement (RESULT) to the oscillation stabilization waiting circuits 23a to 23c.

[0038] Figure 8 is a block diagram illustrating the oscillation stabilization waiting circuits 123a to 123c in a comparative example semiconductor device 101. Figure 9 is a block diagram illustrating the oscillation stabilization waiting circuits 23a to 23c and the timing management circuit 50 in a semiconductor device 1 according to Embodiment 1.

[0039] As shown in Figure 8, in the semiconductor device 101 according to the comparative example, the oscillation stabilization waiting circuits 123a to 123c may have a function for measuring time and a logic gate such as an AND gate. For example, a clock signal CLK may be output when the measurement time matches a predetermined stabilization waiting time.

[0040] On the other hand, as shown in Figure 9, in the semiconductor device 1 of this embodiment, the oscillation stabilization waiting circuits 23a to 23c may have logic gates such as AND gates. The oscillation stabilization waiting circuits 23a to 23c request time measurement from the timing management circuit 50. The timing management circuit 50 has a function to perform time measurement. The timing management circuit 50 outputs the result of the time measurement to the oscillation stabilization waiting circuits 23a to 23c. The oscillation stabilization waiting circuits 23a to 23c output a clock signal CLK when the measurement time output by the timing management circuit 50 matches a predetermined stabilization waiting time. Note that in Figures 8 and 9, the oscillation stabilization waiting circuits 123a to 123c, the oscillation stabilization waiting circuits 23a to 23c, and the timing management circuit 50 are simplified. In reality, they may have complex circuits to prevent clock hazards, etc.

[0041] Figure 10 is a block diagram illustrating the arithmetic processing unit 10, storage device 12, timer 30, and timing management circuit 50 in a semiconductor device 1 according to Embodiment 1. As shown in Figure 10, the semiconductor device 1 may further include a storage device 12 in addition to the arithmetic processing unit 10, timer 30, and timing management circuit 50. The timer 30 has a register 31 and an interface circuit 34. The timing management circuit 50 has a register 51 and a counter circuit 52.

[0042] The storage device 12 stores instruction codes for controlling the arithmetic processing unit 10. For example, the storage device 12 may include ROM (Read Only Memory). Note that the storage device 12 is not limited to ROM; other storage devices are also acceptable as long as they store instruction codes for controlling the arithmetic processing unit 10. The storage device 12 outputs instruction codes to the arithmetic processing unit 10.

[0043] The arithmetic processing unit 10 is controlled by instruction codes stored in the memory device 12. The arithmetic processing unit 10 controls the timer 30 and the timing management circuit 50. Specifically, the arithmetic processing unit 10 sets the operation of the timer 30 by writing instruction codes to the timer 30's register 31. The arithmetic processing unit 10 also sets the operation of the timing management circuit 50 by writing instruction codes to the timing management circuit 50's register 51.

[0044] Register 31 is connected to the internal peripheral bus 11 in a state where it can transmit information. Register 31 controls the operation of timer 30 according to the instruction code written to it. Interface circuit 34 is connected to register 31 in a state where it can transmit information. Interface circuit 34 is also connected to timing management circuit 50 in a state where it can transmit information. Timer 30 requests time measurement from timing management circuit 50 via interface circuit 34. Timer 30 also receives the time measurement result from timing management circuit 50 via interface circuit 34.

[0045] Register 51 is connected to the internal peripheral bus 11 in a state where it can transmit information. Register 51 controls the operation of the timing management circuit 50 according to the instruction code written to it. The counter circuit 52 performs time measurement. The counter circuit 52 performs time measurement by counting the number of high-voltage or low-voltage states of the clock signal CLK. The timing management circuit 50 performs time measurement upon receiving a time measurement request from the timer 30 and outputs the result of the performed time measurement to the timer 30. The timing management circuit 50 may receive time measurement requests from multiple timers 30.

[0046] Figure 11 is a block diagram illustrating a clock generation circuit 20, a timer 30, a peripheral circuit 41, and a timing management circuit 50 in a semiconductor device 1 according to Embodiment 1. The peripheral circuit 41 may include, for example, the timer 30 and a communication IP 40. As shown in Figure 11, the clock generation circuit 20 includes an oscillator circuit A25a, an oscillator circuit B25b, a frequency divider circuit 27, a frequency divider circuit 28, and a selection circuit 29.

[0047] The timing management circuit 50 includes a counter circuit 52, a clock control circuit 53, a timing generation circuit 54, and a counter value conversion unit 55. The counter circuit 52 includes a counter unit 56. The timing generation circuit 54 includes a comparison unit 57a, a comparison unit 57b, a comparison unit 57c, a storage unit 58a, a storage unit 58b, a storage unit 58c, and a calculation circuit 59.

[0048] The oscillator circuit A25a generates a clock signal CLK. The oscillator circuit A25a may include an oscillator A21a. The oscillator circuit A25a outputs the generated clock signal CLK to the selection circuit 29. The oscillator circuit A25a may generate the clock signal CLK under the control of the clock control circuit 53 and output the generated clock signal CLK to the selection circuit 29.

[0049] The oscillator circuit B25b generates a clock signal CLK. The oscillator circuit B25b may include an oscillator B21b. The oscillator circuit B25b outputs the generated clock signal CLK to the selection circuit 29. The oscillator circuit B25b may also output the generated clock signal CLK to the frequency divider circuit 27. Furthermore, the oscillator circuit B25b may output the generated clock signal CLK to the frequency divider circuit 28. The oscillator circuit B25b may generate the clock signal CLK under the control of the clock control circuit 53 and output the generated clock signal CLK to the selection circuit 29, frequency divider circuit 27, and frequency divider circuit 28.

[0050] The frequency divider circuit 27 divides the clock signal CLK. The frequency divider circuit 27 outputs the divided clock signal CLK to the selection circuit 29. The frequency divider circuit 28 also divides the clock signal CLK. The frequency divider circuit 28 outputs the divided clock signal CLK to the selection circuit 29. The frequency divider circuits 27 and 28 may divide the clock signal CLK to mutually different frequencies. Specifically, the frequency divider circuits 27 and 28 may each generate clock signals CLK of mutually different frequencies using the same clock signal CLK generated from the oscillator circuit B25b.

[0051] The selection circuit 29 receives clock signals CLK from oscillator circuits A25a, B25b, frequency divider circuits 27 and 28. The selection circuit 29 selects a clock signal CLK from the received multiple clock signals CLK and outputs it to the counter circuit 52. For example, under the control of the clock control circuit 53, the selection circuit 29 selects a predetermined clock signal CLK from the multiple clock signals CLK and outputs it to the counter circuit 52. The selection circuit 29 outputs the selected clock signal CLK to the counter section 56 of the counter circuit 52.

[0052] Thus, the oscillator circuit A25a generates a first clock signal CLK. The oscillator circuit B25b may generate a second clock signal CLK with the same frequency as the first clock signal CLK, or it may generate a second clock signal CLK with a different frequency from the first clock signal CLK. The frequency divider circuit 27 divides the second clock signal CLK to generate a third clock signal CLK. The frequency divider circuit 28 divides the second clock signal CLK to generate a fourth clock signal CLK. The frequency divider circuit 28 may generate a fourth clock signal CLK with the same frequency as the third clock signal CLK, or it may generate a fourth clock signal CLK with a different frequency from the third clock signal CLK. The selection circuit 29 selects the clock signal CLK to be used for time measurement from the first clock signal CLK, the second clock signal CLK, the third clock signal CLK, and the fourth clock signal CLK according to the requirement for time measurement.

[0053] The timing management circuit 50 may, for example, perform the first and second time measurements based on the same clock signal CLK generated from the clock generation circuit 20. Alternatively, the timing management circuit 50 may perform the first and second time measurements based on mutually different clock signals CLK.

[0054] The counter circuit 52 holds a count of the number of high-voltage and low-voltage states of the clock signal CLK as a counter value. Specifically, the counter unit 56 receives the clock signal CLK from the selection circuit 29. The counter unit 56 performs time measurement using the clock signal CLK. The counter unit 56 generates a counter value. The counter unit 56 outputs the generated counter value to the counter value conversion unit 55, comparison unit 57a, comparison unit 57b, and comparison unit 57c.

[0055] The clock control circuit 53 controls the generation and stopping of the clock signal CLK in the oscillation circuit A25a, and the generation and stopping of the clock signal CLK in the oscillation circuit B25b. The clock control circuit 53 also controls the selection of the clock signal CLK in the selection circuit 29. Based on the control of the calculation circuit 59, the clock control circuit 53 controls the operation of the oscillation circuit A25a, the oscillation circuit B25b, and the selection circuit 29.

[0056] The clock control circuit 53 selects the clock signal CLK to be used in the counter unit 56 based on the peripheral circuit 41 that requested the time measurement. For example, if the peripheral circuit 41 that requested the time measurement requires a high-resolution time measurement, the clock control circuit 53 selects a high-frequency clock signal CLK.

[0057] The timing generation circuit 54 receives a time measurement request from the peripheral circuit 41 and outputs the time measurement result to the peripheral circuit 41. The calculation circuit 59 calculates the target count of the measurement time as the target value from the measurement time in the requested time measurement and the clock signal CLK. In this way, the calculation circuit 59 calculates the target value from the clock setting and the measurement time. The calculation circuit 59 stores the calculated target value in the storage units 58a to 58c.

[0058] Comparison units 57a to 57c compare the counter value with the target value. The counter value is the count obtained by counting the number of times the clock signal CLK is in a high-voltage state or a low-voltage state. Storage units 58a to 58c store the target value.

[0059] The counter value conversion unit 55 converts the counter value received from the counter circuit 52 and outputs it to the timer 30. If the peripheral circuit 41 is the timer 30 and the timing management circuit 50 receives a request for time measurement from the timer 30, the counter value conversion unit 55 outputs the converted counter value to the timer 30. Thus, the timing management circuit 50 may have a function to convert and output the counter value of the counter circuit 52 in response to a request from the peripheral circuit 41.

[0060] For example, suppose that when timer 30 requests time measurement from timing management circuit 50, the counter value of timer 30 is 100 and the counter value of counter circuit 52 is 0. Also, suppose that timer 30 and timing management circuit 50 use the same frequency clock signal CLK. In that case, if the counter value of counter circuit 52 is, for example, 15, the counter value conversion unit 55 outputs 115 to timer 30.

[0061] For example, suppose that when timer 30 requests time measurement from timing management circuit 50, the counter value of timer 30 is 100 and the counter value of counter circuit 52 is 0. Also, suppose that the frequency of the clock signal CLK used by timer 30 is twice the frequency of the clock signal CLK used by timing management circuit 50. In that case, if the counter value of counter circuit 52 is, for example, 15, the counter value conversion unit 55 outputs 130 to timer 30.

[0062] Figure 12 is a block diagram illustrating timers 130a and 130b in the semiconductor device 101 of the comparative example. As shown in Figure 12, timer 130a of the semiconductor device 101 of the comparative example includes comparator A0, comparator B0, and counter circuit TCNT. Timer 130b includes comparator A1, comparator B1, and counter circuit TCNT. Note that some symbols have been omitted to avoid making the figure complicated. The semiconductor device 101 of the comparative example measures time using the counter circuit TCNT and comparator A0, etc.

[0063] In the semiconductor device 101 of the comparative example, when multiple peripheral circuits 41 that require time measurement, such as multiple timers 130a and 130b, are connected, and each peripheral circuit 41 performs time measurement, the current consumption increases.

[0064] Figure 13 is a block diagram illustrating the relationship between timers 30a and 30b and the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1. As shown in Figure 13, the semiconductor device 1 of this embodiment does not use the counter TCNT built into timers 30a and 30b. The timing management circuit 50 has multiple time measurement functions. The timing management circuit 50 receives a time measurement request from timers 30a and 30b, and as a result of the time measurement, outputs the counter value converted by the counter value conversion unit 55 to timers 30a and 30b. Note that the comparator A0, etc. may be configured to use the comparison unit 57a, etc. located in the timing management circuit 50, or to use the comparator A0, etc. built into timers 30a and 30b.

[0065] Next, we will describe an example of its application to a compare match timer. The semiconductor device 1 of this embodiment can be made compatible with a compare match timer function. The functions of this embodiment will be described below in comparison with a comparative example.

[0066] Figure 14 is a flowchart illustrating the procedure for setting the compare match timer operation in the semiconductor device 101 of the comparative example. As shown in Figure 14, in order to operate the compare match function in the semiconductor device 101 of the comparative example, first, the compare match operation is enabled as shown in step S11. Specifically, the compare match operation is enabled by the CMWIOR register. The CMWIOR register is, for example, the timer I / O control register.

[0067] Next, as shown in step S12, the compare match timing is set. Specifically, the timing for generating a compare match is set in the CMWCOR register. The CMWCOR register is, for example, the compare match constant register.

[0068] Next, as shown in step S13, the counting operation is started. Specifically, the CMWCR register is set, and the CMWSTR.STR bit is set to "1" to start the counting operation. The CMWCR register is, for example, a timer control register, and the CMWSTR.STR bit is a bit of the timer start register. The counting operation is then performed until it matches the timing set in the compare match constant register. In this way, the semiconductor device 101 of the comparative example performs the compare match operation.

[0069] Next, an example of applying the compare match timer function to the semiconductor device 1 according to this embodiment will be described. In this embodiment, the semiconductor device 1 does not necessarily need to have a counter circuit in the timer 30. Figure 15 is a flowchart illustrating the procedure for setting the compare match timer operation in the semiconductor device 1 according to Embodiment 1. Steps S21 to S22 in Figure 15 are the same as steps S11 to S12 in Figure 14.

[0070] Next, as shown in step S23, the timer 30 requests the timing management circuit 50 to perform a time measurement. The timing management circuit 50 then performs the time measurement. The timing management circuit 50 then outputs a counter value to the timer 30 as a result of the time measurement. Therefore, as shown in step S24, the timer 30 receives the result of the time measurement from the timing management circuit 50. In this way, the timer 30 in the semiconductor device 1 of this embodiment can perform a compare-match operation. Thus, the semiconductor device 1 of this embodiment can operate functions similar to those of the comparative example semiconductor device 101, such as a compare-match timer function, by causing the timing management circuit 50 to perform a time measurement.

[0071] Figure 16 is a block diagram illustrating a semiconductor device 1 according to Embodiment 1. The semiconductor device 1 includes, for example, an MCU. As shown in Figure 16, the semiconductor device 1 includes an arithmetic processing unit 10, a storage device 12, a clock generation circuit 20, a timer 30, a communication IP 40, and a timing management circuit 50. The multiple peripheral circuits 41, including the timer 30 and the communication IP 40, may include circuits that require time measurement. The timing management circuit 50 includes circuits that perform time measurement, such as a counter circuit 52. The multiple peripheral circuits 41 in the semiconductor device 1, including the timer 30 and the communication IP 40, may be connected in a manner that enables information transmission to other semiconductor devices such as MCU 1 and MCU 2.

[0072] The clock generation circuit 20 has a clock generation function and a clock selection function. In the clock generation circuit 20, the clock generation function includes, for example, the oscillator circuit A25a, oscillator circuit B25b, frequency divider circuit 27 and frequency divider circuit 28. The clock selection function includes the selection circuit 29. The arithmetic processing unit 10 executes the program (instruction code) written to the storage device 12 and sets the timing management circuit 50 and peripheral circuits 41.

[0073] Figure 17 is a block diagram illustrating the relationship between the clock generation circuit 20 and the timing management circuit 50, and the relationship between the timing management circuit 50 and the peripheral circuit 41, in a semiconductor device 1 according to Embodiment 1. As shown in Figure 17, the timing management circuit 50 includes a counter unit 56 for measuring time. The timing management circuit 50 also controls the clock generation circuit 20.

[0074] As mentioned above, the clock generation circuit 20 includes oscillator circuit A25a, oscillator circuit B25b, frequency divider circuit 27, frequency divider circuit 28, and selection circuit 29. The timing management circuit 50 controls the oscillation and stopping of oscillator circuit A25a, the oscillation and stopping of oscillator circuit B25b, frequency divider circuits 27 and 28, and selection circuit 29. The timing management circuit 50 operates the counter unit 56 with the supplied clock signal CLK. The timing management circuit 50 also adjusts the frequency of the clock signal CLK by selection. Furthermore, the timing management circuit 50 reduces current consumption by stopping unnecessary oscillator circuits A25a and B25b.

[0075] The peripheral circuit 41, including the oscillation stabilization waiting circuit 23 and peripheral IPs 41a and 41b, outputs a request to the timing management circuit 50 to start time measurement when timing generation is required during operation. If the measurement time has not been predetermined, the measurement time is also notified. The timing management circuit 50 starts time measurement upon receiving the request and outputs a notification that the measurement is complete after the predetermined time has elapsed.

[0076] Figure 18 is a block diagram illustrating a timing management circuit 50 of a semiconductor device 1 according to Embodiment 1. As shown in Figure 18, the timing management circuit 50 includes a counter circuit 52, a clock control circuit 53, and a timing generation circuit 54. The timing generation circuit 54 receives requests from a plurality of peripheral circuits 41 and selects the optimal clock signal CLK required for the counting operation of the time measurement counter circuit 52. The timing generation circuit 54 then requests the clock control circuit 53 to supply the selected clock signal CLK. The counter circuit 52 performs a counting operation to measure the required time using the supplied clock signal CLK, in response to the control of the timing generation circuit 54.

[0077] Figure 19 illustrates the counting operation of the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1 in the case of a single request for time measurement received from one peripheral circuit 41. As shown in Figure 19, the timing generation circuit 54 receives a request REQUEST1 from one peripheral circuit 41 and selects the optimal clock signal CLK required for the counting operation of the counter circuit 52 for time measurement. The timing generation circuit 54 requests the clock control circuit 53 to supply the selected clock signal CLK. The counter circuit 52 performs a counting operation for time measurement using the supplied clock signal CLK in response to the control of the timing generation circuit 54. After the completion of time measurement END1, the timing generation circuit 54 outputs the measurement result to the peripheral circuit 41.

[0078] Figure 20 illustrates the counting operation of the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1 in the case of multiple requests for time measurement from multiple peripheral circuits 41. As shown in Figure 20, the timing generation circuit 54 first receives a request REQUEST1 from the first peripheral circuit 41 and selects the optimal clock signal CLK required for the counting operation of the time measurement counter circuit 52. The timing generation circuit 54 then requests the clock control circuit 53 to supply the selected first clock signal CLK. The counter circuit 52 performs a counting operation for time measurement using the supplied first clock signal CLK in response to the control of the timing generation circuit 54.

[0079] Next, upon receiving a request REQUEST2 from the second peripheral circuit 41, the timing generation circuit 54 selects the optimal clock signal CLK required for the counting operation of the time measurement counter circuit 52. The timing generation circuit 54 then requests the clock control circuit 53 to supply the selected second clock signal CLK. The counter circuit 52, in response to the control of the timing generation circuit 54, uses the supplied second clock signal CLK to perform a counting operation for time measurement.

[0080] Next, after the completion of time measurement END2 due to request REQUEST2 from the second peripheral circuit 41, the timing generation circuit 54 outputs the measurement result to the second peripheral circuit 41. Then, after the completion of time measurement END1 due to request REQUEST1 from the first peripheral circuit 41, the timing generation circuit 54 outputs the measurement result to the first peripheral circuit 41. In this example, the frequency of the first clock signal CLK is less than the frequency of the second clock signal CLK. Also, the measurement time measured due to request REQUEST1 from the first peripheral circuit 41 is longer than the measurement time measured due to request REQUEST2 from the second peripheral circuit 41.

[0081] Figure 21 is a block diagram illustrating the clock generation circuit 20 and the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1. As shown in Figure 21, in the timing management circuit 50, the clock control circuit 53 controls the clock generation circuit 20 in response to a request from the timing generation circuit 54. For example, if high-resolution time measurement is required, it operates an oscillator that generates a high-frequency clock signal CLK.

[0082] The clock control circuit 53 controls the selection circuit 29 to select the clock signal CLK to be supplied to the counter circuit 52. The clock control circuit 53 also controls the selection circuit 29 to select the division ratio of the frequency divider circuits 27 and 28. In this way, the clock control circuit 53 supplies the counter circuit 52 with a clock signal CLK of the minimum necessary frequency.

[0083] Figure 22 is a block diagram illustrating the connection relationship between the timing generation circuit 54 and peripheral circuits 41 in the timing management circuit 50 of the semiconductor device 1 according to Embodiment 1. As shown in Figure 22, the timing generation circuit 54 includes a calculation circuit 59 for calculating a target value, comparison units 57a to 57c for comparing a counter value and a target value, and storage units 58a to 58c for storing the target value. Note that the timing management circuit 50 does not necessarily include the counter value conversion unit 55 mentioned above.

[0084] Figure 23 is a flowchart illustrating the operation of the timing generation circuit 54 in the semiconductor device 1 according to Embodiment 1. As shown in step S31 of Figure 23, the timing generation circuit 54 receives a request from the peripheral circuit 41 to start time measurement. Next, as shown in step S32, the timing generation circuit 54 acquires the current clock setting from the clock control circuit 53. Next, as shown in step S33, the timing generation circuit 54 acquires the current counter value from the counter circuit 52.

[0085] Next, as shown in step S34, the timing generation circuit 54 calculates a target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates a target value, which is the target count for time measurement, from the frequency of the clock signal CKL and the current counter value. The calculation circuit 59 stores the calculated target value in the storage units 58a to 58c.

[0086] Next, as shown in step S35, the timing generation circuit 54 may, if necessary, cause the clock control circuit 53 to change the counting clock signal CLK. The timing generation circuit 54 may also, if necessary, change the target value to match the changed clock signal CLK. For example, if the clock settings differ for other time measurement requirements, the timing generation circuit 54 will change the counting clock signal CLK and the target value.

[0087] Next, as shown in step S36, the timing generation circuit 54 waits until the counter value and the target value match. Then, as shown in step S37, once the counter value and the target value match, the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete and outputs the time measurement result.

[0088] Next, as shown in step S38, the timing generation circuit 54, if necessary, instructs the clock control circuit 53 to stop the clock signal CLK and the counter circuit 52 to stop counting the clock signal CLK. The timing generation circuit 54 may also, if necessary, change the counting clock signal CLK to the clock control circuit 53. Furthermore, the timing generation circuit 54 may change the target value if necessary.

[0089] Next, we will explain the counting operation of the timing management circuit 50 in the case of a single request, where a time measurement request is received from one peripheral circuit 41. In the case of a single request, the operation of the timing generation circuit 54 in Figure 23 described above can be applied as is.

[0090] Figure 24 illustrates the counting operation of the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1 in the case of a single request for time measurement received from one peripheral circuit 41. As shown in Figure 24, the timing generation circuit 54 receives a request (REQUEST1) to start time measurement (COUNT TIME1) from one peripheral circuit 41. Next, the timing generation circuit 54 acquires the current clock setting (CLK SET A) from the clock control circuit 53. Next, the timing generation circuit 54 acquires the current counter value (AAA) from the counter circuit 52.

[0091] Next, the timing generation circuit 54 calculates a target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates a target value (AAA+α), which is the target count for time measurement, from the frequency of the clock signal CKL and the current counter value (AAA). Next, the timing generation circuit 54 waits until the counter value matches the target value (AAA+α). Once the counter value and the target value match, the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END1).

[0092] Next, if there is no other time measurement request, the timing generation circuit 54 may instruct the clock control circuit 53 to stop the clock signal CLK and the counter circuit 52 to stop counting the clock signal CLK. Alternatively, the timing generation circuit 54 may instruct the clock control circuit 53 to change the counting clock signal CLK.

[0093] Next, when the peripheral circuit 41 requests (REQUEST2) to start time measurement (COUNT TIME2), the timing generation circuit 54 processes it in the same way as the request (REQUEST1). That is, the timing generation circuit 54 takes the current clock setting (CLK SET B) from the clock control circuit 53 and the current counter value (BBB) ​​from the counter circuit 52. Then, the timing generation circuit 54 calculates the target value (BBB+β) from the clock setting and the counter value. Once the counter value and the target value match, the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END2).

[0094] Next, we will explain the counting operation of the timing management circuit 50 in the case of multiple requests, where time measurement requests are received from multiple peripheral circuits 41 simultaneously. In the case of multiple requests, the operation of the timing generation circuit 54 shown in Figure 23 above can be applied in a redundant manner.

[0095] Figure 25 illustrates the counting operation of the timing management circuit 50 in the semiconductor device 1 according to Embodiment 1 in the case of multiple requests for time measurement, where multiple peripheral circuits 41 simultaneously request time measurement. First, the case without switching of the clock signal CLK will be explained. As shown in Figure 25, the timing generation circuit 54 receives a request (REQUEST1) from the peripheral circuit 41 to start time measurement (COUNT TIME1). Next, the timing generation circuit 54 acquires the current clock setting (CLK SET A) from the clock control circuit 53. Next, the timing generation circuit 54 acquires the current counter value (A) from the counter circuit 52.

[0096] Next, the timing generation circuit 54 calculates a target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates a target value (TARGET VALUE 1), which is the target count for time measurement, from the frequency of the clock signal CKL and the current counter value (A). Next, the timing generation circuit 54 waits until the counter value matches the target value (TARGET VALUE 1).

[0097] In the case of multiple requests, while waiting for the counter value to match the target value (TARGET VALUE 1), the timing generation circuit 54 receives a request (REQUEST2) from the peripheral circuit 41 to start time measurement (COUNT TIME 2). In this case, the timing generation circuit 54 receives the clock setting (CLK SET A) from the clock control circuit 53. Next, the timing generation circuit 54 receives the current counter value (A+α) from the counter circuit 52. Next, the timing generation circuit 54 calculates the target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates the target value (TARGET VALUE 2), which is the target count for time measurement, from the frequency of the clock signal CKL and the current counter value (A+α). Next, the timing generation circuit 54 waits until the counter value matches the target value (TARGET VALUE 2).

[0098] When the counter value matches one of the target values, the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END1 or END2). For example, when the counter value matches the target value (TARGET VALUE 2), the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END2). Next, when the counter value matches the target value (TARGET VALUE 1), the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END1).

[0099] Next, the counting operation of the timing management circuit 50 in the case of multiple requests involving the switching of the clock signal CLK will be described. Figure 26 is a diagram illustrating the counting operation of the timing management circuit 50 involving the switching of the clock signal CLK in the case of multiple requests in the semiconductor device 1 according to Embodiment 1, in the case of multiple requests in which time measurement requests are received from multiple peripheral circuits 41. As shown in Figure 26, the timing generation circuit 54 receives a request (REQUEST1) from the peripheral circuit 41 to start time measurement (COUNT TIME 1). Next, the timing generation circuit 54 acquires the current clock setting (CLK SET A) from the clock control circuit 53. Next, the timing generation circuit 54 acquires the current counter value (A) from the counter circuit 52.

[0100] Next, the timing generation circuit 54 calculates a target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates a target value (TARGET VALUE 1), which is the target count for time measurement, from the frequency of the clock signal CKL and the current counter value (A). Next, the timing generation circuit 54 waits until the counter value matches the target value (TARGET VALUE 1).

[0101] In the case of multiple requests, while waiting for the counter value to match the target value (TARGET VALUE 1), the timing generation circuit 54 receives a request (REQUEST2) from the peripheral circuit 41 to start time measurement (COUNT TIME 2). In this example, the request (REQUEST2) involves switching the clock signal CLK. In this case, the timing generation circuit 54 causes the clock control circuit 53 to switch the clock setting. Specifically, the timing generation circuit 54 takes in the clock setting (CLK SET B) corresponding to the request (REQUEST2) from the peripheral circuit 41. Next, the timing generation circuit 54 takes in the current counter value (A+α) from the counter circuit 52.

[0102] Next, the timing generation circuit 54 calculates the target value from the clock setting and the counter value. Specifically, the calculation circuit 59 calculates the target value (TARGET VALUE 2) for the request (REQUEST2) from the clock setting (CLK SET B) and counter value (A+α) corresponding to the request (REQUEST2). Furthermore, when the clock signal CLK is switched, the calculation circuit 59 recalculates the target value corresponding to the request (REQUEST1). Specifically, the calculation circuit 59 recalculates the target value (TARGET VALUE 11) from the reset clock setting (CLK SET B) and counter value (A+α). Next, the timing generation circuit 54 waits until the counter value matches the target value (TARGET VALUE 2) or the target value (TARGET VALUE 11).

[0103] When the counter value matches one of the target values, the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END1 or END2). For example, when the counter value matches the target value (TARGET VALUE 2), the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END2). Next, when the counter value matches the target value (TARGET VALUE 11), the timing generation circuit 54 notifies the peripheral circuit 41 that the time measurement is complete (END1).

[0104] Next, the effects of this embodiment will be explained. Figure 27 is a graph illustrating the current consumption during time measurement in a semiconductor device 101 according to a comparative example, where the horizontal axis shows a configuration in which current-consuming components are stacked, and the vertical axis shows the current consumption. Figure 28 is a graph illustrating the current consumption during time measurement in a semiconductor device 1 according to Embodiment 1, where the horizontal axis shows a configuration in which current-consuming components are stacked, and the vertical axis shows the current consumption.

[0105] As shown in Figure 27, in the comparative example semiconductor device 101, the time measurement functions provided in each of the multiple timers 30, including timers TMR0, TMR1, and TMR2, perform time measurement. As a result, the current consumption in the semiconductor device 101 is the sum of the current consumption of timers TMR0, TMR1, and TMR2, which is 0.129mA, plus the CTS buffer current.

[0106] On the other hand, as shown in Figure 28, in the semiconductor device 1 of this embodiment, the timing management circuit 50 performs time measurement in multiple timers 30, including timers TMR0, TMR1, and TMR2. Therefore, the multiple peripheral circuits 41 do not need to perform time measurement, and thus the current consumption consumed by time measurement can be reduced. For example, the current consumption in the semiconductor device 1 is the amount of current consumed by the timing management circuit 50, which is 0.043mA, plus the CTS buffer current.

[0107] Furthermore, since the number of recipients of the clock signal can be reduced, the current consumed in the transmission path of the clock signal CLK can be reduced. In addition, the amount of the clock signal CLK distributed for time measurement can be reduced. Therefore, the transmission system of the clock signal CLK can be simplified. This makes timing design easier and reduces the CTS buffer, that is, the operating current of the clock generation circuit 20 can be reduced.

[0108] For example, the comparative example semiconductor device 101 has seven PWM circuits and three UART circuits as peripheral circuits. The PWM circuits and UART circuits have a function for measuring time. The current consumption of one PWM circuit is, for example, 0.18mA, and the current consumption of one UART circuit is, for example, 0.15mA. In that case, the current consumption to operate the PWM circuits and UART circuits in the comparative example semiconductor device 101 is 0.18 × 7 + 0.15 × 3 = 1.71mA.

[0109] On the other hand, the semiconductor device 1 of this embodiment has, as peripheral circuits, seven PWM circuits and three UART circuits, as well as a timing management circuit 50 that performs time measurement. The timing management circuit 50 is responsible for time measurement of the PWM circuits and UART circuits. If we estimate that the current consumed by time measurement accounts for about 70% of the current consumed by the PWM circuits and UART circuits, then it becomes 1.71 × 0.7 = 1.20 mA. Therefore, the current consumed by the PWM circuits and UART circuits other than time measurement is 1.71 - 1.20 = 0.51 mA. If we assume that the current consumed by the timing management circuit 50 for time measurement is 0.1 mA, then the current consumed to operate the PWM circuits and UART circuits in the semiconductor device 1 of this embodiment is 0.51 + 0.1 = 0.61 mA. In this way, the semiconductor device 1 of this embodiment can significantly reduce current consumption.

[0110] <Embodiment 2> Next, a semiconductor device according to Embodiment 2 will be described. The semiconductor device of this embodiment has an independent counter unit for each oscillation circuit in order to handle multiple requests. In the semiconductor device 1 described above, when switching the clock source supplied to the counter unit 56 to either oscillation circuit A25a or oscillation circuit B25b, the switching may take time. If multiple requests occur frequently, there is a risk that the switching of the clock signal CLK and the counter operation will not be able to keep up. Therefore, in this embodiment, as a countermeasure against the frequent occurrence of such multiple requests, there are multiple counter units so that no switching time occurs for the clock signal CLK.

[0111] Figure 29 is a block diagram illustrating a semiconductor device 2 according to Embodiment 2. As shown in Figure 29, the timing management circuit 50 in the semiconductor device 2 of this embodiment has a plurality of counter units A56a and counter units B56b. Each of the counter units A56a and B56b performs time measurement using a clock signal CLK. The timing generation circuit 54 selects which of the counter units A56a and B56b to use for each time measurement request from the peripheral circuit 41. The clock control circuit 53 selects the clock signal CLK to be used by the counter units A56a and B56b based on the time measurement request from the peripheral circuit 41. The clock control circuit 53 may select different clock signals CLK for each of the counter units A56a and B56b.

[0112] This configuration reduces the switching time when switching the clock signal CLK. Therefore, even if multiple requests occur frequently, the switching of the clock signal CLK and the counter operation can be kept in sync. In addition, the timing management circuit 50 of this embodiment can also eliminate measurement time errors caused by the switching of the asynchronous clock signal CLK.

[0113] <Embodiment 3> Next, a semiconductor device according to Embodiment 3 will be described. In this embodiment, the semiconductor device has a function for measuring time in a peripheral circuit 41, in addition to the timing management circuit 50. Figure 30 is a block diagram illustrating the arithmetic processing unit 10, clock generation circuit 20, timer 30, peripheral circuit 41, and timing management circuit 50 in the semiconductor device 3 according to Embodiment 3.

[0114] As shown in Figure 30, in the semiconductor device 3 of this embodiment, the timing management circuit 50 has a counter circuit 52 that has a limited number of time measurement requests it can perform, and peripheral circuits 41 such as the communication IP 40 also have counter functions that perform time measurement, such as counter circuits. The timing management circuit 50 has a determination unit 60 that determines whether or not to accept time measurement requests from the peripheral circuits 41. If the determination unit 60 determines that the timing management circuit 50 can operate using only the counter circuit 52, it accepts time measurement requests from the peripheral circuits 41. Therefore, the counter circuits located in the peripheral circuits 41 do not operate.

[0115] On the other hand, the determination unit 60 rejects time measurement requests from the peripheral circuit 41 if it cannot continue the time measurement that is currently being performed, or if the number of time measurement requests that can be measured simultaneously exceeds the upper limit. If a request is rejected, the determination unit 60 instructs the peripheral circuit 41 to perform time measurement using the counter function of the peripheral circuit 41. For example, if multiple time measurement requests occur simultaneously and the timing management circuit 50 cannot perform time measurement, the determination unit 60 activates a counter circuit or the like located in the peripheral circuit 41. Although the effect of reducing current consumption will be small, the time measurement operation in the semiconductor device 3 can be continued.

[0116] Furthermore, the case in which the timing management circuit 50 is unable to perform time measurement is not limited to cases where multiple time measurement requests occur simultaneously and exceed the tolerance range of the timing management circuit 50. For example, the case in which time measurement is impossible may include cases where switching the clock signal CLK makes it impossible to accurately continue time measurement during operation. Also, the case in which time measurement is impossible may include cases where the interface I / F between the timing management circuit 50 and the peripheral circuit 41 reaches a condition where it is no longer possible to receive simultaneous time measurement requests.

[0117] The present inventors' disclosures have been described in detail based on embodiments, but it goes without saying that these disclosures are not limited to the embodiments described above and can be modified in various ways without departing from their essence. For example, as shown below, a time measurement program that causes a computer to execute a time measurement method is also within the scope of the technical concept of these three embodiments. The storage device 12 may store programs that record the processing performed by each component of the semiconductor device 1. The arithmetic processing unit 10 may read the program from the storage device 12 into memory and execute the program. As a result, the arithmetic processing unit 10 realizes the functions of each component in the timing management circuit 50.

[0118] A time measurement program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. A time measurement program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include electrical, optical, acoustic or other forms of propagating signals.

[0119] (Note A1) A processing unit and Multiple peripheral circuits controlled by the aforementioned processing unit, A timing management circuit that outputs the result of the time measurement performed in response to a time measurement request from the peripheral circuit to the peripheral circuit, A time measurement method in a semiconductor device equipped with, The timing management circuit includes a step of performing the time measurement in response to each of the time measurement requests. Method of measuring time. (Appendix A2) The step of performing the aforementioned time measurement is: The step of starting the first time measurement when a first request for first time measurement is received from any of the plurality of peripheral circuits, If a second request for a second time measurement is received while the first time measurement is being performed, the first time measurement is continued while the second time measurement is started. Having, The time measurement method described in Appendix A1. (Note A3) The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. In the step of performing the aforementioned time measurement, When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on the same clock signal generated from the clock generation circuit. The time measurement method described in Appendix A2. (Note A4) In the step of performing the aforementioned time measurement, Upon receiving the request for time measurement from the peripheral circuit, the measurement is performed. After outputting the results of all time measurements that have been requested, the time measurement is stopped until the next request is received. The time measurement method described in Appendix A1. (Note A5) The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. The aforementioned clock generation circuit is A first oscillator circuit that generates a first clock signal, A second oscillator circuit that generates a second clock signal different from the first clock signal, A frequency divider circuit that divides the frequency of the aforementioned second clock signal to generate a third clock signal, A selection circuit that selects a clock signal to be used for time measurement from a plurality of clock signals, including the first clock signal, the second clock signal, and the third clock signal, according to the request, It has, In the step of performing the aforementioned time measurement, Control the selection of the clock signal in the selection circuit. When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on mutually different clock signals. The time measurement method described in Appendix A2. (Note A6) In the step of performing the aforementioned time measurement, Controlling the oscillation and cessation of the first clock signal in the first oscillation circuit, and the oscillation and cessation of the second clock signal in the second oscillation circuit. The time measurement method is as described in Appendix A5. (Note A7) The clock signal includes a signal that alternates between high-voltage and low-voltage states. The step of performing the aforementioned time measurement is: The step of receiving the request for time measurement from the peripheral circuit, A step of calculating a target count for the measurement time as a target value from the measurement time in the time measurement that received the request and the clock signal, The step of storing the aforementioned target value, The steps include: storing the count obtained by counting the number of times the clock signal is in the high-voltage state or the low-voltage state as a counter value; A step of comparing the counter value with the target value, The step of outputting the result of the time measurement to the peripheral circuit when the counter value and the target value match, Having, The time measurement method described in Appendix A1. (Note A8) The step of performing the aforementioned time measurement is: The step of selecting a clock signal based on the peripheral circuit that requested the aforementioned time measurement, The steps include: performing multiple time measurements using the aforementioned clock signal; It has, In the step of selecting the aforementioned clock signal, A different clock signal is selected for each time measurement. The time measurement method described in Appendix A1. (Note A9) The step of performing the aforementioned time measurement is: A step of determining whether the request for time measurement from the peripheral circuit is permissible, The steps include: rejecting the request if the time measurement being performed cannot be continued, or if the number of time measurement requests that can be measured simultaneously exceeds the upper limit; Having, The time measurement method described in Appendix A1. (Note A10) The aforementioned peripheral circuit has a counter function for measuring time, If the request is rejected, the system further includes the step of causing the peripheral circuit to perform the time measurement using the counter function of the peripheral circuit. The time measurement method described in Appendix A9. (Note A11) The aforementioned peripheral circuit is a timer, The step of performing the aforementioned time measurement is: When the timer receives the request for time measurement, the step of converting the counter value, The steps include: causing the converted counter value to be output to the timer, Having, The time measurement method described in Appendix A7. (Note B1) A processing unit and Multiple peripheral circuits controlled by the aforementioned processing unit, A timing management circuit that outputs the result of the time measurement performed in response to a time measurement request from the peripheral circuit to the peripheral circuit, A time measurement program for a semiconductor device equipped with, A time measurement program that causes the computer to perform a step of causing the timing management circuit to perform the time measurement in response to each of the time measurement requests. (Note B2) The step of performing the aforementioned time measurement is: The step of starting the first time measurement when a first request for first time measurement is received from any of the plurality of peripheral circuits, If a second request for a second time measurement is received while the first time measurement is being performed, the first time measurement is continued while the second time measurement is started. Having, The time measurement program described in Appendix B1. (Note B3) The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. In the step of performing the aforementioned time measurement, When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on the same clock signal generated from the clock generation circuit. The time measurement program described in Appendix B2. (Note B4) In the step of performing the aforementioned time measurement, Upon receiving the request for time measurement from the peripheral circuit, the measurement is performed. After outputting the results of all time measurements that have been requested, the time measurement is stopped until the next request is received. The time measurement program described in Appendix B1. (Note B5) The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. The aforementioned clock generation circuit is A first oscillator circuit that generates a first clock signal, A second oscillator circuit that generates a second clock signal different from the first clock signal, A frequency divider circuit that divides the frequency of the aforementioned second clock signal to generate a third clock signal, A selection circuit that selects a clock signal to be used for time measurement from a plurality of clock signals, including the first clock signal, the second clock signal, and the third clock signal, according to the request, It has, In the step of performing the aforementioned time measurement, Control the selection of the clock signal in the selection circuit. When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on mutually different clock signals. The time measurement program described in Appendix B2. (Note B6) In the step of performing the aforementioned time measurement, Controlling the oscillation and cessation of the first clock signal in the first oscillation circuit, and the oscillation and cessation of the second clock signal in the second oscillation circuit. The time measurement program is described in Appendix B5. (Note B7) The clock signal includes a signal that alternates between high-voltage and low-voltage states. The step of performing the aforementioned time measurement is: The step of receiving the request for time measurement from the peripheral circuit, A step of calculating a target count for the measurement time as a target value from the measurement time in the time measurement that received the request and the clock signal, The step of storing the aforementioned target value, The steps include: storing the count obtained by counting the number of times the clock signal is in the high-voltage state or the low-voltage state as a counter value; A step of comparing the counter value with the target value, The step of outputting the result of the time measurement to the peripheral circuit when the counter value and the target value match, Having, The time measurement program described in Appendix B1. (Note B8) The step of performing the aforementioned time measurement is: The step of selecting a clock signal based on the peripheral circuit that requested the aforementioned time measurement, The steps include: performing multiple time measurements using the aforementioned clock signal; It has, In the step of selecting the aforementioned clock signal, A different clock signal is selected for each time measurement. The time measurement program described in Appendix B1. (Note B9) The step of performing the aforementioned time measurement is: A step of determining whether the request for time measurement from the peripheral circuit is permissible, The steps include: rejecting the request if the time measurement being performed cannot be continued, or if the number of time measurement requests that can be measured simultaneously exceeds the upper limit; Having, The time measurement program described in Appendix B1. (Note B10) The aforementioned peripheral circuit has a counter function for measuring time, If the request is rejected, the system further includes the step of causing the peripheral circuit to perform the time measurement using the counter function of the peripheral circuit. The time measurement program described in Appendix B9. (Note B11) The aforementioned peripheral circuit is a timer, The step of performing the aforementioned time measurement is: When the timer receives the request for time measurement, the step of converting the counter value, The steps include: causing the converted counter value to be output to the timer, Having, The time measurement program described in Appendix B7. [Explanation of symbols]

[0120] 1, 2, 3 Semiconductor equipment 10 Arithmetic Processing Unit 11 Internal surrounding bus 12 Storage device 20 Clock generation circuit 21a Oscillator A 21b Oscillator B 23, 23a, 23b, 23c Oscillation stabilization waiting circuit 25a Oscillator Circuit A 25b Oscillator circuit B 27, 28 frequency divider circuit 29 Selection Circuit 30, 30a, 30b timers 31 Registers 34 Interface Circuit 40 IP Communication 41 Peripheral Circuits 50 Timing Management Circuit 51 Registers 52 Counter Circuit 53 Clock control circuit 54 Timing generation circuit 55 Counter value conversion unit 56 Counter section 56a Counter section A 56b Counter section B 57a, 57b, 57c comparison section 58a, 58b, 58c storage section 59 Calculation Circuit 60 Judgment section 101 Semiconductor Equipment 110 Arithmetic Processing Unit 111 Internal surrounding bus 120 Clock generation circuit 121a Oscillator A 121b Oscillator B 121c, 121d, 121e oscillators 123, 123a, 123b, 123c, 123d, 123e Oscillation stabilization waiting circuit 130, 130a, 130b timers 131 Registers 132 Counter Circuit 133 Clock Selection Circuit 140 IP Communications A0, A1 comparator B0, B1 comparator BSC Bus Controller CLK clock signal CMTW Compare Match Timer CPU, MPU (Master Processing Unit) DMAC DMA controller DTC Data Transfer Controller ICU (Interrupt Controller) RAM, ROM storage device TCNT counter circuit TFU Trigonometric Function Calculator TMR Timer

Claims

1. A processing unit and Multiple peripheral circuits controlled by the aforementioned processing unit, A timing management circuit that outputs the result of the time measurement performed in response to a time measurement request from the peripheral circuit to the peripheral circuit, Equipped with, The timing management circuit performs the time measurement in response to each of the time measurement requests. Semiconductor equipment.

2. The aforementioned timing management circuit is When a first request for first time measurement is received from any of the plurality of peripheral circuits, the first time measurement is started. If a second request for a second time measurement is received while the first time measurement is being performed, the second time measurement will be started while the first time measurement continues. The semiconductor device according to claim 1.

3. The timing management circuit further comprises a clock generation circuit that generates a clock signal which serves as a reference for time measurement, The timing management circuit, when performing the first time measurement and the second time measurement, performs the first time measurement and the second time measurement based on the same clock signal generated from the clock generation circuit. The semiconductor device according to claim 2.

4. The aforementioned timing management circuit is Upon receiving the request for time measurement from the peripheral circuit, the time measurement is performed. After outputting the results of all the time measurements for which the aforementioned request was received, the time measurement is stopped until the next aforementioned request is received. The semiconductor device according to claim 1.

5. The timing management circuit further comprises a clock generation circuit that generates a clock signal which serves as a reference for time measurement, The aforementioned clock generation circuit is A first oscillator circuit that generates a first clock signal, A second oscillator circuit that generates a second clock signal different from the first clock signal, A frequency divider circuit that divides the frequency of the second clock signal to generate a third clock signal, A selection circuit that selects a clock signal to be used for time measurement from a plurality of clock signals, including the first clock signal, the second clock signal, and the third clock signal, according to the request, It has, The aforementioned timing management circuit is The selection circuit has a clock control circuit that controls the selection of the clock signal, When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on mutually different clock signals. The semiconductor device according to claim 2.

6. The clock control circuit controls the generation and stopping of the first clock signal in the first oscillation circuit, and the generation and stopping of the second clock signal in the second oscillation circuit. The semiconductor device according to claim 5.

7. The clock signal includes a signal that alternates between high-voltage and low-voltage states. The aforementioned timing management circuit is A timing generation circuit that receives the request for time measurement from the peripheral circuit and outputs the result of the time measurement to the peripheral circuit, A counter circuit that holds a count obtained by counting the number of times the clock signal is in the high-voltage state or the low-voltage state as a counter value, It has, The aforementioned timing generation circuit is A calculation circuit that calculates the target count of the measurement time as a target value from the measurement time in the time measurement that received the request and the clock signal, A storage unit that stores the target value, A comparison unit that compares the counter value with the target value, Having, The semiconductor device according to claim 1.

8. The aforementioned timing management circuit is Multiple counter units that perform the aforementioned time measurement using a clock signal, A clock control circuit that selects the clock signal used in the counter unit based on the peripheral circuit that requested the aforementioned time measurement, It has, The clock control circuit selects mutually different clock signals for each counter unit. The semiconductor device according to claim 1.

9. The timing management circuit has a determination unit that determines whether or not the request for time measurement from the peripheral circuit is valid. The determination unit rejects the request if it cannot continue the time measurement that is currently being performed, or if the number of time measurement requests that can be measured simultaneously exceeds the upper limit. The semiconductor device according to claim 1.

10. The aforementioned peripheral circuit has a counter function for measuring time, If the determination unit rejects the request, it causes the peripheral circuit to perform the time measurement using the counter function of the peripheral circuit. The semiconductor device according to claim 9.

11. The aforementioned peripheral circuit is a timer, The timing management circuit has a counter value conversion unit that converts the counter value, When the counter value conversion unit receives the time measurement request from the timer, it outputs the converted counter value to the timer. The semiconductor device according to claim 7.

12. A processing unit and Multiple peripheral circuits controlled by the aforementioned processing unit, A timing management circuit that outputs the result of the time measurement performed in response to a time measurement request from the peripheral circuit to the peripheral circuit, A time measurement method in a semiconductor device equipped with, The timing management circuit includes a step of performing the time measurement in response to each of the time measurement requests. Method of measuring time.

13. The step of performing the aforementioned time measurement is: The step of starting the first time measurement when a first request for first time measurement is received from any of the plurality of peripheral circuits, If a second request for a second time measurement is received while the first time measurement is being performed, the first time measurement is continued while the second time measurement is started. Having, The time measurement method according to claim 12.

14. The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. In the step of performing the aforementioned time measurement, When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on the same clock signal generated from the clock generation circuit. The time measurement method according to claim 13.

15. In the step of performing the aforementioned time measurement, Upon receiving the request for time measurement from the peripheral circuit, the measurement is performed. After outputting the results of all time measurements that have been requested, the time measurement is stopped until the next request is received. The time measurement method according to claim 12.

16. The semiconductor device further comprises a clock generation circuit that generates a clock signal which serves as the reference for time measurement in the timing management circuit. The aforementioned clock generation circuit is A first oscillator circuit that generates a first clock signal, A second oscillator circuit that generates a second clock signal different from the first clock signal, A frequency divider circuit that divides the frequency of the second clock signal to generate a third clock signal, A selection circuit that selects a clock signal to be used for time measurement from a plurality of clock signals, including the first clock signal, the second clock signal, and the third clock signal, according to the request, It has, In the step of performing the aforementioned time measurement, Control the selection of the clock signal in the selection circuit. When performing the first time measurement and the second time measurement, the first time measurement and the second time measurement are performed based on mutually different clock signals. The time measurement method according to claim 13.

17. In the step of performing the aforementioned time measurement, Controlling the oscillation and stopping of the first clock signal in the first oscillation circuit, and the oscillation and stopping of the second clock signal in the second oscillation circuit. The time measurement method according to claim 16.

18. The clock signal includes a signal that alternates between high-voltage and low-voltage states. The step of performing the aforementioned time measurement is: The step of receiving the request for time measurement from the peripheral circuit, A step of calculating a target count for the measurement time as a target value from the measurement time in the time measurement that received the request and the clock signal, The step of storing the aforementioned target value, The steps include: storing the count obtained by counting the number of times the clock signal is in the high-voltage state or the low-voltage state as a counter value; A step of comparing the counter value with the target value, The step of outputting the result of the time measurement to the peripheral circuit when the counter value and the target value match, Having, The time measurement method according to claim 12.

19. The step of performing the aforementioned time measurement is: The step of selecting a clock signal based on the peripheral circuit that requested the aforementioned time measurement, The steps include: performing multiple time measurements using the aforementioned clock signal; It has, In the step of selecting the aforementioned clock signal, A different clock signal is selected for each time measurement. The time measurement method according to claim 12.

20. A processing unit and Multiple peripheral circuits controlled by the aforementioned processing unit, A timing management circuit that outputs the result of the time measurement performed in response to a time measurement request from the peripheral circuit to the peripheral circuit, A time measurement program for a semiconductor device equipped with, A program that defines the process for setting or performing the operation of the timing management circuit, and is executed by the arithmetic processing unit, including a computer. A time measurement program that causes the computer to perform a step of causing the timing management circuit to perform the time measurement in response to each of the time measurement requests.

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