A quantum system configured for conditional transport using just-in-time waveform selection.

Abstract

To select a quantum system controller arranged so as to carry out conditional transportation using just-in-time wave selection.SOLUTION: A quantum system controller includes a processing device arranged so as to carry out generation of a pair of processed wave files configured so as to cause a quantum processor of a quantum computer to execute a quantum circuit, pre-loading of the processed wave files to one or a plurality of optional waveform generators, and provision of at least one signal to the one or the plurality of optional waveform generators to carry out at least one of the pre-loaded and processed wave files so that the signal supplied to the optional waveform generator to execute at least one of the preloaded and processed wave files should correspond to evaluation of a conditional operation by the quantum system controller. The signal provided to the optional wave generator allows just-in-time selection of a waveform which is not present on a path that the quantum circuit expects.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 208,644, filed on June 9, 2021, the entire content of which is incorporated herein by reference.

[0002] Various embodiments relate to a quantum system controller for a quantum computer and related methods that enable conditional transport using just - in - time waveform selection. For example, some embodiments relate to a quantum system controller for a quantum computer and related methods that may be configured to perform both conditional transport and just - in - time waveform selection.

Background Art

[0003] Large - scale quantum computers are expected to solve problems that are currently intractable with today's technology. Solving such problems involves computations employing quantum algorithms implemented using quantum circuits. Quantum algorithms require that specific waveforms be applied in one or more specific orders to implement a quantum circuit, and the implementation of a specific waveform may depend on the state of one or more qubits. Through expended effort, ingenuity, and innovation, many of the drawbacks of conventional quantum system controllers for quantum computers for executing quantum algorithms and the configurations of quantum system controllers of quantum computers have been solved by developing solutions constructed in accordance with embodiments of the present invention, many examples of which are detailed herein.

Summary of the Invention

Means for Solving the Problems

[0004] Exemplary embodiments provide methods, systems, apparatus, computer program products, etc., for performing conditional transport using just-in-time waveform selection. For example, various embodiments provide methods, systems, apparatus, computer program products, etc., for compiling quantum circuits, which include determining the expected path of a quantum circuit when a conditional state may be evaluated, optimizing the operation of the quantum circuit, just-in-time selecting a waveform when the evaluation of the condition results in a branch that deviates from the expected path, and merging back into the expected path after the branch.

[0005] In exemplary embodiments, according to aspects of the present disclosure, the method includes the steps of: generating a set of processed waveform files configured to cause a quantum processor of a quantum computer to execute a quantum circuit by a processing device of a quantum system controller of a quantum computer; causing the processing device to preload the processed waveform files into one or more arbitrary waveform generators; and causing the processing device to provide at least one signal to one or more arbitrary waveform generators to execute at least one of the preloaded processed waveform files, wherein the signal provided to the arbitrary waveform generators to execute at least one of the preloaded waveform files is in response to an evaluation of conditional operation by the quantum system controller.

[0006] In an exemplary embodiment, the method further includes the steps of: receiving one or more blocks by a processing device before generating a set of processed waveform files; compiling each of the one or more blocks into a quantum circuit by the processing device; analyzing the quantum circuit for the arrangement of qubits; and determining the expected path of the quantum circuit based on at least the arrangement of qubits.

[0007] In an exemplary embodiment, the quantum circuit consists of one or more conditional operations, there is a predicted path for the execution of one or more conditional operations of the quantum circuit, and the response of the quantum system controller to the evaluation of the conditional operations causes the execution of a waveform that is not on the predicted path of the quantum circuit.

[0008] In an exemplary embodiment, the method further includes the step of having a processing device provide at least one second signal to one or more arbitrary waveform generators in order to perform a merge operation to execute at least one of the preloaded waveform files and move it to a position along an expected path.

[0009] In an exemplary embodiment, the quantum circuit is optimized to reduce costs.

[0010] In an exemplary embodiment, cost is the transportation time.

[0011] In an exemplary embodiment, the set of processed waveform files corresponds to the expected path of the quantum circuit.

[0012] In an exemplary embodiment, the step of generating a set of processed waveform files includes determining a waveform file associated with a quantum circuit, receiving calibration data associated with the waveform and the quantum circuit, and formatting the waveform file using the calibration data.

[0013] In an exemplary embodiment, the calibration data includes a unique waveform ID.

[0014] In an exemplary embodiment, the calibration data includes the playback speed.

[0015] In exemplary embodiments, according to another aspect of the present disclosure, a quantum system controller is provided which includes a processing device comprising at least one first processing element. In exemplary embodiments, the first processing element is configured to generate a set of processed waveform files configured to cause a quantum processor of a quantum computer to execute a quantum circuit, to preload the processed waveform files into one or more arbitrary waveform generators, and to provide at least one signal to one or more arbitrary waveform generators to execute at least one of the preloaded waveform files, wherein the signal provided to the arbitrary waveform generators to execute at least one of the preloaded waveform files is provided in response to an evaluation of conditional operation by the quantum system controller.

[0016] In an exemplary embodiment, the first processing element is further configured to receive one or more blocks before the generation of a set of waveform files processed by the first processing element, to compile each of the one or more blocks into a quantum circuit, to analyze the quantum circuit for the arrangement of qubits, and to determine the expected path of the quantum circuit based on at least the arrangement of qubits.

[0017] In an exemplary embodiment, the quantum circuit consists of one or more conditional operations, there is a predicted path for the execution of the quantum circuit, and the response of the quantum system controller to the evaluation of the conditional operations causes the execution of a waveform that is not on the predicted path of the quantum circuit.

[0018] In an exemplary embodiment, the first processing element is further configured such that the processing device provides at least one second signal to one or more arbitrary waveform generators in order to perform a merge operation to execute at least one of the preloaded waveform files and move it to a position along an expected path.

[0019] In an exemplary embodiment, the quantum circuit is optimized to reduce costs.

[0020] In an exemplary embodiment, the cost is the transport time.

[0021] In an exemplary embodiment, the set of processed waveform files corresponds to the expected path of the quantum circuit.

[0022] In an exemplary embodiment, generating the set of processed waveform files includes determining waveform files related to the quantum circuit, receiving calibration data related to the waveforms and the quantum circuit, and formatting the waveform files using the calibration data.

[0023] In an exemplary embodiment, the calibration data includes a unique waveform ID.

[0024] In an exemplary embodiment, the calibration data includes a playback speed.

[0025] Having thus outlined the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale.

Brief Description of the Drawings

[0026] [Figure 1] A schematic diagram showing an exemplary quantum computing system including a quantum system controller according to an exemplary embodiment. [Figure 2] A schematic diagram of an exemplary quantum system controller of a quantum computer. [Figure 3] A schematic diagram of an exemplary computing entity of a quantum computer system that may be used by an exemplary embodiment. [Figure 4] A flowchart showing various processes, operations, and / or procedures executed by a quantum system controller to handle conditional operations according to various embodiments. [Figure 5]This flowchart illustrates various processes, operations, and / or procedures performed by a quantum system controller to address conditional operation in various embodiments. [Figure 6A] This figure shows various processes, operations, and / or procedures performed to illustrate the likely versus unlikely block processing in various embodiments. [Figure 6B] This figure shows various processes, operations, and / or procedures performed to illustrate the likely versus unlikely block processing in various embodiments. [Figure 6C] This figure shows various processes, operations, and / or procedures performed to illustrate the likely versus unlikely block processing in various embodiments. [Figure 6D] This figure shows various processes, operations, and / or procedures performed to illustrate the likely versus unlikely block processing in various embodiments. [Figure 7] This flowchart illustrates various processes, operations, and / or procedures performed by a quantum system controller in various embodiments. [Figure 8] This is a schematic diagram of an exemplary waveform determination system for a quantum computer for an exemplary embodiment. [Figure 9] This is a schematic diagram of exemplary hardware that may be used in exemplary embodiments. [Figure 10] This is a flowchart of processes, procedures, and operations performed, for example by a quantum system, to execute a waveform, according to various embodiments. [Figure 11] This figure shows a 6-bit trigger signal used by a quantum system controller with exemplary hardware configurations in various embodiments. [Modes for carrying out the invention]

[0027] The present invention will be more fully described below with reference to the accompanying drawings, which illustrate embodiments that are part of but not all of the present invention. Indeed, the present invention may be carried out in many different forms and should not be construed as being limited to the embodiments described herein, but rather these embodiments are provided to satisfy any legal requirements to which this disclosure may apply. The term “or” (also written as “ / ”) is used herein in both disjunctive and conjunctive senses unless otherwise indicated. The terms “explanatory” and “exemplary” are used to refer to examples that do not indicate a level of quality. The terms “generally,” “substantially,” and “approximately” mean, unless otherwise indicated, within engineering and / or manufacturing tolerances, and / or within the user’s measurement capabilities. Throughout, similar numbers refer to similar elements.

[0028] Exemplary embodiments provide methods, systems, apparatus, computer program products, etc., for conditional transport using just-in-time waveform selection, which may be real-time or near-real-time. For example, various embodiments provide methods, systems, apparatus, computer program products, etc., for determining the transport function required to execute a quantum circuit, which includes a path through the quantum circuit and / or a path through the quantum circuit having expected behaviors that are likely to occur as opposed to behaviors that are determined to be unlikely to occur. In various embodiments, the waveforms of the expected behaviors are determined in advance, while the waveforms of the unlikely behaviors are selected just in-time, for example, based on conditions within an ion trap, the quantum state of one or more ions confined within the ion trap, etc.

[0029] In various embodiments, the quantum computing system 100 is based on a quantum charge-coupled device (QCCD) architecture. In the QCCD architecture, captured ion qubits are reordered using a dynamic electric field generated by a time-dependent voltage (hereinafter referred to as a waveform) applied to a control electrode on an ion trap, and transported between different processing zones. In various embodiments, the waveform selected to perform the operation chosen to be sent to the ion trap during the operation of the quantum processor is not pre-programmed before the start of the quantum circuit, but rather is selected and programmed just in time immediately before the waveform is output to the ion trap. In various embodiments, the waveform may be selected to minimize any cost, such as latency. The use of just-in-time waveform selection has several important advantages, including, but not limited to, reducing the initialization time of the circuit, reducing the overall runtime of the circuit, eliminating unwanted ion transport and thus reducing harmful ion heating and quantum memory errors associated with transport, and facilitating more complex circuits that require qubit measurements to be performed while the device is operating.

[0030] In various embodiments, a user of a quantum system provides code to be executed on the quantum system. In various embodiments, the quantum system controller of a quantum computer includes classical and / or semiconductor-based processing devices configured to generate or compile a set of operations and execute those operations. The code may be divided into one or more blocks, which may or may not depend on conditions for determining whether a block of code is executed by the quantum system. The quantum system may compile each block independently. In various embodiments, for example, a block may represent a conditional block of code or a loop. The quantum system may merge blocks that share the same conditions, or blocks that require the same operation to be performed on one or more qubits. The quantum system may also compile blocks to add transport operations to one or more qubits, or to change the state of one or more qubits.

[0031] In various embodiments, a user may provide, along with or separately from providing code, weights indicating how likely or unlikely an action related to a portion of the code (e.g., a block) is to be performed. In various embodiments, a user may provide a flat rating where all blocks and / or actions are equally likely to be performed. In various embodiments, a user may provide a preferred taken rating where certain conditions are assumed and the relevant blocks and / or actions are likely to be performed. In various embodiments, a user may provide a preferred untaken rating where certain conditions are assumed and the relevant blocks and / or actions are unlikely to be performed. In various embodiments, a user may provide hint weightings indicating how likely a block or action is to be performed. In various embodiments, such weightings may be used to determine the expected overall cost associated with performing a more likely path. In various embodiments, weightings may alternatively be determined by simulation, modeling, or analytical computation. A simulation, model, or computation may deal with the entire quantum circuit to achieve full fidelity, or it may deal with one or more parts of the quantum circuit. Such a simulation, model, or computation may involve analysis and / or making decisions based on specific hardware used with the quantum circuit. In some embodiments, the simulation, model, or computation may be performed locally, such as by the quantum computing system 100, or it may be performed remotely, such that an output is provided to the quantum computing system 100.

[0032] In various embodiments, the weighting results may be used to determine the expected path and select the associated operations and / or waveforms. Unplanned branches may be treated recursively so that unplanned branches of operations branch from an initial branch point to a re-join point. The initial branch point may be associated with a particular qubit configuration. The re-join point may also be associated with a particular qubit configuration, which may or may not be the same as the initial branch point.

[0033] In various embodiments, optimization may be performed after the expected paths have been identified. In various embodiments, as discussed herein, the execution of blocks, actions, or shards may include ordering qubits in a trap in a particular way, gate-controlling one or more qubits, transporting qubits to a particular location, or performing actions on one or more qubits. In various embodiments, optimization may include, but is not limited to, merging multiple conditional paths, duplicating conditional or unconditional blocks or actions on multiple paths, moving transports in a loop out of a loop, including enabling branching or rejoining points to be more efficient, or any combination thereof. Such optimization may, for example, allow the execution of an action by a waveform sent to a trap to occur only once, rather than by multiple waveform transmissions that may (or may not) occur over multiple time periods.

[0034] Exemplary quantum computing system Figure 1 provides a schematic diagram of an exemplary quantum computing system 100, according to an exemplary embodiment, which includes a quantum processor and an atomic object confinement device 120 (e.g., an ion trap) that confines a plurality of atomic objects (e.g., atoms, ions, etc.) inside. In various embodiments, the quantum computing system 100 includes a computing entity 10 and a quantum computer 110. In various embodiments, the quantum computer 110 includes a quantum system controller 30 and a quantum processor 115. In various embodiments, the quantum system controller 30 is configured and programmed to control the quantum processor 115. In an exemplary embodiment, the quantum processor 115 includes a plurality of qubits (e.g., data qubits which may be organized into logical qubits, ancilla qubits, etc.). In various embodiments, the quantum computer 110 includes or communicates with a database (not shown) as described herein. For example, the database may be stored by one or more computing entities 10 that communicate with the controller 30 via one or more wired and / or wireless networks 20, and / or in the controller 30's local memory.

[0035] In various embodiments, the quantum processor 115 includes means for controlling the evolution of quantum states of qubits. For example, in an exemplary embodiment, the quantum processor 115 includes a cryostat and / or vacuum chamber 40 surrounding a confinement device 120 (e.g., an ion trap), one or more manipulation sources 60, one or more voltage sources 50, and / or one or more optical collection systems 70. For example, the cryostat and / or vacuum chamber 40 may be a chamber with controlled temperature and / or pressure. In an exemplary embodiment, one or more manipulation sources 60 may consist of one or more lasers (e.g., optical lasers, microwave sources, and / or similar). In various embodiments, one or more manipulation sources 60 are configured to manipulate and / or induce controlled quantum state evolution of one or more atomic objects in the confinement device. In various embodiments, atomic objects in the atomic confinement device (e.g., ions trapped in an ion trap) act as data qubits and / or auxiliary qubits of the quantum processor 115 of the quantum computer 110. For example, in an exemplary embodiment in which one or more operating sources 60 include one or more lasers, the lasers may provide one or more laser beams to an atomic object trapped in a cryostat and / or confinement device 120 within a vacuum chamber 40. For example, the operating source 60 may generate and / or provide laser beams configured to ionize the atomic object, initialize the atomic object in a defined two-state qubit space of a quantum processor, perform gate control of one or more qubits of a quantum processor, read the quantum state of one or more qubits of a quantum processor, and so on.

[0036] In various embodiments, the quantum computer 110 includes an optical collection system 70 configured to collect and / or detect photons generated by qubits (for example, during a read procedure). The optical collection system 70 may include one or more optical elements (e.g., lenses, mirrors, waveguides, optical fiber cables, etc.) and one or more photodetectors. In various embodiments, the photodetectors may be photodiodes, photomultiplier tubes, charge-coupled device (CCD) sensors, complementary metal-oxide-semiconductor (CMOS) sensors, micro-electromechanical system (MEMS) sensors, and / or other photodetectors that are highly sensitive to light of the expected fluorescence wavelength of the qubits of the quantum computer 110. In various embodiments, the detectors may communicate electronically with the quantum system controller 30 via one or more A / D converters 225 (see Figure 2), etc.

[0037] In various embodiments, the quantum computer 110 comprises one or more voltage sources 50. For example, the voltage sources 50 may include a plurality of voltage drivers and / or voltage sources, and / or at least one RF driver and / or voltage source. In exemplary embodiments, the voltage sources 50 may be electrically coupled to corresponding potential generating elements (e.g., electrodes) of the confinement device 120. By changing the potential, ions may be moved between locations or states. In various embodiments, how the potential should be changed may be defined by a waveform that specifies one or more voltages to be applied over a period of time.

[0038] In various embodiments, the computing entity 10 is configured to allow a user to provide input to the quantum computer 110 (for example, through the user interface of the computing entity 10) and to receive, view, etc., outputs from the quantum computer 110. The computing entity 10 may communicate with the quantum system controller 30 of the quantum computer 110 via one or more wired or wireless networks 20, and / or via direct wired and / or wireless communication. In exemplary embodiments, the computing entity 10 may translate, configure, format, etc., information / data, quantum computing algorithms and / or circuits, etc., into a computing language, executable instructions, command set, etc., that the quantum system controller 30 can understand and / or execute. For example, the controller 30 is configured to generate machine code-level commands configured to cause the quantum computer 110 to execute quantum circuits when executed by the appropriate components of the quantum computer 110. In various embodiments, the computing entity 10 may provide quantum computing algorithms and / or circuits of a computing language that the quantum system controller 30 resolves into operations and shards (e.g., individual machine code-level commands or sets of machine code-level commands), which will be further discussed below.

[0039] In various embodiments, the quantum system controller 30 is configured to control a voltage source 50, a cryostat system and / or vacuum system that controls the temperature and pressure within the cryostat and / or vacuum chamber 40, an operating source 60, and / or other systems that control various environmental conditions (e.g., temperature, pressure, etc.) within the cryostat and / or vacuum chamber 40, and / or to manipulate and / or induce a controlled evolution of the quantum states of one or more atomic objects within the confinement device. For example, the quantum system controller 30 may induce a controlled evolution of the quantum states of one or more atomic objects within the confinement device in order to execute a quantum circuit and / or algorithm. For example, the quantum system controller 30 may cause a read procedure, possibly including coherent shelving, to be executed, possibly as part of the execution of a quantum circuit and / or algorithm. Furthermore, the quantum system controller 30 is configured to transmit and / or receive input data from the optical acquisition system 70 corresponding to the reading of the quantum states of qubits in the quantum computer 110. In various embodiments, atomic objects confined within a confinement device are used as qubits in a quantum computer 110.

[0040] Exemplary quantum system controller In various embodiments, the quantum computer 110 includes a quantum system controller 30 and a quantum processor 115. The quantum system controller 30 is configured to control various components of the quantum processor 115. For example, various embodiments are configured to perform one or more quantum error corrections on one or more data qubits in real time and / or near real time in response to the occurrence of one or more quantum errors experienced by one or more data qubits, which may be evaluated as conditional blocks.

[0041] In various embodiments, the quantum system controller 30 communicates with the optical acquisition system 70 so that the quantum system controller 30 is configured to receive input data captured and / or generated by the optical acquisition system 70. The quantum system controller 30 is further configured to perform quantum error correction by software-based correction and / or by physical application of quantum error correction to one or more qubits (for example, by controlling one or more voltage sources 50 and / or manipulator sources 60). In various embodiments, the quantum system controller 30 is further configured to control the cryostat system and / or vacuum system, cooling system, and / or other systems that control environmental conditions (e.g., temperature, humidity, pressure, etc.) within the cryostat and / or vacuum chamber 40.

[0042] As shown in Figure 2, in various embodiments, the quantum system controller 30 may include various quantum system controller elements, including a processing device 205, a memory 210, a driver controller element 215, a communication interface 220, an analog-to-digital (A / D) converter element 225, and the like. In various embodiments, the quantum system controller 30 is configured to receive input data generated by an optical acquisition system via the A / D converter 225. In various embodiments, the processing device 205 is configured to operate as described herein. In various embodiments, the quantum system controller 30 may include additional quantum system controller elements described herein, such as a waveform determination system 800 shown in Figure 8.

[0043] In various embodiments, the processing device 205 includes processing elements such as programmable logic devices (CPLDs), microprocessors, coprocessing entities, application-specific instruction-set processors (ASIPs), integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), hardware accelerators, and other processing elements and / or circuits. The term "circuit" may refer to an entirely hardware embodiment or a combination of hardware and computer program products. In an exemplary embodiment, the processing device 205 of the quantum system controller 30 includes and / or communicates with a clock.

[0044] In various embodiments, memory 210 includes non-temporary memory such as volatile and / or non-volatile memory storage, such as one or more of the following: hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. In various embodiments, memory 210 may store a queue of commands executed to run quantum algorithms and / or circuits (e.g., an executable queue), qubit records corresponding to the qubits of a quantum computer (e.g., a qubit record datastore, a qubit record database, a qubit record table, etc.), calibration tables, computer program code (e.g., one or more computer languages, a special quantum system controller language, etc.). In an exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 210 (for example, by processing device 205) causes the quantum system controller 30 to execute one or more steps, operations, processes, procedures, etc., for generating one or more sets of commands configured to cause the quantum processor 115 to execute at least a portion of a quantum circuit, update one or more qubit registries, etc. In an exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 210 causes the quantum system controller 30 to execute one or more commands.

[0045] In various embodiments, the driver quantum system controller element 215 includes one or more drivers and / or quantum system controller elements, each configured to control one or more drivers. In various embodiments, the driver quantum system controller element 215 may include drivers and / or driver controllers. For example, a driver controller may be configured to operate one or more corresponding drivers according to executable instructions, commands, etc., generated, scheduled, and executed by the quantum system controller 30. For example, a processing device 205 may generate one or more commands executed by a first driver.

[0046] In various embodiments, the driver controller element 215 enables the quantum system controller 30 to operate a voltage source 50, an operating source 60, a cooling system, a vacuum system, etc. In various embodiments, the drivers may be a laser driver (configured to operate and / or control one or more operating sources 60), a vacuum component driver, a driver for controlling the current and / or voltage applied to electrodes (configured to operate and / or control one or more voltage sources 50) used to maintain and / or control the trapping potential of the confinement device 120 (as well as other drivers for giving a driver action sequence to the potential generating elements of the confinement device), a cryostat and / or vacuum system component driver, a cooling system driver, etc.

[0047] Each driver controller element 215 corresponds to an endpoint in the system (e.g., a component of the operating source 60, a component of the voltage source 50 (high-frequency voltage source, arbitrary waveform generator (AWG), direct digital synthesizer (DDS), and / or other waveform generators), a component of the cooling and / or vacuum system, a component of the optical acquisition system 70, etc.). Each endpoint in the quantum computer 110 represents an individual hardware control. Each endpoint has its own set of microcommands that it accepts in various embodiments. Examples include, but are not limited to, the voltage source 50 such as a direct digital synthesizer (DDS), a component of the optical acquisition system 70 such as a photomultiplier tube (PMT), a component of the operating source 60 such as a laser driver and / or optical modulator switch, and / or a general-purpose output (GPO). Individual commands for the DDS allow setting the power level, frequency, and phase of the control signals it generates. Commands for the PMT interface include, in various embodiments, starting / stopping and resetting the photon count. Commands for the GPO endpoint include setting and / or clearing one or more output lines. These output lines can be used to control external hardware in a manner synchronized with the execution of the quantum circuit.

[0048] In various embodiments, the quantum system controller 30 includes means for transmitting and / or receiving signals from one or more optical receiver components (e.g., of the optical acquisition system 70). For example, the quantum system controller 30 may include one or more analog-to-digital (A / D) converter elements 225 configured to receive signals from one or more optical receiver components (e.g., photodetectors of the optical acquisition system 70), calibration sensors, etc. In various embodiments, the A / D converter elements 225 are configured to write input data generated by converting received signals generated by one or more optical receiver components of the optical acquisition system 70 to a memory 210.

[0049] In various embodiments, the quantum system controller 30 may include, for example, a communication interface 220 for interfaceing with and / or communicating with the computing entity 10. For example, the quantum system controller 30 may include a communication interface 220 for receiving executable instructions, command sets, etc., from the computing entity 10 and providing the computing entity 10 with outputs received from the quantum computer 110 (for example, from the optical collection system 70) and / or the results of processing those outputs. In various embodiments, the computing entity 10 and the quantum system controller 30 may communicate directly via wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0050] Exemplary Computing Entity Figure 3 provides a descriptive schematic diagram of an exemplary computing entity 10 that may be used in conjunction with embodiments of the present disclosure. In various embodiments, the computing entity 10 is a classical (e.g., semiconductor-based) computer configured to allow a user to provide input to a quantum computer 110 (e.g., through the user interface of the computing entity 10) and to receive, display, analyze, and so on outputs from the quantum computer 110.

[0051] As shown in Figure 3, the computing entity 10 may include an antenna 312, a (e.g., wireless) transmitter 304, a (e.g., wireless) receiver 306, and processing elements 308 that each provide signals to the transmitter 304 and receive signals from the receiver 306. The signals provided to the transmitter 304 and received from the receiver 306 may include signaling information / data according to applicable wireless system wireless interface standards for communicating with various entities such as the quantum system controller 30 and other computing entities 10. The computing entity 10 may include a network interface 320 that provides and receives signals according to applicable network system interface standards for communicating with various entities such as the quantum system controller 30 and other computing entities 10.

[0052] In this regard, the computing entity 10 may be capable of operating with one or more wireless interface standards, communication protocols, modulation types, and access types. For example, the computing entity 10 may be configured to receive and / or provide communications using wired data transmission protocols such as Fiber Optic Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol. Similarly, Computing Entity 10 supports General-Purpose Packet Radio Services (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long-Term Evolution (LTE), Evolutionary Universal Terrestrial Radio Access Network (E-UTRAN), Evolved Data Optimized (EVDO), High-Speed ​​Packet Access (HSPA), High-Speed ​​Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), and Wi-Fi. It may be configured to communicate over a wireless external communication network using any of the following protocols: Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, Near Field Communication (NFC) protocol, Wibree, Bluetooth protocol, Wireless Universal Serial Bus (USB) protocol, and / or any other wireless protocol.Computing entity 10 may communicate using such protocols and standards, including Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP, HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), and Hypertext Markup Language (HTML).

[0053] These communication standards and protocols allow computing entity 10 to communicate with various other entities using concepts such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identification Module Dialer (SIM dialer). Computing entity 10 can also download changes, add-ons, and updates to its firmware, software (including executable instructions, applications, and program modules), and operating system, for example.

[0054] The computing entity 10 may also include user interface devices, including one or more user input / output interfaces (for example, a display 316 and / or speaker / speaker driver coupled to the processing element 308, as well as a touchscreen, keyboard, mouse, and / or microphone coupled to the processing element 308). For example, a user output interface may be configured to provide applications, browsers, user interfaces, interfaces, dashboards, screens, web pages, pages, and / or similar words used herein to be interchangeable, to trigger the display or audible presentation of information / data, and for interaction with that information / data via one or more user input interfaces. A user input interface may include any of many devices that enable the computing entity 10 to receive data, such as a keypad 318 (hard or soft), a touch display, a voice / speech or motion interface, a scanner, a reader, or other input device. In embodiments including a keypad 318, the keypad 318 may include (or trigger the display of) conventional numerals (0-9) and associated keys (#, *), as well as other keys used to operate the computing entity 10, and may include a complete set of alphabet keys, or a set of keys that may be activated to provide a complete set of alphabet keys. In addition to providing input, the user input interface may be used to enable or disable certain functions, such as a screen saver and / or sleep mode. Through such input, the computing entity 10 may collect information / data, user interactions / input, etc.

[0055] The computing entity 10 may also include volatile storage or memory 322 and / or non-volatile storage or memory 324, which may be embedded and / or removable. For example, non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, etc. Volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. The volatile and non-volatile storage or memory may store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, executable instructions, etc., for implementing the functions of the computing entity 10.

[0056] Example of conditional branching behavior In various embodiments, the quantum system controller 30 is configured to control the operation of the quantum computer 110. For example, the quantum system controller 30 is configured to control the execution of operations by the quantum processor 115, such that the quantum processor performs one or more quantum computations by executing one or more quantum circuits. For program flow control, it is advantageous that the quantum system controller 30 can control the application of gates such as one or more qubits and the updating of classical states. Thus, in various embodiments, the control flow is handled at least in part through the real-time or quasi-real-time control mechanism of the quantum system controller 30. In various embodiments, this enables the analysis of conditional statements that may cause conditional branching, resulting in just-in-time waveform selection to deal with branching.

[0057] In various embodiments, the state of a trap is measured and used as input to determine whether a condition is met, in order to enable a real-time or near-real-time control flow to handle conditional branching. Examples of conditions may be whether the qubits in the trap are in a particular state, in a particular order, or a combination thereof. Depending on the state of the qubits, the quantum system controller 30 may be configured to perform at least one of a plurality of operations. Addressing which operation to perform may result in a quantum circuit operating along an expected path or taking a branch, as shown in Figures 4 and 5, which are discussed below. As discussed herein, a branch may include an expected operation, may not include an expected operation, or may include a combination thereof.

[0058] In various embodiments, the quantum system controller 30 may cause the quantum processor 115 to execute a first part of the quantum circuit by generating and executing a first operation or set of operations. Input data may be processed to make one or more decisions based on input values ​​called conditions, which may result in a decision about the next operation to be performed.

[0059] Figure 4 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum system controller to address conditional operations in various embodiments. The embodiment in Figure 4 shows an example in which the quantum system controller 30 processes input data to determine whether or not a conditional operation should be performed.

[0060] Starting from step / operation 402, operation A is performed by the quantum system controller 30 and / or its driver controller element 215. There may be several operations that are performed before reaching step / operation 404, although these are not shown. The execution of operation A causes the quantum processor 115 to execute at least the first part of the quantum circuit.

[0061] In step / operation 404, the input data is processed, and a decision is made based on the processing of the input data to determine whether a conditional operation is performed. In other words, step / operation 404 is a conditional execution point in relation to the execution of a quantum circuit by a quantum computer, where the next step to be performed by the quantum computer is determined in real time or near real time during runtime. For example, the processing device 205 of the quantum system controller 30 processes input data representing the quantum state of one or more qubits as a result of the execution of a first part of a quantum circuit (e.g., operation A). This input data may be the state of one or more qubits in a trap. In step / operation 404, a decision is made depending on the input data and / or its processing. For example, condition B, which takes the input data as input and / or is a variable, is evaluated to determine the result of the condition. When condition B evaluates to yes or true, the process proceeds to step / operation 406. When condition B evaluates to no or false, the process proceeds to step / operation 408. Step / operation 404 illustrates condition B singularly, but condition B may evaluate multiple input data. For example, multiple input data associated with one or more qubits may be used to determine condition B. Furthermore, although condition B is shown in Figure 4 as proceeding to either step / operation 406 or step / operation 408, the condition may allow for three or more options (not shown in Figure 4).

[0062] As shown in Figure 4, if condition B is true, in step / operation 406, the processing device 205 performs conditional operation C. Although shown as operation C, step / operation 406 may include one or more operations performed by the processing device 205. In one example, operation C may include one or more commands configured, for example, to cause a qubit to be acted upon by the application of an operation signal to the qubit. The process may then proceed to step / operation 408, or to follow a different path, such as in embodiments where another condition is determined.

[0063] In step / operation 408, the processing device 205 may perform an operation to trigger a state transition that merges one or more qubits into a desired state. An operation to merge one or more qubits may include, for example, an operation to change the position of a qubit, or an operation to change the order of qubits to bring one or more qubits into a desired state.

[0064] As discussed herein, various embodiments may have expected paths relating to branching processes that depend on how likely a conditional operation is to occur. In various embodiments, as discussed herein, waveforms specific to the state of one or more qubits may be preloaded for execution. For the preloaded waveforms to be used to successfully execute the planned quantum circuit, one or more qubits must be in their expected states.

[0065] In the embodiment shown in Figure 4, and in embodiments where the expected path for condition B is no or false, the expected path is to predict a specific state of one or more qubits after the execution of operation A in step / operation 402, but before operation D in step / operation 410. In this embodiment, the expected path of the quantum circuit could be through operation A and then through operation D. The execution of these operations may predict that one or more qubits will be in a specific state before and after each operation, which may not occur when operation C is executed. In embodiments where only the operations of the expected path are performed (i.e., the condition is no or false), one or more qubits are in the expected state, and merge step / operation 408 does not need to be performed.

[0066] In an alternative embodiment, condition B may evaluate to yes or true, and action C, which is an action that deviates from the expected path, is performed. The execution of action C may put one or more qubits into a different state than would have been if action C had not been performed. A merge step / action 408 may need to be performed to return one or more qubits to the expected state into action D. Because this branch is a deviation from the expected path, in some embodiments, waveform selection may be performed just in time to select the waveform associated with action C and / or merge step / action 408. After the execution of merge step / action 408, the state of one or more qubits is the expected state, and step / action 410 may be performed as expected.

[0067] In step / operation 410, the processing device 205 performs operation D. Although shown as operation D, step / operation 410 may include one or more operations performed by the processing device 205.

[0068] Figure 5 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum system controller to address conditional operation in various embodiments. Figure 5 differs from Figure 4 in that, among other things, operation E of step / operation 507 is performed when condition B is no or false. Performing operation E may result in one or more qubits being in a state different from that of operation C.

[0069] In step / operation 404, the input data is processed and it is determined whether condition B is yes or no. In Figure 5, regardless of the determination of the condition, an operation—either operation C in step / operation 406 or operation E in step / operation 507—will be performed. The expected path may consist of operations A, E, and D, or operations A, C, and D. If the expected path is not taken, the state of one or more qubits may not be as expected before operation D in step / operation 410, as is considered herein, which may require an operation to merge one or more qubits into the expected state.

[0070] As discussed herein, various embodiments may have expected paths relating to branching processes that depend on how likely a conditional operation is to occur. In various embodiments, as discussed herein, waveforms specific to the state of one or more qubits may be preloaded for execution. For the preloaded waveforms to be used to successfully execute the planned quantum circuit, one or more qubits must be in their expected states.

[0071] In embodiments where the expected path anticipates the condition to be no or false (e.g., no branch is taken), the use of a merge step / action may be called a branch-back implication, which refers to one or more qubits being returned to the expected state as if the branch action had not been performed.

[0072] In embodiments where the expected path anticipates a condition to be yes or true (for example, a branch is taken), the use of a merge step / action may be called a branch-forward implication, which refers to one or more qubits being advanced to the expected state as if a branch action had been performed.

[0073] In embodiments using either a branch reversal suggestion or a branch forward suggestion, one or more qubits are brought to a predicted state such that an action performed after the conditional action may be performed as expected.

[0074] Exemplary behavior of block processing: high probability vs. low probability. In various embodiments, the quantum system controller 30 is configured to compile code describing a quantum circuit. In various embodiments, the code may include blocks of operation (hereinafter referred to as “blocks”) that are compiled such that the waveform applied to the trap electrodes may be determined. In various embodiments, at compile time, the code may be divided into one or more blocks, and the blocks may or may not depend on conditions for determining whether a block of code is executed by the quantum system. The quantum system may compile each block independently. Blocks that share the same conditions may be merged, which is sometimes called opportunistic merging. In various embodiments, for example, a block may represent a conditional block of code or a loop. The quantum system may merge blocks that share the same conditions, or blocks that require the same operation to be performed for one or more qubits. Due to conditions of the input data, etc., the compilation of a block may generate branches that may or may not be taken depending on the conditions. Furthermore, quantum systems may compile blocks to add transport operations to one or more qubits, or to change the state of one or more qubits.

[0075] In various embodiments, blocks may be translated into their individual operations. These individual operations may then be translated into shards (e.g., individual machine code-level commands and / or sets of machine code-level commands), which may be schedulable units of operations that provide specific operations to be performed on one or more particular qubits. In various embodiments, these schedulable units of operations may be used in conjunction with determining the waveform to apply, including the starting state of one or more qubits, the ending state of one or more qubits, and / or how long the waveform should be applied. In various embodiments, the shards are sortable when operations are scheduled, depending on the one or more qubits on which the operation is being performed. In various embodiments, the shards may be analyzed to determine the planned position and state of one or more qubits before and after the execution of each shard in the quantum circuit. In various embodiments, once the shards constituting the quantum circuit have been determined, the various operations performed on the qubits according to the shard schedule may be optimized to minimize some cost. The cost may be analyzed, among other things, as transport time, noise, heat, error estimation, fidelity, or a combination of these. In exemplary embodiments where transport time is used as a cost, each transport operation required to move a qubit for a gate control operation may require the application of one or more waveforms to bring the qubit to a desired state in order to enable gate control, and each waveform may be associated with a transport cost. In such embodiments, the transport cost may be reduced or minimized if the operations or shards are sorted or rearranged to minimize the number of waveforms applied to achieve the movement of the qubit to the desired state. The waveforms selected in such minimization may, in some embodiments, be selected based on offset values ​​associated with a processed waveform file, as discussed herein. Optimization may be performed by merging, splitting, or rearranging the operations applied to the electrodes by the waveforms.

[0076] Blocks, actions, and shards may be conditional, depending on the values ​​of input data, such as measurements associated with one or more qubits. As discussed herein, the likelihood of a condition being true or false may be predicted, among other things, as likely, unlikely, or flat. In various embodiments, the likelihood (or unlikelihood) may be assigned a numerical value, such as 0 to 100%. Optimization may incorporate assignments of likelihood (or unlikelihood) of blocks, actions, or conditions occurring during optimization. Furthermore, in various embodiments, a condition may be a loop requiring a block, action, or shard to repeat two or more times (e.g., loop), and such a condition may result in the loop condition being assigned a cost that is a multiple of the cost (e.g., 2x, 3x, 4x…) of the cost otherwise associated with the block, action, or shard. In some embodiments, the cost multiple may be due to the loop requiring one or more transport actions to be performed during each traverse of the loop. Optimization may lead to the determination of an expected path. As discussed herein, various embodiments cause the quantum circuit to determine a likely path of operation that may be optimized to minimize cost. The likely path may branch while avoiding less likely branches. In various embodiments, if a less likely branch is taken that deviates from the likely path, the quantum system controller 30 may select and execute a just-in-time waveform to take the less likely branch. Alternatively, the quantum system controller 30 may ensure that any deviation from the expected state caused by taking the less likely branch is addressed by a merge operation that returns one or more qubits to their expected state before traversing the likely path.

[0077] In various embodiments, determining the quantum circuit also involves verifying that the expected path can be executed without causing errors. This may include determining that all the waveforms applied to perform the operation allow the quantum circuit to be executed in a specific execution flow required for the completion of the quantum circuit. If a condition is evaluated that causes the quantum circuit to branch off from the expected path, the quantum system controller 30 may perform an operation related to the branch and then perform an operation that merges one or more qubits into the expected state where the taken branch began, so that the expected path can be continued, as is considered herein. In such embodiments, verifying only the expected path allows for resource savings of the quantum computing system 100 during compilation.

[0078] Figure 6A shows various processes, operations, and / or procedures performed to illustrate the likely versus unlikely block processing in various embodiments. Figure 6A shows a first unconditional block 602. Conditional block 604 shows a first conditional block with a condition that is likely to be true. Conditional block 606 shows a first conditional block with a condition that is unlikely to be true. Conditional block 608 shows a second conditional block with a condition that is likely to be true. Block 610 shows an unconditional block. In various embodiments where the likelihood of the conditions is as planned, blocks 602 and 610 are executed, blocks 604 and 608 are executed, and block 606 is not executed. Thus, during planning in such embodiments, operations relating to blocks determined to be likely to be executed (e.g., 604, 608) are scheduled as if they were unconditional for planning and optimization purposes, while operations relating to blocks determined to be unlikely to be executed (e.g., 606) are not further processed. In these embodiments, the plan is for conditional blocks 604 and 608 to be executed, but the quantum circuit will not execute these blocks unless the conditions for each of these blocks are met.

[0079] In planning the operation, various embodiments may resolve the blocks in Figure 6A into individual operations within each block of operation, as shown in Figure 6B. In other words, the block of operation 602 may resolve to operation 612, the conditional block of operation 604 may resolve to conditional operation 614, the conditional block of operation 606 may resolve to conditional operation 616, and the block of operation 602 may resolve to operation 612. Since the conditional block 606 in the embodiment shown in Figure 6A was evaluated as unlikely, the conditional block 606 is not resolved into an individual operation. Not resolving the conditional block 606 into an individual operation minimizes the resources required to compile the quantum circuit.

[0080] In the optimization plan, various embodiments may resolve the behavior in Figure 6B to each shard of the behavior, as shown in Figure 6C. In other words, the behavior of 612 may resolve to shard 622, the conditional behavior of 614 may resolve to conditional shard 624, the conditional behavior of 616 may resolve to conditional shard 616, and the behavior of 620 may resolve to shard 630. Conditional block 606 in the embodiment shown in Figure 6A is evaluated as unlikely and does not resolve to a behavior, so conditional block 606 does not resolve to a shard.

[0081] During optimization, shards may be optimized by rearranging them, including by providing scheduling for their operations. In various embodiments, optimizing shards allows for cost evaluation, including minimizing costs such as transport time. In various embodiments, analyzing the position and order of one or more qubits within a trap provides cost evaluation for transporting or gate-controlling one or more qubits.

[0082] Figure 6D shows how a qubit plan might deal with one or more qubits acted upon by shards 622, 624, 628, and 630, while conditional block 606 is not evaluated. Shards 624 and 628, which are determined to be likely to satisfy their conditions, are evaluated as if they were unconditional shards. In other words, the plan includes the execution of these shards. Thus, shards 622 and 624 are planned such that their starting position and state before execution are known, and their ending position and state after execution are known, as shown by qubit plan 632. Similarly, shards 628 and 630 are planned such that their starting position and state before execution are known, and their ending position and state after execution are known, as shown by qubit plan 640. If not resolved to a shard, conditional block 606 may become an obstacle to defining the start or end states associated with the execution of block 606. However, not resolving conditional block 606 to individual operations and / or shards minimizes the resources required to compile the quantum circuit. In such embodiments, the branching operations considered herein may return one or more qubits to a specific state if a condition is met (e.g., true) when it has been previously evaluated as unlikely to occur, in order to return one or more qubits to a position or state expected by qubit plans 632, 640 (e.g., a position along an expected path).

[0083] Figure 7 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum system controller in various embodiments.

[0084] In step / operation 702, Figure 7 shows that a block (e.g., block 602) is resolved into an individual operation. Various embodiments may resolve only unconditional blocks (e.g., 602, 610) and conditional blocks (e.g., 604, 608) that are evaluated as likely to be satisfied into an operation. In alternative embodiments, such as embodiments using flat rating, all blocks (e.g., 602, 604, 606, 608, and 610) may be resolved into an operation. In other alternative embodiments, only unconditional blocks (e.g., 602, 610) may be resolved into an operation. In yet other alternative embodiments, such as embodiments where the likelihood of conditional blocks being satisfied is rated by a numerical rating, unconditional blocks that are either above or below a threshold may be resolved into an operation.

[0085] In step / operation 704, the operation is resolved to the shard.

[0086] In step / operation 706, the shard is converted into a qubit plan (e.g., 632, 640). In various embodiments, all conditional shards (e.g., 624, 628) are treated as unconditional and as to be executed when converted into a qubit plan.

[0087] In various embodiments, the determination of shards related to the qubit plan generates the most likely path for the execution of the quantum circuit. For all blocks that do not lie on this path (e.g., block 606 that was not converted into an operation or shard), various embodiments may handle the requirements of these blocks differently. In an exemplary embodiment, the requirements of this block may be handled recursively with the requirement that the start position and state do not have to be identical to the end position and / or state, but that one or more qubits have defined start and end positions and / or states before and after each block that does not lie on the expected path, respectively.

[0088] In various embodiments, after a qubit plan is determined, optimization is performed according to the qubit plan. The qubit plan may allow for reordering of operations performed on qubits, such as merging multiple conditional paths, duplicating conditional or unconditional blocks on multiple paths, or moving transport operations. Optimization may reorder shards. In various embodiments, optimization may be performed to reduce the number of operations or shards, for example, to minimize transport time. In various embodiments, optimization may be due to one or more other factors, such as noise or heat, measurements taken (e.g., inputs to conditional blocks), and / or causes of errors. In various embodiments involving loops, optimization may be performed so as not to require the start or end state to be locked to a particular transport. In various embodiments, cost-weighting may prefer that transports be transitioned before the start of any loop or after the end of a loop.

[0089] Exemplary operation of a conditional transport protocol In various embodiments, the execution of a quantum circuit with conditional operations requires the selection of a runtime transport waveform that plays a role in moving one or more qubits to specific positions within an ion trap. While multiple conditional operations may exist, the set of waveforms for executing these waveforms is finite. The set of waveforms is developed so that all required transport movements can be achieved for all possible conditional operations that may be present in the user's program. In some embodiments, the conditional statement may trigger a runtime decision to take either a first path or a second path. Furthermore, this requires selecting the correct waveform to execute from the set of waveforms during runtime.

[0090] Figure 8 provides an exemplary schematic diagram of the waveform determination system 800. In various embodiments, the waveform determination system 800 is part of the quantum system controller 30. In exemplary embodiments, the waveform determination system 800 and / or at least a part thereof is part of the computing entity 10. In exemplary embodiments, the waveform determination system 800 includes and / or accesses information stored in a database accessible to the quantum system controller 30. Figure 8 shows four databases: a raw waveform database 815, a waveform metadata database 825, a calibration database 830, and a processed waveform database 840. In alternative embodiments, these databases may reside in the memory of the quantum system controller 30.

[0091] In the shown embodiment, the waveform determination system 800 further includes a waveform solver 810, a waveform processor 820, a waveform formatter 835, and a waveform server 845. In various embodiments, these functions may be performed by the processing elements 205 and / or memory 210 of the quantum system controller 30. In various alternative embodiments, one or more of these may be separate from the quantum system controller 30.

[0092] The waveform determination system 800 shown further illustrates an RPC (Remote Procedure Call) interface 850 that provides an interface to one or more remote interfaces. In various embodiments, the remote interfaces may be to a real-time sequence builder 855, an automatic calibration scheduler 860, and an operator interface 865. The dashed lines in Figure 8 indicate that the data transferred between the RPC interface 850 and the real-time sequence builder 855, the automatic calibration scheduler 860, and / or the operator interface 865 may be remote or over a network. In alternative embodiments, these may be local connections.

[0093] Each waveform required for the execution of a compiled quantum circuit may be assembled into a library. A program known as the waveform server 845 is responsible for processing and loading waveforms that may be required for the execution of the quantum circuit.

[0094] The quantum circuit may be provided to the waveform server 845. Due to hardware differences and hardware calibration, waveforms may need to be calibrated before being executed by the waveform generator. In various embodiments, one or more calibrated waveforms are loaded into one or more AWGs (arbitrary waveform generators) so that a particular waveform can be executed depending on conditions related to a conditional block. Each waveform is individually identified by unique identification information (e.g., a number or string). Depending on the conditions, the waveform identification information may be used to execute the waveform for the trap electrode. Before the waveform is loaded into the AWG module, various embodiments may require the waveform to be calibrated to suit specific hardware.

[0095] In various embodiments, the waveform solver 810 may determine the waveforms required to perform transport, gate functions, etc. The waveform solver may run a model or simulation, or it may be one or more people determining various waveforms. The waveforms to be determined may, for example, be for transporting ions from one position to another while minimizing heat and / or transport time. The waveforms may be represented as a sequence of numbers representing the voltage applied to electrodes over a sequence of time. Each set of waveforms applied to each electrode over a period of time constitutes a waveform file, which may be stored in a raw waveform database 815. However, the waveform file is operation-specific but not calibrated for specific hardware.

[0096] The waveform processor 820 receives an operation to be performed from the waveform server 845 and may query the raw waveform database 815 accordingly for the relevant waveform file to perform the operation. The raw waveform database 815 provides the waveform file, which may then be calibrated. The waveform processor 820 queries the waveform metadata database 825 and the calibration database 830 for data to calibrate the waveform file. The waveform metadata database 825 provides information for interpolating between waveforms and which calibration values ​​are associated with each waveform. Interpolation may be required because the voltages of two waveforms may not end and start at the same voltage, and the interpolation provides a voltage value that falls between the end of the first waveform and the beginning of the second waveform. The calibration database 830 provides calibration data related to specific hardware used to calibrate the waveform file so that the waveform applied to the electrodes is calibrated to perform the desired operation.

[0097] The waveform processor 820 provides the waveform formatter 835 with a waveform file, data from the waveform metadata database 825, and data from the calibration database 830. The waveform formatter formats or processes the waveform file to produce a processed waveform file, which may be stored in the processed waveform database 840. The processed waveform file may provide the voltages that the trap electrodes should have when the waveform is applied. The chain of electronics or hardware (e.g., amplification stages) from the AWG module to the electrodes may require different offsets, such as a DC offset or a time-varying offset that changes the waveform over a period of time. For example, similar electronics (e.g., amplification stages) may be used in various embodiments, but individual electronics may have different electrical characteristics that require different offsets, even if small. Furthermore, certain hardware may require different formats (e.g., binary, CSV files, etc.) for the waveforms to be loaded into the hardware. In various embodiments, the waveform formatter 835 may scale the waveform according to the specific hardware. In various embodiments, the waveform formatter 835 may be unaware of the hardware and simply apply calibration data when it is provided by the waveform processor 820. The processed waveform file is stored in the processed waveform database 840 so that it can be accessed by the waveform server 845, which may access the processed waveform and provide it to the AWG FPGA 870, which may be one or more FPGAs that generate the voltages constituting the processed waveform. In various embodiments, both the waveform file and the processed waveform file may refer to a set of waveforms containing multiple waveforms.

[0098] Due to temporal variations in the operating conditions of the ion trap, the calibrated DC offset value may be periodically updated and applied to the voltages contained in the waveform file. The calibrated DC offset value may be updated periodically or when the operator provides an update. The automatic calibration scheduler 860 performs periodically scheduled updates to the calibrated DC offset value. The operator interface 865 may allow the operator or user to provide, among other things, updated values ​​for calibration. In various embodiments, the operator interface 865 may also allow the operator to initiate a routine that triggers a system measurement used to determine and update the calibration data, for example, adding linear interpolation between waveforms based on an agreed pair of start and end voltages to account for the change between the end of a first waveform and the beginning of a second waveform file that is calibrated and formatted according to the current calibration data. In such embodiments, a user using the operator interface 865 causes the calibration data to be updated.

[0099] The waveform server 845 loads the processed waveform files into the memory of one or more AWG FPGAs 870. In various embodiments, the waveform server 845 further maps the waveform identification number or string to the in-memory index of that waveform on the AWG hardware and the duration of the waveform's playback. The waveform server 845 may provide this mapping to the real-time sequence builder 855. During the construction of a real-time sequence, the real-time sequence builder 855 uses the mapping from the waveform server to insert the appropriate AWG memory waveform index and waveform duration into the real-time sequence code to identify and execute waveforms related to desired operations, such as operations related to conditional blocks (e.g., 606).

[0100] The dashed lines connecting the waveform server 845 and one or more AWG FPGAs 870 indicate that one or more AWG FPGAs 870 may be placed in a physical enclosure.

[0101] The connections in Figure 8 may have arrows pointing in one or more directions to indicate the main data flow, but the arrows are not limiting when data may flow between each of the connected components in Figure 8. For example, in various embodiments, a query may be made between two components, requiring the query to be made in the first direction and the response in the second direction.

[0102] Figure 9 provides a schematic diagram of exemplary hardware that may be used in an exemplary embodiment. Figure 9 shows a PC 910, a control system 920, and three enclosures 930A, 930B, and 930C. Although the embodiment shown in Figure 9 shows three enclosures, any number of enclosures may exist and be connected as roughly shown in Figure 9. The embodiment shown in Figure 9 has a housing comprising PCI modules (e.g., 940A, 940B, and 940C), one or more AWG modules (e.g., 950A1, 950A2 in housing 930A, 950B1, 950B2, 950B3 in housing 930B, and 950C1, 950C2, and 950C3 in housing 930C), and one or more backplane connection cards (e.g., 970A in housing 930A, 970B1 and 970B2 in housing 930B, and 970C1 and 970C2 in housing 930C). In various embodiments, each AWG module may include one or more AWG FPGAs 870. In various embodiments, each AWG module may be loaded with one or more waveforms, each waveform being identified by its unique ID. Furthermore, the embodiment shown in Figure 9 has a digital input module 960 in housing 930A. As shown in Figure 9, PC 910 is connected to PCI module 940A of enclosure 930A via connection 980A, and quantum system controller 30 is connected to AWG module 950A1 via connection 985 and to digital input module 960 via connection 990. In various embodiments, PC 910 may be waveform server 845 of waveform determination system 800, and processed waveform files may be loaded into AWG modules 950A1 and 950A2 of enclosure 930A via connection 980A to PCI module 940A. PCI modules of each enclosure are connected (for example, via connections 980B and 980C), and processed waveform files associated with a particular AWG module are loaded into that AWG module via the PCI module of the enclosure of that particular AWG module. In this way, waveforms may be preloaded into AWG modules before the runtime evaluation of any conditional statements.

[0103] During runtime, an AWG module may be selected, and as a result, the waveform preloaded to that AWG module may be executed. In various embodiments, the waveform may be selected via a register in a digital input module (DIM). In such embodiments, the quantum control system 30 may communicate with the DIM via connection 930 and transmit a signal, such as using TTL (transistor-transistor logic) or other specific protocol, to send a bit to select a waveform in a particular AWG module by waveform ID. In various embodiments, if more bits are required than can be transmitted in parallel to the DIM, multiple transmission rounds of bits may be performed sequentially to identify a single waveform ID. In various embodiments, additional options regarding the waveform, such as playback speed, may be specified by additional data transfers.

[0104] When the waveform ID (or other option) is received by the DIM, the information is transferred to the AWG module via the enclosure's backplane. If multiple enclosures are required due to the hardware of the quantum computer 110, as shown in Figure 9, the backplanes may be connected synchronously via dedicated backplane connection modules and cables. Figure 9 shows one embodiment having backplane connections 970A, 970B1, 970B2, 970C1, 970C2 and connections 995A, 995B connecting the backplanes of enclosures 930A, 930B, and 930C.

[0105] Figure 10 provides flowcharts of processes, procedures, and operations performed by a quantum system in various embodiments. In step / operation 1002, the quantum system controller receives a waveform sequence associated with a quantum circuit. In various embodiments, the quantum circuit is associated with a likely path of the operation to be performed.

[0106] In step / operation 1004, the quantum system controller 30 receives calibration data which may include metadata used to calibrate the waveform. In various embodiments, as described herein, the calibration data may originate from one or more sources of calibration data.

[0107] In step / operation 1006, calibration data may be used to generate a processed waveform file. In various embodiments and as described herein, calibration data may be used to format the waveform file for use with specific hardware.

[0108] In step / operation 1008, the processed waveform file may be used to preload the waveform into the AWG FPGA. In various embodiments, the AWG FPGA may be located in one or more AWG modules of the enclosure.

[0109] In step / operation 1010, one or more of the preloaded waveforms may be executed. In various embodiments, once all AWG modules have been preloaded with waveforms, waveform regeneration is initiated via the connection 985 between the quantum system controller 30 and the AWG modules, which distributes a signal from the quantum system controller 30 to all AWG modules via the housing backplane connection. The quantum system controller 30 provides a signal or trigger to perform waveform regeneration by one or more AWG modules.

[0110] In various embodiments, multiple rounds of parallel bit transfers between quantum system controllers 920 may be used to encode higher bit depth information and additional information in order to identify waveform IDs in the AWG module as well as to provide a playback speed.

[0111] For example, as shown in Figure 11, when using a 6-bit trigger signal, transfers at times T0 and T1 may encode a 6-bit waveform ID together, and transfers T2 and T3 may encode a 6-bit lookup value relating to the playback speed using signals transmitted by channels having, for example, enable, B0, and B1. In alternative embodiments, additional channels may enable the transfer of additional bits, which may allow additional information to be transferred.

[0112] conclusion Many modifications and other embodiments of the invention described herein will come to mind to those skilled in the relevant art, utilizing the teachings shown in the above description and the accompanying drawings. Therefore, it should be understood that the invention should not be limited to any particular embodiment disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. While specific terminology is used herein, these terms are used only in a general and descriptive sense and not for limiting purposes. [Explanation of symbols]

[0113] 10 Computing Entities 20. Wired and / or wireless networks 30 Quantum System Controllers 40 Cryostat and / or vacuum chamber 50 Voltage source 60 Operation source 70 Optical Acquisition System 100 Quantum Computing Systems 110 Quantum Computers 115 Quantum Processors 120 Atomic Object Confinement Device 205 Processing Devices 210 memory 215 Driver Controller Elements 220 Communication Interfaces 225 Analog-to-Digital (A / D) Converter Element 304 Transmitter 306 Receiver 308 processing elements 312 Antenna 316 displays 318 Keypad 320 network interfaces 322 Volatile storage or memory 324 Non-volatile storage or memory 602 Block 1 604 Conditional Blocks 606 Conditional Blocks 608 Conditional Blocks 610 blocks 612 operation 614 Conditional operation 616 Conditional behavior, conditional shards 622 shards 624 Conditional Shards 628 shards 630 shards 632-qubit plan 640-qubit plan 800 Waveform Determination System 810 Waveform Solver 815 Raw Waveform Database 820 Waveform Processors 825 Waveform Metadata Database 830 Calibration Database 835 Waveform Formatter 840 Processed Waveform Databases 845 Waveform Server 850 RPC (Remote Procedure Call) Interface 855 Real-time Sequence Builder 860 Automatic Calibration Scheduler 865 Operator Interface 870 AWG FPGA 910 PC 920 Control System 930A enclosure 930B enclosure 930C chassis 940A PCI module 940B PCI module 940C PCI module 950A1 AWG module 950A2 AWG module 950B1 AWG module 950B2 AWG module 950B3 AWG module 950C1 AWG module 950C2 AWG module 950C3 AWG module 960 Digital Input Module 970A Backplane Connection Card 970B1 Backplane Connection Card 970B2 Backplane Connection Card 970C1 Backplane Connection Card 970C2 Backplane Connection Card 980A connection 980B connection 980C connection 985 connections 990 connections 995A connection 995B connection

Claims

1. It is a quantum system controller, A processing device including at least one first processing element, The at least one first processing element is Generating a set of processed waveform files from a set of waveform files, wherein the set of waveform files is associated with and calibrated for one or more operations, the set of processed waveform files is calibrated for a chain of electronic devices between at least one or more arbitrary waveform generators and one or more electrodes of a quantum computer, and the set of processed waveform files is configured to cause the quantum processor of the quantum computer to perform one or more operations of a quantum circuit. Preloading the processed set of waveform files into one or more arbitrary waveform generators, After the set of processed waveform files has been preloaded into one or more arbitrary waveform generators, at least one signal is provided to the one or more arbitrary waveform generators to execute at least one of the preloaded set of processed waveform files, wherein the at least one signal provided to the arbitrary waveform generators to execute at least one of the preloaded set of processed waveform files is provided in response to an evaluation of conditional operation by the quantum system controller. A quantum system controller configured to perform the following actions.

2. The at least one first processing element is The at least one first processing element receives one or more blocks before generating the set of processed waveform files, The at least one first processing element compiles each of the one or more blocks into the quantum circuit, The quantum circuit is analyzed for the arrangement of qubits, The quantum system controller according to claim 1, further configured to determine the expected path of the quantum circuit based on at least the arrangement of the qubits.

3. The quantum system controller according to claim 1, wherein the quantum circuit comprises one or more conditional operations, there exists a predicted path for the execution of the quantum circuit, the response of the quantum system controller to the evaluation of the conditional operations causes the execution of a waveform corresponding to an unexpected path, and the unexpected path is different from the predicted path of the quantum circuit.

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