Storage system and power consumption reduction method

Abstract

To provide a storage system and a power consumption suppression method for reducing power consumption without deteriorating I / O performance with a host.SOLUTION: There is provided a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host. The storage system includes: a plurality of components each configured to operate in a first power mode or at least one second power mode with lower power consumption in a switchable manner; a device operating state monitoring program 302 as an example of a state monitoring unit that monitors an operating state of each of the plurality of components; and a power mode control unit 305 that determines a power mode of at least one or more specific components to be the power saving mode being the second mode power based on a processing load related to each of the plurality of components, which is a result of monitoring by the state monitoring unit, and switches the power mode to the power saving mode to operate at least one or more specific components. The storage system executes, by the plurality of components with the storage device, control according to the data input / output request.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a storage system and a method for suppressing power consumption, and is suitable for application to a storage system related to a technology for suppressing the power consumption according to the power mode of each device mounted on at least one controller, for example.

Background Art

[0002] In recent years, the importance of technologies that create new value by accumulating and analyzing a huge amount of data represented by AI (Artificial Intelligence) has been increasing. In addition to accumulating a huge amount of data, a storage system having high-performance I / O (Input / Output) performance is required to analyze the accumulated data.

[0003] On the other hand, in order to realize the high performance of the storage system, the mounted CPU (Central Processing Unit) and I / O modules have been enhanced in performance. Along with this, the power consumption of the storage system has been increasing year by year, and in order to reduce the environmental load and power cost, a control technology that can achieve both high performance and energy saving is required. Regarding the power control of the storage system, Patent Document 1 discloses a technology for solving the problem that the power consumption of the SSD (Solid State Drive) is increasing.

[0004] In the technology disclosed in Patent Document 1, a function for limiting the power consumption and performance of the SSD is provided, and the power mode setting is determined in advance for each product model regarding the performance and power requirements (product specifications such as the maximum configuration) of the storage system to be mounted. Furthermore, in the technology disclosed in Patent Document 1, based on the configuration and load state of the SSD, the power modes of the SSD and the CPU are determined, and measures are taken to enable operation within the range of power that can be supplied to the storage system.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] International Publication No. 2018 / 193608 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, the technology disclosed in Patent Document 1 is a measure to address the increased power consumption of SSDs and cannot cope with the increased power consumption of the various components installed in the storage system. As a result, it does not reduce the overall power consumption of the storage system. To reduce the power consumption of the storage system, one could consider using devices with lower processing performance but lower power consumption for various components, but any of these methods risk degrading I / O performance with the host.

[0007] This invention was made in consideration of the above points, and aims to propose a storage system and a power consumption reduction method that can reduce power consumption without degrading I / O performance with the host. [Means for solving the problem]

[0008] To solve the above problems, the present invention provides a storage system having a storage device that stores data or outputs the stored data in response to data input / output requests from a host, comprising: a plurality of components that can switch between a first power mode and at least one second power mode having lower power consumption than the first power mode and operate accordingly; a state monitoring unit that monitors the operating state of each of the plurality of components; and a power mode control unit that determines the power mode of at least one specific component to be the second power mode based on the processing load for each of the plurality of components as a result of monitoring by the state monitoring unit, and operates the at least one specific component in the second power mode, wherein the plurality of components perform control with the storage device in response to the data input / output requests.Furthermore, the plurality of components are a plurality of devices that control data input / output processing with the host, the storage system comprises at least one controller that is equipped with the plurality of devices and controls data input / output processing with the host by the plurality of devices, the controller comprises the state monitoring unit and the power mode control unit, the power mode control unit comprises a power mode determination unit that determines to set the power mode of a specific device operating in the first power mode to the second power mode based on the magnitude of the impact on the data input / output processing when the power mode of a specific device among the plurality of devices is changed to the second power mode, and the power mode of the specific device The controller comprises a power mode change unit that switches to the determined second power mode, and the controller comprises a device management table that manages information about the plurality of devices, and a device operation history table that manages the operating status of the plurality of devices monitored by the status monitoring unit, and the power mode determination unit determines, with respect to the plurality of devices managed in the device management table, that changing the power mode of a particular device to the second power mode will have less than or equal to a predetermined standard impact on the data input / output processing, and that the power mode determination unit will set the power mode of the particular device to the second power mode based on the operating status of the plurality of devices managed in the device operation history table. I did that.

[0009] Furthermore, the present invention relates to a method for reducing power consumption of a storage system having a storage device that stores data or outputs the stored data in response to data input / output requests from a host, comprising: a status monitoring step in which a status monitoring unit monitors the operating status of each of a plurality of devices that control data input / output processing with a host, each of which can be switched between a first power mode and at least one second power mode having lower power consumption than the first power mode and operate accordingly; and a power mode control step in which a power mode control unit determines the power mode of at least one specific device to the second power mode based on the processing load for each of the plurality of devices as a result of the monitoring by the status monitoring step, and operates the at least one specific device in the second power mode, wherein the power mode control step is performed on the plurality of devices that are operating in the first power mode. Special The power mode determination step includes determining that the power mode of a particular device should be the second power mode based on the magnitude of the impact on the data input / output processing when the power mode of a particular device is changed to the second power mode, and changing the power mode of the particular device to the determined second power mode, wherein the power mode determination step determines, based on a device management table that manages information about a plurality of devices and a device operation history table that manages the operating status of the plurality of devices monitored by the status monitoring step, that changing the power mode of the particular device to the second power mode will have less than or equal to a predetermined standard impact on the data input / output processing, and the plurality of devices perform control with the storage device in response to the data input / output request. [Effects of the Invention]

[0010] According to the present invention, power consumption can be reduced without degrading the input / output performance with the host. [Brief explanation of the drawing]

[0011] [Figure 1] This is a system configuration diagram showing an example of the configuration of an information system including a storage system according to this embodiment. [Figure 2] This figure shows an example of the memory configuration shown in Figure 1. [Figure 3] Figure 2 shows an example of the program area configuration. [Figure 4] Figure 2 shows an example of the configuration of the management information area. [Figure 5] This figure shows an example of the configuration of a device management table. [Figure 6] This figure shows an example of the configuration of a device operation history table. [Figure 7] This figure shows an example of the procedure for power consumption control processing. [Figure 8] This figure shows an example of the procedure for monitoring the operating status of a device. [Figure 9] Figure 9 is a flowchart illustrating an example of the procedure for determining the power mode of the connected device. [Figure 10] Figure 9 is a flowchart illustrating an example of the procedure for determining the power mode of a device. [Figure 11] This figure shows an example of a processing flow for determining the power mode on a per-connected device basis. [Figure 12] Figure 9 is a flowchart illustrating an example of the procedure for determining the controller unit power mode. [Figure 13] This flowchart shows an example of the procedure for determining the power mode combination. [Figure 14] This flowchart shows an example of the procedure for changing the power mode. [Figure 15] This is a system configuration diagram showing an example of the configuration of an information system according to the second embodiment. [Figure 16]It is a diagram showing a configuration example of the memory of the management terminal shown in FIG. 15. [Figure 17] It is a diagram showing an example of a program stored in the program area shown in FIG. 16. [Figure 18] It is a diagram showing an example of information stored in the management information area shown in FIG. 16. [Figure 19] It is a diagram showing a configuration example of the controller management table shown in FIG. 18. [Figure 20] It is a diagram showing a configuration example of the controller operation history table shown in FIG. 18. [Figure 21A] It is a diagram showing a setting example of the controller power setting information table shown in FIG. 18. [Figure 21B] It is a diagram showing a setting example of the controller power setting information table shown in FIG. 18. [Figure 21C] It is a diagram showing a setting example of the controller power setting information table shown in FIG. 18. [Figure 22] It is a diagram showing an example of data exchanged in the process request and response between the storage system and the management terminal shown in FIG. 15. [Figure 23] It is a diagram showing an example of the storage system management screen. [Figure 24] It is a flowchart showing an example of the procedure of the controller power consumption control process. [Figure 25] It is a flowchart showing an example of the procedure of the controller operation state monitoring process shown in FIG. 24. [Figure 26] It is a flowchart showing an example of the procedure of the controller power mode determination and change process shown in FIG. 24. [Figure 27] It is a system configuration diagram showing a configuration example of the storage system. [Figure 28] It is a flowchart showing an example of the procedure of the controller power mode determination process. [Figure 29] It is a diagram explaining a configuration example of OQ and IQ. [Figure 30] It is a diagram explaining the data transfer path related to the host I / O process before the host I / O takeover. [Figure 31] This diagram illustrates the data transfer sequence related to host I / O processing before host I / O handover. [Figure 32] This diagram illustrates an example of a P2P data transfer path. [Figure 33] This diagram illustrates the data transfer path involved in host I / O processing after host I / O handover. [Figure 34] This diagram illustrates the data transfer sequence related to host I / O processing after host I / O handover. [Figure 35] This flowchart shows an example of the procedure for host I / O handover between controllers and controller power mode change. [Figure 36] This flowchart shows an example of the procedure for monitoring the controller status. [Figure 37] This flowchart shows an example of the procedure for resuming host I / O processing and changing the controller's power mode on a controller that was set to power-saving mode. [Figure 38] This diagram illustrates the data transfer path for host I / O processing after host I / O handover when using interrupts instead of polling. [Figure 39] This diagram illustrates the data transfer sequence related to host I / O processing after host I / O handover when using interrupts instead of polling. [Figure 40] This diagram illustrates the data transfer path involved in host I / O processing after host I / O handover. [Figure 41] This diagram illustrates the data transfer sequence related to host I / O processing after host I / O handover. [Figure 42] This flowchart shows an example of the procedure for host I / O handover between controllers and controller power mode change. [Figure 43] This flowchart shows an example of the procedure for resuming host I / O processing on a controller that was in power-saving mode and changing the controller's power mode. [Modes for carrying out the invention]

[0012] One embodiment of the present invention will be described in detail below with reference to the drawings.

[0013] In the following explanation, various types of information may be described using the expression "xxx table," but these types of information may also be represented by data structures other than tables. To indicate that the information is independent of the data structure, "xxx table" can be referred to as "xxx information." Furthermore, while names and alphanumeric characters are used as element identifiers in the following explanation, other types of identifiers (such as symbols) may also be used. Furthermore, in the following explanation, when describing similar elements without distinction, the common code (or reference code) in the reference code may be used, and when describing similar elements with distinction, the reference code (or element ID) may be used. Furthermore, in the following explanation, "memory" refers to the main memory in a typical computer system and may consist of one or more storage devices. For example, memory may consist of at least one main memory device among main memory devices (typically volatile storage devices) and auxiliary storage devices (typically non-volatile storage devices). Furthermore, in the following explanation, "PDEV" refers to a physical storage device, which is typically a non-volatile storage device (e.g., an auxiliary storage device). A PDEV can be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive). Furthermore, in the following explanation, each device constituting the storage system has the ability to adjust power consumption and processing power, and the adjustable levels are referred to as "power modes." In the following explanation, "power modes" are shown as defined finite levels, but they may also be infinitely adjustable. Furthermore, when describing processing with "program" as the subject, the program is executed by a processor (e.g., CPU (Central Processing Unit)) included in the storage controller, performing defined processing using memory resources (e.g., main memory) and / or communication interface devices as appropriate. Therefore, the subject of the processing may be the storage controller or the processor. The storage controller may also include hardware circuits that perform some or all of the processing. Computer programs may be installed from program source code. Program source code may be, for example, a program distribution server or a computer-readable storage medium. Furthermore, in the following description, "host" refers to a host system that sends I / O requests to a storage system, and may have interface devices, storage units such as memory, and processors connected thereto. The host system may consist of one or more host computers. At least one host computer may be a physical computer, and may include virtual host computers in addition to the physical host computers.

[0014] (1) First Embodiment Figure 1 is a system configuration diagram showing an example of the configuration of an information system 101 including a storage system 102 according to this embodiment. The information system 101 comprises one or more storage systems 102 and one or more host machines 103.

[0015] The storage system 102 comprises one or more controllers 104 and one or more PDEV boxes 105. The PDEV box 105 comprises one or more PDEV switches 112 and one or more PDEVs 113. In Figure 1, the controllers 104 and PDEV boxes 105 are directly connected, but they may also be connected via a network (not shown).

[0016] The controller 104 includes a CPU 106, memory 107, host I / F 108, PDEV I / F 109, accelerator 110, and network switch 111. In this embodiment, the CPU 106, memory 107, host I / F 108, PDEV I / F 109, accelerator 110, and network switch 111 included in the controller 104 are collectively referred to as "devices." Note that the devices mounted on the controller 104 are not limited to those described above and may include other devices, such as power supply-related devices.

[0017] The controller 104 has, as described above, a normal power mode (first power mode), at least one power-saving mode (second power mode) with lower power consumption than the normal power mode, a power-off mode (power-off mode) that turns off the power, and a standby mode (third power mode). The controller 104 incorporates multiple devices as an example of multiple components that can switch between any of these modes and operate in each mode. The controller 104 controls data input / output processing (I / O) between itself and the host machine 103 using these multiple devices.

[0018] The CPU 106 has one or more cores 114 and controls the entire controller 104. The CPU 106 operates based on a program stored in memory 107.

[0019] The host interface 108 is controlled by the CPU 106 and handles I / O requests and transmission / reception of I / O data from the host machine 103. The PDEV interface 109 is also controlled by the CPU 106 and handles data transmission / reception with the PDEV 113 via the PDEV switch 112 of the PDEV box 105.

[0020] The storage system 102 is configured with logical volumes capable of storing data, and data input / output processing is performed by the controller 104.

[0021] In this embodiment, the CPU 106, host I / F 108, PDEV switch, and accelerator 110 are connected via the network switch 111, but they may also be connected without going through the network switch 111, such as by being directly connected to the CPU 106. The memory 107 is directly connected to the CPU 106, but it may also be connected without going through the network switch 111, such as by being directly connected to the network switch 111. The controller 104 is connected via the network switch 111, but it may also be connected without going through the network switch 111, such as by being directly connected to the CPU 106. The PDEV 113 is connected to the PDEV I / F 109 via the PDEV switch 112, but it may also be connected without going through the PDEV switch 112.

[0022] In the storage system 102 described above, when the host I / F 108 receives I / O requests and transmission / reception of I / O data from the host machine 103 under the control of the CPU 106 via the network switch 111, the CPU 106 controls the PDEV I / F 109 via the network switch 111 and performs data input / output processing to the PDEV 113 via the PDEV switch 112 of the PDEV BOX 105. At this time, within the controller 104, each device set to a predetermined power mode consumes power according to that power mode. The CPU 106 constantly monitors the operating status of each device and acquires operating information indicating the operating status of each device.

[0023] Figure 2 shows an example configuration of the memory 107 shown in Figure 1. Memory 107 is allocated a program area 201, a management information area 202, and a cache area 203. The program area 201 is the area where each program used by the CPU 106 to perform processing is stored.

[0024] The management information area 202 is an area accessed by the CPU 106 and stores various management tables. The cache area 203 is an area where data is temporarily stored during data transfer via the host I / F 108 and PDEV I / F 109, etc.

[0025] Figure 3 shows an example of a program stored in the program area 201 shown in Figure 2. The program area 201 stores, for example, a power consumption control program 301, a device operating status monitoring program 302, and, as an example of a power mode control unit 305, a power mode determination program 303 and a power mode change program 304. In the following description, when there is no need to distinguish between the power mode determination program 303 and the power mode change program 304, the power mode control unit 305 may be used as an example.

[0026] The power consumption control program 301 controls the power consumption of various devices mounted on the controller 104 of the storage system 102. The power consumption control program 301 controls the power consumption of these devices by changing their power modes. The power consumption control program 301 controls the device operating status monitoring program 302 and the power mode control unit 305.

[0027] The device operating status monitoring program 302 is an example of a status monitoring unit and monitors the operating status of multiple devices.

[0028] The power mode control unit 305 switches the power mode of at least one specific component with a low processing load among multiple devices to a power-saving mode, in accordance with the results of monitoring by the device operating status monitoring program 302, and operates that specific device. This makes it possible to suppress power consumption.

[0029] In this embodiment, the multiple components are multiple devices that control data input / output processing with the host. The controller 104 includes at least one controller 104 that is equipped with these multiple devices and controls data input / output processing with the host by the multiple devices, and a power mode control unit 305. The controller 104 includes a device operation status monitoring program 302 as an example of a status monitoring unit, a power mode determination program 303 and a power mode change program 304 included in the power mode control unit 305. It should be noted that controlling input / output processing as used herein is not limited to specific I / O processing, but may also include other functions such as acting as a communication channel or intervening in communication with the host.

[0030] As described above, the power mode control unit 305 includes a power mode determination program 303 and a power mode change program 304. The power mode determination program 303 is an example of a power mode determination unit, and for example, if it is determined that changing the power mode of a specific device among several devices that is operating in normal mode to a power saving mode will not affect data input / output processing with the host machine 103, it decides to set the power mode of that specific device to power saving mode. The power mode change program 304 is an example of a power mode change unit, and switches the power mode of the specific device to the determined power saving mode. The above-mentioned determination that changing to power saving mode will not affect data input / output processing with the host machine 103 also includes, for example, if changing to power saving mode will have an effect on data input / output processing with the host machine 103 that is below a predetermined standard. The setting of the standard may be determined according to the characteristics of each device.

[0031] The storage system 102 can reduce power consumption without degrading its I / O performance by executing the power consumption control program 301. The power consumption control program 301 also calls a device operating status monitoring program 302, which monitors the processing load of the devices and stores historical information, and a power mode determination program 303, which determines the power mode of each device based on the aforementioned historical information. The power mode determination program 303 also calls a power mode change program 304, which performs the necessary processing to change the power mode of a device and changes the determined power mode of the device.

[0032] Figure 4 shows an example of the information stored in the management information area 202. The management information area 202 stores the device management table 401 and the device operation history table 402.

[0033] The device management table 401 manages information about multiple devices that make up the storage system 102, such as the CPU 106, and is used in the process of determining the power mode, as will be described later.

[0034] The device operation history table 402 holds historical information such as processing load from the past to the present for devices constituting the storage system 102, such as the CPU 106, and is used in the process of determining the power mode. The device operation history table 402 manages the operating status of multiple devices monitored by the device operation status monitoring program 302.

[0035] The power mode determination program 303 described above determines, based on the operating status of multiple devices managed in the device operation history table 402, that changing the power mode of a particular device to power saving mode would have less than a predetermined threshold impact on data input / output processing with the host machine 103, and therefore decides to set the power mode of that particular device to power saving mode.

[0036] Figure 5 shows an example of the configuration of the device management table 401. The device management table 401 manages the power consumption and processing capacity for at least the normal power mode and power saving mode for each of the multiple devices. The power mode control unit 305, as described above, determines the power saving mode for the power mode of a particular device based on the power consumption and processing capacity for the normal power mode and power saving mode for each of the multiple devices managed in the device management table 401, and changes the power mode of that particular device to the power saving mode. This will be explained in more detail below.

[0037] The device management table 401 has entries for device identifier (type) 501, power control unit 502, normal mode 503, power OFF 504, power saving mode A 505, and power saving mode B 506.

[0038] Device identifier (type) 501 is an identifier for a device installed in the storage system 102, such as the CPU 106 or the host I / F 108.

[0039] As described above, the device management table 401 manages power control units 502 related to the extent to which multiple devices relate to other devices in terms of power consumption control. In other words, the power control unit 502 is information that manages and defines categories for controlling the power mode of multiple devices, including categories that are performed independently of other devices (first category) and categories that are performed in combination with other devices (second category). This power control unit 502 indicates which unit to use when changing the power mode of each device. In this embodiment, for example, device units, connected device units, and controller units are provided as power control units.

[0040] In this embodiment, such power control units are illustrative examples, and details will be described later, but for example, the device management table 401 may also manage, as power control units, device units including devices that are independent from other devices in terms of power consumption, connected device units including devices whose power modes should be changed to match those of other devices, and controller units including groups of controllers (e.g., accelerators 110) that should exhibit substantially similar performance for each of the multiple controllers 104.

[0041] Normal mode 503, power off 504, power saving mode A 505, and power saving mode B 506 indicate the power modes of the devices installed in the storage system 102, and each has power consumption and processing capacity (relative value when normal mode is set to 100%).

[0042] In this embodiment, for example, there can be four power modes, but two or more are sufficient. Also, depending on the device, there may be differences in the number of corresponding power modes, or some devices may not have multiple power modes. Furthermore, in this embodiment, there are two items: power consumption and processing power, but other information necessary for selecting a power mode may also be included, such as limitations when using the power mode (e.g., limited functionality).

[0043] Figure 6 shows an example of the configuration of the device operation history table 402. The device operation history table 402 has entries for acquisition time 601, device identifier (type) 602, mounted controller # 603, mounted location identifier 604, mounted status 605, power mode 606, and processing load 607. In this embodiment, "#" indicates an identification number.

[0044] The acquisition time 601 indicates the time when the device history was acquired, and may be, for example, the elapsed time since the storage system 102 was started. The device identifier (type) 602 is the identifier of a device installed in the storage system 102, such as the CPU 106 or the host I / F 108, and indicates the correspondence with the device identifier (type) 501 in the device management table 401.

[0045] The mounted controller # is 603, an identifier used to identify the controller 104 on which the device is mounted. The mounting location identifier 604 is an identifier used to identify where the device is mounted if multiple units of the device are mounted. The mounting status 605 indicates whether or not the device is mounted.

[0046] Power mode 606 indicates the power mode of the device and can be one of the following: normal mode 503, power off 504, power saving mode A 505, or power saving mode B 506 in the device management table 401. Processing load 607 indicates the processing load of the device.

[0047] In this embodiment, the device identifier (type) 602, the mounted controller # 603, and the mounting position identifier 604 are used to identify which device it is. However, the system is not limited to these; any identifier that can identify the device is acceptable, such as the device's serial number, or any other unique identifier.

[0048] Figure 7 is a flowchart illustrating an example of the procedure for power consumption control processing to reduce power consumption in the storage system 102. This power consumption control processing mainly consists of the following three steps. This power consumption control processing is executed by the programs shown in Figure 3 under the control of the CPU 106 when the storage system 102 is started up.

[0049] First, an overview of the power consumption suppression method according to this embodiment will be described. The power consumption suppression method is a power consumption suppression method for a storage system having a storage device that saves data or outputs saved data in response to data input / output requests from a host. The method includes a device operation status monitoring program 302, which is an example of a status monitoring unit, which monitors the operating status of each of a plurality of devices that can operate by switching between a normal power mode and at least one power-saving mode that consumes less power than the normal power mode, and a power mode control unit 305, which determines the power mode of at least one specific device to a power-saving mode based on the processing load for each of the plurality of devices as a result of the monitoring by the status monitoring step, and switches to the power-saving mode to operate at least one specific device. The plurality of devices perform control with the storage device in response to the data input / output requests. An example of power consumption control processing will be described in detail below.

[0050] In this embodiment, for example, when the storage system 102 is started up, the CPU 106 executes the power consumption control program 301 stored in the program area 201 of the memory 107. While the power consumption control program 301 is being executed, the device operating status monitoring program 302, the power mode determination program 303, and the power mode change program 304 are executed.

[0051] First, in the first step, the CPU 106 monitors the processing load of the devices installed in the storage system 102 and records it in the device operation history table 402 (step S701). More specifically, the CPU 106 initiates the execution of the power consumption control program 301 in response to the fulfillment of predetermined criteria (triggers) regarding the execution of power consumption control processing. At the same time, the CPU 106 can also acquire a sampling time 601 corresponding to the monitoring of the operating status of the device, which will be described later. As the processing of the power consumption control program 301 progresses, the CPU 106 reads and executes the device operation status monitoring program 302 from the program area 201 of the memory 107, thereby executing device operation status monitoring processing to monitor the processing load of the monitored device. The device operation status monitoring program 302 accesses the device management table 401 to obtain information on the device identifier 501 and the power control unit 502. Based on the device identifier 501 and the power control unit 502, the device operation status monitoring program 302 checks the processing load and the currently applied power mode. The device operation status monitoring program 302 records the power mode information and processing load information obtained as a result of the verification in the device operation history table 402, along with the corresponding device identifier 602, the identification information of the controller to which the device identifier 602 belongs (mounted controller #603), the mounting location identifier 604, the mounting status 605, and the sampling time 601. Further details of this process will be described later.

[0052] In the second step, the CPU 106 (power mode control unit 305) refers to the device management table 401 and the device operation history table 402, and determines the power mode of each device based on the device's power control unit 502 and operation history, and performs power mode determination and modification if necessary. The power mode modification program 304 modifies the power mode of the device if necessary, in accordance with the determination of the power mode determination program 303 (step S702). Specifically, the CPU 106 reads and executes the power mode determination program 303 as part of the processing of the power consumption control program 301. The power mode determination program 303 accesses the device operation history table 402 in the management information area 202 to obtain relevant information and determines the power mode to apply to each device. Next, the CPU 106 reads and executes the power mode modification program 304 as part of the processing of the power consumption control program 301. The power mode change program 304 transmits the power mode determined by the power mode determination program 303 to the target device identified based on the device identifier 501, power control unit 502, mounted controller #603, and mounting location identifier 604, causing the power mode to be changed. For target devices that do not have a function to actively limit power consumption, and whose power consumption is determined by the usage status of the CPU 106 or other devices, the CPU 106 implements usage restrictions according to the power mode. Further details of this process will be described later.

[0053] In the third step, the CPU 106 determines the trigger for the next execution of this power consumption control process and terminates the process (step S703). The trigger for the next execution may be, for example, after a certain period of time has elapsed, or one or more conditions may be set, such as when an I / O request is received from the host machine 103, or when a device is installed or removed.

[0054] Figure 8 is a flowchart showing an example of the procedure for device operating status monitoring processing performed in the power consumption control processing of the storage system 102. The device operating status monitoring program 302, under the control of the CPU 106, refers to the device management table 401 and starts monitoring from the device listed in the first row (step S801). Note that although monitoring starts from the device listed in the first row here, the order is not limited to this.

[0055] The device operation status monitoring program 302 obtains the mounting location of the device (step S802). The mounting location refers to information used to identify multiple identical devices when they are mounted in the storage system 102. For example, this corresponds to the mounting controller #603 and mounting location identifier 604 in the device operation history table 402.

[0056] The device operating status monitoring program 302 targets the first item in the list of possible mounting locations for the device obtained in step S802 and starts monitoring (step S803).

[0057] The device operation status monitoring program 302 obtains the current date and time (step S804). The date and time obtained here corresponds to the data collection time 601 in the device operation history table 402, and may be, for example, the time of day, or it may be the elapsed time since the storage system 102 was started.

[0058] The device operation status monitoring program 302 obtains whether or not the target device is installed at the installation location (step S805). Note that the presence or absence of the device can be confirmed by referring to a table containing device installation information, or by accessing the device at this point.

[0059] Based on the result of step S805, the device operating status monitoring program 302 determines whether or not the device is installed at the mounting location of the target device (step S806). If the determination is that the device is installed (step S806: Yes), step S807 is executed. On the other hand, if the device is not installed (step S806: No), step S809 is executed.

[0060] The device operating status monitoring program 302 obtains the current power mode of the monitored device (step S807). The device's power mode can be determined by referring to a table containing the device's current power mode, or by accessing the device at this point.

[0061] The device operation status monitoring program 302 obtains the current processing load of the monitored device (step S808). The processing load of the device can be obtained by referring to a table that periodically records the processing load, or by accessing the device at this point. Several existing methods exist for calculating the processing load of this device, so one of these can be used.

[0062] The device operation status monitoring program 302 appends the information acquired in steps S804, S805, S807, and S808 to the device operation history table 402 (step S809).

[0063] The device operation status monitoring program 302 refers to the list of possible mounting locations for the device obtained in step S802 and determines whether there is a next possible mounting location after the currently targeted location (step S810). If the determination shows that a next location exists (step S810: Yes), step S811 is executed. On the other hand, if no next location exists (step S810: No), step S812 is executed.

[0064] The device operating status monitoring program 302 refers to the list of possible mounting locations for the device obtained in step S802, targets the next possible mounting location after the currently targeted mounting location, and starts monitoring (step S811). Subsequently, step S804 is executed.

[0065] The device operation status monitoring program 302 refers to the device management table 401 and determines whether there is a device after the currently targeted device (step S812). If the determination is made and a device exists (step S812: Yes), step S813 is executed. If no device exists (step S812: No), the device operation status monitoring program 302 terminates the device operation status monitoring process.

[0066] The device operation status monitoring program 302 refers to the device management table 401, targets the next device after the currently targeted device, and starts monitoring (step S813). Then, step S802 is executed.

[0067] Here, the classification of devices with respect to power modes in this embodiment will be explained. The power mode determination program 303 (power mode control unit 305) described above classifies multiple devices into devices that are grouped together with low mutual independence from the perspective of controlling power consumption with respect to multiple devices, and devices that are not grouped together with high mutual independence from the perspective of controlling power consumption with respect to multiple devices. For each device that can be grouped and each device that cannot be grouped, the power mode may be switched to a power saving mode according to the results of monitoring by the device operating status monitoring program 302. Note that "independence" from the perspective of controlling power consumption may be understood as the degree of functional and performance coupling with other devices based on the processing, performance, or cooperation content regarding processing with other devices that each device is responsible for. Controlling power consumption, that is, limiting it, affects the performance of the target device. However, the scope of that impact varies depending on the function of the device and its relationship with other devices. In this embodiment, with respect to the degree of coupling between multiple devices, power control units are defined according to the range identified by setting a boundary where the degree of coupling is low (high independence) (i.e., independence is low within the range). For example, a first category of devices can be defined, which are highly independent as individual devices and therefore have little need to be grouped, and a second category of devices that, while having low independence from other devices as individual devices, have high independence in relation to other devices outside of that combination (group) when viewed as such. The criteria for determining independence can be set arbitrarily, and it is predetermined which category each device belongs to according to the required performance.

[0068] Furthermore, the power mode determination program 303 (power mode control unit 305) may, when there are multiple devices that can be grouped, classify them into a first group of devices whose power mode change patterns should be the same, and a second group of devices whose power mode change patterns do not need to be the same. The power mode of the first group of devices may be changed so that the target power mode is the same.

[0069] Furthermore, the power mode determination program 303 (power mode control unit 305) classifies devices into those that allow power off as a power-saving mode and those that do not allow power off as a power-saving mode (for example, a connected host I / F) (determined, for example, in step S1008 of Figure 10). For devices that allow power off as a power-saving mode, the power mode is switched to power off according to the results of monitoring by the device operation status monitoring program 302. On the other hand, for devices that do not allow power off as a power-saving mode, the power mode is switched to the aforementioned power-saving mode (excluding power off) according to the results of monitoring by the device operation status monitoring program 302.

[0070] Figure 9 is a flowchart showing an example of the procedure for power mode determination processing performed in power consumption control processing. Power mode determination processing is executed by power mode determination program 303 under the control of CPU 106.

[0071] The power mode determination program 303 refers to the device management table 401 and starts processing from the device listed in the first row (step S901). Note that although it is stated here that processing starts from the device listed in the first row, the order is not limited to this.

[0072] The power mode determination program 303 obtains the target device identifier (type) 501 (step S902). The power mode determination program 303 obtains the power control unit 502 of the target device (step S903).

[0073] The power mode determination program 303 determines, based on the information obtained in step S903, whether the power control unit 502 is the device unit (step S904). If the determination is that it is the device unit (step S904: Yes), step S905 is executed. On the other hand, if it is not the device unit (step S904: No), step S906 is executed. The power mode determination program 303 calls the device unit power mode determination process (step S905). After that, step S910 is executed.

[0074] The power mode determination program 303 calls the device-specific power mode determination process (step S905). Then, step S910 is executed.

[0075] The power mode determination program 303 determines, based on the information obtained in step S903, whether the power control unit 502 is a connected device unit or not (step S906). If the determination is that it is a connected device unit (step S906: Yes), step S907 is executed. On the other hand, if it is not a connected device unit (step S906: No), step S908 is executed. The power mode determination program 303 calls the connected device unit power mode determination process (step S907). After that, step S910 is executed.

[0076] The power mode determination program 303 determines whether the power control unit 502 is a controller unit or not based on the information obtained in step S903 (step S908). If the determination is that it is a controller unit (step S908: Yes), step S909 is executed. On the other hand, if it is not a controller unit (step S908: No), step S911 is executed. The power mode determination program 303 calls the controller unit power mode determination process described later (step S909). After that, step S910 is executed.

[0077] The power mode determination program 303 calls a power mode change process to change the power mode of the target device based on the power mode determined in step S905, step S907, or step S909 (step S910). Then, step S911 is executed.

[0078] The power mode determination program 303 refers to the device management table 401 and determines whether there is a successor to the currently targeted device (step S911). If the determination shows that a successor exists (step S911: Yes), step S912 is executed. On the other hand, if no successor exists (step S911: No), the power mode determination program 303 terminates the power mode determination process.

[0079] The power mode determination program 303 refers to the device management table 401, targets the next device after the currently targeted device, and starts processing (step S912). Then, step S902 is executed.

[0080] Figure 10 is a flowchart showing an example of the procedure for the device-specific power mode determination process shown in Figure 9. This device-specific power mode determination process is called from the device power mode determination process performed in the power consumption control process of the storage system 102. The device-specific power mode determination process is executed by the power mode determination program 303 under the control of the CPU 106.

[0081] The power mode determination program 303 obtains the mounting location of the device (step S1001). The mounting location refers to information used to identify multiple identical devices when they are mounted in the storage system 102. For example, this corresponds to the mounting controller #603 and mounting location identifier 604 in the device operation history table 402.

[0082] The power mode determination program 303 targets the first item in the list of possible mounting locations for the device obtained in step S1001 and starts processing (step S1002).

[0083] The power mode determination program 303 obtains whether or not the device is installed at the mounting location of the target device (step S1003). Note that the presence or absence of the device can be confirmed by referring to a table containing device mounting information, or by accessing the device at this point.

[0084] Based on the result of step S1003, the power mode determination program 303 determines whether or not the device is mounted at the mounting location of the target device (step S1004). If the determination result is that the device is mounted (step S1004: Yes), step S1005 is executed. On the other hand, if the device is not mounted (step S1004: No), step S1013 is executed.

[0085] The power mode determination program 303 refers to the device operation history table 402 and obtains information to predict the processing load for the device (step S1005).

[0086] The power mode determination program 303 uses the information acquired in step S1005 to predict the future processing load of the device (step S1006). Hereinafter, this prediction result will also be referred to as the "predicted value of future processing load". For example, by acquiring the sampling time 601 and the processing load 607, the fluctuations in the processing load of the device can be confirmed in time series, and the future processing load can be predicted. Note that the future processing load may also be predicted using information other than that acquired in step S1005. For example, the change in the number of logical volumes defined in the storage system 102 or the change in the number of connected hosts may be used. Furthermore, the method for predicting the future processing load may be to predict it from past operating history or from the most recent operating state.

[0087] Based on the result of step S1006, the power mode determination program 303 determines whether the predicted future processing load of the device is zero or not (step S1007). If the result of the determination is that the predicted future processing load is zero (step S1007: Yes), the program proceeds to step S1008. On the other hand, if the predicted future processing load is not zero (step S1007: No), step S1011 is executed.

[0088] The power mode determination program 303 determines whether the power mode of the device can be turned off (step S1008). Even if the predicted future processing load is zero, there are cases where the device cannot be turned off, and therefore, individual determination is required when turning off the power mode. For example, in the case of the host I / F 108, if it is connected to the host machine 103, even if there are no I / O requests from the host machine 103, turning off the power mode will disconnect the connection to the host I / F 108, affecting the operation of the host machine 103. In addition, in the case of a device that takes time to transition from power off to another power mode, the long transition time may affect the I / O performance of the storage system, and this process takes these factors into account when making a decision.

[0089] The power mode determination program 303 determines whether the power mode of the device can be turned off based on the determination result of step S1008 (step S1009). If the determination result is that the power can be turned off (step S1009: Yes), step S1010 is executed. On the other hand, if the power cannot be turned off (step S1009: No), step S1012 is executed.

[0090] The power mode determination program 303 determines the power mode of the device to "Power OFF" (step S1010). Then, step S1013 is executed.

[0091] The power mode determination program 303 determines the power mode of the device based on the predicted future processing load obtained in step S1006 (step S1011). This process assumes that the power mode will be selected to provide processing power exceeding the predicted future processing load of the device, without affecting the I / O performance of the storage system 102, and with the lowest power consumption. Alternatively, the power mode may be determined in a way that prioritizes power consumption reduction by providing an operating mode for the storage system that allows for a decrease in I / O performance, which the user of the storage system 102 can select. After that, step S1013 is executed.

[0092] The power mode determination program 303 determines the power mode of the device to the one with the lowest power consumption other than power off (step S1012). As mentioned above, the predicted future processing load of the device is zero, but power off cannot be selected. Subsequently, step S1013 is executed.

[0093] The power mode determination program 303 refers to the list of possible mounting locations for the target device obtained in step S1001 and determines whether there is a next possible mounting location after the currently targeted location (step S1013). If the determination shows that a next location exists (step S1013: Yes), step S1014 is executed. On the other hand, if no next location exists (step S1013: No), step S1015 is executed.

[0094] The power mode determination program 303 refers to the list of possible mounting locations for the device obtained in step S1001, targets the next possible mounting location after the currently targeted location, and starts processing (step S1014). Subsequently, step S1003 is executed.

[0095] The power mode determination program 303 returns the power mode determination results calculated in steps S1010, S1011, and S1012 to the caller of the device-specific power mode determination process, and terminates the device-specific power mode determination process (step S1015).

[0096] Figure 11 is a flowchart showing an example of the procedure for determining the power mode on a connected device, as shown in Figure 9. This power mode determination process on a connected device is called from the device power mode determination process performed in the power consumption control process of the storage system 102.

[0097] The difference from the device-specific power mode determination process shown in Figure 10 is that instead of determining the power mode for each individual device, it considers specific combinations of devices that have dependencies as connected devices and determines the power mode combination for these specific combinations of devices. For example, memory 107 is connected to CPU 106, but CPU 106 may use memory 107, for example, through interleaving control. In this case, it is necessary to match the processing performance of multiple memory 107s connected to the same CPU 106, that is, to select the same power mode.

[0098] The power mode determination program 303 obtains a list of devices to which the target device is connected (step S1101). For the connected devices, a table containing the device's connection information can be prepared and referred to, or the device can be accessed at this point to confirm its location.

[0099] The power mode determination program 303 obtains a list of possible mounting locations for the target device (step S1102). The possible mounting locations refer to information used to identify multiple identical devices when they are mounted in the storage system 102. For example, this includes the mounting controller #603 and mounting location identifier 604 in the device operation history table 402.

[0100] Based on the results of steps S1101 and S1102, the power mode determination program 303 classifies the possible mounting locations for each connected device (step S1103).

[0101] The power mode determination program 303 targets the first item in the list of possible mounting locations for each connected device, which is the result of step S1103, and starts processing (step S1104).

[0102] The power mode determination program 303 obtains whether or not a device is installed at the mounting location for each target connected device (step S1105). Note that the presence or absence of a device can be determined by referring to a table containing device mounting information, or by accessing the device at this point.

[0103] Based on the result of step S1105, the power mode determination program 303 determines whether or not a device is mounted at a mountable location for the target connected device (step S1106). If even one device is mounted, it is determined that the device is mounted. If the determination results in a device being mounted (step S1106: Yes), step S1107 is executed. On the other hand, if no devices are mounted (step S1106: No), step S1110 is executed.

[0104] The power mode determination program 303 refers to the device operation history table 402 and obtains information to predict the processing load for the device (step S1107).

[0105] The power mode determination program 303 uses the information acquired in step S1107 to predict the future processing load of the device on a per-connected device basis (step S1108). For example, by acquiring the sampling time 601 and processing load 607, the fluctuations in the processing load of the device can be confirmed in time series, and this can be used to predict the future processing load. Note that the future processing load may also be predicted using information other than that acquired in step S1107. For example, the change in the number of logical volumes defined in the storage system 102 or the change in the number of connected hosts may be used. Note that the prediction method may be the same as the procedure shown in Figure 10.

[0106] The power mode determination program 303 calls a process to determine the power mode combination of the device (the power mode combination determination process shown in Figure 13, described later) based on the predicted future processing load obtained in step S1108 (step S1109).

[0107] The power mode determination program 303 refers to the list of connected device units, which is the result of step S1103, and determines whether there is a successor to the currently targeted connected device unit (step S1110). If the determination shows that a successor exists (step S1110: Yes), step S1111 is executed. On the other hand, if a successor does not exist (step S1110: No), step S1112 is executed.

[0108] The power mode determination program 303 refers to the list of connected device units, which is the result of step S1103, targets the next connected device unit after the currently targeted one, and starts processing (step S1111). Then, step S1105 is executed.

[0109] The power mode determination program 303 returns the power mode determination result calculated in step S1109 to the caller of the connected device-specific power mode determination process, and terminates the device-specific power mode determination process (step S1112).

[0110] Figure 12 is a flowchart showing an example of the procedure for determining the controller unit power mode shown in Figure 9. This controller unit power mode determination process is called from the device power mode determination process performed in the power consumption control process.

[0111] The only difference between the controller unit power mode determination process and the connected device unit power mode determination process shown in Figure 11 is whether the dependent is a connected device or a controller; therefore, a detailed explanation is omitted. An example to which this controller unit power mode determination process can be applied is, for example, the accelerator 110.

[0112] Although there are four accelerators 110 mounted on the controller 104, the CPU 106 can arbitrarily distribute and aggregate processing requests. In other words, when the processing load on an accelerator 110 is low, it is possible to combine power modes such as stopping processing requests to a specific accelerator 110 and turning off its power.

[0113] Figure 13 is a flowchart showing an example of the procedure for determining the power mode combination. The power mode combination determination process is called from the connected device unit power mode determination process sequence and the controller unit power mode determination process sequence. Because the power mode combination determination process involves the combination of power modes, it is called from step S1109 shown in Figure 11 and step S1209 shown in Figure 12. The power mode combination determination process is executed by the power mode determination program 303 under the control of the CPU 106.

[0114] In this embodiment, the power mode determination program 303 determines that, when the predicted future processing load for multiple specific devices is zero and it is permissible to turn off the power, and when it is necessary to unify the power modes of multiple specific devices, it will unify the power modes of multiple specific devices to power off. This will be explained in detail below.

[0115] The power mode determination program 303 receives a list of target devices and a predicted value of the future processing load from the calling process (step S1301).

[0116] The power mode determination program 303 determines whether the future processing load value of the target device is zero or not based on the information received in step S1301 (step S1302). If the result of the determination is that the predicted value of the future processing load is zero (step S1302: Yes), step S1303 is executed. On the other hand, if the predicted value of the future processing load is not zero (step S1302: No), step S1306 is executed.

[0117] The power mode determination program 303 determines whether all target devices can be powered off (step S1303). Even if the predicted future processing load is zero, there are cases where it is not possible to power off all target devices, and a determination is necessary. For example, in the case of a device that takes time to transition from power off to another power mode, if all devices are powered off, the long transition time may degrade the I / O performance of the storage system or cause I / O processing to time out. This process takes these factors into consideration when making a determination.

[0118] Based on the result of step S1303, the power mode determination program 303 determines whether or not all of the target devices can be powered off (step S1304). If the determination shows that all of the target devices can be powered off (step S1304: Yes), step S1305 is executed. On the other hand, if it is not possible to power off all of the target devices (step S1304: No), step S1306 is executed.

[0119] The power mode determination program 303 determines the power mode of all target devices to power OFF (step S1306). Then, step S1315 is executed.

[0120] The power mode determination program 303 determines whether or not it is possible to power off some of the target devices (step S1306). There are cases where it is not possible to power off some of the target devices, and a determination is necessary. For example, there may be cases where there is some kind of processing coordination between the target devices and processing cannot continue unless all devices are running, and this process takes these into consideration when making a determination.

[0121] Based on the result of step S1306, the power mode determination program 303 determines whether or not it is possible to power off a portion of the target device (step S1307). If the determination shows that it is possible to power off a portion of the target device (step S1307: Yes), step S1308 is executed. On the other hand, if it is not possible to power off a portion of the target device (step S1307: No), step S1309 is executed.

[0122] The power mode determination program 303 allows some of the target devices to include power OFF as a power mode and continues processing (step S1308). Then, step S1310 is executed.

[0123] The power mode determination program 303 continues processing to ensure that the power mode of the target device does not include power off (step S1309). Then, step S1310 is executed.

[0124] The power mode determination program 303 determines whether or not it is necessary to unify the power modes of all target devices (step S1310). For this determination, a table containing information on whether or not it is necessary to unify the power modes may be prepared and referred to, or the determination may be made by accessing the devices at this point. For example, memory 107 is connected to CPU 106 as the target device, but CPU 106 may interleave and use memory 107. In this case, it is necessary to unify the power modes of multiple memory 107 connected to the same CPU 106, that is, to equalize their processing performance. Therefore, the determination is made considering the cooperation between these devices.

[0125] Based on the result of step S1310, the power mode determination program 303 determines whether or not it is necessary to unify the power modes of all target devices (step S1311). If the determination results in a need to unify the power modes of all target devices (step S1311: Yes), the program proceeds to process 1312. On the other hand, if it is not necessary to unify the power modes of all target devices (step S1311: No), step S1313 is executed.

[0126] The power mode determination program 303 continues processing to unify the power modes of the target devices (step S1312). Then, step S1314 is executed.

[0127] The power mode determination program 303 determines that it is not necessary to unify the power modes of the target devices and continues processing (step S1313). Subsequently, step S1314 is executed.

[0128] Based on the results of steps S1301, S1308, S1309, S1312, and S1313, the power mode determination program 303 determines the combination of power modes that can achieve the lowest power consumption while satisfying these requirements. For example, if the processing load can be concentrated on a specific device, it may be possible to create a device with zero processing load. By combining this with the OFF power mode, it may be possible to provide processing power that exceeds the predicted future processing load while reducing power consumption compared to equalizing the processing load across devices.

[0129] For example, if the predicted future processing load for the four accelerators 110 is 50%, and the processing is evenly distributed among the four accelerators 110, they can operate in power-saving mode B506, resulting in a total power consumption of 20W × 4 = 80W (average processing capacity 50%). On the other hand, if the processing load is concentrated on two accelerators 110 and processing is not requested from those two accelerators 110, the accelerator with the concentrated processing load can operate in normal mode 503, while the remaining two accelerators 110 can operate with the power OFF 504, resulting in a total power consumption of 30W × 2 + 0W × 2 = 60W (average processing capacity 50%). If the requirements are met, the latter power mode combination is selected.

[0130] Alternatively, a storage system operating mode that tolerates a decrease in I / O performance may be provided, and the user of the storage system 102 may select this mode to determine the power mode in a way that prioritizes reducing power consumption. After that, step S1315 is executed.

[0131] The power mode determination program 303 returns the power mode determination result calculated in step S1305 or step S1314 to the caller and terminates the power mode combination determination process (step S1315).

[0132] Figure 14 is a flowchart illustrating an example of the procedure for power mode change processing. This power mode change processing is called from the device power mode determination processing performed in the power consumption control processing described above. This power mode change processing is executed by the power mode change program 304 under the control of the CPU 106.

[0133] The power mode change program 304 receives a list of target devices and the determined power mode from the calling process (step S1401).

[0134] The power mode change program 304 obtains information about the target device from the device operation history table 402 (step S1402).

[0135] The power mode change program 304 starts processing from the beginning of the list of target devices received in step S1401 (step S1403).

[0136] The power mode change program 304 compares the current power mode with the power mode to be changed based on the information about the target device obtained in steps S1401 and S1402, and determines whether or not it is necessary to change the power mode of the target device (step S1404).

[0137] The power mode change program 304 determines, based on the comparison, that a power mode change is necessary if the power modes are different, and that a power mode change is unnecessary if they are the same. If the determination indicates that a power mode change is necessary (step S1404: Yes), step S1405 is executed. On the other hand, if a power mode change is unnecessary (step S1404: No), step S1415 is executed.

[0138] The power mode change program 304 determines whether the target power mode is power OFF based on the information obtained in step S1401 (step S1405). If the power mode is power OFF as a result of the determination (step S1405: Yes), step S1406 is executed. On the other hand, if the power mode is not power OFF (step S1405: No), step S1409 is executed.

[0139] The power mode change program 304 stops processing requests to the device (step S1406). The power mode change program 304 waits until all processing requests to the device are completed (step S1407). Steps S1406 and S1407 are performed to ensure that processing requests to the device are completed normally so that the I / O processing of the storage system 102 does not stop abnormally.

[0140] The power mode change program 304 changes the power mode of the device to power OFF (step S1408). Then, step S1415 is executed.

[0141] The power mode change program 304 determines whether specific processing is required when changing the power mode of the device (step S1409). In this determination, information on whether specific processing is required when changing the power mode for each device may be stored in advance as a table and referred to.

[0142] Based on the result of step S1409, the power mode change program 304 determines whether specific pre-processing is required when changing the power mode of the device (step S1410). If the determination indicates that specific pre-processing is required (step S1410: Yes), step S1411 is executed. On the other hand, if specific pre-processing is not required (step S1410: No), step S1412 is executed.

[0143] The power mode change program 304 performs specific preprocessing associated with the power mode change (step S1411). For example, when changing the power mode from power OFF, it performs the startup process for the device.

[0144] The power mode change program 304 changes the power mode of the device to the determined one (step S1412).

[0145] Based on the result of step S1409, the power mode change program 304 determines whether specific post-processing is required after changing the power mode of the device (step S1413). If the determination indicates that specific post-processing is required (step S1413: Yes), step S1414 is executed. On the other hand, if specific pre-processing is not required (step S1413: No), step S1415 is executed.

[0146] The power mode change program 304 performs specific post-processing associated with the power mode change (step S1414). For example, if the power mode has been changed from power OFF, it authorizes processing requests to the device.

[0147] The power mode change program 304 refers to the list of target devices received in step S1401 and determines whether there is a device after the current device (step S1415). If the determination shows that there is a next device (step S1415: Yes), step S1416 is executed. On the other hand, if there is no next device, the power mode change process is terminated. .

[0148] The power mode change program 304 refers to the list of target devices received in step S1401 and starts processing from the device following the current device (step S1416). Then, step S1404 is executed.

[0149] As described above, in the storage system 102, the power mode of each device is appropriately changed so that the power consumption of each device mounted on at least one controller 104 is minimized, without affecting the I / O performance with the host machine 103. Furthermore, in the storage system 102, if the I / O load from the host machine 103 changes, the power mode of each device, which has been changed as described above, is further changed, within a range that does not affect the I / O performance with the host machine 103.

[0150] As described above, the storage system 100 according to this embodiment is a storage system having a storage device that stores data or outputs the stored data in response to data input / output requests from a host, and comprises a plurality of components (a plurality of devices) that can be switched between and operate in a normal power mode and at least one power-saving mode (including a power-off mode) that consumes less power than the normal power mode, a device operation status monitoring program 302 as an example of a status monitoring unit that monitors the operating status of each of the plurality of components, and a power mode control unit 305 (power mode determination program 303, power mode change program 304) that determines the power mode of at least one specific device to a power-saving mode based on the processing load for each of the plurality of devices as a result of monitoring by the device operation status monitoring program 302, and operates at least one specific device in the power-saving mode.

[0151] The power consumption reduction method according to this embodiment is a power consumption reduction method for a storage system having a storage device that stores data or outputs stored data in response to data input / output requests from a host, and comprises a status monitoring step in which a device operation status monitoring program 302, as an example of a status monitoring unit, monitors the operating status of each of a plurality of devices, which are an example of a plurality of components that can each operate by switching between a normal power mode and at least one power-saving mode that consumes less power than the normal power mode, and a power mode control step in which a power mode control unit 305 determines the power mode of at least one specific device to the power-saving mode based on the processing load for each of the plurality of devices as a result of the monitoring by the status monitoring step, and operates at least one specific device in the power-saving mode, and the plurality of devices perform control in response to the data input / output requests with the storage device.

[0152] Generally, storage systems consist of various devices such as multiple CPUs and I / O modules, and each of these devices has its own power management function. Power management functions include power modes that reduce power consumption at the expense of processing performance, and the ability to individually turn off the power to each device. Furthermore, storage systems do not always operate at maximum load; they are operated with a margin to ensure that services can continue without problems even if some of the redundant parts fail and the I / O performance that can be provided decreases. Therefore, as described above, the storage system 102 monitors the processing load of each device and switches devices with low processing loads to an operating mode with low power consumption within a range that does not affect I / O performance, or turns off the power to some of them. With this configuration, the power consumption of the storage system 102 can be reduced by suppressing the power consumption of devices that do not affect I / O performance without reducing the input / output performance with the host machine 103.

[0153] In this embodiment, the multiple components are multiple devices that control data input / output processing with the host, and the controller 104 comprises at least one controller 104 that is equipped with these multiple devices and controls data input / output processing with the host by the multiple devices, and the controller 104 comprises a device operation status monitoring program 302 as an example of a status monitoring unit, a power mode determination program 303 and a power mode change program 304 included in the power mode control unit 205. In this way, the power consumption of the storage system 102 can be reduced by suppressing the power consumption of devices that do not affect I / O performance without degrading the I / O performance with the host machine 103.

[0154] In this embodiment, the power mode control unit 305 includes a power mode determination program 303 that determines whether to set the power mode of a specific device to the power-saving mode based on the magnitude of the impact on the I / O performance with the host machine 103 when the power mode of a specific device operating in power-saving mode among a plurality of devices is changed to the power-saving mode, and a power mode change program 304 that switches the power mode of the specific device to the determined power-saving mode. In this way, the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0155] The storage system 102 according to this embodiment includes a device management table 401 that manages information about multiple devices, and a device operation history table 402 that manages the operating status of multiple devices monitored by a device operation status monitoring program 302. The power mode determination program 303 determines, based on the operating status of multiple devices managed in the device operation history table 402, that changing the power mode of a particular device to power-saving mode will have no impact on data input / output processing (e.g., I / O performance with the host machine 103) below a predetermined standard. In this way, the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0156] In this embodiment, the device management table 401 manages the power consumption and processing capacity for each of the multiple devices in both normal power mode and power saving mode. The power mode control unit 305 determines the power saving mode for a specific device based on the power consumption and processing capacity for each of the multiple devices in both normal power mode and power saving mode managed in the device management table, and changes the power mode of that specific device to power saving mode. In this way, the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0157] In this embodiment, the device management table 401 manages a first category in which power mode control is performed independently of other devices, a second category in which power mode control is performed in combination with other devices, and a defined power control unit 502 (see Figure 5). In this way, the power mode determination program 303 takes into account the power control unit 502 of the device management table 401 and finely changes the power mode for at least one device, thereby further reducing the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0158] In this embodiment, the device management table 401 manages, as power control units 502, device units including devices that are considered independent from other devices in terms of power consumption control, connected device units (e.g., memory group 107) including devices whose power mode should be changed to match that of other devices, and controller units including groups of controllers (e.g., accelerator group 110) that should exhibit approximately the same performance for each of the multiple controllers 104. In this way, the power mode of devices is changed in a more preferable unit, so that the power consumption of the storage system 102 can be further reduced without degrading the I / O performance with the host machine 103.

[0159] In this embodiment, the power mode control unit 305 classifies multiple devices into two categories: devices that are grouped together due to their low independence from the perspective of controlling power consumption with respect to other devices, and devices that are not grouped together due to their high independence from the perspective of controlling power consumption with respect to other devices. For each grouped and ungrouped device, the power mode is switched to a power-saving mode according to the results of monitoring by the device operating status monitoring program 302. In this way, the power mode of each device is changed considering its independence from other devices, so that the power consumption of the storage system 102 can be further reduced without degrading the I / O performance with the host machine 103.

[0160] In this embodiment, when there are multiple devices that can be grouped, the power mode control unit 305 classifies them into a first group of devices (e.g., memory 107) whose power mode change patterns should be standardized across the grouped devices, and a second group of devices whose power mode change patterns do not need to be standardized across the grouped devices. For the first group of devices, the power mode is changed to standardize the target power mode. In this way, the first group of devices whose power mode change patterns should be standardized across the grouped devices are controlled to have standardized power modes after the change, thus reducing the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0161] In this embodiment, the power mode control unit 305 classifies devices into those that allow power off as a power-saving mode and those that do not allow power off as a power-saving mode (for example, a host I / F connected to the host machine 103) (determined, for example, in S1008 of Figure 10). For devices that allow power off as a power-saving mode, the power mode is switched to power off according to the results of monitoring by the device operation status monitoring program 302. For devices that do not allow power off as a power-saving mode, the power mode is switched to a power-saving mode (not including power off) according to the results of monitoring by the device operation status monitoring program 302. In this way, if devices are classified appropriately, devices that are allowed to be completely powered off will not consume any power at all, thus reducing the power consumption of the storage system 102 without degrading the I / O performance with the host machine 103.

[0162] In this embodiment, the power mode determination program 303 considers a specific combination of devices that have dependencies as connected devices and determines the power mode of that specific combination of devices. In this way, a combination of power modes for multiple dependent devices is determined, so that the dependencies of that specific combination of devices are not disrupted, and the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0163] In this embodiment, the power mode determination program 303 determines that, for multiple specific devices, if the predicted future processing load is zero and it is permissible to turn off the power, and if it is necessary to unify the power modes of multiple specific devices, it will unify the power modes of multiple specific devices to power off. In this way, the power consumption of the storage system 102 can be reduced without degrading the I / O performance with the host machine 103.

[0164] (2) Second embodiment In the second embodiment, the same configuration and operation as in the first embodiment will not be described, and the following description will mainly focus on the differences from the first embodiment.

[0165] Figure 15 is a system configuration diagram showing an example of the configuration of the information system 1501 according to the second embodiment. In the first embodiment, the power mode according to the processing load was controlled mainly at the device level, such as various electronic devices and components that constitute the storage system, but in the second embodiment, the power mode according to the processing load is controlled at the unit level, such as each controller 1506, which is implemented in the storage system 1502.

[0166] The information system 1501 comprises one or more storage systems 1502, one or more host machines 1503, and one or more storage area networks (SANs) 1504. One or more management terminals 1505 are configured, for example, as part of the storage system 1502.

[0167] The storage system 1502 comprises one or more controllers 1506, one or more inter-storage controller networks 1507, one or more PDEV boxes 1508, and one or more networks for management terminals.

[0168] The PDEV BOX 1508 includes one or more PDEV 1514s. Although not shown in the diagram, the PDEV BOX 1508 may have the same configuration as the PDEV BOX 105. In Figure 15, the controller 1506 and the PDEV BOX 1508 are directly connected, but they may also be connected via a network, which is not shown.

[0169] Controller 1506 includes a host interface 1510, an inter-controller interface 1511, a PDEV interface 1512, and a management terminal interface 1513. Although not shown in the figures, controller 1506 may have the same configuration as controller 104 in Figure 1 of the first embodiment, and may also include a CPU (Central Processing Unit), memory, accelerator, and network switch.

[0170] The host interface 1510 is connected to the host machine 1503 via the SAN 1504 and performs I / O requests and transmission / reception of I / O data. The inter-controller interface 1511 is connected to the inter-controller interface 1511 of other controllers 1506 via the inter-storage controller network 1507 and performs processing requests / responses and data exchange between controllers 1506.

[0171] The PDEV I / F 1512 communicates with the PDEV 1514 of the PDEV BOX 1508 to send and receive data. The management terminal I / F 1513 is connected to the management terminal 1505 via the management terminal network 1509 and receives processing requests from the management terminal 1505 and responds with processing results.

[0172] The management terminal 1505 includes a CPU 1515, memory 1516, auxiliary storage device 1517, input device 1518, output device 1519, and network I / F 1520.

[0173] The CPU 1515 controls the entire management terminal 1505 and operates based on the program stored in memory 1516. The auxiliary storage device 1517 is controlled by the CPU 1515 and becomes non-volatile by writing to and reading programs and management information stored in memory 1516.

[0174] The input device 1518 is controlled by the CPU 1515 and is used by the storage administrator when operating the management terminal 1505. The output device 1519 is controlled by the CPU 1515 and is used by the storage administrator when accessing information held by the management terminal 1505. The network interface 1520 is controlled by the CPU 1515 and requests processing from the controller 1506 of the storage system 1502 and receives the processing results.

[0175] In this embodiment, the management terminal 1505 is configured independently of the storage system 1502, but it may also be built into the storage system 1502. Furthermore, components connected via a network, such as the SAN 1504, the storage controller network 1507, and the management terminal network 1509, may be directly connected, while components not connected via a network may be connected via a network.

[0176] Figure 16 shows an example configuration of the memory 1516 of the management terminal 1505 shown in Figure 15. Memory 1516 is allocated for a program area 1601 and a management information area 1602.

[0177] The program area 1601 is the area where each program used by the CPU 1515 to perform processing is stored. The management information area 1602 is an area accessed by the CPU 1515 and stores various management tables. Details of the program area 1601 and the management information area 1602 will be described later.

[0178] Figure 17 shows an example of a program stored in the program area 1601 shown in Figure 16. Figure 17 corresponds to Figure 3 in the first embodiment, except that the control target for the power mode is different. The program area 1601 stores, for example, a controller management program 1701, a controller power consumption control program 1702, a controller operating status monitoring program 1703, and a controller power mode determination and change program 1704.

[0179] The management terminal 1505 executes the controller management program 1701 to perform input / output control and other actions so that the storage administrator can manage the controller 1506.

[0180] Furthermore, the management terminal 1505 can reduce power consumption without degrading the I / O performance of the storage system 1502 by executing the controller power consumption control program 1702. The controller power consumption control program 1702 has the same functionality as the power consumption control program 301 in the first embodiment, except that the power mode control target is the controller 1506 instead of a device.

[0181] Furthermore, the controller power consumption control program 1702, during its processing, calls the controller operating status monitoring program 1703, which monitors the processing load of the controller 1506 and stores historical information, and the power mode determination and change program 1704, which controls the power mode of each controller 1506 based on the aforementioned historical information.

[0182] Here, the storage system according to this embodiment is a storage system having a storage device that stores data or outputs the stored data in response to data input / output requests from a host, and comprises a plurality of components (a plurality of controllers 1506) as an example of a plurality of components that can switch between a normal power mode and at least one power-saving mode that consumes less power than the normal power mode and operate accordingly. The storage system according to this embodiment comprises a controller operating state monitoring program 1703 as an example of a state monitoring unit that monitors the operating state of each of the plurality of components, and a controller power mode determination and change program 1704 as an example of a power mode control unit that determines the power mode of a specific component to a power-saving mode based on the processing load for each of the plurality of components as a result of monitoring by the controller operating state monitoring program 1703, and operates the specific component in the power-saving mode.

[0183] In this embodiment, the above-mentioned plurality of components are a plurality of controllers 1506 that control data input / output processing with the host, and the storage system according to this embodiment includes a management terminal 1505 that controls the plurality of controllers, and the management terminal 1505 includes a controller operating status monitoring program 1703 as an example of a status monitoring unit, and a controller power mode determination and change program 1704 as an example of a power mode control unit.

[0184] The controller operating status monitoring program 1703 has the same functionality as the device operating status monitoring program 302 in the first embodiment, except that the control target for power mode is the controller 1506 instead of the device.

[0185] Except that the power mode control target is the controller 1506 instead of a device, it has the same functions as the power mode control unit 305 (power mode determination program 303 and power mode change program 304) in the first embodiment.

[0186] In this embodiment, the controller power mode determination and modification program 1704, based on the redundancy setting (e.g., controller failure tolerance (N-redundancy)), selects a specific power mode in response to the detection of a failure in any of the multiple controllers, which allows the other controllers to immediately transition to a state where input / output processing can be performed. In this way, even if a failure occurs in any of the controllers, input / output processing can be performed immediately.

[0187] Furthermore, in this embodiment, the controller power mode determination and modification program 1704 enables other controllers to transition to a state where they can perform input / output processing immediately afterward, while operating some of the cores of a CPU (Central Processing Unit) equipped with multiple cores and putting the other cores into standby mode. In this way, since the CPU is operated with a minimum number of cores, power consumption can be further reduced.

[0188] Figure 18 shows an example of the information stored in the management information area 1602 shown in Figure 16. The management information area 1602 stores the controller management table 1801, the controller operation history table 1802, and the controller power setting information table 1803.

[0189] The controller management table 1801 contains information about the controller 1506 that constitutes the storage system 1502 and is used in the process of determining the power mode. Details of the controller management table 1801 will be described later.

[0190] The controller operation history table 1802, located in the controller 1506 that constitutes the storage system 1502, contains historical information such as processing load from the past to the present, and is used in the process of determining the power mode. Details of the controller operation history table 1802 will be described later.

[0191] The controller power setting information table 1803 contains information set by the storage system administrator to control the power consumption of the storage system 1502. Details of the controller power setting information table 1803 will be described later.

[0192] Figure 19 shows an example configuration of the controller management table 1801 shown in Figure 18. The controller management table 1801 has entries for controller identifier 1901, normal mode 1902 (first power mode), power OFF 1903, standby mode 1904 (third power mode), power saving mode A 1905 (one of the second power modes), and power saving mode B 1906 (one of the second power modes).

[0193] Controller identifier 1901 is the identifier for controller 1506 installed in storage system 1502. For example, each controller 1506 in Figure 15 is assigned identifiers ABC_1, ABC_2, ABC_3, and ABC_4 from top to bottom.

[0194] The normal mode 1902, power off 1903, standby mode 1904, power saving mode A 1905, and power saving mode B 1906, corresponding to each controller identifier 1901, indicate the power modes of the controller 1506 installed in the storage system 1502, and each has power consumption and processing capacity (relative value with normal mode set to 100%).

[0195] In this embodiment, there are five power modes, but any two or more are acceptable. Furthermore, some controllers 1506 may have different numbers of corresponding power modes, or some may not have multiple power modes. To further mention the case of having no power modes, in a storage system 1502 having multiple controllers 1506, some controllers have changeable power modes, while others are configured so that the power modes cannot be changed, or do not have a power mode change function. In addition, in this embodiment, we mainly refer to the two items of power consumption and processing capacity, but other items such as limitations (limited functionality) when using the power mode may also be mentioned as information necessary for selecting a power mode.

[0196] Here, we will explain the difference between Power OFF 1903 and Standby Mode 1904. Both modes share the common characteristic of having 0% processing power and being unable to perform I / O processing in the current state. Power OFF 1903 is a state in which the controller 1506 is stopped, and although power consumption is zero, it is a mode that takes time to make it possible to perform I / O processing (start up). On the other hand, Standby Mode 1904 consumes some power, but it is a mode in which the time it takes to make it possible to perform I / O processing is extremely short. This Standby Mode 1904 focuses on the multi-core configuration of the CPU that is commonly used in the controller 1506 and takes advantage of its benefits. For example, in Standby Mode 1904, only one core of the CPU installed in the controller 1506 is started, and the remaining cores are stopped, so that when it becomes necessary to transition to a state in which I / O processing can be performed, the stopped core of the CPU and the devices necessary for I / O can be started immediately. Generally, in storage systems used for business purposes, it is necessary to be able to continue I / O processing even if at least one storage controller fails and stops. This is because, even if the processing load of the storage system 1502 is low and processing capacity is not a problem even if some storage controllers are stopped, there are cases where it is necessary to have a state where I / O processing can be performed immediately in anticipation of a storage controller failure. In such cases, the use of standby mode 1904 is very useful in achieving both power saving and continuity (availability) of I / O processing.

[0197] Figure 20 shows an example configuration of the controller operation history table 1802 shown in Figure 18. The controller operation history table 1802 has entries for acquisition time 2001, controller identifier 2002, status 2003, power mode 2004, and processing load 2005.

[0198] The sampling time 2001 indicates the time when the storage controller history was collected. The sampling time 2001 could also be, for example, the elapsed time since the storage system started up. The controller identifier 2002 is the identifier of controller 1506 and shows the correspondence with the controller identifier 1901 in the controller management table 1801.

[0199] Status 2003 indicates the operating status of controller 1506. Status 2003 contains information such as "normal" or "abnormal (unable to start, unable to process I / O)". Power mode 2004 indicates the power mode of the storage controller. Power mode 2004 is one of the following in controller management table 1801: normal mode 1902, power off 1903, standby mode 1904, power saving mode A 1905, and power saving mode B 1906. Processing load 2005 indicates the processing load of controller 1506.

[0200] Figures 21A to 21C show examples of the settings for the controller power setting information table 1803 shown in Figure 18. These figures 21A to 21C comprehensively show the power setting information for the controller 1506 included in the storage system 1502, and are managed separately from the power modes set for individual controllers 1506.

[0201] The controller power setting information table 1803 contains entries for power saving mode setting 2101, redundancy setting value 2102, and power consumption upper limit value 2103. Here, we show an example of the information stored based on three setting examples, which will be explained further below.

[0202] Figure 21A shows a configuration example where the power consumption reduction method in this embodiment is not used (the case where the normal mode is always used as the power mode of the controller 1506, as before). In this case, the redundancy setting value 2102 and the power consumption upper limit value 2103 do not contain any information.

[0203] Figure 21B shows an example of the settings where the storage system 1502 is subjected to a method that reduces power consumption according to the processing load without degrading the I / O processing performance in this embodiment. In this case, the redundancy setting value 2102 indicates information on whether the system is operating at an arbitrary degree of redundancy so that I / O processing can continue even if the controller 1506 fails. In this embodiment, redundancy is defined as "n-multiplex (n: natural number)", where redundancy 1 refers to 2-multiplex (i.e., duplication), meaning that any I / O can be processed by two or more controllers 1506, and that I / O processing can continue even if one storage controller fails. In other words, in the case of N-multiplex (in other words, when an N-1 redundancy is given), it means that any I / O can be processed by N or more controllers 1506, and that I / O processing can continue even if N-1 storage controllers fail. In the event of a storage controller failure, if any of the normally functioning storage controllers detect that the current redundancy of the storage system 1502 falls below the specified redundancy level, the normally functioning storage controller will respond by starting up a storage controller that is powered off or in standby mode to restore redundancy. In this recovery process, for example, if both a powered-off storage controller and a storage controller in standby mode exist, the standby storage controller will be made active, and the powered-off storage controller will be moved back to standby mode. This enables rapid redundancy recovery and provides a stock of standby storage controllers that can be quickly started up in the event of further storage controller failures.

[0204] In the configuration example shown in Figure 21C, the storage system 1502 is configured to further set an upper limit on power consumption, ensuring that the system does not exceed a specified power consumption limit even when the processing load increases. In this case, the power consumption limit 2103 stores the upper limit on power consumption set by the user.

[0205] Figure 22 shows an example of the data exchanged in processing requests and responses between the storage system 1502 and the management terminal 1505 shown in Figure 15.

[0206] The operational information acquisition request 2201 is sent from the management terminal 1505 to the storage system 1502 when it wants to acquire operational information for each controller 1506. The operational information acquisition request 2201 includes the identifier of the destination controller 1506, the requester, and the content of the request.

[0207] Response 2202 to the request for operational information is sent from the controller 1506, which has acquired the operational information, to the management terminal 1505 in the storage system 1502. Response 2202 to the request for operational information includes the recipient, the identifier of the requesting controller 1506, the content of the request, and the acquired operational information. Note that the operational information corresponds to one entry in the controller operational history table 1802.

[0208] The power mode change request 2203 is sent from the management terminal 1505 to the storage system 1502 when it wants to change the power mode of the controller 1506. The power mode change request 2203 includes the identifier of the destination controller 1506, the requester, the content of the request, and information about the power mode to be changed.

[0209] Response 2204 to a power mode change request is sent from the controller 1506 that has completed the power mode change in the storage system 1502 to the management terminal 1505. Response 2204 to a power mode change request includes the recipient, the identifier of the requesting controller 1506, and the result of the processing (content).

[0210] Figure 23 shows an example of the storage system management screen 2301. The storage system management screen 2301 is displayed on the management terminal 1505.

[0211] The storage system management screen 2301 includes a menu bar 2302 and screens 2303 corresponding to each menu. This example shows the screen with the power mode settings menu selected.

[0212] Screen 2303 contains system operation information 2304, controller-specific operation information 2305, power saving mode setting information 2306 for the storage system 1502, and redundancy setting information 2307 for the storage system 1502.

[0213] The system-level operational information 2304 displays information about the storage system 1502 managed by the management terminal 1505. For example, it includes information collected from the controller 1506, such as the current processing load value, predicted future processing load value, current power consumption value, current power reduction effect (according to this embodiment), maximum power consumption (upper limit), and maximum processing capacity, as well as other information set by the user.

[0214] The controller-specific operational information 2305 displays current information about each controller 1506 included in the storage system 1502. For example, this includes the controller identifier, status, power mode, and processing load.

[0215] The power saving mode setting information 2306 is an interface that accepts user input for selecting a power saving mode for the storage system 1502, and also functions as a display interface for referring to the current setting information.

[0216] The redundancy setting information 2307 is an interface that accepts user input for selecting the redundancy level (how many levels of redundancy the storage system will be operated with) for the storage system 1502, and also functions as a display interface for referring to the current setting information. In addition, information such as the maximum power consumption (upper limit) included in the power saving mode setting information 2306, redundancy setting information 2307, and operation information 2304 is also reflected in the controller power setting information table 1803 shown in Figures 21A to 21C, and is used to set the power mode for each controller 1506. Note that the screen configuration shown here is just an example, and it may be implemented in a different format. For example, an interactive command-line interface may also be used.

[0217] Figure 24 is a flowchart illustrating an example of the controller power consumption control process. This controller power consumption control process is performed on the management terminal 1505 to reduce power consumption.

[0218] The controller power consumption control process is executed by the CPU 1515 when the management terminal 1505 is started up, and is an example of automatically performing power consumption reduction control (for example, in Figure 23, it is assumed that "Automatic" is selected as the power saving mode setting information).

[0219] The process for monitoring the processing load of each controller 1506, the monitoring results, the set redundancy level, and the power mode request / response process determined for each controller 1506 based on the specified maximum power consumption are outlined in Figure 22 above.

[0220] In Figure 24, the automatic execution of the controller power consumption control process described above involves, for example, the following three steps. These steps can be implemented by having the CPU 1515 read the controller management program 1701 stored in the program area 1601 of the memory 1516 in response to the startup of the management terminal 1505 or the update of the power saving mode setting information 2306, and then executing the controller power consumption control program 1702, the controller operating status monitoring program 1703, and the controller power mode determination and change program 1704 in response to the execution of this controller management program 1701.

[0221] In the first step, when the management terminal 1505 is started up, the CPU 1515 monitors the processing load of the controller 1506 connected to the management terminal 1505 and records it in the controller operation history table 1802 (step S2401). More specifically, for example, if automatic is specified as the power saving mode setting, power mode optimization is performed periodically or according to user instructions. First, the controller management program 1701 is executed, and as a step included in its processing, the CPU 1515 reads and executes the controller operation status monitoring program 1703 and performs processing load monitoring of the controller 1506.

[0222] The controller operation status monitoring program 1703 accesses the controller management table 1801 to obtain information on the controller identifier 1901. Based on the controller identifier 1901, the controller operation status monitoring program 1703 determines the recipient (destination) to request confirmation of the processing load status, identifies itself (i.e., the management terminal 1505) as the requesting party, and sends the request details (request for acquisition of operation information) to the storage system 1502 as an operation information acquisition request 2201. In parallel with these processes, the CPU 1515 records the acquisition time 2001, which is performed, for example, in step S2502 shown in Figure 25, described later.

[0223] When any controller 1506 in the storage system 1502 receives the operation information acquisition request 2201, that controller 1506 forwards the operation information acquisition request 2201 to the controller 1506 to which the corresponding controller identifier 1901 is assigned, according to the controller identifier 1901 contained in the operation information acquisition request 2201.

[0224] Upon receiving the forwarded operational information acquisition request 2201, the controller 1506 acquires its own operational information in accordance with the request for operational information acquisition contained in the operational information acquisition request 2201. Subsequently, the controller 1506 executes a response 2202 to the operational information acquisition request, which includes a completion notification of the acquisition of operational information for the operational information acquisition request 2201, source information (i.e., the controller identifier 1901 assigned to itself as the requester), and destination information (management terminal 1505). The operational information includes, for example, the controller identifier 1901, status, applied power mode, and processing load. As an example of processing load, the percentage is expressed by dividing the I / O processing amount per unit time by the maximum amount specified in the specifications, but the definition of processing load is not limited to this.

[0225] Upon receiving response 2202 to the request for obtaining operational information, the management terminal 1505 writes the operational information to the controller operational history table 1802 stored in memory 1516, as shown in Figure 20. Further details of this step 2401 are explained in Figure 25.

[0226] Next, in the second step, the controller power mode determination and modification program 1704 refers to the controller management table 1801, the controller operation history table 1802, and the controller power setting information table 1803, and determines the power mode of each controller 1506 based on the operation history and setting information, and changes the power mode if necessary (step S2402). Details of the processing in steps S2401 and S2402 when automated will be described later, but for example, the following processing is performed.

[0227] First, the controller management program 1701 reads and executes the controller power consumption control program 1702. The controller power consumption control program 1702 accesses the management information area 1602 to obtain relevant information and determines the power mode to apply to each controller 1506. The determined power mode is transmitted from the management terminal 1505 to the storage system 1502.

[0228] For example, as shown in Figure 22 above, the management terminal 1505 issues a power mode change request 2203 to the storage system 1502, which includes destination information (controller identifier 1901), the requester (i.e., the management terminal 1505), the instruction content (i.e., the power mode change request), and the specified power mode (the power mode to be applied). The issued power mode change request 2203 is received by one of the controllers 1506 and forwarded to the corresponding controller 1506 based on the controller identifier 1901. For example, upon receiving a power mode change request 2203 addressed to itself, the controller 1506 performs the necessary processing. This necessary processing includes steps S1407 (waiting for processing requests) and S1411 (specific pre-processing) in Figure 14 of the first embodiment.

[0229] The controller 1506, having processed the issued power mode change request 2203, executes a response to the management terminal 1505 (response to the power mode change request 2204).

[0230] In the third step, the CPU 1515 determines the trigger for the next execution of the power consumption control process and terminates the process (step S2403). The trigger for the next execution may be, for example, after a certain period of time has elapsed, or one or more conditions may be set, such as when the storage administrator operates the management terminal 1505, or when the storage controller is installed or removed. In any case, information regarding the determined trigger may be stored as a variable related to the startup of the controller management program 1701 in a designated area (not shown) of the management information area 1602.

[0231] Figure 25 is a flowchart showing an example of the procedure for the controller operating status monitoring process shown in Figure 24. This controller operating status monitoring process is performed in the storage system power consumption control process executed on the management terminal 1505.

[0232] CPU 1515 refers to the controller management table 1801 and starts monitoring from the controller listed in the first row (step S2501). Note that although monitoring starts from the controller listed in the first row, the order is not limited to this. That's fine.

[0233] CPU 1515 obtains the current date and time (step S2502). The date and time obtained here corresponds to the data collection time 2001 in the controller operation history table 1802, and can be either a specific time or, for example, the elapsed time since the storage system 102 was started.

[0234] The CPU 1515 issues a processing request to the target controller 1506 to obtain operational information (status, power mode, and processing load), waits for the result to be received, and proceeds to the next process upon receipt of the result (step S2503).

[0235] CPU 1515 acquires operational information of the target controller 1506 (step S2504) and appends the acquired information (current date and time, status, power mode, and processing load) to the storage system management history table (not shown) (step S2505).

[0236] CPU 1515 refers to the controller management table 1801 to determine whether there is a successor storage controller to the currently targeted storage controller (step S2506). If the determination shows that a successor exists (step S2506: Yes), the process proceeds to step S2507. On the other hand, if no successor exists (step S2506: No), the process terminates.

[0237] CPU 1515 refers to the controller management table 1801, targets the next storage controller after the currently targeted storage controller, starts the controller operational status monitoring program 1703, and begins monitoring the load of each controller 1506 (step S2507). Then proceeds to step S2502.

[0238] Figure 26 is a flowchart showing an example of the procedure for determining and changing the controller power mode shown in Figure 24. This controller power mode determination and change procedure is an example of a process (for example, process 2402 shown in Figure 24) performed in the storage system power consumption control process at the management terminal 1505.

[0239] The CPU 1515 starts the controller power mode determination and modification program 1704, refers to the controller power setting information table 1803, and obtains the setting information (power saving mode, redundancy setting value, and power consumption upper limit) (step S2601).

[0240] The controller power mode determination and modification program 1704 determines whether the power saving mode of the storage system 1502 is OFF or OFF based on the information obtained in step S2601 (i.e., it checks whether the power saving mode setting function of the storage system 1502 is stopped or OFF). If the result of the determination is that it is not OFF (step S2602: Yes), the program proceeds to step S2603. On the other hand, if the result of the determination is OFF (step S2602: No), the program proceeds to step S2604.

[0241] The controller power mode determination and modification program 1704 calculates the minimum number of I / O-processing storage controllers (X) that can maintain redundancy, based on the redundancy setting value obtained in step S2601 (step S2603). An "I / O-processing storage controller" refers to a controller whose power mode is not zero, such as "power off" or "standby mode". For example, if the redundancy setting value is 1 and there are 2 multiplexed controllers, (X) will be 2, and if the redundancy setting value is 2 and there are 3 multiplexed controllers, (X) will be 3. The process then proceeds to step 2605.

[0242] The controller power mode determination and modification program 1704 determines the power mode of all controllers 1506 of the storage system 1502 to "normal mode" (step S2604). Then, the process proceeds to 2616.

[0243] The controller power mode determination and change program 1704 refers to the controller operation history table 1802 and predicts the future processing load (step S2605). For example, by obtaining the sampling time 2001 and the processing load 2005, the fluctuations in the processing load of the device can be confirmed in chronological order, and the future processing load can be predicted. Note that information other than the controller operation history table 1802 may also be used to predict the future processing load. For example, the change in the number of logical volumes defined in the storage system 1502 or the change in the number of connected hosts may be used.

[0244] Next, the controller power mode determination and modification program 1704 calculates the minimum number of I / O-capable storage controllers (Y) that can support the future processing load (step S2606). This calculation method can, for example, be based on the maximum processing performance of the controllers to determine how many controllers are needed to support the future processing load. In other words, in a device that uses general-purpose semiconductor devices such as storage controllers, when attempting to provide a predetermined I / O processing capacity, the minimum number of controllers (Y) that is estimated to be able to support the future processing load based on the maximum processing performance of the controllers can be calculated. This allows the storage system 1502 to determine the conditions under which it can perform I / O processing of the required scale while avoiding performance degradation and minimizing power consumption. In this embodiment, the controllers 1506 mounted on the storage system 1502 have substantially the same design performance. Furthermore, when calculating the minimum number of controllers (Y) as described above, a margin may be added to the assumed maximum processing performance or to the number of controllers (Y) itself.

[0245] The controller power mode determination and modification program 1704 compares (X) and (Y) obtained in steps S2603 and S2606 and determines whether (X) ≤ (Y) (step S2607). If the result of the determination is (X) ≤ (Y) (step S2607: Yes), the program proceeds to step S2608. On the other hand, if the result of the determination is not (X) ≤ (Y) (step S2607: No), the program proceeds to step S2609.

[0246] The controller power mode determination and modification program 1704 determines the number of I / O-capable storage controllers (required number) as calculated in step S2606 (Y) and continues processing (step S2608). Then proceeds to process 2610.

[0247] The controller power mode determination and modification program 1704 calculates the number of storage controllers capable of I / O processing (required number) in process 2603 (X) and continues processing (step S2609). Then proceeds to process 2610.

[0248] The controller power mode determination and modification program 1704 calculates the combination of power modes (Z) of the controller 1506 that can minimize power consumption (step S2610). For example, if the processing load can be concentrated on a specific controller 1506, it is possible to create a device with zero processing load, and by combining it with power mode OFF, it is possible to provide processing power that exceeds the predicted future processing load while reducing power consumption compared to equalizing the processing load across devices. However, in order to maintain redundancy, the combination is determined so that the (required number) or more controllers 1506 are in a power mode other than "power OFF" or "standby mode".

[0249] Furthermore, for example, the number of I / O-capable storage controllers identified in step 2608 or step 2609 is calculated based on the maximum processing performance of a single controller 1506, so there may be some margin for the expected processing load. In such cases, it is possible to assign normal mode to a specific controller 1506 and power-saving mode A or power-saving mode B to the other controllers 1506. Note that any method can be used for this assignment, and one or more combinations may be identified. In any case, the combination of power modes (Z) that can minimize power consumption is identified. Also, if controller 1506 fails, and there are other controllers 1506 that are not currently capable of I / O processing, redundancy can be restored by changing the other controllers 1506 to an I / O-capable state. At this time, the shorter the time (transition time) to transition the other controllers 1506 to an I / O-capable state, the better the availability of controller 1506 can be, and the shorter the time during which processing capacity is reduced. Therefore, in power mode combinations where other controllers 1506 that are not capable of I / O processing exist, setting one controller to the "standby mode" power mode significantly reduces the transition time compared to the "power off" case.

[0250] The controller power mode determination and modification program 1704 refers to the power saving mode setting information 2306 obtained in step S2601 (i.e., accesses the controller power setting information table 1803) and determines whether the power saving mode is "specified" or not (step S2611). If the determination result is that the power saving mode is "specified" (step S2611: Yes), the program proceeds to step S2612. On the other hand, if the determination result is that the power saving mode is not "specified", the program proceeds to step S2615.

[0251] The controller power mode determination and modification program 1704 calculates the maximum power consumption value (α) for the power mode combination (Z) calculated in step S2610 (step S2612).

[0252] The controller power mode determination and change program 1704 determines whether the power consumption value (α) for the power mode combination (Z) calculated in step S2612 exceeds the power consumption upper limit value 2103 obtained in step S2601 (step S2613). If the result of the determination is that it exceeds the limit (step S2613: Yes), the program proceeds to step S2614. On the other hand, if the result of the determination is that it does not exceed the limit (step S2613: No), the program proceeds to step S2615.

[0253] The controller power mode determination and modification program 1704 modifies the power mode combination (Z) that minimizes power consumption, determined in step S2610, so as not to exceed the power consumption limit 2103 (step S2614). Specifically, the controller power mode determination and modification program 1704 calculates the power mode combination (Z) that does not exceed the power consumption limit 2103 and is determined in step S2603 as the required number of storage controllers capable of I / O processing (X). In other words, even if the minimum number of storage controllers capable of I / O processing (Y) expected to be necessary to support the expected processing load is greater than (X), the program updates the number of storage controllers capable of I / O processing (X) that can ensure redundancy while prioritizing power consumption reduction to the required number, and then determines the power mode combination that can provide maximum processing performance while adhering to the power consumption limit 2103 condition. After that, the program proceeds to step S2615 (I). Furthermore, the system may be configured to ask the user whether or not to prioritize reducing power consumption. For example, if (required number) was determined based on (Y), and it is determined that further reduction (e.g., setting (X) to (required number)) is necessary in relation to the power consumption limit 2103, the administrator of the storage system 1502 may be prompted to confirm whether to allow or reject the reduction. In addition to this confirmation of whether or not to allow it, the system may also notify (warn) the user that the system has been set to a power mode that may not be able to support future processing loads in order to not exceed the power consumption limit 2103. By providing these notification functions, the storage system 1502 can be provided in a way that is more convenient for the user and aligns with the desired performance indicators (processing performance and power consumption reduction).

[0254] The controller power mode determination and change program 1704 confirms (Z) obtained in the above process as the power mode combination and proceeds with the subsequent processing (step S2615). Controllers 1506 with (Y) or (X) units are assigned a power mode in which I / O processing can be performed, while controllers 1506 that are in a state in which I / O processing can be performed at the time the controller power mode determination and change process starts and are not included in (Y) and (X) transition to standby mode or power-off mode. The method for selecting (X) or (Y) units of controllers, or the method for selecting controllers to be excluded from (X) or (Y) units of controllers, can be any criterion, such as operating history or cumulative processing load.

[0255] The controller power mode determination and modification program 1704 requests the storage system 1502 to change the power mode of controller 1506, waits for a completion response, and terminates processing once a completion response is received (step S2616). Note that changing the power mode of controller 1506 requires processing in the storage system 1502, such as rebalancing the processing load among multiple controllers 1506 and changing the destination of I / O processing requests from the host machine 1503. These processes are implemented, for example, by utilizing a method in which another controller 1506 takes over processing if controller 1506 fails.

[0256] The storage system according to this embodiment is a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, and includes a plurality of components (a plurality of controllers 1506) that can be switched between a normal power mode and at least one power-saving mode with a lower power consumption than the normal power mode and operate in each mode, a controller operation state monitoring program 1703 as an example of a state monitoring unit that monitors the operation state of each of the plurality of components, and a power mode control unit (controller power mode determination and change program 1704) that determines the power mode of at least one specific component to be the power-saving mode based on the processing load for each of the plurality of components that is the result of the monitoring by the controller operation state monitoring program 1703, and operates at least one specific component in the power-saving mode. The plurality of components execute control in response to the data input / output request with the storage device. This can reduce power consumption without degrading the I / O performance with the host.

[0257] The method for suppressing power consumption of the storage system according to this embodiment is a method for suppressing power consumption of a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, and includes a state monitoring step in which a controller operation state monitoring program 1703 as an example of a state monitoring unit monitors the operation state of each of a plurality of components that can be switched between a normal power mode and at least one power-saving mode with a lower power consumption than the normal power mode and operate in each mode, and a power mode control step in which a controller power mode determination and change program 1704 as an example of a power mode control unit determines the power mode of at least one specific component to be the power-saving mode based on the processing load for each of the plurality of components that is the result of the monitoring in the state monitoring step, and operates the specific component in the power-saving mode. The plurality of components execute control in response to the data input / output request with the storage device.

[0258] In this embodiment, the above-described plurality of components are a plurality of controllers 1506 that control data input / output processing with a host. The storage system according to this embodiment includes a management terminal 1505 that controls the plurality of controllers. The management terminal 1505 includes a controller operation state monitoring program 1703 as an example of a state monitoring unit and a controller power mode determination and change program 1704 as an example of a power mode control unit.

[0259] In this embodiment, the controller power mode determination and change program 1704 selects a specific power mode that can shift to a state where input / output processing can be executed by other controllers immediately after detecting a failure that has occurred in any one of the plurality of controllers based on redundancy setting (for example, setting of durability (N-fold) against controller failure). By doing so, even when a failure occurs in any one of the controllers, input / output processing can be executed immediately thereafter.

[0260] In this embodiment, the controller power mode determination and change program 1704 operates a part of the CPU (Central Processing Unit) cores equipped with a plurality of cores while enabling other controllers to shift to a state where input / output processing can be executed immediately thereafter, and makes other cores standby. By doing so, since the CPU is operating with a minimum number of cores, power consumption can be further reduced.

[0261] Also, the method of changing the power consumption mode with the storage controller described in the above-described present embodiment as a control unit can be extended from the storage controller to the component level with respect to the control unit. Specifically, it is possible to apply the concept shown in Example 1 and the concepts of redundancy, power-off mode, and standby mode shown in Example 2.

[0262] Taking the system configuration shown in Figure 1 as an example, each CPU 106 has multiple cores 114 (four in this figure), and redundancy is provided among the cores 114 contained within a single CPU. An example of this configuration is as follows.

[0263] For example, two of the four cores 114 included in the CPU 106 are set to the Active state (capable of performing I / O processing), and the remaining two cores 114 are set to the Standby state (not capable of performing I / O processing). Furthermore, the Active state can be selectively set for each core 114 to either a state where the function can be used without any particular restrictions (normal Active) or a state where power saving techniques such as changing the operating frequency or voltage change control are applied (power saving Active). The setting of this Active state is envisioned to be controlled and managed in the following way, for example.

[0264] The power mode setting for each core 114 (Active state) is set in conjunction with the power mode of the controller 1506 as described in the second embodiment. For example, if the power mode of the controller 1506 is "Normal", then the Normal Active mode is applied to the cores in the Active state among the multiple cores of the CPU included in the controller 1506. When any one power saving mode is applied to the controller 1506, at least some of the cores in the Active state transition to the Power Saving Active state in accordance with that power saving mode. "At least some" means that in order to satisfy the conditions for the maximum power consumption allowed in the predetermined power saving mode set for the controller 1506, the cores in the Active state may all shift to Power Saving Active, or a combination of cores that continue to operate in Normal Active and cores that transition to Power Saving Active may be used. Furthermore, by setting multiple cores to the Active state in this manner, it is possible to provide redundancy to the functions within the CPU 106. For example, even if one of the cores in the Active state fails, the CPU 106 can continue processing externally using the other Active cores, and in addition to controlling power consumption according to the processing load, improved fault tolerance can be expected.

[0265] On the other hand, setting a Standby state can be achieved by applying clock gating or power gating. The number of cores in the CPU that are in the Active state and those that are in the Standby state can be arbitrarily designed according to the performance required of the controller. The difference between the Active state and the Standby state is, for example, whether or not the power mode change linked to the power mode applied to the controller as described above is applied. In this example, the aforementioned linked change operation is applied to the cores in the Active state.

[0266] A core in standby mode is configured to become a new active core when it detects that the redundancy of cores within the CPU has fallen below an arbitrarily set value due to the failure of one or more active cores operating within the same CPU. To speed up the switch from standby to active mode, preferably, at least one core in standby mode has its power limited by a power-saving technique suitable for fast startup (clock gating), while the other cores have their power consumption reduced by a technique such as power gating, which has a significant power consumption reduction effect. By adopting such a configuration, it is possible to improve CPU availability while contributing to power saving as a storage system.

[0267] Regarding the Active and Standby states described above, the power control methods applied to each core may differ between the two settings, or at least some of the methods may be common. Even if there are cores in the Active state and I / O processing is possible, if the state of the controller to which the CPU containing those cores belongs is, for example, standby mode or power-off mode, the CPU as a whole will not perform I / O processing. Furthermore, although power control and redundancy in a multi-core CPU have been described here, the concepts described can be applied to devices included in other controllers (especially devices with redundancy). In such cases, power control methods for target devices other than clock gating and power gating (such as limiting the maximum applicable voltage) can be used. Also, the clock gating and power gating described above are merely examples of power control technologies that can be used, and are not the only ones that can be applied.

[0268] (3) Third Embodiment The storage system according to the third embodiment is the same as the storage systems according to the first and second embodiments, except for the differences described below, so the descriptions of the similar parts will be omitted. Note that the storage system according to the third embodiment may have different reference numerals for components such as the CPU and controller compared to the storage systems according to the first and second embodiments, but unless otherwise specifically mentioned in the following description, it has the same configuration and functions as the storage systems according to the first and second embodiments.

[0269] A description of the storage system according to the third embodiment will be given with reference to Figures 27 to 37. Figure 27 is a system configuration diagram showing an example of the configuration of a storage system 2700 according to a third embodiment. The storage system 2700 includes controllers 2701 and 2721, and a PDEV BOX 2740 having multiple PDEVs, including PDEVs 2742 and 2762.

[0270] The storage system 2700 is configured with logical volumes capable of storing data, and data input / output processing is performed by controllers 2701 and 2721.

[0271] Controller 2701 has a host interface (I / F) 2702, a CPU 2703, memory 2704, and a non-transparent bridge (NTB) 2708. The host interface 2702, CPU 2703, and NTB 2708 are interconnected, for example, via a PCIe (Peripheral Component Interconnect Express) link. Similarly, controller 2721 has a host interface 2722, a CPU 2723, memory 2724, and NTB 2728. The host interface 2722, CPU 2723, and NTB 2728 are interconnected via a PCIe link. The CPU 2703 and memory 2704, and the CPU 2723 and memory 2724 are connected via memory buses, respectively.

[0272] Furthermore, similar to the controller 104 in Figure 1 in the first embodiment, the controllers 2701 and 2721 may each include a CPU 2703 or 2723 and an accelerator (not shown) connected, for example, by a PCIe link.

[0273] Furthermore, controllers 2701 and 2721 are each equipped with management terminal interfaces 2771 and 2772 for connecting to the management terminal 2774 via the management terminal network 2773. The management terminal 2774 has the same functionality as the management terminal 1505 in Figure 15 of the second embodiment.

[0274] The CPU 2703 contains multiple cores 2705 and an uncore 2706, which is the remaining portion. Here, in this embodiment, "uncore" refers to components other than the so-called core components that perform calculations in a processor such as a CPU (Central Processing Unit). The uncore 2706 includes, for example, a DMA (Direct Memory Access) 2707. Similarly, the CPU 2723 contains multiple cores 2725 and an uncore 2726, which is the remaining portion. The uncore 2726 includes a DMA 2727.

[0275] The host machines 2750 and 3100, which access the storage system 2700, are connected to the storage system 2700 via host interfaces 2702 and 2722, respectively. The host machines 2750 and 3100 are connected to the host interfaces 2702 and 2722 by transmission lines such as Fibre Channel cables or Ethernet cables. Alternatively, the host machines 2750 and 3100 and the host interfaces 2702 and 2722 may be connected via a storage area network (not shown) consisting of multiple transmission lines and multiple switches.

[0276] Host interfaces 2702 and 2722 convert the data transfer protocol between the host machines 2750 and 3100 and the storage system 2700, and the data transfer protocol within controllers 2701 and 2721.

[0277] PDEV BOX 2740 is connected to controllers 2701 and 2721 via links 2731, 2732, 2751, and 2752. PDEV BOX 2740 includes PDEV switches 2741 and 2761 that connect PDEV 2742 and 2762 via links 2743, 2744, 2763, and 2764. In this embodiment, links 2731, 2732, 2743, 2744, 2751, 2752, 2763, and 2764 are, for example, PCIe links. PDEV switches 2741 and 2761 are PCIe switches, and PDEV 2742 and 2762 are NVMe drives with dual ports. In this embodiment, the PDEV I / F is not used for the connection between the CPU and the PDEV switch, and the CPU and the PDEV switch are directly connected via a PCIe link.

[0278] CPUs 2703 and 2723 control data transfer between host machines 2750 and 3100 connected via host I / Fs 2702 and 2722 and PDEV 2742 and 2762 connected via PDEV switches 2741 and 2761. Further, CPUs 2703 and 2723 control data transfer between the controllers.

[0279] Memories 2704 and 2724 are the main memory devices of CPUs 2703 and 2723, respectively, and store programs (such as storage control programs) executed by CPUs 2703 and 2723 and management tables referred to by CPUs 2703 and 2723. Also, memories 2704 and 2724 are also used as cache memories for controllers 2701 and 2721, respectively.

[0280] NTB2708 and NTB2728 are connected by, for example, an inter-controller link 2711, which is a PCIe link. CPU 2703 and CPU 2723 can communicate with each other via the inter-controller link 2711. In this way, the storage system 2700 is configured as a dual controller with two controllers 2701 and 2721. CPUs 2703 and 2723 transfer data received from the host, which is duplicated between the two controllers, and metadata used for controller control, over the inter-controller link 2711.

[0281] Memory units 2704 and 2724 have OQ (Outbound Queue) and IQ (Inbound Queue), which are queues for controlling message transfer between CPUs 2703 and 2723 and host interfaces 2702 and 2722. OQ is a queue that controls message transfer from the host interface to the CPU, and IQ is a queue that controls message transfer from the CPU to the host interface. Memory unit 2704 has OQ2709 and IQ2710, which are queues for controlling message transfer between CPU 2703 and host interface 2702. Memory unit 2724 also has OQ2729 and IQ2730, which are queues for controlling message transfer between CPU 2723 and host interface 2722.

[0282] In Figure 27, OQ2709 is denoted as "OQ01", IQ2710 as "IQ01", OQ2729 as "OQ11", and IQ2730 as "IQ11".

[0283] The process by which host interfaces 2702 and 2722 store data received from host machines 2750 and 3100 in memory 2704 and 2724, or the process by which host interfaces 2702 and 2722 send data from memory 704 and 2724 to host machines 2750 and 3100, and related processes, will be referred to as "host I / O processing".

[0284] Furthermore, the process of writing data stored in memory 2704 and 2724 to PDEV2742 and 2762, or the process of reading data stored in PDEV2742 and 2762 to memory 2704 and 2724, and related processes will be referred to as backend processing.

[0285] Furthermore, the process of duplicating data received from host machines 2750 and 3100 between memory 2704 and memory 2724 using DMA 2707 and 2727, and related processes, will be referred to as "data duplication processing."

[0286] In this embodiment, the PCIe link used has its power management function, ASPM (Active State Power Management), enabled as needed. In ASPM, the state in which the PCIe link is active and capable of executing transactions is the L0 state, which is when the link's power consumption is at its maximum. In ASPM, a state in which the link is power-saving is, for example, L 0s There are different states, such as L0 and L1. For example, when data is being transferred between the CPU and PDEV, the PCIe link between them is in the L0 state. When there is no data transfer between the CPU and PDEV and the link is idle, the PCIe link between them automatically transitions to a power-saving state, such as L1.

[0287] Figure 28 is a flowchart of the controller power mode determination process in the storage system 2700. Hereinafter, this process flow will be described assuming it is executed on the management terminal 2774, but it may also be executed on the CPU 2703 or CPU 2723. This process flow will be referred to as the controller power mode determination program 2800. In the second embodiment, this controller power mode determination program 2800 may be executed as part of the process performed in the storage system power consumption control process (step S2402 in Figure 24).

[0288] Furthermore, the storage system 2700 is assumed to have its power saving mode setting set to "Automatic" and its redundancy setting value set to "Redundancy 1," similar to Figure 21B. In other words, on the management screen of the management terminal 2774, which is similar to the storage system management screen 2301 in Figure 23, the power saving mode setting information 2306 is displayed as "Automatic" and the redundancy setting information is displayed as "Redundancy 1 (2-way)."

[0289] First, the controller power mode determination program 2800 predicts the future processing load of each controller 2701, 2721 constituting the dual controller, similar to the controller power mode determination and change program 1704 in the second embodiment (step S2801).

[0290] In the storage system 2700 of this embodiment, the controller power mode determination program 2800 sets some of the multiple cores of the CPU that are set to power saving mode to the Active state, and sets the other cores to the Standby state (corresponding to the "Standby state" described above). In this way, the CPU can be operated with the minimum necessary cores, thereby reducing the CPU's power consumption.

[0291] In other words, in this embodiment, the controller power mode determination program 2800, as an example of a power mode control unit, sets the power mode of components with a high predicted processing load to a power-saving mode C1, which is an example of a predetermined second power mode (for example, setting N cores of the controller's cores to the Active state and the remaining cores to the Standby state), and the power mode of components with a low predicted processing load to a power-saving mode C2, which is an example of a specific second power mode (for example, lowering the operating frequency of the CPU's uncores compared to the normal mode, which is the first power mode of the controller), and compares this with the power consumption of a second case (B) (corresponding to the first and second embodiments described above), in which the power mode is determined for each component. On the condition that the power consumption of the second case (B) is greater than the power consumption of the first case (A), the power mode of components with a high predicted processing load is set to a predetermined second power mode (for example, power-saving mode C1), and the power mode of components with a low predicted processing load is set to a specific second power mode (for example, power-saving mode C2). On the other hand, if the above condition is not met, power mode control is performed, for example, as in the first and second embodiments described above.

[0292] The aforementioned multiple components are, for example, multiple sub-elements (for example, cores and uncores that make up CPU2703 and CPU2723) of each processor in multiple controllers (for example, CPU2703 of "CPU0" and CPU2723 of "CPU1"). When one processor of one controller 2721 (CPU2723 of "CPU1") is operating, the control of a core, as an example of a sub-element of that processor, is switched to the other processor of the other controller (for example, CPU2703 of "CPU0"). The power mode of that processor is set to a power-saving mode C2 as a specific second power mode, and the power mode of the other processor is set to a predetermined power-saving mode C, which has higher power consumption than the power-saving mode C2 as an example of a specific second power mode. 1 Set it.

[0293] The controller power mode determination program 2800 is an example of a power mode control unit, which switches the other processor to control data input / output requests from the host using one of the uncores as an example of a subset element of the one controller. The memory of the one controller (e.g., "memory 2724") includes control queues (IQ11 (2730), OQ11 (2729) described later), and the other processor accesses these control queues using the uncore, which is a subset element of the one controller, to control data input / output requests from the host. This will be explained in detail below.

[0294] First, the controller power mode determination program 2800 calculates the minimum number of I / O-capable active cores N that can support the future processing load per dual controller (step S2802).

[0295] This calculation method can, for example, determine how many Active cores are needed to support the future processing load based on the maximum processing performance of each Active core. In other words, for a device using a general-purpose CPU such as a storage controller, when attempting to provide a predetermined I / O processing capacity, the minimum number of Active cores N estimated to be able to support the future processing load is calculated based on the maximum processing performance of each Active core. This allows the storage system 2700 to determine the conditions under which it can perform I / O processing of the required scale while avoiding performance degradation and minimizing power consumption. In this embodiment, the CPUs 2703 and 2723 installed in the storage system 2700 have substantially the same design performance in terms of the number of cores and operating frequency. Furthermore, when calculating the number of Active cores N, a margin may be added to the assumed maximum processing performance or to the number of Active cores N itself. In addition, when calculating the number of Active cores N, a condition may be included that the impact on data input / output processing with the host machine is below a predetermined standard.

[0296] Next, the controller power mode determination program 2800 compares the number of cores per controller with the number of active cores N (step S2803). In the storage system 2700, the number of cores per controller refers to the number of cores that CPUs 2703 and 2723 each have. If the number of cores per controller is greater than or equal to the number of active cores N (step S2803: Yes), the controller power mode determination program 2800 proceeds to step S2804. Otherwise (step S2803: No), it proceeds to step S2807.

[0297] In dual-controller systems, the CPUs installed in the controllers may have different performance characteristics, such as the number of cores or operating frequency, or even within a single CPU, the core performance and operating frequency may not be uniform. In such cases, it may be difficult to express the processing performance of the controllers using the number of active cores. In such cases, instead of steps S2802 and S2803, it may be possible to determine whether the future processing load per dual controller of the storage system 2700 can be handled by only one controller.

[0298] In step S2804, the controller power mode determination program 2800 calculates the power consumption (A) of the storage system 2700 when the power mode of the controller with the higher predicted processing load in step S2801 is set to power saving mode C1, and the power mode of the controller with the lower predicted processing load is set to power saving mode C2. The controller power mode determination program 2800 calculates the power consumption (B) of the storage system 2700 when the power mode is set for each controller in the same manner as in Figure 12 of the first embodiment. The controller power mode determination program 2800 compares power consumption (A) and power consumption (B).

[0299] Here, power-saving mode C1 includes setting N cores of the controller to the Active state and the remaining cores to the Standby state.

[0300] Furthermore, power-saving mode C2 includes setting cores other than the core executing the controller state monitoring processing program (Figures 36, 3600), which will be described later, to the Standby state. Power-saving mode C2 also includes lowering the operating frequency of the CPU's uncores compared to when the controller's power mode is in normal mode, and enabling the PCIe link's ASPM.

[0301] Here, we explain the purpose of setting two different power modes, power-saving mode C1 and power-saving mode C2, for each controller that makes up the dual controller. If the processing load can be concentrated on one of the dual controllers, the processing load on the other controller will decrease, and power consumption can be reduced for many devices. In some cases, this can reduce the power consumption of the storage system as much as power saving is achieved on each controller individually. In other words, it is thought that setting one of the dual controllers to power-saving mode C1 and the other controller to power-saving mode C2 may further reduce the power consumption per storage system.

[0302] In the following, setting the power mode of one controller of a dual controller to power-saving mode C1 and the power mode of the other controller to power-saving mode C2 may be simply referred to as setting the power mode to power-saving mode C.

[0303] Next, the controller power mode determination program 2800 proceeds to step S2806 (step S2805: Yes) if the power consumption (A) when power saving mode C is set is less than the power consumption (B) when the power mode is set for each controller in the same manner as in Figure 12 of the first embodiment. Otherwise (step S2805: No), it proceeds to step S2807.

[0304] The controller power mode determination program 2800 determines the power mode of the controller with the higher predicted processing load in step S2801 to power saving mode C1, and the power mode of the controller with the lower predicted processing load to power saving mode C2 (step S2806).

[0305] The controller power mode determination program 2800 determines the power mode for each controller in the same manner as shown in Figure 12 of the first embodiment (step S2807).

[0306] The redundancy setting value of the storage system 2700 is 1 (2-multiplex), which allows input / output processing to be performed even if one of the two controllers fails. Even when the power mode of the dual controller is set to power saving mode C, the redundancy setting value of the storage system 2700 in this embodiment is 1 (2-multiplex), which allows input / output processing to be performed even if one of the two controllers fails.

[0307] Even when the power mode is set to power-saving mode C, the storage system 2700 maintains a redundancy level of 1 (2x multiplex). Therefore, the controller set to power-saving mode C1 takes over the host I / O processing that was being performed by the controller set to power-saving mode C2. Furthermore, even after the host I / O processing is handed over between the controllers, the data duplication process, which duplicates the data received from the host machine between memory 2704 and memory 2724, continues. The following describes this host I / O handover process, the data duplication process, and the related controller operations. to Let me explain. First, I will explain OQ and IQ, which are used to control host I / O processing.

[0308] Figure 29 illustrates an example of the OQ and IQ configuration in storage system 2700. While the example uses OQ2729 and IQ2730, the same applies to other OQ and IQ configurations such as OQ2709 and IQ2710.

[0309] Both OQ2729 and IQ2730 store entries in a total of N elements, numbered from 0 to N-1. In OQ2729, the content of an entry is, for example, a host I / O command received from the host machine. In IQ2730, the content of an entry is, for example, a response corresponding to a completed host I / O command, or a data transfer list instructed by the CPU to the host interface. Each entry also contains exchange identification information (i.e., exchange ID) indicating which host I / O exchange the entry is related to. An exchange refers to a series of operations related to read and write operations between the host machine and storage.

[0310] In Figure 29, OQ2729, as an example, from the (i-1)th to i+ 4 The entry is stored in the i-th element. The other elements of OQ2729 are empty. OQPI (Producer Index) 2901 indicates the location of the element where the host interface will next store an entry. OQCI (Consumer Index) 2902 indicates the location of the element where the next entry to be read by the CPU is stored. If OQPI 2901 and OQCI 2902 point to the same element, it indicates that OQ2729 is empty and contains no unprocessed entries. Additionally, the i-1th element stores the most recently processed entry. The CPU can determine which exchange the entry associated with has been processed by examining the exchange ID of this entry.

[0311] In Figure 29, for example, with an IQ of 2730, starting from the (j-1)th term... jThe entry is stored in the +3rd element. The other elements of IQ2730 are empty. IQPI2911 indicates the location of the element where the CPU will store the next entry. IQCI2912 indicates the location of the element where the next entry to be read by the host interface is stored. If IQPI2911 and IQCI2912 point to the same element, it indicates that IQ2730 is empty and contains no unprocessed entries. Additionally, the j-1th element stores the most recently processed entry. The CPU can determine which exchange the entry associated with has been processed by examining the exchange ID of this entry.

[0312] The queue indices OQPI, OQCI, IQPI, and IQCI are stored, as needed, at predetermined addresses in memory, in host interface registers, or both.

[0313] Figure 30 illustrates the data transfer path related to host I / O processing before host I / O handover in the storage system 2700. As an example, it illustrates the data transfer path when the CPU 2723 core 3000 controls the host I / F 2722 in the controller 2721.

[0314] The host interface 2722, which receives host I / O from the host machine 3100, accesses OQ2729, IQ2730, and their queue indices OQPI and IQCI located in memory 2724 via a data transfer path 3001 through CPU 2723.

[0315] Furthermore, the host interface 2722 either stores data received from the host machine 3100 in the memory 2724 via the data transfer path 3001, or sends data stored in the memory 2724 to the host machine 3100.

[0316] Core 3000 accesses OQ2729, its queue index OQPI, and IQ2730 located in memory 2724 via the data transfer path 3002.

[0317] Furthermore, Core 3000 accesses OQCI, the queue index for OQ2729 located on the host I / F2722, and IQPI, the queue index for IQ2730, via the data transfer path 3003.

[0318] Furthermore, Core 3000 receives data from the host machine 3100 and stores it in memory 2724. Core 3000 then uses DMA 2727 to transfer this data from memory 2724 to memory 2704 of controller 2701 via a data transfer path 3004 that passes through CPU 2723, inter-controller link 2711, and CPU 2703. This allows the data received from the host machine 3100 to be duplicated in memory 2704 of controller 2701 and memory 2724 of controller 2721.

[0319] Figure 31 illustrates the data transfer sequence related to host I / O processing before host I / O handover in the storage system 2700.

[0320] Here, as an example, we describe the case where the host I / F 2722 and CPU 2723's core 3000 use OQ2729 and IQ2730 located in memory 2724. Note that in Figure 31, OQ2729 is displayed as "OQ11" and IQ2730 as "IQ11".

[0321] First, the host machine 3100 sends a host I / O command 3101 to the host interface 2722. Upon receiving the host I / O command 3101, the host interface 2722 enqueues an entry 3102 containing the command details to the OQ 2729 (step S3103).

[0322] Next, the host interface 2722 updates the OQPI of OQ2729 in memory 2724 to notify core 3000 that it has enqueued entry 3102 to OQ2729 (step S3104).

[0323] Core 3000 checks for any unprocessed entries in OQ2729 by polling OQPI of OQ2729 (step S3105). If there are unprocessed entries, Core 3000 reads the entries containing the contents of the host I / O commands from OQ2729 (step S3106). Furthermore, Core 3000 updates OQCI of OQ2729 on host I / F2722 (step S3107).

[0324] Next, core 3000 enqueues an entry to IQ2730 containing a data transfer list corresponding to host I / O command 3101 (step S3108). Furthermore, core 3000 updates the IQPI of IQ2730 located on host I / F2722 (step S3109).

[0325] The host interface 2722, with its updated IQPI, reads an entry containing the data transfer list from IQ2730 (step S3110). Subsequently, the host interface 2722 performs data transfer between the host machine 3100 and memory 2724 according to the data transfer list contained in the entry read from IQ2730 (step S3111).

[0326] Once the data transfer is complete, the host I / F 2722 updates the IQCI of IQ2730 located in memory 2724 (step S3112). In this way, CPU2723 CPU core 3000 can process host I / O command 3101 received by host I / F 2722.

[0327] Figure 32 illustrates an example of a P2P (peer-to-peer) data transfer path in CPU2723.

[0328] The CPU2723's uncore 2726 includes a PCIe root complex 3201. Furthermore, root complex 3201 has multiple root ports, including root ports 3202 and 3203. Root port 3202 is connected to the host I / F 2722, and root port 3203 is connected to the NTB2728. As shown in Figure 27, the NTB2728 connects to other controllers 2701 via an inter-controller link 2711. Data transfer via the path 3204, passing through root port 3202, root complex 3201, and root port 3203, is called P2P data transfer.

[0329] Figure 33 illustrates the data transfer path related to host I / O processing after host I / O handover in the storage system 2700. As an example, it illustrates the data transfer path when the core 3300 of CPU 2703, which belongs to controller 2701, controls the host I / F 2722 of controller 2721.

[0330] The host interface 2722, which receives host I / O from the host machine 3100, accesses OQ2729, IQ2730, and their queue indices OQPI and IQCI located in memory 2724 via a data transfer path 3301 through the CPU 2723.

[0331] Furthermore, the host I / F 2722 either stores data received from the host machine 3100 in the memory 2724 via the data transfer path 3301, or sends data stored in the memory 2724 to the host machine 3100.

[0332] Core 3300 accesses OQ2729, its queue index OQPI, and IQ2730 in memory 2724 via the inter-controller link 2711 and the data transfer path 3302 through CPU 2723.

[0333] Furthermore, Core 3300 accesses OQCI, the queue index for OQ2729, and IQPI, the queue index for IQ2730, located on the host I / F 2722, via a data transfer path 3303 that passes through the inter-controller link 2711 and CPU 2723. The data transfer path 3303 includes a P2P data transfer path in CPU 2723.

[0334] Furthermore, Core 3300 receives data from the host machine 3100 and stores it in memory 2724. Core 3300 then uses DMA 2707 to transfer this data from memory 2724 to memory 2704 of controller 2701 via a data transfer path 3304 that passes through CPU 2723, inter-controller link 2711, and CPU 2703. This allows the data received from the host machine 3100 to be duplicated in memory 2704 of controller 2701 and memory 2724 of controller 2721.

[0335] Figure 34 illustrates the data transfer sequence related to host I / O processing after host I / O handover in the storage system 2700.

[0336] Here, as an example, we describe the case where the host I / F 2722 and CPU 2703's core 3300 use OQ2729 and IQ2730 located in memory 2724. Note that in Figure 34, OQ2729 is displayed as "OQ11" and IQ2730 as "IQ11".

[0337] First, the host machine 3100 sends a host I / O command 3401 to the host interface 2722. Upon receiving the host I / O command 3401, the host interface 2722 enqueues an entry 3402 containing the command details to the OQ 2729 (step S3403).

[0338] Next, the host interface 2722 updates the OQPI of OQ2729 in memory 2724 to notify core 3300 that it has enqueued entry 3402 to OQ2729 (step S3404). Core 3300 checks for any unprocessed entries in OQ2729 by polling OQPI of OQ2729 (step S3405). If there are unprocessed entries, Core 3300 reads the entries containing the contents of the host I / O commands from OQ2729 (step S3406). Furthermore, Core 3300 updates OQCI of OQ2729 on host I / F2722 (step S3407).

[0339] Next, core 3300 enqueues an entry to IQ2730 containing a data transfer list corresponding to host I / O command 3401 (step S3408). Furthermore, core 3300 updates the IQPI of IQ2730 on host I / F2722 (step S3409). The updated IQPI host I / F2722 reads entries containing the data transfer list from IQ2730 (step S3410).

[0340] Next, the host interface 2722 performs data transfer between the host machine 3100 and memory 2724 according to the data transfer list contained in the entry read from IQ2730 (step S3411). Once the data transfer is complete, the host interface 2722 updates the IQCI of IQ2730 located in memory 2724 (step S3412).

[0341] In this way, core 3300 can process host I / O command 3401 received by host I / F 2722.

[0342] Figure 35 is a flowchart illustrating an example of the procedure for host I / O handover processing and controller power mode change processing between controllers in the storage system 2700. This processing flow is executed by CPU 2703 or CPU 2723 of the controller that receives a power mode change instruction to power saving mode C from the management terminal 2774. Hereafter, this processing flow will be referred to as the host I / O handover processing program 3500. As an example, we will describe the case where controller 2701 takes over host I / O processing from controller 2721, and the power mode of controller 2701 changes to power saving mode C1, and the power mode of controller 2721 changes to power saving mode C2.

[0343] First, the host I / O handover processing program 3500 stops the host I / F 2722 driver running on the CPU 2723 of the controller 2721 (step S3501). / F (Sometimes referred to as "Host IF") Stopping the driver means stopping processing for the host interface control queue. Therefore, even if the host interface driver is stopped, the host interface is not initialized, so host link down does not occur. Next, the host I / O handover processing program 3500 executes the host interface 2722 driver on the controller 2701's CPU 2703 (step S3502). The execution of the host interface driver here means stopping processing for the host interface control queue. Where This signifies the start of the process. Therefore, even if the host IF driver is executed, the host IF is not initialized, so host link down, etc., does not occur. The host I / F 2722 driver running on CPU 2703 can take over the host I / O processing of the host I / F 2722 driver that was running on CPU 2723 by checking the queue indices of OQ2729 and IQ2730. In other words, even if the entity operating the host IF control queue changes, the host IF can continue to operate. In addition, the CPU 2703 transitions the cores other than the N cores that are in the Active state to the Standby state with power gating applied. As a result, the power mode of the controller 2701 is changed to power saving mode C1.

[0344] Next, the host I / O handover processing program 3500 stops the backend processing running on the CPU 2723 of the controller 2721 (step S3503). 3100 Since the data received is duplicated in memory 2704 and memory 2724, even if the backend processing of CPU 2723 is stopped, the operation of storage system 2700 can continue as long as CPU 2703 is performing backend processing.

[0345] Next, the host I / O handover processing program 3500 reduces the operating frequency of the uncore 2726 of the CPU 2723 of the controller 2721 to a range where the impact on P2P data transfer and data duplication processing is below a predetermined standard (step S3504). As explained in Figure 33, the data duplication processing after host I / O handover uses the DMA 2707 of the CPU 2703. As a result, even if the operating frequency of the uncore 2726 is reduced, the data duplication processing can be executed without problems.

[0346] Cores of the CPU2723 that no longer perform host I / O processing, backend processing, or other processing transition to a Standby state with power gating applied. In this state, at least one core of the CPU2723 is executing the controller state monitoring process (Figures 36, 3600) described later.

[0347] As a result, the power mode of controller 2721 is changed to power-saving mode C2. When CPU 2723 stops performing backend processing, PCIe links 2751 and 2752 between CPU 2723 and PDEV BOX 2740 transition to the power-saving L1 state via ASPM. Furthermore, when CPU 2703 performs backend processing, only PCIe link 2731 between CPU 2703 and PDEV BOX 2740 is used, and PCIe link 2732 is not used. This causes PCIe link 2732 and the PCIe links between PDEV switch 2761 and PDEVs 2742 and 2762 (e.g., 2763 and 2764) to also transition to the power-saving L1 state. In particular, when the storage system 2700 is equipped with many PDEVs, the links connecting one of the PCIe ports of the many PDEVs with dual ports will transition to the power-saving state, resulting in a significant reduction in power consumption.

[0348] In addition to enabling ASPM, the power consumption of the PCIe link may be reduced by lowering the PCIe link speed. Alternatively, instead of enabling ASPM, the power consumption of the PCIe link may be reduced when the PCIe is idle. e The power consumption of the PCIe link may be reduced by lowering the link speed.

[0349] Figure 36 is a flowchart showing an example of the procedure for controller status monitoring in the storage system 2700. This processing flow is executed on CPU 2703 or CPU 2723 of the controller that has transitioned to power saving mode C2. Hereafter, this processing flow will be referred to as the controller status monitoring program 3600. As an example, we will describe the case in which the controller status monitoring program 3600 is executed on either core of CPU 2723 of controller 2721 that has transitioned to power saving mode C2.

[0350] First, the controller status monitoring program 3600 checks the operating status of the controller 2701. For example, the CPU 2723 checks the operating status of the controller 2701 by reading the operating information of the controller 2701 stored in memory 2704 and predetermined registers of the CPU 2703 via the inter-controller link 2711 (step S3601).

[0351] Next, the controller status monitoring program 3600 proceeds to step S3603 if the controller 2701 is functioning normally (step S3602: Yes). Otherwise, if an abnormality is detected in the controller 2701 (step S3602: No), it proceeds to step S3608.

[0352] Next, the controller status monitoring program 3600 checks the operating status of the devices within the controller 2721 (step S3603).

[0353] Next, the controller status monitoring program 3600 proceeds to step S3606 if the device is normal (step S3604: Yes). Otherwise, it proceeds to step S3605 if an abnormality is detected in the device (step S3604: No).

[0354] Next, the controller status monitoring program 3600, which has detected an abnormality in the device, blocks the device in question (step S3605).

[0355] Next, the controller state monitoring program 3600 transitions the core on which the controller state monitoring program 3600 is running to a Standby state with power gating or the like applied (step S3606).

[0356] Next, the controller status monitoring program 3600 waits for a predetermined time (step S3607). As a result, the core on which the controller status monitoring program 3600 is running remains in the Standby state for the predetermined time, thereby reducing the power consumption of the CPU 2723 while the controller status monitoring program 3600 is running.

[0357] After a predetermined time has elapsed, the controller status monitoring program 3600 transitions the core to the Active state. Then the controller status monitoring program 3600 returns to step S3601 and repeats the controller status monitoring flow.

[0358] In step S3602, the controller status monitoring program 3600 detects an abnormality in the controller 2701 and blocks the controller 2701 (step S3608).

[0359] Next, in order to resume host I / O processing and backend processing on controller 2721, the controller status monitoring program 3600 increases the operating frequency of the uncore 2726 of the CPU 2723 of controller 2721 (step S3609).

[0360] Next, the controller status monitoring program 3600 restarts the host I / F 2722 driver on the CPU 2723 of the controller 2721 (step S3610).

[0361] Next, the controller status monitoring program 3600 restarts backend processing on the CPU 2723 of the controller 2721 (step S3611).

[0362] In a controller 2721 set to power-saving mode C2, the controller status monitoring program 3600 is executed on at least one core of the CPU 2723, while the other cores are transitioned to a Standby state with power gating applied. This reduces the power consumption of the CPU 2723 while the controller status monitoring program 3600 is running.

[0363] Also, the host machine 3100 If the frequency of access to the storage system 2700 decreases and it is predicted that the future processing load on controllers 2701 and 2721 will decrease, the power consumption of the CPU 2723 at low processing loads may be reduced by applying clock gating to the uncore 2726 as well. Clock gating for the uncore 2726 becomes effective, for example, when all cores of the CPU 2723 transition to the Standby state and there is no access to memory 2724 via the uncore 2726. Therefore, by changing the setting of the polling interval from core 3300 to OQ2729 (Figure 34, S3405) to a longer setting, the likelihood of clock gating for the uncore 2726 becoming effective can be increased. In addition, in this embodiment, if the clock of the uncore 2726 is stopped due to clock gating, the memory connected to the uncore 2726 also enters a power-saving state (e.g., self-refresh mode), so the power consumption of the memory can also be reduced.

[0364] Figure 37 is a flowchart illustrating an example of the procedure for resuming host I / O processing on a controller that was set to power-saving mode C2 in the storage system 2700, and for changing the controller's power mode. This processing flow is executed by CPU 2703 or CPU 2723 of the controller that receives a power mode change instruction to normal mode from the management terminal 2774. Hereafter, this processing flow will be referred to as the host I / O resumption processing program 3700. As an example, we will describe the case where controller 2721 takes over host I / O processing from controller 2701, and the power mode of controller 2721 changes from power-saving state (power-saving mode) C2 to power-saving state (power-saving mode) C1.

[0365] First, the host I / O restart processing program 3700 increases the operating frequency of the uncore 2726 of the CPU 2723 of the controller 2721 (step S3701). Next, the host I / O restart processing program 3700 stops the host I / F 2722 driver running on the CPU 2703 of the controller 2701 (step S3702). Stopping the host IF driver here means stopping processing for the host IF control queue. Therefore, even if the host IF driver is stopped, the host IF is not initialized, and host link down or similar issues do not occur.

[0366] Next, the host I / O restart processing program 3700 restarts the host I / F 2722 driver on the CPU 2723 of the controller 2721 (step S3703). Restarting the host I / F driver here means restarting processing on the host I / F control queue. Therefore, restarting the host I / F driver does not initialize the host I / F, so host link down or similar issues do not occur. The host I / F 2722 driver running on CPU 2723 can take over the host I / O processing of the host I / F 2722 driver that was running on CPU 2703 by checking the queue indices of OQ2729 and IQ2730. In other words, even if the entity operating the host I / F control queue changes, the host I / F can continue to operate.

[0367] Next, the host I / O restart processing program 3700 restarts backend processing on the CPU 2723 of the controller 2721 (step S3704). On the CPU 2723, the cores that perform host I / O processing, backend processing, and other processing are set to the Active state, and the other cores are set to the Standby state.

[0368] As a result, host I / O processing is handed over from controller 2701 to controller 2721, and the power mode of controller 2721 is changed to power-saving state (power-saving mode) C1.

[0369] As explained above, in the third embodiment, the dual-controller storage system 2700 determines whether the future processing load can be handled by only one controller and whether power consumption can be reduced. If it is determined that this is possible, the storage system 2700 shifts the host I / O processing and backend processing of one controller to the other controller and lowers the uncore operating frequency of the CPU which is now under low load. This reduces the power consumption of the storage system 2700.

[0370] Furthermore, the storage system 2700 allows one controller's CPU to access the other controller's host interface via the inter-controller link and the CPU's P2P data transfer path, thereby taking over host I / O processing between the controllers. This maintains the availability of the dual controllers during power-saving mode operation. In addition, even when one controller's CPU is in a power-saving state, the other controller's CPU uses DMA to duplicate data received from the host machine between the dual controllers' memories. This maintains the redundancy of the dual controllers during power-saving mode operation.

[0371] As described above, in this embodiment, the controller power mode determination program 2800, as an example of a power mode control unit, sets the power mode of components with a high predicted processing load to a power-saving mode C1, which is an example of a predetermined second power mode (for example, setting N cores of the controller's cores to the Active state and the remaining cores to the Standby state), and the power mode of components with a low predicted processing load to a power-saving mode C2, which is an example of a specific second power mode (for example, lowering the operating frequency of the CPU's uncores compared to the normal mode, which is the first power mode of the controller), and compares this with the power consumption of components with a power mode determined for each component in a second case (B) (corresponding to the first and second embodiments described above). If the power consumption in the second case (B) is greater than the power consumption in the first case (A), the power mode of components with a high predicted processing load is set to a predetermined second power mode (for example, power-saving mode C1), and the power mode of components with a low predicted processing load is set to a specific second power mode (for example, power-saving mode C2). On the other hand, if the above condition is not met, for example, power mode control is performed as in the first and second embodiments described above. In this way, multiple portion Because power consumption can be controlled for each element, further energy savings can be achieved.

[0372] The aforementioned multiple components are, for example, multiple sub-elements (cores, uncores) of each processor in multiple controllers (e.g., CPU2703 of "CPU0", CPU2723 of "CPU1"). When one processor of one controller 2721 (CPU2723 of "CPU1") is operating, the control of a core, as an example of a sub-element of that processor, is switched to the other processor of the other controller (CPU2703 of "CPU0"). The power mode of that processor is set to a power-saving mode C2, which is a specific second power mode, and the power mode of the other processor is set to a predetermined second power mode C, which consumes more power than the specific second power mode (e.g., power-saving mode C2). 1Configure the settings. This allows for more granular control over the power consumption of each sub-element (core, uncore), thus enabling further power savings.

[0373] The controller power mode determination program 2800 (power mode control unit) switches the other processor to control data input / output requests from the host using one of the uncores, which is an example of a sub-component of the one controller. The memory of the one controller (e.g., "memory 2724") includes control queues (IQ11 (2730), OQ11 (2729) described later), and the other processor accesses these control queues using the uncore, which is a sub-component of the one controller, to control data input / output requests from the host. In this way, power consumption can be controlled in fine detail, thus further reducing power consumption.

[0374] (4) Fourth Embodiment Referring to Figures 38 and 39, the storage system according to the fourth embodiment will be described. The configuration of the storage system according to the fourth embodiment is the same as that of the storage system according to the third embodiment shown in Figures 27 to 37, except for the differences described below, so the description of the similar parts will be omitted. Note that the storage system according to the fourth embodiment may have different reference numerals for each component such as the CPU and controller compared to the storage system according to the third embodiment, but unless otherwise specifically mentioned in the following description, it has the same configuration and functions as the storage system according to the third embodiment.

[0375] Figure 38 is a system configuration diagram showing an example of the configuration of a storage system according to the fourth embodiment. As described above, the storage system according to the fourth embodiment basically has the same configuration and functions as the storage system according to the third embodiment.

[0376] In the storage system according to the fourth embodiment, as shown in Figures 38 and 39, instead of the core 3300 polling the OQPI of the OQ2729, the host I / F 2722 notifies the core 3300 by sending an interrupt when the host I / F 2722 has enqueued an entry related to a new host I / O to the OQ2729.

[0377] In other words, the controller power mode determination program 2800, as an example of a power mode control unit, instead of polling as described later, has the host I / F 2722 send a predetermined interrupt to the other processor (CPU 2703 of "CPU0") via the other processor (CPU 2723 of "CPU1"), thereby causing the other processor to access the uncore 2726, which is an example of a sub-element that constitutes part of the one processor (CPU 2723 of "CPU1") after the clock has restarted. The processing by the controller power mode determination program 2800 will be described in detail below.

[0378] Figure 38 illustrates the data transfer path for host I / O processing after host I / O handover when interrupts are used instead of polling. Figure 38 is the same as Figure 33 except for the differences described below, so only the differences will be explained.

[0379] The host interface 2722 sends an interrupt to the core 3300 via a data transfer path 4201 that passes through the CPU 2723 and the controller link 2711. The data transfer path 4201 includes a P2P data transfer path in the CPU 2723.

[0380] Furthermore, Core 3300 accesses OQ2729 in memory 2724, its queue index OQPI, and IQ2730 via the inter-controller link 2711 and the data transfer path 4202 through CPU 2723. However, in Figure 38, Core 3300 does not poll OQPI.

[0381] Figure 39 illustrates the data transfer sequence for host I / O processing after host I / O handover when interrupts are used instead of polling. Figure 39 is the same as Figure 34 except for the differences described below, so only the differences will be explained.

[0382] In step S3405 of Figure 34, core 3300 checked for any unprocessed entries in OQ2729 by polling the OQPI of OQ2729. In Figure 39, host I / F 2722 enqueues entry 3402 to OQ2729 (step S3403), updates the OQPI of OQ2729 in memory 2724 (step S3404), and then hosts I / F 2722 sends interrupt 4301 to core 3300.

[0383] Upon receiving interrupt 4301, core 3300 reads the OQPI of OQ2729 (step S4302). After reading the OQPI, core 3300 determines whether there are any unprocessed entries in OQ2729, and if so, reads the entry containing the contents of the host I / O command from OQ2729 (step S3406).

[0384] Thus, the polling process for OQPI of OQ2729 by Core 3000, which was performed before the host I / O handover from Core 3000 to Core 3300, is changed to an interrupt process from Host I / F 2722 to Core 3300 after the host I / O handover. As a result, the frequency of access from Core 3300 to Uncore 2726 is reduced, so the clock gating of Uncore 2726 works effectively, and the power consumption of CPU 2723 can be reduced. In addition, in this embodiment, the power consumption of memory 2724 can also be reduced during the clock stop period of Uncore 2726.

[0385] Furthermore, if the clock of the uncore 2726 is stopped, and the core 3300 attempts to access OQ2729, IQ2730, etc., it will need to restart the clock of the uncore 2726, which could lead to a longer access time. Therefore, in this embodiment, as described above, the host I / F 2722 sends an interrupt via the CPU 2723 prior to accessing OQ2729, IQ2730, etc., causing the core 3300 to access the uncore 2726 after its clock has restarted. As a result, when the core 3300 accesses OQ2729, IQ2730, etc., the clock of the uncore 2726 has restarted, thus suppressing the increase in access time.

[0386] As described above, in this embodiment, the controller power mode determination program 2800, as an example of a power mode control unit, instead of the core 3300 polling the OQPI of the OQ2729, has the host I / F 2722 send a predetermined interrupt to the other processor (e.g., the CPU 2703 of "CPU0") via the other processor (e.g., the CPU 2723 of "CPU1"), thereby causing the other processor (e.g., the CPU 2703 of "CPU0") to access the uncore 2726, which is an example of a sub-element that constitutes a part of the other processor (e.g., the CPU 2723 of "CPU1") after the clock has restarted. In this way, as described above, when the core 3300 accesses the OQ2729 or IQ2730, the clock of the uncore 2726 has restarted, so the increase in access time can be suppressed.

[0387] (5) Fifth embodiment Referring to Figures 40 to 43, the storage system according to the fifth embodiment will be described. The configuration of the storage system according to the fifth embodiment is the same as that of the third embodiment shown in Figures 27 to 37 and the storage system according to the fourth embodiment shown in Figures 38 and 39, except for the differences described below, so the description of the similar parts will be omitted. Note that the reference numerals assigned to each component such as the CPU and controller may differ between the storage system according to the fifth embodiment and the storage systems according to the third and fourth embodiments, but unless otherwise specifically mentioned in the following description, it has the same configuration and functions as the storage systems according to the third and fourth embodiments.

[0388] Figure 40 illustrates the data transfer path related to host I / O processing after host I / O handover in the storage system 3800. Here, similar to the storage system 2700 in the third embodiment, it is assumed that the host I / O received by the host I / F 3822 is handed over from controller 3821 to controller 3801.

[0389] Storage system 3800 has the same configuration as storage system 2700, except for controllers 3801 and 3821. Controllers 3801 and 3821 have the same configuration as controllers 2701 and 2721, except for host interfaces 3802 and 3822.

[0390] The host interfaces 3802 and 3822 have functions that are almost the same as the host interfaces 2702 and 2722 in the embodiments described above, respectively. However, they differ from the host interfaces 2702 and 2722 in the embodiments described above in that, for example, each core of the CPU 3703 and 2723 that controls the host interfaces 3802 and 3822 ("Core00" 3300, "[Core11] 3000") can be assigned a different pair of OQ and IQ (a pair of "OQ02" 3809 and "IQ02" 3810, or a pair of "OQ11" 3829 and "1Q11" 3830).

[0391] For example, when core 3000 of CPU 2723 controls host I / F 3822, it uses the pair OQ3829 and IQ3830 located in memory 2724. Conversely, when core 3300 of CPU 2703 controls host I / F 3822, it uses the pair OQ3809 and IQ3810 located in memory 2704. In this embodiment, instructions from CPU 2703 or CPU 2723 to host I / F 3822 determine which OQ and IQ pair to access.

[0392] As an example, we will describe the data transfer path when the core 3300 of the CPU 2703 belonging to controller 3801 controls the host I / F 3822 of controller 3821.

[0393] The host interface 3822, which receives host I / O from the host machine 3100, accesses the pair of OQ3809 and IQ3810 in memory 2704, and their queue indices, OQPI and IQCI, via a data transfer path 3811 that passes through CPU 2723, inter-controller link 2711, and CPU 2703. The data transfer path 3811 includes a P2P data transfer path in CPU 2723.

[0394] Furthermore, the host interface 3822 either stores data received from the host machine 3100 in memory 2724 via the data transfer path 3812, or sends data stored in memory 2724 to the host machine 3100.

[0395] Core 3300 accesses OQ3809, its queue index OQPI, and IQ3810 located in memory 2704 via data transfer path 3813.

[0396] Furthermore, Core 3300 accesses OQCI, the queue index for OQ3809, and IQPI, the queue index for IQ3810, located on the host I / F 3822, via a data transfer path 3814 that passes through the inter-controller link 2711 and CPU 2723. The data transfer path 3814 includes a P2P data transfer path on CPU 2723.

[0397] Furthermore, the core 3300 receives data from the host machine 3100 and stores it in memory 2724, and then uses DMA 2707 to transfer it from memory 2724 to the controller via a data transfer path 3815 that passes through CPU 2723, inter-controller link 2711, and CPU 2703. 3801 The data is transferred to memory 2704. This allows the controller to receive the data from the host machine 3100. 38 The memory can be duplicated using memory 2704 in unit 21 and memory 2724 in controller 2721.

[0398] The data transfer path when the core 3000 of the CPU 2723 belonging to the controller 3821 controls the host I / F 3822 of the controller 3821 is the same as that described in Figure 30 above, so the explanation will be omitted.

[0399] Figure 41 illustrates the data transfer sequence related to host I / O processing after host I / O handover in the storage system 3800. Here, as an example, we describe the case where the host interface 3822 and the CPU 2703 core 3300 use OQ3809 and IQ3810 located in memory 2704. In Figure 41, OQ3809 is denoted as "OQ02" and IQ3810 as "IQ02".

[0400] First, the host machine 3100 sends a host I / O command 3901 to the host interface 3822. Upon receiving the host I / O command 3901, the host interface 3822 enqueues an entry 3902 containing the command details to the OQ 3809 (step S3903).

[0401] Next, the host interface 3822 updates the OQPI of the OQ3809 in memory 2704 to notify the core 3300 that it has enqueued entry 3902 to the OQ3809 (step S3904). The core 3300 checks for any unprocessed entries in the OQ3809 by polling the OQPI of the OQ3809 (step S3905). If there are unprocessed entries, the core 3300 reads the entry containing the contents of the host I / O command from the OQ3809 (step S3906). Furthermore, the core 3300 updates the OQCI of the OQ3809 in the host interface 3822 (step S3907).

[0402] Next, core 3300 enqueues an entry to IQ3810 containing a data transfer list corresponding to host I / O command 3901 (step S3908). Furthermore, core 3300 updates the IQPI of IQ3810 on host I / F 3822 (step S3909).

[0403] The host interface 3822, whose IQPI has been updated, reads an entry containing the data transfer list from the IQ3810 (step S3910). Subsequently, the host interface 3822 performs a data transfer between the host machine 3100 and memory 2724 according to the data transfer list contained in the entry read from the IQ3810 (step S3911). Once the data transfer is complete, the host interface 3822 updates the IQCI of the IQ3810 in memory 2704 (step S3912).

[0404] In this way, the CPU2703's core 3300 can process the host I / O command 3901 received by the host I / F 3822.

[0405] Figure 42 is a flowchart illustrating an example of the procedure for host I / O handover processing and controller power mode change processing between controllers in the storage system 3800. This processing flow is executed by CPU 2703 or CPU 2723 of the controller that receives a power mode change instruction to power saving mode C from the management terminal. Hereafter, this processing flow will be referred to as the host I / O handover processing program 4000. As an example, we will describe the case where controller 3801 takes over host I / O processing from controller 3821, and the power mode of controller 3801 changes to power saving mode C1, and the power mode of controller 3821 changes to power saving mode C2.

[0406] First, the host I / O handover processing program 4000 executes the host I / F 3822 driver on the controller 3801's CPU 2703 (step S4001). At this time, OQ3809 and IQ3810 are empty, and host I / O processing using them has not yet been performed. Executing the host IF driver here means starting processing on the host IF control queue. Therefore, executing the host IF driver does not initialize the host IF, and thus host link down issues do not occur.

[0407] Next, the host I / O handover processing program 4000 instructs the host I / F 3822 to switch queues (step S4002). Before receiving the queue switching instruction, the host I / F 3822 is the host machine 3100Host I / O commands received from IQ3829 are enqueued to OQ3829 along with the corresponding entries. After receiving a queue switch instruction, Host I / F3822 enqueues entries related to newly received host I / O commands with new exchange IDs to OQ3809. As long as there are incomplete entries remaining in OQ3829, host I / O processing related to OQ3829 and IQ3830, and host I / O processing related to OQ3809 and IQ3810 are executed in parallel. After the queue switch instruction, no new entries are enqueued to OQ3829, so eventually there will be no incomplete entries left in OQ3829 and IQ3830.

[0408] Next, the host I / O handover processing program 4000 waits for OQ3829 and IQ3830 to become empty (step S4003: No). If OQ3829 and IQ3830 become empty (step S4003: Yes), the host I / O handover processing program 4000 proceeds to step S4004.

[0409] Next, the host I / O handover processing program 4000 stops the host I / F 3822 driver running on the controller 3821's CPU 2723 (step S4004). Stopping the host IF driver here means stopping processing on the host IF control queue. Therefore, stopping the host IF driver does not initialize the host IF, and thus host link down or similar issues do not occur.

[0410] Next, the host I / O handover processing program 4000 stops the backend processing running on the CPU 2723 of the controller 3821 (step S4005). 3100 Since the data received is duplicated in memory 2704 and 2724, even if the backend processing of CPU 2723 is stopped, the storage system 3800 can continue to operate as long as CPU 2703 is performing backend processing.

[0411] Next, the host I / O handover processing program 4000 reduces the operating frequency of the uncore 2726 of the CPU 2723 of the controller 3821 to a range where the impact on P2P data transfer and data duplication processing is below a predetermined standard (step S4006). As explained in Figure 40, the data duplication processing after host I / O handover uses the DMA 2707 of the CPU 2703. As a result, even if the operating frequency of the uncore 2726 is reduced, the data duplication processing can be executed without problems.

[0412] Figure 43 is a flowchart illustrating an example of the procedure for resuming host I / O processing on a controller that was set to power-saving mode C2 in the storage system 3800, and for changing the controller's power mode. This processing flow is executed by CPU 2703 or CPU 2723 of the controller that receives a power mode change instruction to normal mode from the management terminal. The host I / O restart processing program 4100 then executes this processing flow. As an example, we will describe the case where controller 3821 takes over host I / O processing from controller 3801, and the power mode of controller 3821 changes from power-saving mode C2 to power-saving mode C1.

[0413] First, the host I / O restart processing program 4100 increases the operating frequency of the uncore 2726 of the CPU 2723 of the controller 3821 (step S4101).

[0414] Next, the host I / O restart processing program 4100 restarts the host I / F 3822 driver on the controller 3821's CPU 2723 (step S4102). At this time, OQ3829 and IQ3830 are empty, and host I / O processing using them has not yet been performed. Restarting the host IF driver here means restarting processing on the host IF control queue. Therefore, restarting the host IF driver does not initialize the host IF, so host link down and other issues do not occur.

[0415] Next, the host I / O restart processing program 4100 restarts backend processing on the CPU 2723 of the controller 3821 (step S4003). In the CPU 2723, the cores that perform host I / O processing, backend processing, and other processing are set to the Active state, and the other cores are set to the Standby state.

[0416] Next, the host I / O restart processing program 4100 instructs the host I / F 3822 to switch queues (step S4104). Before receiving the queue switching instruction, the host I / F 3822 is the host machine 3100 Host I / O commands received from IQ3810 are enqueued to OQ3809 along with the entries associated with them. After receiving a queue switch instruction, Host I / F3822 enqueues entries associated with newly received host I / O commands with new exchange IDs to OQ3829. As long as there are incomplete entries remaining in OQ3809, host I / O processing related to OQ3809 and IQ3810, and host I / O processing related to OQ3829 and IQ3830 are executed in parallel. After the queue switch instruction, no new entries are enqueued to OQ3809, so eventually there will be no incomplete entries left in OQ3809 and IQ3810.

[0417] Next, the host I / O restart processing program 4100 waits for OQ3809 and IQ3810 to become empty (step S4105: No). If OQ3809 and IQ3810 become empty (step S4105: Yes), the host I / O restart processing program 4100 proceeds to step S4106.

[0418] Next, the host I / O restart processing program 4100 stops the host I / F 3822 driver running on the controller 3801's CPU 2703 (step S4106). Stopping the host IF driver here means stopping processing on the host IF control queue. Therefore, stopping the host IF driver does not initialize the host IF, and thus host link down or similar issues do not occur.

[0419] Therefore, the controller 3801 From the controller 38 The host I / O processing is handed over to 21, and the power mode of controller 2721 is changed to power-saving state (power-saving mode) C1.

[0420] Furthermore, the power control of the CPU cores described above can be achieved by utilizing software functions, such as those provided by the controller's operating system or the CPU's BIOS, to control the relevant elements and circuits within the CPU. Other devices may also benefit from using firmware and drivers specific to each device.

[0421] It should be noted that the present invention is not limited to the embodiments described above, and includes various modifications and equivalent configurations within the spirit of the attached claims. For example, the embodiments described above are described in detail to make the present invention easier to understand, and the present invention is not necessarily limited to having all the configurations described. For example, "power mode control unit" can be read as a power mode control circuit or a power mode control function. Therefore, the functional units and means included in the embodiments described above in the present invention may be realized as dedicated devices using hardware resources, as electronic circuits on a circuit board, as functions of software or programs, or as a combination of these means. In addition, each element described in parallel in this embodiment may be configured such that at least one of each element is connected in series with respect to the other elements. [Industrial applicability]

[0422] The present invention can be applied to a storage system relating to a technology for suppressing power consumption according to the power mode of each device mounted on at least one controller. [Explanation of symbols]

[0423] 102...Storage system, 103...Host machine, 301...Power consumption control program, 302...Device operating status monitoring program, 303...Power mode determination program, 304...Power mode change program, 305...Power mode control unit, 1701...Controller management program, 1702...Controller power consumption control program, 1703...Controller operating status monitoring program, 1704...Controller power mode determination program, 2700...Storage system, 2701, 2721...Controller, 3800...Storage system, 3801, 3821...Controller

Claims

1. A storage system having a storage device that stores data or outputs the stored data in response to data input / output requests from a host, Multiple components that can be switched between a first power mode and at least one second power mode with lower power consumption than the first power mode, and each can operate accordingly. A status monitoring unit that monitors the operating status of each of the aforementioned multiple components, A power mode control unit determines the power mode of at least one specific component to be the second power mode based on the processing load for each of the plurality of components, which is the result of monitoring by the state monitoring unit, and operates the at least one specific component in the second power mode. Equipped with, The aforementioned plurality of components perform control with the storage device in response to the data input / output request, Furthermore, the aforementioned plurality of components are a plurality of devices that control data input / output processing between the host and the host. The storage system includes the plurality of devices and at least one controller that controls the input / output processing of data between the plurality of devices and the host, The controller comprises the state monitoring unit and the power mode control unit, The power mode control unit is A power mode determination unit determines that the power mode of a specific device operating in the first power mode among the plurality of devices is set to the second power mode based on the magnitude of the impact on the data input / output processing when the power mode of that specific device is changed to the second power mode, A power mode changing unit that switches the power mode of the specific device to the determined second power mode, Equipped with, The aforementioned controller, A device management table that manages information about the aforementioned multiple devices, The system includes a device operation history table that manages the operating status of the plurality of devices monitored by the status monitoring unit, The power mode determination unit is With respect to the multiple devices managed in the device management table, if it is determined that changing the power mode of a particular device to the second power mode would have less than or equal to a predetermined standard impact on the data input / output processing, based on the operating status of the multiple devices managed in the device operation history table, then the power mode of the particular device is set to the second power mode. A storage system characterized by the following features.

2. The aforementioned device management table is: For each of the aforementioned multiple devices, the power consumption and processing capacity for each of the first power mode and the second power mode are managed. The power mode control unit is Based on the power consumption and processing capacity for each of the multiple devices managed in the device management table, the second power mode is determined for the power mode of a particular device, and the power mode of that particular device is changed to the second power mode. The storage system according to feature 1.

3. The aforementioned device management table is: The power mode control for the aforementioned multiple devices is managed by a first category in which the control is performed independently of other devices, a second category in which the control is performed in combination with other devices, and a defined power control unit. The storage system according to feature 1.

4. The device management table, as the power control unit, A device unit that includes devices that are independent from other devices in terms of power consumption, A connected device unit including a device whose power mode should be changed to match the other devices, A controller unit includes a group of controllers that should exhibit nearly the same performance for each of the aforementioned controllers, The storage system according to claim 3, characterized in that it manages the storage system.

5. The power mode control unit is The aforementioned multiple devices are classified into two categories: devices that are grouped together with low mutual independence from the standpoint of controlling power consumption with respect to the aforementioned multiple devices, and devices that are not grouped together with high mutual independence from the standpoint of controlling power consumption with respect to the aforementioned multiple devices. For each of the grouped devices and the non-grouped devices, the power mode is switched to the second power mode according to the results of monitoring by the status monitoring unit. The storage system according to claim 2, characterized by the features described above.

6. The power mode control unit is When there are multiple devices that can be grouped, they are classified into a first group of devices in which the power mode change patterns should be standardized, and a second group of devices in which the power mode change patterns do not need to be standardized. For the first group of devices, change the power mode to match the power mode of the target device. The storage system according to claim 5, characterized by the features described above.

7. The power mode control unit is Devices are classified into those that allow power off as the second power mode and those that do not allow power off as the second power mode. For devices that allow power off as the second power mode, the power mode is switched to power off according to the results of monitoring by the status monitoring unit, while for devices that do not allow power off as the second power mode, the power mode is switched to the second power mode according to the results of monitoring by the status monitoring unit. The storage system according to claim 5, characterized by the features described above.

8. The power mode control unit is If the predicted future processing load for multiple of the aforementioned specific devices is zero and it is permissible to turn off the power, and it is necessary to unify the power mode of the multiple aforementioned specific devices, then it is decided to unify the power mode of the multiple aforementioned specific devices to power off. The storage system according to feature 1.

9. The aforementioned multiple devices are These are multiple controllers that control the input and output processing of data between the host and the system. The system includes a management terminal that controls the aforementioned multiple controllers, The aforementioned management terminal is The aforementioned status monitoring unit, The power mode control unit, The storage system according to claim 1, characterized by comprising:

10. The power mode control unit is Based on the redundancy setting, in response to the detection of a failure in any of the multiple controllers, a power mode is selected that allows the other controllers to immediately transition to a state where input / output processing can be performed. The storage system according to feature 9.

11. The power mode control unit is The aforementioned other controller is made capable of transitioning to a state where it can perform input / output processing immediately afterward, while operating some of the cores of the CPU (Central Processing Unit) cores, which has multiple cores, and keeping the other cores on standby. The storage system according to claim 10.

12. The power mode control unit is In the first case, the power mode of a device with a high predicted processing load is set to a predetermined second power mode, and the power mode of a device with a low predicted processing load is set to a specific second power mode. The power consumption in this first case is compared with the power consumption in the second case, where the power mode is determined for each device. If the power consumption in the second case is greater than the power consumption in the first case, the power mode of a device with a high predicted processing load is set to a predetermined second power mode, and the power mode of a device with a low predicted processing load is set to a specific second power mode. The storage system according to feature 1.

13. The aforementioned multiple devices are Multiple components of each processor in multiple controllers, While one processor of one controller is operating, control of a portion of that processor's elements is switched to the other processor of the other controller, setting the power mode of the first processor to a specific second power mode, and setting the power mode of the other processor to a predetermined second power mode that consumes more power than the specific second power mode. The storage system according to feature 12.

14. The power mode control unit is The other processor switches to control data input / output requests from the host using a subset of the first controller. The storage system according to claim 13, characterized by the features described above.

15. The aforementioned storage device is Includes control queues, The other processor accesses the control queue when using a sub-element of the first controller to control data input / output requests from the host. The storage system according to feature 14.

16. The power mode control unit is By sending a predetermined interrupt via the first processor, the second processor is made to access a subset element that constitutes a part of the first processor after the clock has resumed. The storage system according to claim 13, characterized by the features described above.

17. A method for reducing power consumption of a storage system having a storage device that stores data or outputs the stored data in response to a data input / output request from a host, A status monitoring step involves a status monitoring unit monitoring the operating status of each of a plurality of devices that control data input / output processing with a host, each of which can be switched between a first power mode and at least one second power mode that consumes less power than the first power mode, and each can operate accordingly. A power mode control step in which the power mode control unit determines the power mode of at least one specific device to the second power mode based on the processing load for each of the plurality of devices as a result of monitoring by the state monitoring step, and operates the at least one specific device in the second power mode, Includes, The power mode control step is, A power mode determination step in which, based on the magnitude of the impact on the data input / output processing when the power mode of a specific device among the plurality of devices that is operating in the first power mode is changed to the second power mode, the power mode of the specific device is determined to be the second power mode; A power mode change step of switching the power mode of the specific device to the determined second power mode, Includes, The power mode determination step includes determining, based on a device management table that manages information about a plurality of devices and a device operation history table that manages the operating status of the plurality of devices monitored by the status monitoring step, that changing the power mode of a particular device to the second power mode will have less than or equal to a predetermined standard impact on the data input / output processing, and that the plurality of devices perform control with the storage device in response to the data input / output requests. A method for reducing power consumption of a storage system, characterized by the following features.

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