Capacitor networks for harmonic control in power devices

Abstract

To provide novel types, structures, and arrangments of capacitor networks for harmonic control and the other purpose.SOLUTION: An integrated device includes: a capacitor network; and one or more power devices. The capacitor network includes: a bond pad; and metal-insulation-metal (MIM) capacitors. The capacitor includes: a first metal layer; a second metal layer; an insulation layer between the first and second metal layers; and one or more substrate penetration vias. The first metal layer is connected to the bond pad, and the second metal layer is connected to a ground plane on a bottom side of a substrate by the vias. A plurality of capacitors for an adaptive electrostatic capacity can be arranged around the bond pad in the capacitor network. A matching network in the integrated device can incorporate the capacitor network to reduce a loss, provides better harmonic termination, and achieve better phase alignment of the power devices.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] High-speed power amplifiers made from semiconductor materials have a variety of useful applications, including radio frequency (RF) communications, radar, RF energy, power conversion, and microwave applications. When supporting mobile communications based on current and proposed communication standards such as WiMAX, 4G, and 5G, high performance requirements may be imposed on high-speed amplifiers composed of semiconductor transistors. Amplifiers may need to meet performance specifications, particularly those related to output power, signal linearity, signal gain, bandwidth, and efficiency.

[0002] Efficient, high-speed, broadband, and high-power amplifiers can be constructed from multiple transistors operating in a parallel circuit path, and can, though not limited to, semiconductor materials such as gallium nitride (GaN). In recent years, GaN materials have attracted considerable attention due to their desirable electronic and electro-optical properties. Due to their wide bandgap, GaN materials are useful for high-speed, high-voltage, and high-power applications. [Overview of the project] [Means for solving the problem]

[0003] The structure and configuration of capacitor networks for harmonic control and other purposes are presented. In one example, a capacitor network formed on a substrate includes a bond pad, a metal-insulator-metal (MIM) capacitor, and through-substate vias. The MIM capacitor includes a first metal layer, a second metal layer, and an insulating layer between the first and second metal layers. The first metal layer is electrically coupled to the bond pad, and the second metal layer is electrically coupled to the ground plane at the bottom of the substrate by through-substate vias. In another example, the capacitor network includes multiple through-substate vias, and the second metal layer of the MIM capacitor is electrically coupled to the ground plane by through-substate vias.

[0004] In other examples, the capacitor network includes multiple MIM capacitors electrically coupled to bond pads, each of which is electrically coupled to ground via multiple through-vias. In one example, multiple MIM capacitors can be arranged along one side of the bond pad. In other examples, MIM capacitors can be arranged along two or more sides of the bond pad. In yet another example, the capacitor network includes multiple bond pads and multiple MIM capacitors electrically coupled to each bond pad. Each of the MIM capacitors can be electrically coupled to ground via multiple through-vias.

[0005] In another embodiment, the integrated device includes a power transistor formed on a first substrate and a capacitor network formed on a second substrate. The first and second substrates can together be arranged within a single device package of the integrated device. The capacitor network includes a bond pad, a metal-insulator-metal (MIM) capacitor, and through-substrate vias. The MIM capacitor includes a first metal layer, a second metal layer, and an insulating layer between the first and second metal layers. The first metal layer is electrically coupled to the bond pad, and the second metal layer is electrically coupled to the ground surface on the bottom side of the substrate by through-substrate vias.

[0006] In other examples, the integrated device may include a second capacitor network formed on a third substrate. The first, second, and third substrates can all be located within a single device package of the integrated device. The integrated device may include at least one bond wire electrically coupled between the power transistor and the capacitor network. The integrated device may also include at least one other bond wire electrically coupled between the power transistor and the second capacitor network. In one embodiment of the design, the capacitor network may be embodied as a MIM capacitor network, and the second capacitor network may be embodied as a metal-oxide-semiconductor (MOS) capacitor network.

[0007] Aspects of this disclosure can be better understood by referring to the following drawings. Note that the elements in the drawings are not necessarily to scale, and the focus is rather on clearly illustrating the principles of the embodiments. Throughout the drawings, similar but not identical, or corresponding elements are indicated by the same reference numerals across multiple views. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows examples of amplifiers according to various embodiments described herein. [Figure 2] This figure shows examples of package layouts for amplifier components according to various embodiments described herein. [Figure 3] This figure shows examples of capacitor networks according to various embodiments described herein. [Figure 4A] This figure shows examples of capacitor configurations used in the capacitor network shown in Figure 3, according to various embodiments described herein. [Figure 4B] This figure shows a cross-sectional view AA, identified in Figure 4A, according to various embodiments described herein. [Figure 5]This figure shows another example of a capacitor network according to various embodiments described herein. [Figure 6] This figure shows an example package layout for an amplifier including a capacitor network, based on the concepts described herein. [Modes for carrying out the invention]

[0009] For example, applications supporting mobile communications and wireless internet access may impose high performance requirements on high-speed RF amplifiers composed of semiconductor transistors. Amplifiers may need to meet performance specifications, particularly those related to output power, signal linearity, signal gain, bandwidth, and efficiency. Multiple transistors can be used in the various stages of an amplifier. Individual transistors within a single amplifier may have many different characteristics compared to one another, as the requirements of each design stage may differ.

[0010] While many different amplifier topologies are known, one method for amplifying signals for communication is to use a Doherty amplifier. A standard Doherty power amplifier utilizes two transistors: a main or carrier transistor and an auxiliary or peaking transistor. Typically, the main transistor is designed to operate linearly and efficiently over a wide input power range and consume a relatively large amount of power. The auxiliary transistor is designed to operate at a relatively high input power and consume a relatively small amount of power.

[0011] Among the many advantages of the embodiments described herein, the aspects of the embodiments can be used for better second-harmonic termination using an input network at the input of a power transistor in a power amplifier. These embodiments can increase the peak drain efficiency and peak output power of the transistor and associated integrated devices in the power amplifier. Accordingly, novel types, structures, and configurations of capacitor networks for harmonic control and other purposes in power amplifiers are described.

[0012] In one example, an integrated device includes a capacitor network and one or more power devices. The capacitor network includes a bond pad and one or more metal-insulator-metal (MIM) capacitors. Each capacitor includes a first metal layer, a second metal layer, an insulating layer between the first and second metal layers, and one or more through-vias. The first metal layer is bonded to the bond pad, and the second metal layer is bonded to the ground surface on the bottom side of the substrate by vias. Multiple capacitors can be arranged around the bond pad in the capacitor network for matched capacitance with a relatively high quality ("Q") coefficient. A matching network within the integrated device can incorporate the capacitor network to reduce losses, provide better harmonic processing, and achieve better phase alignment of the power devices.

[0013] Referring to the drawings, Figure 1 shows an example amplifier 10 according to various embodiments described herein. Amplifier 10 includes a Doherty amplifier as described later. Amplifier 10 is provided as a representative example of one type of integrated circuit that can benefit from the use of the capacitor network and harmonic control concepts described herein. Other types of amplifiers and other integrated circuits may also rely on and incorporate these concepts, and the concepts are not limited to use with any particular type of amplifier, integrated circuit, or integrated device package.

[0014] Amplifier 10 includes a 90-degree power splitter 11 that splits the received RF input signal into two outputs, which are coupled to a main amplifier 16 and an auxiliary or peaking amplifier 20, respectively, located on a parallel circuit branch. The power splitter 11 also delays the phase of the signal supplied to the peaking amplifier 20 relative to the phase of the signal supplied to the main amplifier 13 (for example, by about 90 degrees).

[0015] Amplifier 10 also includes impedance matching components 12 and 14 respectively connected in front of main amplifier 16 and peaking amplifier 20. The impedance matching components match the output impedance of power splitter 11 to the input impedances of main amplifier 16 and peaking amplifier 20, reducing signal reflection and other undesirable effects.

[0016] Further impedance matching components 22 and 24 that match the impedance among main amplifier 16, peaking amplifier 20, and coupling node 27 are connected to the outputs of main amplifier 16 and peaking amplifier 20. Impedance inverter 26 rotates the phase of the signal output from main amplifier 16 so that the signals from main amplifier 16 and peaking amplifier 20 are substantially in phase at coupling node 27. As shown in FIG. 1, an output impedance matching component 28 that matches the output impedance of amplifier 10 to the impedance of a load (not shown) can also be connected between coupling node 27 and the output of amplifier 10.

[0017] Normally, peaking amplifier 20 is designed to be off at low power levels that main amplifier 16 can handle alone. At high power levels, there is a risk that the linearity of amplifier 10 will be lost because main amplifier 16 saturates and the gain of main amplifier 16 is compressed. The compression point of main amplifier 16 can vary depending on its design. When peaking amplifier 20 is turned on, it not only effectively adds a load impedance to main amplifier 16 (reducing the gain of main amplifier 16), but also helps to extend the linearity of amplification to high power levels.

[0018] There are many different concerns in the design of amplifier 10. Amplifier 10 should be designed, among other design considerations, for low loss, phase alignment, and harmonic processing and control. Impedance matching components 12 and 14 can be adapted to improve these operating modes of amplifier 10 according to this embodiment. Impedance matching components 12 and 14 can include capacitors and capacitor networks of new types, structures, and configurations. The improvements to the capacitors and capacitor networks described herein can be used, among other advantages, for better second harmonic processing using an input network at the input of a power transistor. These improvements can also be extended for better first harmonic processing using a large capacitance design. These embodiments can also increase the peak drain efficiency and peak output power of transistors and related integrated devices within a power amplifier.

[0019] Figure 2 shows an example 80 of a package layout of components of an amplifier according to various embodiments described herein. Layout 80 is for a dual-flat no-leads (DFN) package. This package is designed for physical and electrical connection to large-scale circuits such as circuits implemented using a printed circuit board (PCB). However, layout 80 can also be extended for use in other packages such as a quad-flat no-leads (QFN) package or other suitable packages regardless of the presence or absence of leads. This concept can also be implemented using other plastic overmold packages or enclosures, ceramic air cavity packages, and plastic air cavity packages, but is not limited to use with any particular type of package.

[0020] Package layout 80 is provided as an example of an integrated device that can rely on the capacitor network described herein. Layout 80 includes several components of the amplifier 10 shown in Figure 1. However, Figure 2 does not show all components or circuit elements of the amplifier 10. Some components of the amplifier 10 can be mounted outside of package layout 80, or are omitted from the view in Figure 2 for simplification.

[0021] The package layout 80 is shown in its unencapsulated state. The package layout 80 includes, among other things, a thermal pad 50 and several lead frame pads 60-63. In the illustrated example, impedance matching components 12 and 14, the main amplifier 16, and the peaking amplifier 20 are mounted on the thermal pad 50 and electrically connected.

[0022] In one example, the main amplifier 16 can be implemented as a multi-finger planar field-effect transistor (FET), and the peaking amplifier 20 can also be implemented as a multi-finger planar FET. The layout of a multi-finger planar FET consists of an interdigitated gate, drain, and source terminals or electrodes. As will be described in more detail below, the main amplifier 16 and the peaking amplifier 20 can be formed on the same or different types of substrates (e.g., semiconductor material wafers). The size and power handling capabilities of amplifiers 16 and 20 can differ from each other and depending on the application.

[0023] In one example, amplifiers 16 and 20 can be formed as GaN-on-silicon (Si) power transistors. Amplifiers 16 and 20 can also be formed as GaN-on-silicon carbide (GaN-on-SiC) transistors or GaN transistors formed on other suitable types of substrates. In other examples, amplifiers 16 and 20 can be formed from other group III nitrides or group III-V direct bandgap active semiconductor devices (e.g., GaAs, InP, InGaP, AlGaAs, etc.). However, this concept is not limited to group III-V semiconductor devices. While this concept is described as being useful for use with power transistors formed from GaN materials, processes for devices formed from other semiconductor materials, and, without limitation, for other types of circuits including Si LDMOS, can also be relied upon.

[0024] The main amplifier 16 includes a drain contact 40, a gate contact 41, and a source contact. The source contact of the main amplifier 16 is located on the bottom side of the semiconductor die of the main amplifier 16 and is not visible in Figure 2. Similarly, the peaking amplifier 20 includes a drain contact 44, a gate contact 45, and a source contact. The source contact of the peaking amplifier 20 is located on the bottom side of the semiconductor die of the peaking amplifier 20 and is not visible in Figure 2. The bottom source contacts of the main amplifier 16 and the peaking amplifier 20 can be electrically connected to the thermal pad 50 using solder, conductive thermal epoxy, or another preferred means. Typically, the thermal pad 50 is electrically coupled to circuit ground.

[0025] The impedance matching component 12 includes capacitor networks 30 and 32. The impedance matching component 14 includes capacitor networks 34 and 36. Capacitor network 30 can be embodied as one or more metal-oxide-semiconductor (MOS) capacitors formed on a substrate. The MOS capacitor is electrically coupled between a bond pad 42, which is a first contact on the upper side of the substrate, and a second contact on the lower side of the substrate. The lower contact of capacitor network 30 is electrically connected to a thermal pad 50. Thus, capacitor network 30 can be a shunt-connected input capacitor network.

[0026] Capacitor network 32, like capacitor network 30, can be realized as a MOS capacitor formed on a substrate. The MOS capacitor is electrically coupled between a bond pad 43, which is a first contact on the upper side of the substrate, and a second contact on the lower side of the substrate. The lower contact of capacitor network 32 is electrically connected to a thermal pad 50. Capacitor networks 34 and 36 are similar to capacitor networks 30 and 32, but capacitor networks 30, 32, 34 and 36 can all be different from each other. For example, capacitor networks 30, 32, 34 and 36 can differ from each other in size, capacitance, internal resistance, Q coefficient and other coefficients.

[0027] In package layout 80, the drain contact 40 of the main amplifier 16 is electrically coupled to the lead frame pad 60 by multiple bond wires. The gate contact 41 of the main amplifier 16 is electrically coupled to the bond pad 42 of the capacitor network 30 by multiple bond wires. The gate contact 41 of the main amplifier 16 is also electrically coupled to the bond pad 43 of the capacitor network 32 by several other bond wires. The bond pad 43 of the capacitor network 32 is also electrically coupled to the lead frame pad 61 by multiple bond wires. Figure 2 shows these bond wires as a representative example, so the number and pitch of the bond wires may differ from those shown.

[0028] The drain contact 44 of the peaking amplifier 20 is electrically coupled to the lead frame pad 62 by multiple bond wires. The gate contact 45 of the peaking amplifier 20 is electrically coupled to the bond pad 46 of the capacitor network 34 by multiple bond wires. The gate contact 45 of the peaking amplifier 20 is also electrically coupled to the bond pad 47 of the capacitor network 36 by several other bond wires. The bond pad 47 of the capacitor network 36 is also electrically coupled to the lead frame pad 63 by multiple bond wires. Figure 2 shows these bond wires as a representative example, so the number and pitch of the bond wires may differ from those shown.

[0029] Accordingly, capacitor networks 30 and 32, along with other intrinsic parasitic inductances (e.g., from bond wires) and capacitances, provide an input network at the input of the main amplifier 16. Capacitor networks 34 and 36 provide an input network at the input of the peaking amplifier 20. Capacitor networks 30 and 34 can be relied upon, in particular, for second harmonic processing and control of the main amplifier 16 and the peaking amplifier 20, respectively. As an example, amplifier 10 can be designed to operate at carrier frequencies of approximately 2 GHz to 6 GHz, such as 2.5 GHz, 3 GHz, or 4 GHz, but can also be used at other frequencies and frequency ranges. The second harmonic can be in the range of 4 to 9 GHz or higher, depending on the operating frequency. Among the many advantages of improved second harmonic processing at the inputs of amplifiers 16 and 20, among others, it can increase the peak drain efficiency of amplifiers 16 and 20 and potentially increase the peak output power of amplifiers 16 and 20.

[0030] However, the MOS capacitor networks 30 and 34 have some limitations for second harmonic processing of the main amplifier 16 and the peaking amplifier 20. For example, it is difficult to improve the internal resistance and Q coefficient of the MOS capacitors beyond a certain level using current processing techniques. Capacitor networks 30 and 34 may also limit their ability to adjust phase alignment and related improvements. These coefficients limit the ability to improve second harmonic control of the main amplifier 16 and the peaking amplifier 20. Below, new types, structures, and configurations of capacitor networks are described to address the limitations of capacitor networks 30 and 34, among other purposes. These new capacitor networks can be relied upon for improved second harmonic control of the amplifier 10 and other purposes. The new capacitor networks are not shown in Figure 2, and examples of new capacitor networks are described below with reference to Figure 6.

[0031] Figure 3 shows the capacitor network 100 of the MIM capacitor according to various embodiments described herein. For example, the capacitor network 100, and its variations and extensions, can be used in place of one or more of the capacitor networks 30, 32, 34, and 36 in the package layout 80 of Figure 2, and the amplifier 10 in Figure 1, although the capacitor network 100 can also be used in other designs. The capacitor network 100 is shown as an example, and several different variations of the capacitor network 100 are described in more detail below.

[0032] As shown in Figure 3, the capacitor network 100 is formed on the substrate 110. The capacitor network 100 includes capacitor configurations 120, 140, and 160. The capacitor configurations 120, 140, and 160 can be formed using a relatively high voltage semiconductor manufacturing process (e.g., 20V or higher) for operation and robustness against physical elements (e.g., heat and humidity), but can rely on any preferred semiconductor manufacturing process.

[0033] Capacitor configuration 120 includes a MIM capacitor 121. Similarly, capacitor configuration 140 includes a MIM capacitor 141, and capacitor configuration 160 includes a MIM capacitor 161. The upper conductive plate or metal layer of the MIM capacitor 121 is electrically coupled to the upper bond pad 150 of the substrate 110 using a first metal layer. The lower conductive plate or metal layer of the MIM capacitor 121 is electrically coupled to the lower contacts of the substrate 110, in particular by through-substrate vias 122. The MIM capacitor 121 also includes an insulating layer, such as a layer of suitable dielectric material, between the upper conductive plate and the lower conductive plate. Capacitor configurations 140 and 160 are similar to capacitor configuration 120.

[0034] Each of the MIM capacitors 121, 141, and 161 can be designed for a specific amount of capacitance. For example, the MIM capacitors 121, 141, and 161 can be designed to have capacitances of approximately 0.4pF to 1.2pF, respectively, such that the total capacitance of the capacitor network 100 is approximately 1.2pF to 3.6pF when the MIM capacitors 121, 141, and 161 are coupled in parallel with each other. However, other capacitances are also within the scope of this embodiment, and the MIM capacitors 121, 141, and 161 can be designed for relatively precise capacitances up to 1 / 10 picofarad (or less) in the range of approximately 0.1pF to 2.0pF. However, the MIM capacitors 121, 141, and 161 can also be designed for larger capacitances of 2.0pF, 3.0pF, 4.0pF, or even greater. The capacitance of each of the MIM capacitors 121, 141, and 161 can be controlled or determined by design based on the size of the conductive plate. Alternatively, one or more of the MIM capacitors 121, 141, and 161 can be omitted from the capacitor network 100. Other variations are described below.

[0035] The capacitor network 100, including MIM capacitors 121, 141, and 161, offers several advantages over a MOS capacitor network. For example, the dimensions of the MIM capacitors 121, 141, and 161 can be individually fitted for better overall capacitance accuracy. The configuration of through-vias around each of the MIM capacitors 121, 141, and 161 reduces the overall intrinsic resistance. The Q coefficient of each of the MIM capacitors 121, 141, and 161 is based on the ratio of the energy stored in the capacitor to the energy dissipated by heat loss in the equivalent series resistance within the capacitor. Thus, the Q coefficient of the capacitor network 100 is improved compared to a MOS capacitor network due to the improved intrinsic resistance of the MIM capacitors 121, 141, and 161. In addition, the bond pad 150 provides a relatively large area for wire bonding, and the spacing of the wire bonds along the bond pad 150 can facilitate phase alignment using the capacitor network 100. The spacing of the MIM capacitors 121, 141, and 161 along the bond pad 150 also facilitates phase alignment using the capacitor network 100. These and other improvements better suit the capacitor network 100 for second harmonic processing as part of the input network at the inputs of power transistors and amplifiers. These improvements can also better suit the capacitor network 100 for first harmonic processing. Further details of the capacitor network 100 and its variations are described below.

[0036] Figure 4A shows the capacitor configuration 120 in more detail, and Figure 4B shows the cross-sectional view AA identified in Figure 4A. Figures 4A and 4B are not necessarily to scale, and the relative dimensions of some layers and components may differ in practice and between embodiments. Also, since these figures are shown as examples to illustrate the concept, the capacitor configuration 120 may include other layers and features that are omitted from the views in Figures 4A and 4B for simplification.

[0037] Referring between Figures 4A and 4B, the capacitor configuration 120 includes a MIM capacitor 121 formed on the upper surface 130 of the substrate 110. The MIM capacitor 121 includes a first metal layer 170, a second metal layer 171, and an insulating layer 172 between the first metal layer 170 and the second metal layer 171. The first metal layer 170 and the second metal layer 171 are conductive plates of the MIM capacitor 121. The metal layers 170 and 171 can be formed from any one or more suitable metals depending on the integrated semiconductor processing technique used. For example, the metal layers 170 and 171 can be aluminum, copper, gold, nickel, other metals, or combinations thereof. If necessary, an adhesive layer of, for example, titanium or chromium can be deposited before depositing aluminum, copper, gold, nickel, or other metals. The metal layers 170 and 171 can also be formed using any suitable processing technique and steps. The insulating layer 172 can be embodied as any suitable (single or double) dielectric material such as an oxide, silicon oxide (SiO), silicon nitride (SiN), or other material.

[0038] The size of the MIM capacitor 121 can vary by design to achieve a specific capacitance. For example, the length "L" and / or width "W" of the MIM capacitor 121 can differ from those shown in Figure 4A. The shape of the MIM capacitor 121 can also differ from the rectangle shown. Another way to vary the capacitance of the MIM capacitor 121 is to vary the thickness of the insulating layer 172.

[0039] The second bottom metal layer 171 of the MIM capacitor 121 is electrically coupled to the substrate through-vias 122-124 by metal pads 125-127 extending into the bottom metal layer 171. Although the metal pads 125-127 are physically separated from each other, they can be formed from the same metal material in a single processing step. In some cases, the second metal layer 171 can also be formed from the same metal material and in the same processing step as the metal pads 125-127. In other cases, the metal pads 125-127 and the second metal layer 171 can be formed using different metals and in different processing steps. In any case, the metal pads 125-127 and the second metal layer 171 are electrically coupled to each other.

[0040] The first upper metal layer 170 of the MIM capacitor 121 is electrically coupled to the bond pad 150 by a metal trace 151. The upper metal layer 170 and the metal trace 151 can be formed from the same metal material in the same processing step. In other cases, the upper metal layer 170 and the metal trace 151 can be formed using different metals in different processing steps. The bond pad 150 can be formed from two metal layers for additional thickness. For example, the layers of the bond pad 150 can be formed when the metal layers 170 and 171 of the MIM capacitor 121 are formed. In other cases, the bond pad 150 can be formed in a single metalworking step. The shape, dimensions and relative positions of the metal pads 125-127, the first metal layer 170, the second metal layer 171, and the bond pad 150 can also differ from those shown in Figures 4A and 4B.

[0041] Referring to Figure 4B, the first metal layer 170 of the MIM capacitor 121 is electrically coupled to the bond pad 150 by a metal trace 151. The second metal layer 171 is electrically coupled to a grounding surface 111 formed on the bottom side of the substrate 110 by a through-substrate via 123. The grounding surface 111 can be electrically coupled, for example, to a thermal pad 50 (see Figure 2) in the package layout 80. Thus, the MIM capacitor 121 can be relied upon as a shunt-connected capacitor in an input network, for example, but other connections are also within the scope of this embodiment.

[0042] Although not shown in Figure 4B, through-substrate vias 122 and 124 also connect the second metal layer 171 of the MIM capacitor 121 to the ground surface 111 through the substrate 110. The number of through-substrate vias can vary between embodiments. For example, additional vias other than vias 122-124 can be mounted around the MIM capacitor 121. Alternatively, one or more of vias 122-124 can be omitted. For example, vias 122 and 124 can be omitted so that the capacitor configuration 120 includes only via 123. In another case, via 123 can be omitted so that the capacitor configuration 120 includes vias 122 and 124. Other modifications are also within the scope of this embodiment. The equivalent series resistance and Q coefficient of the MIM capacitor described herein can vary depending on the number of through-substrate vias. Therefore, in some cases, it is considered preferable to use at least two or three through-substrate vias to increase the Q coefficient of the MIM capacitor.

[0043] Referring again to Figure 3, capacitor configurations 140 and 160 can be similar to capacitor configuration 120 shown in Figures 4A and 4B. In other cases, capacitor configurations 120, 140, and 160 can differ from one another. For example, one or more of the MIM capacitors 121, 141, and 161 can differ in size from one another. In another example, capacitor configurations 120, 140, and 160 can include different numbers of through-substrate vias. Furthermore, one or more of the capacitor configurations 120, 140, and 160 can be omitted from the capacitor network 100. For example, capacitor configuration 140 can be omitted while capacitor configurations 120 and 160 are retained, but other combinations are also within the scope of this embodiment. Also, the dimensions of the bond pad 150 can differ from those shown, and the relative positions of capacitor configurations 120, 140, and 160 around the bond pad 150 can differ. In some cases, the capacitor configurations can be arranged around multiple sides or edges of the bond pad 150.

[0044] Figure 5 shows another capacitor network example 200 according to various embodiments described herein. This capacitor network includes capacitor configurations 220, 240, and 260. Capacitor configurations 220, 240, and 260 are similar to capacitor configurations 120, 140, and 160 shown in Figure 3, but they are not electrically coupled to a common bond pad. Instead, capacitor configurations 220, 240, and 260 include their respective bond pads 251, 252, and 253. Bond pads 251, 252, and 253 are electrically isolated from each other. Capacitor network 200 can offer greater design flexibility compared to capacitor network 100 shown in Figure 3. The number of bond wires that can be attached to bond pads 251, 252, and 253 may be limited by design rules, and therefore, in some cases, a larger shared bond pad may be preferred.

[0045] Figure 6 shows an example package layout 300 based on the concepts described herein. Among several components, package layout 300 includes, in particular, the main amplifier 20, the capacitor network 36, and the capacitor network 100. Other components are omitted for simplification. Package layout 300 is similar to package layout 80 shown in Figure 2, but includes the capacitor network 100 (see Figure 2) instead of the capacitor network 34. The gate contact 45 of the peaking amplifier 20 is electrically coupled to the bond pad 150 of the capacitor network 100 by multiple bond wires. Since the bond pad 150 is relatively long, it is designed to accommodate bond wires of different numbers and positions. In other embodiments, the number, pitch, and arrangement of bond wires may differ from those shown in Figure 6.

[0046] Capacitor network 100 provides an input network at the input of the peaking amplifier 20. In one example, capacitor network 100 can be relied upon for second harmonic processing and control of the peaking amplifier 20. Improved second harmonic processing at the input of the amplifier 20 has several advantages, including increasing the peak drain efficiency of the amplifier 20 and potentially increasing the peak output power. Capacitor network 34 can be relied upon for first harmonic processing or fundamental termination of the peaking amplifier 20. However, in other examples, depending on the respective capacitances of capacitor networks 34 and 100 and the bond wires coupling them to the peaking amplifier 20, capacitor network 34 can be relied upon for second harmonic processing and capacitor network 100 for fundamental processing.

[0047] Although not shown in Figure 6, other MIM capacitor networks can be used instead of capacitor network 100. For example, according to the embodiments described herein, an MIM capacitor network can be used that includes one, two, three, or four or more individual MIM capacitors having the same or different capacitances and the same or different number of through-substrate vias. According to the embodiments described herein, an MIM capacitor network can also be used that includes one, two, three, or four or more individual bond pads. In some cases, an MIM capacitor network according to this concept can be used instead of capacitor network 36. Similarly, an MIM capacitor network according to this concept can be used instead of one or both of the capacitor networks 30 and 32 of the main amplifier 16.

[0048] This embodiment can be used with Group III-V direct transition active semiconductor transistor devices, including Group III nitrides (aluminum (Al), gallium (Ga), indium (In), and alloys thereof (AlGaIn) based nitrides), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaP), and aluminum gallium arsenide (AlGaAs), as well as devices such as high electron mobility transistors (HEMTs), pseudomorphic high-electron mobility transistors (pHEMTs), and metamorphic high-electron mobility transistors (mHEMTs). However, this concept is not limited to Group III-V semiconductor devices. Although this concept has been described as beneficial for use with power transistors formed from GaN materials, processes for devices formed from other semiconductor materials, and, without limitation, for other types of circuits including Si LDMOS, can also be relied upon.

[0049] Among the embodiments described in this specification, some relate to GaN-on-Si transistors, but it should be understood that the embodiments described in this specification can also be applied to GaN-on-SiC transistors and other types of transistors. In any case, the technologies and optimizations described in this specification provide many improvements in cost and size, among other improvements in numerous possible device characteristics. As used herein, the expression "gallium nitride material" or GaN semiconductor material refers, among other things, to aluminum gallium nitride (Al (1-a-b) , b ,

[0050] , , Ga (1-x) N), indium gallium nitride (In y Ga (1-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium arsenide phosphide nitride (GaAs a P b N (1-a-b) ), aluminum indium gallium arsenide phosphide nitride (Al x In y Ga (1-x-y) As a P b N (1-a-b) ), and any alloys thereof. Typically, arsenic and / or phosphorus, when present, are present at low concentrations (e.g., less than 5 weight percent). The term "gallium nitride" or GaN semiconductor directly refers to gallium nitride and does not include its alloys.

[0050] The features, structures, or properties described above can be combined in any preferred manner in one or more embodiments, and the features described in the various embodiments can be replaced where possible. The above description provides numerous specific details to allow for a full understanding of the embodiments of the Disclosure. However, those skilled in the art will understand that the technical solutions of the Disclosure may be implemented without one or more of these specific details, or may employ other methods, components, and materials. In other instances, well-known structures, materials, or operations are not illustrated or described in detail so as not to obscure the aspects of the Disclosure.

[0051] While relative terms such as "on," "below," "upper," and "lower" are sometimes used to describe the relative relationships of some components, these terms are merely for convenience, indicating the direction, for example, as shown in the diagrams. It should be understood that if the device is inverted, the aforementioned "upper" components become "lower" components. When one structure exists "on" another structure, this structure can be integrally formed on the other structure, placed "directly" on the other structure, or placed "indirectly" on the other structure through the other structure.

[0052] In this specification, terms such as the indefinite articles (a, an), the definite article (the), and "said" are used to indicate the presence of one or more elements and components. The terms "comprise, include, have, contain" and their variants are used open-ended and are intended to include additional elements and components beyond those listed unless otherwise specified. Terms such as "first" and "second" are used solely as labels and not to limit the number of objects.

[0053] Although embodiments have been described in detail in this specification, these descriptions are illustrative. The features of the embodiments described herein are representative, and in other embodiments, some features and elements may be added or omitted. Furthermore, those skilled in the art may modify the embodiments described herein without departing from the spirit and scope of the invention as defined by the following claims, the scope of which should be interpreted in the broadest way to include modifications and equivalent structures.

Claims

1. A capacitor network formed on a substrate, A bond pad provided on the upper surface of the substrate, A metal-insulator-metal (MIM) capacitor formed on the upper surface of the substrate and arranged along one side of the bond pad, comprising a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, Multiple through-board vias, Equipped with, The first metal layer of the MIM capacitor is electrically coupled to the bond pad by metal wiring extending on the upper surface of the substrate between the first metal layer of the MIM capacitor and the bond pad. The second metal layer is electrically coupled to the ground surface on the bottom side of the substrate by the plurality of substrate through vias. The plurality of through-substrate vias are arranged along multiple different sides of the first metal layer, the second metal layer, and the insulating layer of the MIM capacitor. A capacitor network characterized by the following features.

2. The capacitor network includes a plurality of MIM capacitors arranged along one side of the bond pad and electrically coupled to the bond pad. Each of the plurality of MIM capacitors includes a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer. The capacitor network according to claim 1.

3. Each of the multiple MIM capacitors is electrically coupled to the ground surface by multiple through-vias. The capacitor network according to claim 2.

4. The capacitor network includes a plurality of MIM capacitors, The plurality of MIM capacitors are arranged along multiple different sides of the bond pad. The capacitor network according to claim 1.

5. The aforementioned capacitor network is Multiple bond pads, The plurality of MIM capacitors electrically coupled to the plurality of bond pads, The capacitor network according to claim 1.

6. Each of the aforementioned MIM capacitors is electrically coupled to the ground surface by a plurality of through-substrate vias. The capacitor network according to claim 5.

7. An integrated device, A power transistor formed on the first substrate, A capacitor network formed on a second substrate, The capacitor network is equipped with, A bond pad provided on the upper surface of the second substrate, A metal-insulator-metal (MIM) capacitor disposed on the upper surface of the second substrate along one side of the bond pad, wherein the MIM capacitor includes a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, and the first metal layer of the MIM capacitor is electrically coupled to the bond pad by metal wiring extending on the upper surface of the second substrate between the first metal layer of the MIM capacitor and the bond pad, A plurality of through-substrate vias electrically coupling the second metal layer to the ground surface on the bottom side of the second substrate, wherein the plurality of through-substrate vias are arranged along a plurality of different sides of the first metal layer, the second metal layer and the insulating layer of the MIM capacitor, Furthermore, it comprises at least one bond wire electrically coupled between the power transistor and the bond pad of the capacitor network, An integrated device characterized by the following features.

8. The capacitor network includes a plurality of MIM capacitors arranged along one side of the bond pad and electrically coupled to the bond pad. Each of the plurality of MIM capacitors includes a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer. The integrated device according to claim 7.

9. Each of the multiple MIM capacitors is electrically coupled to the ground surface by multiple through-vias. The integrated device according to claim 8.

10. The capacitor network includes a plurality of MIM capacitors, The plurality of MIM capacitors are arranged along multiple different sides of the bond pad. The integrated device according to claim 7.

11. The aforementioned capacitor network is Multiple bond pads, Multiple MIM capacitors, The plurality of MIM capacitors are coupled to different bond pads among the plurality of bond pads, The integrated device according to claim 7.

12. The aforementioned at least one bond wire includes a plurality of bond wires, Each of the plurality of bond pads is electrically coupled to the power transistor by at least one of the plurality of bond wires. The integrated device according to claim 11.

13. Each of the aforementioned MIM capacitors has the same capacitance. The integrated device according to claim 11.

14. Each of the multiple MIM capacitors is electrically coupled to the ground surface by multiple through-vias. The integrated device according to claim 11.

15. The first substrate and the second substrate are both arranged within a single device package of the integrated device. The integrated device according to claim 7.

16. The device further comprises a second capacitor network formed on a third substrate, wherein the first substrate, the second substrate, and the third substrate are all arranged within the single device package of the integrated device. The integrated device according to claim 15.

17. The system further comprises at least one bond wire electrically coupled between the power transistor and the second capacitor network. The integrated device according to claim 16.

18. The second capacitor network includes at least one metal-oxide-semiconductor (MOS) capacitor. The integrated device according to claim 16.

19. The MIM capacitor on the second substrate provides second harmonic processing for the power transistor. The second capacitor network formed on the third substrate includes a second MIM capacitor. The second MIM capacitor on the third substrate provides fundamental wave processing for the power transistor. The integrated device according to claim 16.

20. A capacitor network formed on a substrate, A metal-insulator-metal (MIM) capacitor disposed on the upper surface of the substrate, comprising a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, A bond pad is placed on the upper surface of the substrate and on the side of the MIM capacitor, The MIM capacitor comprises a through-via positioned on the side of the substrate, The first metal layer of the MIM capacitor is electrically coupled to the bond pad by a first metal wiring that extends across a first region on the upper surface of the substrate between the MIM capacitor and the bond pad located on the side of the MIM capacitor. The second metal layer of the MIM capacitor is electrically coupled to the through-via by a second metal wiring that extends across a second region on the upper surface of the substrate between the MIM capacitor and the through-via located on the side of the MIM capacitor. The vias through the substrate are electrically coupled to the ground surface on the bottom side of the substrate. A capacitor network characterized by the following features.

21. The capacitor network includes a plurality of MIM capacitors arranged on the side of the bond pad and electrically coupled to the bond pad. The capacitor network according to claim 20.

22. The capacitor network includes a plurality of MIM capacitors arranged along a plurality of different sides of the bond pad, The capacitor network according to claim 20.

23. The capacitor network includes a plurality of through-substrate vias, The plurality of through-substrate vias are arranged along multiple different sides of the first metal layer, the second metal layer, and the insulating layer of the MIM capacitor. The capacitor network according to claim 20.

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