Compilation device, compilation method, and compilation program

Abstract

In the present invention, in order to enable a computer to execute a program more quickly, this compiling device 300 includes a loop unrolling means 301 for performing loop unrolling of an outer loop in a multilayered loop in the source program, and a packed vectorization means 302 for converting a command in the loop into a packed vector command after the loop unrolling is performed.

Description

Technical Field

[0001] The present invention relates to a compilation device, a compilation method, and a compilation program for improving the processing performance of a computer.

Background Art

[0002] The access time from the arithmetic unit of a computer (e.g., CPU: Central Processing Unit) to the main memory is long compared to the arithmetic time of the arithmetic unit. Therefore, in order to improve the processing performance of a computer, in other words, to speed up the processing of a computer, it is important to reduce the access frequency to the main memory.

[0003] Patent Document 1 describes a method for reducing access to the main memory when there are adjacent memory access instructions in a source program executable on a vector computer. Specifically, a compiler (compilation device) reduces duplicate memory accesses to improve the processing performance of the vector computer.

[0004] Adjacent memory access instructions mean a plurality of instructions that each access data assigned to adjacent areas in the main memory. Access to adjacent data means accessing data in adjacent areas in the main memory. Note that access to adjacent data may be expressed as adjacent access.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The compiler device described in Patent Document 1 generates an instruction to slide the data in the first vector register and store it in the second vector register. This may result in a shortage of elements to be used in the calculation (see Figure 4 in Patent Document 1). In that case, the compiler device described in Patent Document 1 generates additional vector instructions or scalar instructions for load / store or calculation to compensate for the missing elements. In other words, the compiler device described in Patent Document 1 may not have sufficiently optimized the source program, and therefore may not be able to achieve sufficient speed.

[0007] The present invention aims to provide a compilation device, a compilation method, and a compiled program that can enable faster execution of programs on a computer. [Means for solving the problem]

[0008] The compilation device according to the present invention includes loop unrolling means for performing loop unrolling of the outer loop in a multiple loop in a source program, and packed vectorization means for converting instructions in the loop into packed vector instructions after loop unrolling has been performed. , an adjacent access determination means that determines whether or not access to data allocated to an adjacent area in memory is included in the outer loop, Includes Furthermore, the loop unrolling means performs loop unrolling if access to data allocated to an adjacent area in memory is included in the outer loop. .

[0009] The compilation method according to the present invention performs loop unrolling of the outer loop in a nested loop within the source program, and after loop unrolling, converts the instructions within the loop into packed vector instructions. Then, it is determined whether accessing data allocated to adjacent memory regions is included in the outer loop, and if accessing data allocated to adjacent memory regions is included in the outer loop, loop unrolling is performed. .

[0010] The compilation program according to the present invention provides a computer with the following processes: loop unrolling of the outer loop in a nested loop within the source program; and after loop unrolling, converting the instructions within the loop into packed vector instructions. The system then performs a process to determine whether accessing data allocated to an adjacent memory region is included in the outer loop, and if accessing data allocated to an adjacent memory region is included in the outer loop, it performs loop unrolling. . [Effects of the Invention]

[0011] According to the present invention, a program can be executed faster in a computer.

Brief Description of the Drawings

[0012] [Figure 1] It is a block diagram showing a configuration example of a compilation device. [Figure 2] It is a block diagram showing a configuration example of a vector computer capable of executing a target program. [Figure 3] It is a flowchart showing the operation of the compilation device. [Figure 4] It is an explanatory diagram showing an example of a source program that cannot be vectorized. [Figure 5] It is an explanatory diagram showing an example of a source program. [Figure 6] It is an explanatory diagram showing an example of a source program with loop unrolling applied. [Figure 7] It is an explanatory diagram showing an example of a packed vector instruction. [Figure 8] It is an explanatory diagram for explaining the operation of the packed vector instruction. [Figure 9] It is a block diagram showing an example of a computer having a CPU. [Figure 10] It is a block diagram showing the main part of the compilation device.

Embodiments of the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0014] FIG. 1 is a block diagram showing a configuration example of a compilation device. The compilation device 100 shown in FIG. 1 includes a syntax analysis unit 10, a first intermediate language storage unit 20, an optimization unit 30, a second intermediate language storage unit 40, and a code generation unit 50.

[0015] The optimization unit 30 includes a loop analysis unit 31, an outer loop unroll processing unit 32, and a packed vectorization processing unit 33.

[0016] The syntax analysis unit 10 performs syntax analysis on the input source program. Based on the result of the syntax analysis, the syntax analysis unit 10 generates a first intermediate language and temporarily stores the first intermediate language in the first intermediate language storage unit 20.

[0017] The optimization unit 30 reads the first intermediate language from the first intermediate language storage unit 20. The optimization unit 30 performs optimization processes such as loop unrolling, loop vectorization, and register allocation on the first intermediate language. The optimization unit 30 temporarily stores the first intermediate language on which the optimization process has been performed in the second intermediate language storage unit 40 as the second intermediate language.

[0018] The code generation unit 50 reads the second intermediate language from the second intermediate language storage unit 40. The code generation unit 50 translates the second intermediate language into machine language and generates an object program executable by the vector computer.

[0019] In the optimization unit 30, the loop analysis unit 31 determines whether access to adjacent data is included in nested loops in the source program. Also, the loop analysis unit 31 determines whether the inner loop can be vectorized. In the following description, a double loop is taken as an example of nested loops.

[0020] The outer loop unrolling processing unit 32 performs loop unrolling of the outer loop (the outermost loop).

[0021] The packed vectorization processing unit 33 applies packed vectorization to the operations of the loop after the outer loop has been loop unrolled. Vectorization is to convert the operations within the loop into vector operations. Packed vectorization is to convert the operation instructions within the loop into packed vector instructions or SIMD (Single Instruction Multiple Data) instructions. A packed vector instruction is an operation instruction that can process a plurality of data strings with one instruction.

[0022] Figure 2 is a block diagram showing an example of a vector computer capable of executing the target program generated by the compilation unit 100.

[0023] In the vector computer 200, the arithmetic unit 210 consists of a CPU and a GPU (Graphics Processing Unit). The arithmetic unit 210 obtains data from the main memory 220 or the vector registers 230. The main memory 220 holds the arrays and data of the results of the calculations that the arithmetic unit 210 needs to perform.

[0024] The vector register 230 is a memory device that the arithmetic unit 210 can access faster than the main memory 220. The vector register 230 stores data sequences loaded from the main memory 220. The arithmetic unit 210 can also store data in the vector register 230. It should be noted that vector computers that perform vector operations on data sequences held in the vector register 230, rather than on data sequences held in the main memory 220, are now the mainstream.

[0025] Next, the operation of the compilation device will be explained with reference to Figure 3. Figure 3 is a flowchart showing the operation of the compilation device 100.

[0026] The parsing unit 10 receives a source program as input (step S101). The input source program is a program written in a high-level language. The high-level language is, for example, FORTRAN. The parsing unit 10 parses the source program and generates a first intermediate language (steps S102, S103). The parsing unit 10 temporarily stores the first intermediate language in the first intermediate language storage unit 20.

[0027] The loop analysis unit 31 detects a double loop in the source program (step S104). If no double loop exists in the source program, the process proceeds to step S109. If a double loop exists, the loop analysis unit 31 determines whether the outer loop of the double loop includes access to adjacent data in main memory (adjacent access) (step S105). If no adjacent access exists, the process proceeds to step S109.

[0028] When a program written in FORTRAN is used, a two-dimensional array (let's call it A(I,J)) is generally allocated in main memory so that the elements of the first dimension are adjacent, such as A(I,J) and A(I+1,J). On the other hand, adjacent elements in the second dimension, such as A(I,J) and A(I,J+1), are allocated in main memory to a region separated by the number of elements in the first dimension (or N if the maximum value of I is N). In other words, in FORTRAN, when I is a variable handled in an outer loop, there is generally adjacent access in the outer loop.

[0029] If adjacent access exists, the loop analysis unit 31 checks whether the inner loop in the double loop is vectorizable (step S106). The loop analysis unit 31 determines that vectorization is not possible, for example, if there is a dependency between the definition and reference relationship of arrays or variables within the loop.

[0030] Figure 4 is an explanatory diagram illustrating an example of a source program that cannot be vectorized. In the example shown in Figure 4, vectorization is not possible because array A has dependencies. In such cases, a loop swap is generally attempted. In the example shown in Figure 4, the loop in I and the loop in J are swapped. Since the loop in J has no dependencies, the swap makes it possible to vectorize the inner loop.

[0031] However, swapping loops prevents adjacent access. As a result, the processing speed of a computer running an object program generated from a source program with swapped loops decreases.

[0032] As described below, this embodiment makes it possible to improve processing speed while avoiding a decrease in the processing speed of the computer caused by the inability to access adjacent systems.

[0033] If the inner loop is vectorizable, the outer loop unrolling unit 32 performs loop unrolling of the outer loop (step S107).

[0034] Figures 5 and 6 are explanatory diagrams illustrating loop unrolling. Figure 5 shows an example of a source program. Figure 6 shows an example of a source program with loop unrolling applied.

[0035] Figure 5 shows an example with two stages of loop unrolling, but the number of unrolling stages may be more than two. However, increasing the number of stages reduces the number of main memory accesses, but it may lead to a shortage of vector registers and a decrease in performance. Therefore, the number of unrolling stages should be set such that, for example, the performance improvement due to the reduction in the number of main memory accesses is not compromised by a decrease in performance due to a shortage of vector registers. For this reason, it is preferable that the number of unrolling stages be two.

[0036] The packed vectorization processing unit 33 converts the instructions within the loop into packed vector instructions (step S108). In other words, the packed vectorization processing unit 33 applies packed vectorization to both the outer and inner loops together.

[0037] Figure 7 is an explanatory diagram illustrating an example of packed vector instructions. Assume that the target program is executed on the vector computer 200 illustrated in Figure 2, and that the vector register 230 is a register capable of storing 256 elements of 8 bytes of data.

[0038] The PVLD instruction illustrated in Figure 7 loads two consecutive 4-byte data sets, separated by (N*4) bytes, from main memory 220 into one element of vector register 230. The PVAD instruction is an arithmetic instruction that adds the two 4-byte data sets stored in one element of vector register 230 element by element. The PVST instruction stores the data sequence of vector register 230, separated by (N*4) bytes, into main memory 220.

[0039] Figure 8 is an explanatory diagram illustrating the operation of packed vector instructions. The PVAD instruction is shown as an example in Figure 8. As shown in Figure 8, the PVAD instruction executes the operations B(I,J)+C(I,J) and B(I+1,J)+C(I+1,J) in the loop (see Figure 6) simultaneously.

[0040] When using the compilation device 100 of this embodiment, source programs that cannot vectorize the outer loop in multiple loops, or in which swapping loops reduces the main memory access efficiency (making adjacent access impossible), can be converted into source programs that can be processed at high speed by a computer.

[0041] Furthermore, the greater the number of iterations in a loop, the greater the speed-up effect of vectorization. In other words, the speed-up effect of vectorization is small when the number of iterations is small. Even source programs containing loops with a small number of iterations can be converted into source programs that can be processed at high speed by a computer by applying the compilation method of the compilation device of this embodiment.

[0042] Each function (each process) in the above embodiment can be implemented by a computer having a processor such as a CPU and memory. For example, a program for implementing the method (process) in the above embodiment may be stored in a storage device (storage medium), and each function may be implemented by executing the program stored in the storage device with the CPU.

[0043] Figure 9 is a block diagram showing an example of a computer having a CPU. The computer is implemented in a compilation device 100. The CPU 1000 realizes each of the functions in the above embodiment by executing processing according to the program (software element: code) stored in the storage device 1001. That is, it realizes the functions of the syntax analysis unit 10, the optimization unit 30, and the code generation unit 50 in the compilation device 100 shown in Figure 1.

[0044] The storage device 1001 is, for example, a non-transitory computer-readable medium. Non-transitory computer-readable media include various types of tangible storage media. Specific examples of non-transitory computer-readable media include magnetic recording media (e.g., hard disks), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Compact Disc-Read Only Memory), CD-Rs (Compact Disc-Recordable), CD-R / Ws (Compact Disc-ReWritable), and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs).

[0045] Furthermore, the program may be stored in various types of transient computer-readable medium. The program may be supplied to the transient computer-readable medium, for example, via a wired or wireless communication channel, i.e., via electrical signals, optical signals, or electromagnetic waves.

[0046] Memory 1002 is implemented, for example, as RAM (Random Access Memory) and is a storage means that temporarily stores data when the CPU 1000 executes processing. It is also conceivable that a program held by the storage device 1001 or a temporary computer-readable medium is transferred to memory 1002, and the CPU 1000 executes processing based on the program in memory 1002. The first intermediate language storage unit 20 and the second intermediate language storage unit 40 can be implemented in memory 1002.

[0047] Figure 10 is a block diagram showing the main components of the compilation device. The compilation device 300 shown in Figure 10 includes a loop unrolling means 301 (implemented in an outer loop unrolling processing unit 32 in an embodiment) that performs loop unrolling of the outer loop in a multiple loop in the source program, and a packed vectorization means 302 (implemented in an embodiment, a packed vectorization processing unit 33) that converts the instructions in the loop into packed vector instructions after loop unrolling has been performed.

[0048] The compilation device 300 includes an adjacent access determination means (implemented in the loop analysis unit 31 in this embodiment) that determines whether access to data allocated to an adjacent area in memory (e.g., main memory) is included in the outer loop, and the loop unrolling means 301 may be configured to perform loop unrolling when access to data allocated to an adjacent area in memory is included in the outer loop.

[0049] Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above embodiments. Various modifications to the structure and details of the present invention can be made, as can be understood by those skilled in the art within the scope of the present invention.

[0050] This application claims priority based on Japanese Patent Application No. 2023-046153, filed on 23 March 2023, and incorporates all of its disclosures herein. [Explanation of Symbols]

[0051] 10. Parsing Unit 20 1st intermediate language holding section 30 Optimization Unit 31 Loop Analysis Section 32. Outer loop unroll processing unit 33 Packed Vectorization Processing Unit 40 Second intermediate language holding unit 50 Code generation unit 100 Compilation Units 200 Vector Computers 210 Arithmetic equipment 220 Main Memory 230 vector registers 300 Compilation Units 301 Loop unrolling means 302 Packed vectorization means 1000 CPU 1001 Storage device 1002 memory

Claims

1. A loop unrolling means for performing loop unrolling of the outer loop in a nested loop within a source program, After the aforementioned loop unrolling is performed, a packed vectorization means is provided to convert the instructions within the loop into packed vector instructions, It includes an adjacent access determination means for determining whether access to data allocated to an adjacent area in memory is included in the outer loop, The loop unrolling means performs loop unrolling when access to data allocated to an adjacent area in the memory is included in the outer loop. Compilation device.

2. Multiple loops are double loops. The compilation device according to claim 1.

3. The aforementioned loop unrolling means performs two stages of loop unrolling. The compilation device according to claim 1.

4. Perform loop unrolling on the outer loop in a nested loop within the source program. After the aforementioned loop unrolling is performed, the instructions within the loop are converted into packed vector instructions. Determine whether accessing data allocated to adjacent memory regions is included in the outer loop. Loop unrolling is performed when accessing data allocated to an adjacent area in the aforementioned memory is included in the outer loop. Compilation method.

5. On the computer, The process involves unrolling the outer loop in a nested loop within the source program, After the aforementioned loop unrolling is performed, the process involves converting the instructions within the loop into packed vector instructions, The process involves determining whether accessing data allocated to adjacent memory regions is included in the outer loop. Loop unrolling is performed when accessing data allocated to an adjacent area in the aforementioned memory is included in the outer loop. A compilation program for that purpose.

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