Conversion device, conversion method, inverse conversion device, inverse conversion method, and program

Abstract

One aspect of the present disclosure relates to a conversion device including: an acquisition unit that acquires a first bit string of a first bit length L1; and a conversion unit that, in accordance with conversion information associating respective bit strings having the first bit length L1 with a bit string having a second bit length L2 uniquely allocated to the respective bit strings, converts the first bit string into a second bit string having the second bit length L2, wherein the conversion information is generated by searching a clique including 2L1 or more nodes from a graph formed by nodes and edges representing the respective bit strings having the second bit length L2 satisfying predetermined constrained conditions.

Description

Technical Field

[0001] This disclosure relates to transmission path encoding technology in digital communication.

Background Art

[0002] General transmission path codes do not have an error correction function, and it is necessary to perform error correction of multiple bits in the upper layers of the physical layer and the data link layer. For example, it is difficult to use an 〖8b / 10b〗 transmission path code for bit-level error correction, and a block error correction code such as a Reed-Solomon code is performed in packet units.

[0003] To solve this problem, an encoding technology with an error correction function for a 〖4b / 10b〗 transmission path code has been proposed (Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, according to the 〖4b / 10b〗 transmission path code, the coding rate is only 60% compared to the 〖8b / 10b〗 transmission path code, and the processing ability deteriorates. Also, in the 〖4b / 10b〗 transmission path code, since 4 bits are converted into 10 bits, the overhead (the part not used for data transmission such as control information) for performing additional operations is large, which significantly affects the processing ability. Furthermore, in the 〖4b / 10b〗 transmission path code, only 20 codes that satisfy the constraint conditions required for predetermined functions such as embedded clock, DC balancing, and error detection can be detected. Therefore, only a minimum number of special characters can be assigned as control information, and it is difficult to implement additional functions such as a handshake sequence.

[0006] ]> In view of the above-mentioned problems, the object of this disclosure is to provide a transmission line code that satisfies predetermined constraints. [Means for solving the problem]

[0007] To solve the above problems, one aspect of the present disclosure includes an acquisition unit that acquires a first bit sequence of a first bit length L1, and a conversion unit that converts the first bit sequence into a second bit sequence of a second bit length L2 according to conversion information that associates each bit sequence composed of the first bit length L1 with a bit sequence of a second bit length L2 uniquely assigned to each bit sequence, wherein the conversion information is derived from a graph composed of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, L1 Generated by exploring cliques containing one or more nodes. When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) each bit sequence made up of the second bit length L2 is made up of the same number of "0" and "1" bits; 2) the run length of all bit sequences made up of the second bit length L2 is 5 or less; 3) the run length of all bit sequences made up of the second bit length L2 is 7 or less even if any one bit is inverted; 4) the run length of the bit sequence obtained by concatenating two bit sequences made up of the second bit length L2 is 5 or less; 5) the run length of the bit sequence obtained by concatenating two bit sequences made up of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted; and 6) the Hamming distance between the two bit sequences made up of the second bit length L2 is 4 or more. Regarding conversion devices. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a transmission line code that satisfies predetermined constraints. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram showing a transmission channel coding according to one embodiment of the present disclosure. [Figure 2] This figure shows an example of a computer hardware configuration according to one embodiment of the present disclosure. [Figure 3] This block diagram shows the functional configuration of a conversion device according to one embodiment of the present disclosure. [Figure 4] This is a schematic diagram showing a 1-bit flip according to one embodiment of the present disclosure. [Figure 5] This is a schematic diagram showing the concatenation of bit sequences according to one embodiment of the present disclosure. [Figure 6] This is a schematic diagram showing a 2-bit flip of a concatenated bit sequence according to one embodiment of the present disclosure. [Figure 7] This is a schematic diagram showing the Hamming distance of a bit sequence according to one embodiment of the present disclosure. [Figure 8] A flowchart showing the conversion process according to an embodiment of the present disclosure. [Figure 9] A block diagram showing the functional configuration of the inverse conversion device according to an embodiment of the present disclosure. [Figure 10] A flowchart showing the inverse conversion process according to an embodiment of the present disclosure. [Figure 11] A flowchart showing the process of creating conversion information according to an embodiment of the present disclosure. [Figure 12] A diagram showing an example of an 8b / 14b transmission line code according to an embodiment of the present disclosure. [Figure 13] A diagram showing an example of an 8b / 14b transmission line code according to an embodiment of the present disclosure. [Figure 14] A diagram showing an example of an 8b / 14b transmission line code according to an embodiment of the present disclosure. [Figure 15] A diagram showing conversion information according to an embodiment of the present disclosure. [Figure 16] A diagram showing a conversion table for 8b / 14b transmission line coding according to an embodiment of the present disclosure. [Figure 17] A diagram showing a conversion table for 8b / 14b transmission line coding according to an embodiment of the present disclosure. [Figure 18] A diagram showing a conversion table for 8b / 14b transmission line coding according to an embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described based on the drawings.

[0011] In the following embodiments, a conversion device that converts data to be transmitted into a bit string having a predetermined function such as error correction, and an inverse conversion device that restores the transmitted bit string to the original data are disclosed.

[0012] To briefly outline the embodiments described later, as shown in Figure 1, a conversion device 100 according to one embodiment of the present disclosure is a communication device equipped with a conversion circuit (encoder) 101 that converts a bit sequence of predetermined bit length L1 constituting the data to be transmitted into a bit sequence of bit length L2 (>L1) according to conversion information 10 such as a conversion table. The conversion circuit 101 is implemented by hardware logic composed of, for example, AND gates, OR gates, and flip-flops. The conversion information 10 is pre-stored in a memory area readable from the conversion circuit 101, such as a ROM (Read Only Memory), flip-flops, or storage device.

[0013] In the conversion table according to the following embodiment, each bit sequence of bit length L1 is uniquely assigned to a bit sequence of bit length L2 that satisfies constraints to provide predetermined functions such as DC balancing, clock recovery, error detection, and error correction. For example, in 8b / 14b transmission line coding, as shown in the figure, the conversion device 100 converts an 8-bit sequence "x0x1x2x3x4x5x6x7" (where xi=0 / 1) to a 14-bit sequence "y0y1y2y3y4y5y6y7y8y9y10y11y12y13" (where yi=0 / 1) according to the conversion information (conversion table) 10.

[0014] The inverse converter 200 is a communication device equipped with an inverse converter circuit (decoder) 201 that inversely converts a bit sequence of bit length L2 converted by the converter 100 into a bit sequence of bit length L1 according to the conversion information 10. The inverse converter circuit 201 is implemented by hardware logic, for example, similar to the converter circuit 101. The conversion information 10 is pre-stored in a memory area readable from the inverse converter circuit 201, for example. When the inverse converter circuit 201 receives a 14-bit sequence converted by the converter circuit 101, for example, it uses the conversion information 10 to restore the original 8-bit sequence.

[0015] Furthermore, the conversion device 100 may also have an inverse conversion circuit 201. For example, the conversion device 100 may be a communication device having a conversion / inverse conversion circuit (codec) that includes both the conversion circuit 101 and the inverse conversion circuit 201, instead of the conversion circuit 101. Similarly, the inverse conversion device 200 may also have a conversion circuit 101. For example, the inverse conversion device 200 may be a communication device having a conversion / inverse conversion circuit that includes both the conversion circuit 101 and the inverse conversion circuit 201, instead of the inverse conversion circuit 201.

[0016] According to this disclosure, in 8b / 14b transmission channel coding, 1) Each bit sequence with a bit length of 14 consists of an equal number of "0" and "1" bits. 2) The run length of all bit sequences with a bit length of 14 is 5 or less. 3) The run length of all bit sequences consisting of 14 bits is 7 or less per bit flip. 4) The run-length of the bit string obtained by concatenating two bit strings, each consisting of 14 bits, is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences, each consisting of a bit length of 14, is 11 or less after a 2-bit flip, and the distance between the two bits to be flipped is 4 bits or more, and 6) A bit sequence of bit length 14 that satisfies all six constraints, including that the Hamming distance between two bit sequences of bit length 14 is 4 or greater, is used as the converted bit sequence in the converted information 10.

[0017] Here, the bit sequence that satisfies the above constraints is the bit sequence that satisfies constraints 1) to 3) as a node, and the edges that connect the nodes that satisfy constraints 4) to 6) in a graph. 8 The bit sequence is determined by finding a clique (complete subgraph) with at least one node, particularly by finding the maximum clique. In this way, by reducing the determination of a bit sequence that satisfies a given constraint to a maximum clique search problem in a graph, it becomes possible to efficiently determine the bit sequence.

[0018] As another example, the converter 100 and the inverse converter 200 may have a typical computer 20 hardware configuration, such as that shown in Figure 2. In this case, the functions of the converter circuit 101 or the inverse converter circuit 201 in Figure 1 can be realized, for example, by a predetermined program executed by the computer 20.

[0019] Figure 2 shows an example of a computer hardware configuration according to one embodiment of the present disclosure. In the example in Figure 2, the computer 20 has a drive device 21, an auxiliary storage device 22, a memory device 23, a CPU (Central Processing Unit) 24, an interface device 25, and a communication I / F (Interface) 26, all interconnected via bus B.

[0020] Various computer programs, including programs that implement the various functions and processes of the converter 100 and inverse converter 200 as described later, may be provided on a recording medium 27 such as a CD-ROM (Compact Disk-Read Only Memory). When the recording medium 27 containing the program is set in the drive device 21, the program is installed from the recording medium 27 to the auxiliary storage device 22 via the drive device 21. However, program installation does not necessarily have to be done by the recording medium 27; it may be downloaded from an external device via a network or the like. The auxiliary storage device 22 stores the installed program as well as necessary files and data. When a program startup command is received, the memory device 23 reads the program and data from the auxiliary storage device 22 and stores them. The CPU 24, which functions as a processor, executes the various functions and processes of the converter 100 and inverse converter 200 as described later, according to the program and various data such as parameters necessary to execute the program stored in the memory device 23. The interface device 25 is used as a communication interface for connecting to a network or external device. Communication I / F26 includes transmitting and receiving circuits, etc., for communicating with external devices.

[0021] The communication I / F26 may also be a communication device including, for example, the conversion circuit 101 or the inverse conversion circuit 201 shown in Figure 1. Furthermore, the conversion device 100 and the inverse conversion device 200 are not limited to the hardware configuration described above, but may be implemented by any other suitable hardware configuration. [Conversion device] Next, a conversion device 100 according to one embodiment of the present disclosure will be described with reference to Figures 3 to 7. Figure 3 is a block diagram showing the functional configuration of the conversion device 100 according to one embodiment of the present disclosure.

[0022] As shown in Figure 3, the conversion device 100 has an acquisition unit 110 and a conversion unit 120.

[0023] The acquisition unit 110 acquires a bit sequence to be converted with a bit length L1. Specifically, when transmitting data, the acquisition unit 110 acquires the data, divides the acquired data into bit sequences of a predetermined bit length L1, and passes them to the conversion unit 120. For example, in 8b / 14b transmission channel coding, the acquisition unit 110 divides the data to be transmitted into 8-bit bit sequences and sequentially passes the divided bit sequences to the conversion unit 120.

[0024] The conversion unit 120 converts the bit sequence to be converted, acquired from the acquisition unit 110, into a bit sequence for transmission of bit length L2, according to the conversion information 10 which associates each bit sequence composed of bit length L1 with a bit sequence of bit length L2 uniquely assigned to each bit sequence. Here, the conversion information 10 is derived from a graph composed of nodes and edges representing each bit sequence composed of bit length L2 that satisfies predetermined constraints, and L1 It is generated by exploring cliques containing one or more nodes.

[0025] A bit sequence with bit length L2, which has DC balancing, clock recovery, error detection, and error correction functions, is used in the conversion information 10.

[0026] For example, in 8b / 14b transmission channel coding, the conversion information 10 shows the correspondence between each bit sequence, which consists of 8 bits, and the 14-bit bit sequence uniquely assigned to each bit sequence. The 14-bit bit sequence used in the conversion information 10 satisfies the following six constraints. 1) Each bit sequence, consisting of 14 bits in length, is composed of an equal number of "0" and "1" bits. 2) The run length of all bit sequences consisting of 14 bits is 5 or less. 3) The run length of all bit sequences consisting of 14 bits is 7 or less per bit flip. 4) The run length of the bit string obtained by concatenating two bit strings, each consisting of a 14-bit length L2, is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences, each consisting of a 14-bit length L2, is 11 or less after a 2-bit flip, and the distance between the two bits being flipped is 4 bits or more. 6) The Hamming distance between the two bit sequences, each consisting of the second bit length L2, is 4 or greater.

[0027] Constraint 1) relates to the DC balancing function, constraints 2) to 5) relate to the clock recovery function, and constraint 6) relates to the error detection and error correction function. Here, generally, the importance of the code is clock recovery function > DC balancing function >= error detection and error correction function.

[0028] In other words, a 14-bit bit sequence with DC balancing functionality consists of an equal number of "0" and "1" bits.

[0029] Furthermore, the run length of the entire 14-bit bit sequence with clock recovery functionality, i.e., the longest length of consecutive 0s or 1s, is 5 or less.

[0030] Furthermore, the run length of the entire 14-bit bit sequence with clock recovery functionality is 7 or less for each bit flip. That is, even if any one bit in the bit sequence is flipped, the run length of the resulting bit sequence is 7. 7 The following applies. For example, in the bit sequence "00010011011101" shown in Figure 4, even if the fourth bit from the most significant bit, "0", is flipped to "1", the resulting bit sequence "00000011011101" has a run-length of 6, which is less than or equal to 7.

[0031] Furthermore, the run-length of a bit sequence obtained by concatenating two 14-bit bit sequences with clock recovery functionality is 5 or less. For example, the run-length of the bit sequence "0011101110010000010011011101", obtained by concatenating the two bit sequences "0011101110010000010011011101" shown in Figure 5, is 5, and therefore 5 or less.

[0032] Furthermore, the run-length of a bit sequence formed by concatenating two 14-bit bit sequences with clock recovery functionality is determined by a 2-bit flip where the distance between the two bits to be flipped is set to 4 bits or more. 11 The following applies: That is, even if any two bits of the concatenated bit string are inverted, the run-length of the resulting bit string remains the same. 11 The following applies. For example, the bit sequence "00111011100" is obtained by concatenating the two bit sequences "00111011100100" and "00010011011101" shown in Figure 6. 1 00000 1 If we invert the 12th most significant bit and the 18th bit, which is more than 4 bits away from that bit, the resulting bit sequence "0011101110000000000011011101" has a run-length of 11, which is less than or equal to 11.

[0033] Furthermore, the Hamming distance between two 14-bit bit sequences that have error detection and error correction functions is 4 or greater. For example, the Hamming distance between the two bit sequences "11101100110000" and "00010011011101" shown in Figure 7 is 12, which is 4 or greater.

[0034] The above-mentioned conversion information 10 relates to 8b / 14b transmission line coding that realizes DC balancing function, clock recovery function, error detection function, and error correction function, but the conversion information 10 provided in this disclosure is not limited thereto. For example, more generally, for L1b / L2b transmission line coding, when L3 is a constant related to run length, L4 is a constant related to the distance between bit inversions, and L5 is a constant related to the Hamming distance, 1) Each bit sequence consists of the same number of "0" and "1" bits. 2) The run length of all bit sequences is less than or equal to L3. 3) The run length of all bit sequences is less than or equal to L3 after a 1-bit flip. 4) The run-length of the bit string obtained by concatenating two bit strings is less than or equal to L3. 5) The run length of the bit sequence obtained by concatenating two bit sequences is L3 or less for 2 bit flips separated by L4 or more bits, and the distance between the two bits to be flipped is L5 bits or more, and 6) The Hamming distance between the two bit sequences is greater than or equal to L5. The following conditions may be used. In this case, L3, L4, and L5 will be at most L2 or less. When L1 and L2 are fixed, due to the nature of transmission line codes, it is preferable that L3 and L4 be as small as possible and L5 be as large as possible. That is, the smaller L3 is, the easier it is to reconstruct the clock from the bit signal, and the smaller L4 is, the greater the tolerance of clock reconstruction to bit errors. Furthermore, the size of L5 is directly related to the strength of the code correction function, so the larger it is, the more bit errors can be corrected and detected. However, the stronger these conditions are, the smaller the maximum clique that can be found becomes, and a trade-off relationship exists. Therefore, L3 to L5 may be appropriately selected after determining L1 and L2. [Conversion process] Next, with reference to Figure 8, a conversion process according to one embodiment of the present disclosure will be described. Figure 8 is a flowchart of the conversion process according to one embodiment of the present disclosure. This process shows an example of a conversion process performed by the conversion device 100 described in Figure 3.

[0035] As shown in Figure 8, in step S101, the converter 100 acquires a bit sequence with bit length L1. For example, when it acquires the data to be transmitted, the converter 100 divides the acquired data into bit sequences with bit length L1.

[0036] In step S102, the conversion device 100 converts each bit sequence into a bit sequence of bit length L2 according to the conversion information 10. The conversion information 10 is derived from a graph consisting of nodes and edges representing each bit sequence composed of bit sequences of bit length L2 that satisfy predetermined constraints. L1 It is generated by exploring cliques containing one or more nodes.

[0037] Here, the predetermined constraints are for adding DC balancing, clock recovery, error detection, and error correction functions to a bit sequence of bit length L1. For example, in 8b / 14b transmission line coding, the predetermined constraints are: 1) Each bit sequence, consisting of bit length L2, is composed of an equal number of "0" and "1" bits. 2) The run length of all bit sequences consisting of bit length L2 is 5 or less. 3) The run length of all bit sequences consisting of bit length L2 is 7 or less with 1 bit flip. 4) The run length of the bit sequence obtained by concatenating two bit sequences of bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences of bit length L2 is 11 or less after a 2-bit flip, and the distance between the two bits to be flipped is 4 bits or more, and 6) The Hamming distance between two bit sequences, each consisting of bit length L2, is 4 or greater. It can be composed of.

[0038] The bit sequence with bit length L2 converted by the conversion device 100 is transmitted to the destination of the data to be transmitted. [Inverse converter] Next, with reference to Figure 9, an inverse converter 200 according to one embodiment of the present disclosure will be described. The inverse converter 200 acquires a bit sequence of bit length L2 converted by the converter 100 and restores the acquired bit sequence to a bit sequence of bit length L1 according to the conversion information 10. Figure 9 is a block diagram showing the functional configuration of the inverse converter 200 according to one embodiment of the present disclosure.

[0039] As shown in Figure 9, the inverse converter 200 has an acquisition unit 210 and an inverse converter unit 220.

[0040] The acquisition unit 210 acquires a bit sequence of bit length L2. Specifically, the acquisition unit 210 acquires a bit sequence of bit length L2 that has been converted by the conversion device 100 from a bit sequence of bit length L1 representing the data to be transmitted. For example, in 8b / 14b transmission channel coding, the acquisition unit 210 acquires a bit sequence of 14 bits.

[0041] The inverse conversion unit 220 inversely converts the acquired bit sequence back to a bit sequence of bit length L1 according to the conversion information 10 which associates each bit sequence composed of bit length L1 with a bit sequence of bit length L2 uniquely assigned to each bit sequence. As described above, the conversion information 10 is derived from a graph composed of nodes and edges representing each bit sequence composed of bit length L2 that satisfies predetermined constraints, and L1 It is generated by exploring cliques containing one or more nodes. For example, in 8b / 14b transmission channel coding, the inverse conversion unit 220 inversely converts the 14-bit bit sequence obtained according to the conversion information 10 into a corresponding 8-bit bit sequence. The restored bit sequences are combined to restore the data to be transmitted. [Inverse transformation process] Next, with reference to Figure 10, an inverse transformation process according to one embodiment of the present disclosure will be described. Figure 10 is a flowchart of the inverse transformation process according to one embodiment of the present disclosure. This process shows an example of the inverse transformation process performed by the inverse transformation device 200 described in Figure 9.

[0042] As shown in Figure 10, in step S201, the acquisition unit 210 of the inverse converter 200 acquires a bit sequence with bit length L2. For example, in 8b / 14b transmission line coding, the inverse converter 200 acquires a bit sequence with a length of 14 bits.

[0043] In step S202, the inverse conversion unit 220 of the inverse conversion device 200 calculates the Hamming distance between the bit sequence (bit length L2) acquired by the acquisition unit 210 and all the bit sequences (bit length L2) included in the conversion information 10.

[0044] In step S203, the inverse transformer 220 selects the bit sequence (bit length L2) with the smallest Hamming distance included in the transformed information 10.

[0045] In step S204, the inverse transformer 220 determines whether the minimum Hamming distance is 0. If the minimum Hamming distance is 0, the inverse transformer 220 proceeds to step S205. On the other hand, if the minimum Hamming distance is not 0, the inverse transformer 220 proceeds to step S206.

[0046] When the process moves to step S205, the inverse conversion unit 220 converts the bit sequence (bit length L2) selected in step S203 to a bit sequence (bit length L1) according to the conversion information 10. For example, in 8b / 14b transmission channel coding, the inverse conversion unit 220 converts a 14-bit bit sequence to an 8-bit bit sequence.

[0047] On the other hand, when the process moves from step S204 to step S206, the inverse transformer 220 determines whether the minimum Hamming distance is 1. If the minimum Hamming distance is 1, the inverse transformer 220 moves the process to step S207. On the other hand, if the minimum Hamming distance is not 1, the inverse transformer 220 moves the process to step S209.

[0048] When the process moves to step S207, the inverse transformer 220 performs 1-bit error correction on the bit sequence (bit length L2) obtained in step S201, and converts the corrected bit sequence (bit length L2) to a bit sequence (bit length L1) according to the conversion information 10. For example, in 8b / 14b transmission channel coding, the Hamming distance between any two symbols is 4 or more, so when a so-called 1-bit error occurs, where one bit in the 14 bits is inverted, there is only one symbol that matches with a Hamming distance difference of 1. Therefore, if the Hamming distance is 1, 1-bit error correction is possible. Note that if the Hamming distance is 1, as mentioned above, there is only one symbol that matches with a Hamming distance difference of 1, so the inverse transformer 220 may convert the bit sequence (bit length L2) selected in step S203 to a bit sequence (bit length L1).

[0049] In step S208, the inverse conversion unit 220 notifies the upper layer that it has performed 1-bit error correction. For example, the inverse conversion unit 220 outputs an interrupt signal (correct error) to the CPU or the like to indicate that 1-bit error correction has been performed.

[0050] On the other hand, when the process moves from step S206 to step S209, the inverse conversion unit 220 performs error detection on the bit sequence obtained in step S201 and notifies the detection result. For example, if a 2-bit error occurs during communication, the minimum Hamming distance is 2. In this case, the Hamming distance between multiple bit sequences (bit length L2) included in the conversion information 10 may be 2. In other words, since it matches with multiple bit sequences (bit length L2), error correction cannot be performed, but error detection is possible. Note that if 3 or more bits of error occur during communication, there are cases where error detection is possible and cases where it is not. (There is a possibility of incorrectly matching with another bit sequence.)

[0051] Furthermore, the inverse conversion unit 220 notifies the upper layer of the detection result detected by error detection. For example, the inverse conversion unit 220 outputs an interrupt signal (fatal error) to the CPU or the like, indicating that an error has been detected.

[0052] As shown in Figure 10, the inverse converter 200 can inversely convert the bit sequence of bit length L2 (bit length L2) converted by the converter 100 back into the data to be transmitted (bit sequence of bit length L1). Furthermore, the inverse converter 200 according to this embodiment has the feature of being able to detect and correct errors, even though it is a line code. For example, the inverse converter 200 can detect errors of up to 2 bits and correct 1 bit errors that occur during transmission in an 8b / 14b transmission line code.

[0053] <How to create conversion information> Next, a method for creating the conversion information 10 will be described. In this disclosure, in order to extract a bit sequence that satisfies predetermined constraints 1) to 6), a computer 20 as shown in Figure 2 executes a predetermined program (conversion information creation program) to perform, for example, the conversion information creation process shown in Figure 11.

[0054] In 8b / 14b transmission channel coding, the given constraints are: 1) Each bit sequence, consisting of bit length L2, is composed of an equal number of "0" and "1" bits. 2) The run length of all bit sequences consisting of bit length L2 is 5 or less. 3) The run length of all bit sequences consisting of bit length L2 is 7 or less with 1 bit flip. 4) The run length of the bit sequence obtained by concatenating two bit sequences of bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences of bit length L2 is 11 or less after a 2-bit flip, and the distance between the two bits to be flipped is 4 bits or more, and 6) The Hamming distance between two bit sequences, each consisting of bit length L2, is 4 or greater. It can be composed of

[0055] Figure 11 is a flowchart illustrating the process of creating conversion information according to one embodiment of the present disclosure. This process shows an example of the process of creating conversion information that is executed when a computer 20 executing a predetermined program creates conversion information 10.

[0056] In step S301, the computer 20 first extracts a 14-bit bit sequence that satisfies the above constraints 1) to 3) in 8b / 14b transmission channel coding, and uses the extracted bit sequence as a node in the graph.

[0057] In step S302, the computer 20 connects the extracted bit sequences with edges for pairs of bit sequences that satisfy constraints 4) to 6). This derives a graph consisting of nodes representing bit sequences that satisfy constraints 1) to 3) and edges connecting pairs of nodes that satisfy constraints 4) to 6).

[0058] In step S303, the computer 20 applies the following to the graph derived in step S302: 8 Search for cliques containing one or more nodes. The bit sequences corresponding to the nodes in the extracted cliques satisfy constraints 1) to 6).

[0059] Preferably, the computer 20 searches for the clique with the maximum number of nodes, i.e., the maximum clique, in order to make available more transmission control codes, such as special characters, in addition to the 28 bit sequences of 8 bits to be converted. Several algorithms are known for the maximum clique search problem in graphs (e.g., Tomita's MCT algorithm, Battiti and Protasi's metaheuristic-based algorithm for Reactive Local Search), and any of these maximum clique search algorithms may be used.

[0060] Here, the MCT algorithm finds an exact solution, while the Reactive Local Search algorithm finds an approximate solution. The computation time required for the Maximum Clique problem increases exponentially as the problem size increases. For this reason, in practice, the Reactive Local Search algorithm, which finds the Maximum Clique approximately, can be used in the calculation of 8b / 14b transmission line codes. For the sake of simplicity, both the exact solution and the approximate solution of the Maximum Clique will be referred to as the Maximum Clique from here on.

[0061] Applying the Reactive Local Search algorithm to 8b / 14b transmission channel coding extracts 266 bit sequences as shown in Figures 12-14. Of these 266 bit sequences, 256 are uniquely assigned to the 8-bit sequences to be converted, and the remaining 10 bit sequences are used as Special Characters for transmission control. By assigning these 266 bit sequences, a conversion table as shown in Figure 15 can be obtained. By converting the 8-bit sequences to be transmitted to 14-bit sequences according to the conversion table, DC balancing, clock recovery, error detection, and error correction functions can be added. For each bit sequence, the run length of a single code is 5, and the run length across any code is also 5, resulting in a dramatic improvement in clock recovery performance. Furthermore, the run length when a 1-bit error occurs within a code is 7, and the run length when a 1-bit error occurs in a code formed by concatenating any two codes is 8.

[0062] The codes obtained using 8b / 14b transmission channel coding in this manner have the following characteristics. 1) Clock recovery performance • If there are no bit errors, the run-length within the sign is 5. • If there are no bit errors, the run-length is 5, even across any sign. In other words, if there are no errors, in any bit sequence, consecutive 0s or 1s will always be 5 or less. 2) DC balance performance If there are no bit errors, the number of 0s and 1s in the sign will always be equal (7 out of 14 bits). 3) Error detection and correction function Error correction is possible if any single bit in the code is corrupted. • Error detection is possible if any two bits within the sign are corrupted. The following are characteristics of the error. - For any single bit error, the run-length within the sign is always 7 or less. - For any single-bit bit error, the run-length is always 8 or less, even across any sign. - For any 2-bit bit error, if the bit errors are separated by 4 bits or more, the run-length is always 11 or less, even across any sign. Furthermore, the number of control codes (K codes) is 10.

[0063] (Example of conversion information) In 8b / 14b transmission channel coding, the converter 100 and the inverse converter 200 maintain a conversion table (an example of conversion information 10) as shown in Figures 16-18, and can perform coding and decoding using this conversion table. Each bit sequence in the illustrated conversion table is assigned to DX (X=0-255) data and KY (Y=0-9) code corresponding to each 8-bit bit sequence. Note that the illustrated assignment is merely an example, and the conversion table provided in this disclosure is not limited thereto.

[0064] This code table allows any 8-bit (0-255) data and 10 types of K codes to be converted to 14b. For example, the 8-bit 128 is converted to the 14-bit "01111001001001" corresponding to D.128 in the conversion table. Similarly, the control code K.7 is converted to the 14-bit "11101010100010". The inverse converter 200 calculates the Hamming distance of all the codes and 14b in the code table for the 14-bit data to be converted (generally the received 14-bit data), and selects the code if there is a code with a Hamming distance of 0 (i.e., a perfect match in 14b), indicating no error. If there is no code with a Hamming distance of 0 (a perfect match), it selects the code if there is a code with a Hamming distance of 1, assuming a 1-bit error correction. (Only one code can have a Hamming distance of 1.) In all other cases, it detects an error.

[0065] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments described above, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0066] This application claims priority to Patent Application No. 2021-166735, filed with the Japan Patent Office on 11 October 2021, the entire contents of which are incorporated herein by reference. [Explanation of symbols]

[0067] 10 Conversion Information 100 Conversion device 110 Acquisition Department 120 Conversion Unit 200 Inverse converter 210 Acquisition Department 220 Inverse Transform Section

Claims

1. An acquisition unit that acquires a first bit sequence with a first bit length L1, A conversion unit converts the first bit sequence into a second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the first It has, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. Composed of, Conversion device.

2. The aforementioned creek is Table 1 Table 2 Table 3 The conversion device according to claim 1, comprising a group of 266 nodes corresponding to the bit sequence.

3. The conversion device is a communication device that converts the first bit sequence of first bit length L1 that constitutes the data to be transmitted into the second bit sequence of second bit length L2 for transmission according to the conversion information, The bit sequences corresponding to the 256 nodes of the aforementioned node group are uniquely assigned to each bit sequence consisting of the first bit length L1. The conversion device according to claim 2, wherein the bit sequences corresponding to the remaining 10 nodes of the node group are used for transmission control.

4. The steps include: one or more processors obtaining a first bit sequence of first bit length L1, The steps include: one or more processors converting the first bit sequence into a second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the first It has, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. Composed of, Conversion method.

5. The aforementioned creek is Table 4 Table 5 Table 6 The conversion method according to claim 4, comprising a group of 266 nodes corresponding to the bit sequence of .

6. The conversion method is performed by a communication device that converts the first bit sequence of the first bit length L1 that constitutes the data to be transmitted into the second bit sequence of the second bit length L2 for transmission, according to the conversion information. The bit sequences corresponding to the 256 nodes of the aforementioned node group are uniquely assigned to each bit sequence consisting of the first bit length L1. The conversion method according to claim 5, wherein the bit sequences corresponding to the remaining 10 nodes of the node group are used for transmission control.

7. The process of obtaining the first bit sequence with a first bit length L1, A process of converting the first bit sequence into a second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the second bit sequence of the first Have the computer run it, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. program.

8. An acquisition unit that acquires a second bit sequence with a second bit length L2, An inverse conversion unit that inversely converts the second bit sequence to the first bit sequence of It has, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. Composed of, Inverse converter.

9. The aforementioned creek is Table 7 Table 8 Table 9 The inverse transformer according to claim 8, comprising a group of 266 nodes corresponding to the bit sequence of .

10. The inverse conversion device is a communication device that inversely converts the second bit sequence of the second bit length L2 for transmission to the first bit sequence of the first bit length L1 that constitutes the data to be transmitted, according to the conversion information, The bit sequences corresponding to the 256 nodes of the aforementioned node group are uniquely assigned to each bit sequence consisting of the first bit length L1. The inverse converter according to claim 9, wherein the bit sequences corresponding to the remaining 10 nodes of the node group are used for transmission control.

11. The steps include: one or more processors obtaining a second bit sequence of second bit length L2, The steps include: one or more processors inversely converting the second bit sequence to the first bit sequence of the first bit sequence of the first bit sequence, according to conversion information relating each bit sequence consisting of a first bit sequence of bit length L1 to a bit sequence of second bit length L2 uniquely assigned to each bit sequence; It has, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. Composed of, Inverse transformation method.

12. The aforementioned creek is Table 10 Table 11 Table 12 The inverse transformation method according to claim 11, comprising a group of 266 nodes corresponding to the bit sequence of .

13. The inverse conversion method is performed by a communication device that inversely converts the second bit sequence of the second bit length L2 for transmission to the first bit sequence of the first bit length L1 that constitutes the data to be transmitted, according to the conversion information. The bit sequences corresponding to the 256 nodes of the aforementioned node group are uniquely assigned to each bit sequence consisting of the first bit length L1. The inverse transformation method according to claim 12, wherein the bit sequences corresponding to the remaining 10 nodes of the node group are used for transmission control.

14. The process of obtaining a second bit sequence with a second bit length L2, A process of inversely converting the second bit sequence to the first bit sequence of the first bit sequence of the first bit sequence, according to conversion information that associates each bit sequence consisting of a first bit sequence of bit length L1 with the second bit sequence of bit length L2 that is uniquely assigned to each bit sequence, Have the computer run it, The conversion information is obtained from a graph consisting of nodes and edges representing each bit sequence composed of the second bit length L2 that satisfies predetermined constraints, Ｌ１ Generated by exploring cliques containing one or more nodes, When the first bit length L1 is 8 and the second bit length L2 is 14, the predetermined constraints are: 1) Each bit sequence consisting of the second bit length L2 is composed of the same number of "0" and "1" bits. 2) The run length of all bit sequences composed of the second bit length L2 is 5 or less. 3) The run length of all bit sequences composed of the second bit length L2 is 7 or less even if any one bit is inverted. 4) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 5 or less. 5) The run length of the bit sequence obtained by concatenating two bit sequences composed of the second bit length L2 is 11 or less even if two bits that are 4 bits or more apart are inverted, and 6) The Hamming distance between the two bit sequences composed of the second bit length L2 is 4 or more. Composed of, program.

Images