Driver circuit and its driving method, array substrate, and display device.

Abstract

The present invention provides a driver circuit (MIC), a driving method thereof, an array substrate, and a display device, which belong to the display technology field. The driver circuit (MIC) includes a logic control module (CTR), a data pin (DataP), and at least two output pins (OUTP), the data pin (DataP) is used for receiving driving data (Data), the logic control module (CTR) is arranged to generate a driving control signal corresponding to each output pin (OUTP) one-to-one based on the driving data (Data), and the driving control signal is used for controlling a current flowing through the corresponding output pin (OUTP). The provided driver circuit (MIC) can reduce the number of driver circuits (MIC) in the array substrate.

Description

Technical Field

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[0001] The present disclosure relates to the field of display technologies, and particularly to a driver circuit, a driving method thereof, an array substrate, and a display device.

Background Art

[0002] In a liquid crystal display device, an LED (light emitting diode) array substrate having a local dimming function can be used as a backlight. By integrating a driving chip on the LED array substrate, it is possible to solve the problems that the control complexity by the conventional passive matrix scan control method is high and the light emission of the LED array is discontinuous and prone to flicker.

[0003] It should be noted that the information disclosed in the above section of the background art is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those skilled in the art.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to overcome the above-mentioned drawbacks of the prior art, and to provide a driver circuit, a driving method thereof, an array substrate, and a display device, and to reduce the usage amount of the driver circuit in the array substrate.

Means for Solving the Problems

[0005] According to one aspect of the present disclosure, a driver circuit including a logic control module, a data pin, and at least two output pins is provided. The data pin is used to receive driving data, and the logic control module is arranged to generate a driving control signal corresponding one-to-one to each of the output pins based on the driving data. The driving control signal is used to control the current flowing through the corresponding output pin.

[0006] According to one embodiment of the present disclosure, the drive data includes address information and drive information.

[0007] The logic control module is further configured to acquire the drive information of the drive data and generate the drive control signal based on the drive information of the drive data when the address information of the drive data matches the address information of the driver circuit.

[0008] According to one embodiment of the present disclosure, the driver circuit further includes an address pin and a relay pin.

[0009] The aforementioned address pin can receive an address signal.

[0010] The logic control module is further configured to arrange the address information of the driver circuit based on the address signal and to generate a relay signal, the relay signal may be the address signal of the connected driver circuit.

[0011] The relay pin is used to output the relay signal.

[0012] According to one embodiment of the present disclosure, the number of output pins is four, and the driver circuit further includes a ground pin and a chip power supply pin, the ground pin being used to apply a ground voltage to the driver circuit, and the chip power supply pin being used to apply a chip power supply voltage to the driver circuit to drive the operation of the driver circuit.

[0013] Here, each pin of the driver circuit is arranged in two pin rows, each pin row includes a plurality of pins arranged linearly, and at least one pin row includes five pins.

[0014] The four output pins are all located at the ends of the pin rows, the chip power pin and the data pin are located on different pin rows, and the address pin and the relay pin are located on the same pin row.

[0015] According to another aspect of the present disclosure, a method for driving a driver circuit is provided, wherein the driver circuit includes at least two output pins, and the method for driving the driver circuit is The device control stage includes receiving drive data, generating a drive control signal that corresponds one-to-one with each output pin based on the drive data, and using the drive control signal to control the current flowing through the corresponding output pin.

[0016] According to one embodiment of the present disclosure, the drive data includes address information and drive information, and the drive method of the driver circuit is The addressing stage further includes receiving an address signal, arranging the address information of the driver circuit based on the address signal, and generating and outputting a relay signal, wherein the relay signal may be the address signal of the connected driver circuit.

[0017] Generating a drive control signal that corresponds one-to-one with each output pin based on the drive data is: The process includes obtaining drive information for the drive data and generating a drive control signal based on the drive information for the drive data when the address information for the drive data matches the address information for the driver circuit.

[0018] According to another aspect of the present disclosure, an array substrate is provided, comprising a plurality of device control regions arranged in an array, wherein a driver circuit is installed on the array substrate, and a device unit is installed which is connected one-to-one with each of the output pins of the driver circuit, and each of the device units comprises one or a plurality of electrically connected functional elements.

[0019] According to one embodiment of the present disclosure, the device control region is arranged in a plurality of device control region columns, and any of the device control region columns includes a plurality of device control regions arranged sequentially along the column direction.

[0020] In any one of the device control region columns, a device power line and a drive data line extending along the column direction are provided on the array substrate. One end of the device unit is electrically connected to the device power line, and the other end is electrically connected to the corresponding output pin. The data pin is electrically connected to the drive data line.

[0021] According to an embodiment of the present disclosure, each of the driver circuits located in the same device control region column is cascaded in order. The driver circuit further includes an address pin and a relay pin.

[0022] In any one of the device control region columns, a plurality of address lines corresponding one-to-one to each of the driver circuits are provided on the array substrate, and each of the address lines extends along the column direction.

[0023] The address pin of the driver circuit is electrically connected to the corresponding address line, and the relay pin of the previous-stage driver circuit is electrically connected to the address line corresponding to the next-stage driver circuit.

[0024] According to an embodiment of the present disclosure, in any one of the device control region columns, a chip power line and a ground voltage line extending along the column direction are further provided on the array substrate.

[0025] The driver circuit further includes a chip power pin and a ground pin. The chip power pin is used to apply a chip power voltage for driving the operation of the driver circuit to the driver circuit. The chip power line is electrically connected to the chip power pin. The ground pin is used to apply a ground voltage to the driver circuit. The ground pin is electrically connected to the ground voltage line.

[0026] According to an embodiment of the present disclosure, in any one of the device control region columns, the device units are arranged in two device unit columns, and any one of the device unit columns includes a plurality of device units arranged in sequence along the column direction.

[0027] In any one of the device control region columns, the number of the device power lines is two, and the two device power lines are respectively located on both sides of the ground voltage line and are installed in one-to-one correspondence with the two device unit columns. Each of the device units in the device unit column is electrically connected to the corresponding device power line.

[0028] According to an embodiment of the present disclosure, in any one of the device control region columns, the address line, the drive data line, and the chip power line are all located between the device power line and the ground voltage line.

[0029] According to an embodiment of the present disclosure, in at least one of the device control region columns, a feedback line is further installed on the array substrate. In the device control region column, the relay pin of the driver circuit at the last stage is electrically connected to the feedback line, and the feedback line is located between the device power line and the ground voltage line.

[0030] According to an embodiment of the present disclosure, in two adjacent device control region columns, two adjacent device power lines are connected to each other to form one line.

[0031] According to an embodiment of the present disclosure, the array substrate includes a base substrate, a driver circuit layer, and a device layer that are stacked and installed in sequence.

[0032] Here, the driver circuit layer includes, in order, a drive line layer, a first insulating layer, and a metal wiring layer, which are laminated on the base substrate, and the thickness of the drive line layer is greater than the thickness of the metal wiring layer.

[0033] The ground voltage line, the device power line, the chip power line, the drive data line, and the address line are located in the drive line layer.

[0034] Device pads, chip pads, and wiring lines are installed on the metal wiring layer, the functional elements and the driver circuit are located on the device layer, the functional elements are connected by binding to the device pads, the driver circuit is connected by binding to the chip pads, and the device pads and chip pads and the drive line layer are electrically connected by the wiring lines.

[0035] According to another aspect of this disclosure, a display device is provided, which includes the array substrate described above.

[0036] Both the general description above and the detailed description below are illustrative and explanatory only and do not limit the scope of this disclosure.

[0037] The accompanying drawings are incorporated herein, constitute part of this specification, illustrate embodiments consistent with this disclosure, and are used together with this specification to illustrate the principles of this disclosure. The drawings in the following description are only a few embodiments of this disclosure, and it will be apparent to those skilled in the art that other drawings can be derived from these drawings without any creative effort. [Brief explanation of the drawing]

[0038] [Figure 1] This is a schematic diagram illustrating the principle at a local location on an array substrate in one embodiment of the present disclosure. [Figure 2] This is a schematic diagram of the pin configuration of a driver circuit in one embodiment of the present disclosure. [Figure 3]This is a schematic diagram illustrating the principle of a driver circuit in one embodiment of the present disclosure. [Figure 4] This is a sequence diagram of a driver circuit in one embodiment of the present disclosure. [Figure 5] This is a sequence diagram of cascaded driver circuits in one embodiment of the present disclosure. [Figure 6] This is a flowchart illustrating a method for driving a driver circuit in one embodiment of the present disclosure. [Figure 7] This is a schematic diagram of the driving process of the array substrate in an embodiment of the present disclosure. [Figure 8] This is a schematic diagram of the structure of one control region in one embodiment of the present disclosure. [Figure 9] This is a schematic diagram of the structure of two control regions adjacent to the binding region in one embodiment of the present disclosure. [Figure 10] In one embodiment of this disclosure, this is a schematic diagram of the structure of an array substrate. [Figure 11] In one embodiment of this disclosure, Figure 11 is a schematic diagram of the structure of two control regions adjacent to the binding region, and the device layer is not shown. [Figure 12] This is a schematic diagram illustrating the principle of a driver circuit in one embodiment of the present disclosure. [Figure 13] This is a schematic diagram illustrating the principle of a control circuit in one embodiment of the present disclosure. [Modes for carrying out the invention]

[0039] Next, exemplary embodiments will be described in more detail with reference to the accompanying drawings. However, exemplary embodiments can be realized in a variety of forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to fully convey to those skilled in the art the concept of the exemplary embodiments and to ensure that this disclosure is comprehensive and complete. In the drawings, the same reference numerals indicate the same or similar components, and their detailed description is omitted. Furthermore, the drawings are only schematic diagrams of this disclosure and are not necessarily drawn to scale.

[0040] In the drawings, the thickness of areas and layers may be exaggerated for clarity. In the drawings, the same reference numerals indicate the same or similar structures, and therefore their detailed descriptions are omitted. The features, structures, or properties described may be combined in any preferred manner in one or more embodiments. In the following description, many specific details are provided to provide a complete understanding of the embodiments of the disclosure. However, those skilled in the art will understand that the technical aspects of the disclosure can be carried out without one or more of the specific details, or that other methods, components, materials, etc., can be employed. In other cases, well-known structures, materials, or operations are not illustrated or described in detail to avoid obscuring the main technical idea of ​​the disclosure.

[0041] When one structure is "on top of" another structure, it may mean that one structure is integrally formed with the other structure, or that one structure is "directly" installed on the other structure, or that one structure is "indirectly" installed on the other structure by another structure.

[0042] The terms “one,” “the one,” “the said,” and “at least one” are used to indicate the presence of one or more elements / components / etc. The terms “includes” and “have” mean that they are included in an open expression and that additional elements / components / etc. may exist in addition to the listed elements / components / etc. The terms “first,” “second,” and “third” are used merely as designations and do not limit the number of items they refer to.

[0043] This disclosure provides a driver circuit and an array substrate and display device that apply the driver circuit. Figure 1 is a schematic diagram of the principle at a local location of the array substrate. Referring to Figure 1, the array substrate provided by this disclosure includes a plurality of device control regions AA arranged in an array, and within any of the device control regions AA, a driver circuit MIC and a device unit EC driven by the driver circuit MIC are installed on the array substrate. Referring to Figure 8, any of the device unit EC may include one functional element or a plurality of electrically connected functional elements FE. Optionally, referring to Figure 1, the device control regions AA are arranged in a plurality of device control region columns BB, and any device control region column BB includes a plurality of device control regions AA arranged sequentially in the column direction. Furthermore, within a single device control region column BB, each driver circuit MIC may be arranged linearly in the column direction.

[0044] Note that Figure 1 is simply intended to show the electrical connection relationships between the driver circuit MIC, the device unit EC, and each line. In Figure 1, in order to make the electrical connection relationships easier to understand, the sizes of the driver circuit MIC, the device unit EC, and each line are not drawn to scale, and the relative positions between the driver circuit MIC, the device unit EC, and each line are not shown according to their actual positions.

[0045] Optionally, in this disclosure, the driver circuit MIC may be an integrated circuit, and in particular may be a packaged chip having pins.

[0046] In this disclosure, the functional element may be a current-driven electronic element, such as a heating element, a light-emitting element, or a sound-emitting element, or it may be an electronic element that realizes a detection function, such as a photosensitive element, a thermal element, or an electroacoustic conversion element. Any device unit EC may contain one type of functional element or may contain multiple different types of electronic elements. The number, type, relative position, and electrical connection method of the functional elements contained in any two device units EC may be the same or different.

[0047] Optionally, with reference to Figure 1, each device unit EC can be distributed in an array to improve the uniformity of the distribution of the device units EC and the uniformity of the array substrate. In some embodiments of this disclosure, the functional elements in the device units EC are of the same type, for example, all are light-emitting elements. By distributing each functional element in an array on the array substrate, uniformity of the distribution of functional elements throughout the array substrate is ensured, further improving the uniformity of the array substrate. Furthermore, in each device unit EC, the number, type, relative position, and electrical connection method of the functional elements are exactly the same, for example, all are light-emitting elements. Thus, each device unit EC is identical, which is advantageous for driving and debugging the array substrate.

[0048] Optionally, at least some of the functional elements in the device unit EC may be light-emitting elements, such as LEDs (light-emitting diodes), MicroLEDs (micro light-emitting diodes), miniLEDs (mini light-emitting diodes), OLEDs (organic electroluminescent diodes), QD-OLEDs (quantum dot-organic electroluminescent diodes), QLEDs (quantum dot light-emitting diodes), PLEDs (organic polymer electroluminescent diodes), etc. In this embodiment, the array substrate can emit light when driven by a driver circuit MIC and can be applied to devices such as display devices and lighting devices.

[0049] In some embodiments, each functional element in the device unit EC is a light-emitting element, and each light-emitting element on the array substrate is distributed in an array. The display device may be a liquid crystal display device, which includes a stacked liquid crystal display module and a backlight module, and the array substrate can be the backlight of the backlight module. In this embodiment, each device unit EC can operate independently by driving a driver circuit MIC, thereby allowing each device unit EC to emit light independently. In this way, the display device can achieve local dimming, realize the HDR (High-Dynamic Range) effect, and improve the display quality of the display device. In any of the device units EC, the number of functional elements and the electrical connection method are the same. In this way, uniformity of the distribution of light-emitting elements on the array substrate can be guaranteed, improving the uniformity of light emission of the array substrate and reducing the difficulty of debugging the backlight module.

[0050] In some other embodiments, the display device may be a MicroLED display device. Here, the light-emitting element as a functional element (e.g., MicroLED, LED, etc.) may emit light to directly display a pattern. In one embodiment, the light-emitting elements may be light-emitting elements capable of emitting light of the same color, for example, they may all be blue LEDs, red LEDs, green LEDs, or yellow LEDs. Thus, the display device may be a monochrome display device or a display device such as an instrument dial or a signal indicator screen. In some other embodiments, the light-emitting elements may include multiple light-emitting elements of different colors, for example, at least two of the red LEDs, green LEDs, blue LEDs, and yellow LEDs, and each of the different colored light-emitting elements can be controlled independently. Thus, the display device can mix light to display in color.

[0051] Furthermore, in one embodiment of this disclosure, each functional element on the array substrate is distributed in an array-like manner at equal intervals in the matrix direction. Specifically, each functional element may be arranged in multiple element rows, each element row being arranged at equal intervals along the column direction, and each element row containing multiple functional elements arranged at equal intervals along the row direction. Each functional element may also be arranged in multiple element columns, each element column being arranged at equal intervals along the row direction, and each element column containing multiple functional elements arranged at equal intervals along the column direction. In this way, the uniformity of the distribution of functional elements on the array substrate can be further improved.

[0052] Optionally, each driver circuit MIC is distributed in an array-like manner in at least a portion of the array substrate. This reduces the difficulty of designing and manufacturing the array substrate, reduces the difficulty of debugging the array substrate, and reduces the cost of the array substrate and the display device. In some embodiments, each driver circuit MIC is distributed in an array-like manner on the array substrate. Furthermore, each driver circuit MIC may have the same relative position to the device unit EC it drives. In some other embodiments, referring to Figure 9, the array substrate may include adjacent first region C1 and second region C2. Here, each driver circuit MIC located in the first region is distributed in an array-like manner. The driver circuit MICs located in the second region are distributed in an array-like manner. The driver circuit MICs are not distributed in an array-like manner across the entire first and second regions. Furthermore, the relative position of the driver circuit MIC in the first region C1 with respect to the device unit EC it drives may be different from the relative position of the driver circuit MIC in the second region C2 with respect to the device unit EC it drives. Furthermore, the array substrate has a binding region, and circuit board binding pads for binding and connecting to external circuits (e.g., circuit boards, flexible circuit boards, chip-on-films, etc.) are provided within the binding region. The second region may be located at one end adjacent to the binding region of the array substrate, while the first region may be located on the side of the second region that is away from the binding region.

[0053] Exemplary, in one embodiment of the present disclosure, as shown in Figure 9, the driver circuit MIC has two output pins OUTP (e.g., Out1, Out2, etc.) for driving two device units EC. The array substrate is provided with a fan-out region and a binding region, and within the fan-out region there are fan-out lines electrically connected to the circuit board binding pads in the binding region, and the fan-out lines are electrically connected to drive lines that drive the driver circuit MIC and the device units EC. Here, in the array substrate, each device control region AA closest to the binding region can constitute a second region C2, and the remaining control regions AA can constitute a first region C1. Thus, the second region C2 can overlap with the fan-out region, and in particular each device unit EC in the second region C2 can overlap with the fan-out region. In the control region AA in the second region C2, the driver circuit MIC may be located on one side away from the binding region of the two device units EC. In the control region AA in the first region C1, the driver circuit MIC may be located on the side closer to the binding region of the two device units EC.

[0054] Furthermore, the array substrate of this disclosure incorporates a driver circuit for driving the device unit, which simplifies the external circuit that drives the array substrate and simplifies its control method, thereby contributing to the miniaturization of the external circuit. In particular, this can reduce the volume of the integrated circuit in the external circuit and thus reduce the cost of the integrated circuit, while also reducing the area of ​​the circuit board in the external circuit.

[0055] Referring to Figure 3, the driver circuit MIC provided by this disclosure includes a logic control module CTR, a data pin DataP, and at least two output pins OUTP, wherein the data pin DataP is used to receive drive data Data, and the logic control module CTR is configured to generate a drive control signal that corresponds one-to-one with each output pin OUTP based on the drive data Data, and the drive control signal is used to control the current flowing through the corresponding output pin OUTP. Referring to Figures 1 and 3, in either device control region AA, a device unit EC on the array substrate is installed in one-to-one correspondence with each output pin OUTP of the driver circuit MIC. Across the entire array substrate, each device unit EC is installed in one-to-one correspondence with each output pin OUTP.

[0056] Thus, the driver circuit MIC receives drive data during the device control phase, generates a drive control signal that corresponds one-to-one with each output pin OUTP based on the drive data, and the drive control signal can be driven by a drive method that controls the current flowing through the corresponding output pin OUTP.

[0057] According to this driving method, the logic control module CTR of the driver circuit MIC can control the current flowing through the output pin OUTP based on the driving data Data, thereby controlling the driving current flowing through the device unit EC electrically connected to the output pin OUTP, and realizing control and driving of the device unit EC. The driver circuit MIC of this disclosure can drive at least two device unit ECs simultaneously, thereby reducing the number of driver circuit MICs on the array substrate and lowering the cost of the array substrate. In addition, because the amount of driver circuit MICs used is reduced, the manufacturing difficulty of the array substrate is further reduced, and the impact of the driver circuit binding yield on the array substrate yield is reduced, thereby improving the yield of the array substrate. When there are multiple driver circuit MICs arranged in an array, multiple driver MICs can simultaneously provide driving signals to multiple device unit ECs connected to them, that is, to operate device unit ECs driven by multiple different driver MICs simultaneously. As can be understood, in order to ensure the stability of the driver circuit MIC and extend the service life of the driver circuit MIC, the "simultaneous driving" and "simultaneous operation" described in this disclosure may have a temporal sequence at the nanosecond level.

[0058] In one embodiment of the present disclosure, referring to Figure 3, four output pins OUTP are provided on a single driver circuit MIC, namely, a first output pin Out1, a second output pin Out2, a third output pin Out3, and a fourth output pin Out4. In this way, the driver circuit MIC of the present disclosure can drive four device units EC simultaneously. Compared to a method in which one driver circuit MIC drives one device unit EC, the number of driver circuit MICs is reduced to one-quarter, significantly reducing the amount of driver circuit MICs used and thereby lowering the cost of the array substrate.

[0059] Although the driver circuit MIC of this disclosure has a slightly larger volume than a driver circuit with only one output pin, this disclosure can significantly reduce the amount of driver circuit MIC used, thereby achieving significant improvements in reducing the overall area occupancy of the driver circuit MIC, improving the binding efficiency of the driver circuit MIC, and improving the yield of the array substrate. Exemplarily, in one embodiment of this disclosure, the driver circuit MIC of this disclosure has four output pins OUTP, and its area is twice that of a driver circuit MIC with only one output pin OUTP. However, the amount of driver circuit MIC used in this disclosure can be reduced to one-quarter, thereby reducing the area occupancy of the driver circuit MIC on the array substrate of this disclosure to one-half (for an array substrate in which one driver circuit MIC drives one device unit EC).

[0060] Referring to Figure 1, in any one device control region column BB, a device power line VLEDL and a drive data line DataL are installed on the array substrate, extending along the column direction. One end of the device unit EC is electrically connected to the device power line VLEDL, and the other end is electrically connected to the corresponding output pin OUTP (for example, any one of Out1 to Out4). The data pin DataP is electrically connected to the drive data line DataL.

[0061] Optionally, in either device control region column BB, device units EC are arranged in two device unit columns, and either device unit column contains multiple device units EC arranged sequentially along the column direction. In either device control region column BB, there are two device power lines VLEDL. The two device power lines VLEDL are arranged in a one-to-one correspondence with the two device unit columns. Each device unit EC in a device unit column is connected to the device power line VLEDL closest to it (i.e., the device power line VLEDL corresponding to that device unit EC).

[0062] Furthermore, in one embodiment of the present disclosure, in two adjacent control region rows, two adjacent device power lines VLEDL can be connected to each other to form a single line, i.e., the two adjacent device power lines VLEDL are integrated into a single device power line VLEDL'. Thus, the integrated device power line VLEDL' may be installed corresponding to two device unit rows, and each device unit EC in the two device unit rows is connected to the integrated device power line VLEDL'. The width of the integrated device power line VLEDL' may be greater than the device power line VLEDL connected to the device unit row closest to the edge of the array substrate, and the integrated device power line VLEDL' may include a hollow portion. Naturally, the width of the integrated device power line VLEDL' may be the same as the width of the device power line VLEDL connected to the device unit row closest to the edge of the array substrate.

[0063] In this embodiment, an external circuit (e.g., a circuit board) can provide drive data Data to the drive data line DataL, thereby transmitting the drive data Data to the data pin DataP. The external circuit can further provide the device power supply voltage VLED to the device unit EC via the device power supply line VLEDL. Furthermore, the driver circuit MIC includes a ground pin GNDP, which is used to apply the ground voltage GND to the driver circuit MIC. In any device control region column BB, a ground voltage line GNDL is provided on the array substrate extending along the column direction, and the ground pin GNDP is electrically connected to the ground voltage line GNDL. The external circuit can apply the ground voltage GND to the ground voltage line GNDL, thereby loading the ground voltage GND to the driver circuit MIC. Thus, the device unit EC is connected between the device power supply line VLEDL and the ground voltage line GNDL. The logic control module CTR controls the on / off state of the current path of the device unit EC via the output pin OUTP, thereby controlling the current passing through the device unit EC and the output pin OUTP.

[0064] Optionally, in any device control region row BB, there are two device power lines VLEDL. The two device power lines VLEDL are located on either side of the ground voltage line GNDL.

[0065] Optionally, in any device control region row BB, the driver circuit MIC may be positioned to overlap with the ground voltage line GNDL in order to provide electromagnetic shielding to the driver circuit MIC by the ground voltage GND loaded onto the ground voltage line GNDL.

[0066] Optionally, referring to Figure 3, the logic control module CTR may include a control module CLM and modulation modules (e.g., PWMM1 to PWMM4 in Figure 3) arranged in one-to-one correspondence with each output pin OUTP. Each modulation module is electrically connected to its corresponding output pin OUTP. The control module CLM is configured to generate a drive control signal corresponding one-to-one with each modulation module by drive data Data. The drive control signal is used to control the on or off of the corresponding modulation module, thereby controlling the electrical conduction or interruption between the output pin OUTP and the ground voltage line GNDL, and thereby achieving control over the device unit EC. In some embodiments, the drive control signal controls the modulation module, thereby converting the signal flowing through the modulation module (and the output pin OUTP connected to the modulation module, and the device unit EC) into a pulse-width modulated signal. The drive control signal is used to modulate the pulse-width modulated signal, for example, by adjusting elements such as the duty cycle of the pulse-width modulated signal, thereby controlling the average current flowing through the output pin OUTP and the device unit EC.

[0067] Exemplary, in one embodiment of the present disclosure, with reference to Figures 1 to 3, the driver circuit MIC includes four output pins OUTP, which are the first to fourth output pins Out1 to Out4, respectively. The logic control module CTR includes four modulation modules, namely, the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4. The first to fourth output pins Out1 to Out4 are connected in a one-to-one correspondence with the first to fourth modulation modules PWMM1 to Out4. The control module CLM is used to generate the first, second, third, and fourth drive control signals based on the drive data Data, and to transmit them to the first, second, third, and fourth modulation modules PWMM1, PWMM2, PWMM3, and PWMM4, respectively.

[0068] The first modulation module PWMM1 is electrically connected to the first output pin Out1 and can be turned on or off under the control of the first drive control signal, thereby turning the connection between the first output pin Out1 and the ground voltage line GNDL on or off. When the first modulation module PWMM1 is turned on, the ground voltage line GNDL, the first output pin Out1, the device unit EC electrically connected to the first output pin Out1, and the device power line VLEDL form a signal circuit, and the device unit EC operates. When the first modulation module PWMM1 is turned off, the above signal circuit is disconnected, and the device unit EC does not operate. In this way, the first modulation module PWMM1 can modulate the current flowing through the device unit EC under the control of the first drive control signal, thereby representing the current flowing through the device unit EC as a pulse width modulated signal. Based on the first drive control signal, the first modulation module PWMM1 can modulate elements such as the duty cycle of the pulse width modulated signal flowing through the device unit EC, thereby controlling the operating state of the device unit EC. If the device unit EC includes LEDs, increasing the duty cycle of the pulse width modulation signal can improve the total illumination time of the LEDs within a single display frame, further increasing the total luminous brightness of the LEDs within that display frame, thereby increasing the brightness in that area of ​​the array substrate. Conversely, decreasing the duty cycle of the pulse width modulation signal can decrease the total illumination time of the LEDs within a single display frame, further decreasing the total luminous brightness of the LEDs within that display frame, thereby reducing the brightness in that area of ​​the array substrate.

[0069] Correspondingly, the second modulation module PWMM2 is electrically connected to the second output pin Out2 and can be turned on or off under the control of the second drive control signal, thereby indicating the current flowing through the device unit EC connected to the second output pin Out2 as a pulse-width modulated signal. The third modulation module PWMM3 is electrically connected to the third output pin Out3 and can be turned on or off under the control of the third drive control signal, thereby indicating the current flowing through the device unit EC connected to the third output pin Out3 as a pulse-width modulated signal. The fourth modulation module PWMM4 is electrically connected to the fourth output pin Out4 and can be turned on or off under the control of the fourth drive control signal, thereby indicating the current flowing through the device unit EC connected to the fourth output pin Out4 as a pulse-width modulated signal.

[0070] In one embodiment of this disclosure, the first modulation module PWMM1 to the fourth modulation module PWMM4 may be switch elements, and may be transistors such as MOS (metal-oxide-semiconductor field-effect transistors) and TFT (thin-film transistors). The first to fourth drive control signals may be pulse-width modulated signals, and the switch elements are turned on or off under the control of the pulse-width modulated signals.

[0071] Optionally, as described in this disclosure with reference to Figure 3, the first modulation module PWMM1 to the fourth modulation module PWMM4 may be electrically connected to the control module CLM via a data bus DB, or each may be electrically connected to the control module via data lines, or otherwise electrically connected to the control module, and this disclosure is not particularly limited thereto.

[0072] In one embodiment of the present disclosure, the control module CLM may include a DataLink circuit and a ControlLogic module circuit, the DataLink circuit being used to electrically connect to circuits / modules or structures other than the Control Module CLM, for example, to electrically connect to an address pin Di_in, a data pin DataP, and a data bus DB, and the ControlLogic module circuit being used to receive external signals (e.g., an address signal input by data pin DataP, drive data input by data pin DataP) via the DataLink circuit, and to generate drive control signals (e.g., outputting a first drive control signal to a fifth drive control signal) and output them via the DataLink circuit.

[0073] In some embodiments, the drive data includes address information and drive information, and the logic control module CTR is further configured to acquire the drive information of the drive data if the address information of the drive data matches the address information of the driver circuit MIC, and to generate a drive control signal using the drive information of the drive data.

[0074] Thus, the method for driving the driver circuit MIC can further include the following: In the addressing stage, an address signal is received, the address information of the driver circuit MIC is assigned based on the address signal, and a relay signal is generated and output. The relay signal can be the address signal of the connected driver circuit MIC. In the device control stage, generating a drive control signal that corresponds one-to-one with each output pin OUTP based on the drive data can be achieved by acquiring the drive information of the drive data when the address information of the drive data matches the address information of the driver circuit MIC, and generating a drive control signal using the drive information of the drive data.

[0075] Optionally, an encoder may be provided in an external circuit (e.g., a circuit board), and a decoder may be provided in the logic control module CTR. The encoder can encode according to a 4b / 5b coding protocol, an 8b / 10b coding protocol, or another coding protocol to generate drive data Data and transmit it to the drive data line DataL. The decoder of the logic control module CTR can decode the drive data Data and obtain address information and drive information in the drive data Data.

[0076] Thus, in the array substrate, referring to Figure 1, the data pins DataP of multiple driver circuit MICs can be connected to the same drive data line DataL. Multiple different drive data Data can be loaded onto the drive data line DataL, and each driver circuit MIC can determine the corresponding drive data Data based on the address information where it is placed, and drive the respective connected device unit EC based on the corresponding drive data Data. In this disclosure, the driver circuit MIC can receive drive data Data via the data pin DataP, and the array substrate can transmit drive data Data via the drive data line DataL. Therefore, the problem of having too many pads and lines due to transmitting data using SPI (Serial Peripheral Interface) can be avoided, and the structure of the array substrate, external circuitry, and driver circuit MICs can be simplified, thereby reducing the cost of the array substrate and driver circuit MICs. In one embodiment of this disclosure, referring to Figure 1, one device control area column BB is equipped with one column of driver circuit MICs and one drive data line DataL, and the data pins DataP of each driver circuit MIC are all connected to the drive data line DataL.

[0077] Optionally, in this disclosure, the driver circuit MIC may have address information pre-configured, or the address information may be configured after power-on. In one embodiment of this disclosure, address information can be assigned to each driver circuit MIC after power-on, and such address information may be dynamic addresses.

[0078] Illustratively, referring to Figures 1 and 3, the driver circuit MIC may further include an address pin Di_in and a relay pin Di_out. Here, the address pin Di_in can receive an address signal, and the logic control module CTR is further configured to place the address information of the driver circuit MIC based on the address signal and generate a relay signal. The relay signal may be the address signal of the connected driver circuit MIC, and the relay pin Di_out is used to output the relay signal. In this disclosure, when the driver circuit MICs are cascaded, the next stage driver circuit MIC is the connected driver circuit MIC to the previous stage driver circuit MIC. In this way, when multiple driver circuit MICs on an array board are sequentially cascaded, the previous stage driver circuit MIC can place the address information of the next stage driver circuit MIC based on its own address information, thereby enabling the assignment of dynamic addresses to the cascaded driver circuit MICs.

[0079] In one embodiment of this disclosure, the address information may be a digital signal, which may be modulated into the address signal. After one driver circuit MIC receives an address signal, it can analyze, acquire, and store the address information in the address signal, and can also increment the address information by 1 or a fixed amount and modulate the incremented address information (new address information) into a relay signal, which becomes the address signal of the next driver circuit MIC. Naturally, the driver circuit MIC can generate new address information using other different functions.

[0080] In one embodiment of the present disclosure, with reference to Figure 3, the logic control module CTR may further include a fifth modulation module PWMM5, which is electrically connected to the relay pin Di_out. The control module CLM can receive an address signal from the address pin Di_in, generate a relay control signal based on the address signal, and transmit it to the fifth modulation module PWMM5. The fifth modulation module PWMM5 can generate a relay signal in response to the relay control signal and load it to the relay pin Di_out.

[0081] In this disclosure, the fifth modulation module PWMM5 may be electrically connected to the control module CLM via a data bus DB, electrically connected to the control module via a dedicated data line, or electrically connected to the control module in any other way, and this disclosure is not particularly limited thereto.

[0082] Exemplary, with reference to Figure 3, in one embodiment of the present disclosure, the driver circuit MIC further includes a data bus DB, and the first modulation modules PWMM1 to the fifth modulation modules PWMM5 and the control module CLM are all connected to the data bus DB, thereby causing the control module DB to interact with the first modulation modules PWMM1 to the fifth modulation modules PWMM5.

[0083] In one embodiment of this disclosure, the fifth modulation module PWMM5 may include a switch element, such as a transistor like a MOS (metal-oxide-semiconductor field-effect transistor) or a TFT (thin-film transistor). The relay control signal may be a pulse-width modulated signal, and the switch element is turned on or off under the control of the pulse-width modulated signal. When the switch element is on, the fifth modulation module PWMM5 may output a current or voltage, and when the switch element is off, the fifth modulation module PWMM5 may not output a current or voltage. In this way, the fifth modulation module PWMM5 can modulate one pulse-width modulated signal to create a relay signal.

[0084] Optionally, referring to Figure 1, each driver circuit MIC located in the same device control area column BB is sequentially cascaded. In any device control area column BB, multiple address lines ADDRL are installed on the array substrate, each corresponding one-to-one with each driver circuit MIC, and each address line ADDRL extends along the column direction. The address pin Di_in of the driver circuit MIC is electrically connected to the corresponding address line ADDRL, and the relay pin Di_out of the preceding driver circuit MIC is electrically connected to the address line ADDRL corresponding to the next driver circuit MIC. In this way, in the device control area column BB, the cascaded driver circuits MIC can be electrically connected via the address lines ADDRL, and the relay signal of the preceding driver circuit MIC can be loaded into the address line ADDRL corresponding to the next driver circuit MIC, and becomes the address signal of the next driver circuit MIC. Furthermore, an external circuit can load an address signal into the address line ADDRL corresponding to the first driver circuit MIC.

[0085] Referring to Figure 1, in one embodiment of the present disclosure, in any device control region row BB, the extension direction of each address line ADDRL is the same. In other words, the extension lines of each address line ADDRL can overlap. Thus, in the row direction, each address line ADDRL can occupy only the width of one address line ADDRL, which avoids address lines ADDRL occupying a large line space in the row direction and is advantageous in increasing the width of lines such as the device power line VLEDL and the ground voltage line GNDL, thereby reducing the sheet resistance of these lines.

[0086] Referring to Figure 1, in one embodiment of the present disclosure, in any device control region row BB, each address line ADDRL is located between the device power line VLEDL and the ground voltage line GNDL.

[0087] In one embodiment of the present disclosure, with reference to Figure 1, a feedback line FBL is further provided on the array substrate in at least one device control region row BB. In a plurality of sequentially cascaded driver circuits MIC, the relay pin Di_out of the final stage driver circuit MIC can be connected to the feedback line FBL.

[0088] Furthermore, the array board may include multiple signal channels, each signal channel including one device control area row BB or multiple sequentially adjacent device control area row BBs. Within a single signal channel, each driver circuit MIC is sequentially cascaded. Within any signal channel, at least one feedback line FBL may be provided on the array board, thereby electrically connecting the relay pin Di_out of the final stage driver circuit MIC in that signal channel to the feedback line FBL. Exemplarily, referring to Figure 1, one signal channel includes one device control area row BB. Further exemplarily, referring to Figure 1, any device control area row BB has one feedback line FBL. Optionally, in a device control area row BB, the feedback line FBL is located between the ground voltage line GNDL and the device power supply line VLEDL.

[0089] Optionally, referring to Figures 1 and 3, the driver circuit MIC further includes a chip power supply pin VCCP, which is used to load the chip power supply voltage VCC into the driver circuit MIC to drive the operation of the driver circuit MIC. Furthermore, the driver circuit MIC may further include a power supply module PWRM, where the chip power supply pin VCCP can load the chip power supply voltage VCC into the power supply module PWRM, and the power supply module is arranged to distribute power to each circuit of the driver circuit MIC to ensure power supply to the driver circuit MIC.

[0090] Referring to Figure 1, in the device control region column BB, a chip power line VCCL can be installed on the array substrate, extending along the column direction, and an external circuit can apply the chip power supply voltage VCC to the driver circuit MIC via the chip power supply line VCCL. Furthermore, referring to Figure 1, the chip power supply line VCCL is located between the device power supply line VLEDL and the ground voltage line GNDL.

[0091] In this embodiment, the array substrate loads the chip power supply voltage VCC and drive data Data using different lines, simplifying the internal circuit structure of the driver circuit. This eliminates the need to install a power adjustment circuit (which generates the chip power supply voltage based on the DC component of the power supply signal and generates drive data based on the modulation component of the power supply signal) within the driver circuit, thereby reducing the area of ​​the driver circuit. Furthermore, this installation method simplifies the configuration of external circuits, avoids the installation of a modulation circuit that modulates the chip power supply voltage and drive data for power line carrier communication, and reduces the quality requirements for the chip power supply voltage. Therefore, the driver circuit and array substrate installation method of this disclosure simplifies the structure of the driver circuit and external circuits and reduces their costs. Moreover, the array substrate loads the chip power supply voltage VCC and drive data Data using different lines, further ensuring the signal quality of the chip power supply voltage VCC and drive data Data, and further improving the stability of the array substrate and the accuracy of local dimming.

[0092] Naturally, in other embodiments of this disclosure, the data pin DataP and the chip power pin VCCP of the driver circuit MIC may be integrated into a single power pin. A power line may be provided on the array board, and the power pin is electrically connected to the power line. Here, an external circuit (e.g., a circuit board) can modulate the chip power voltage VCC and drive data Data into a power line carrier communication signal and transmit it to the power line. The power line transmits the power line carrier communication signal to the driver circuit MIC. The driver circuit MIC is configured to generate the chip power voltage VCC and drive data Data based on the power line carrier communication signal, and to generate drive control signals that correspond one-to-one with each of the output pins based on the drive data. Furthermore, a power adjustment circuit is provided within the driver circuit, which is used to generate the chip power voltage VCC based on the DC component of the power line carrier communication signal, and to generate the drive data Data based on the modulation component of the power line carrier communication signal PWR.

[0093] In an exemplary embodiment, referring to Figures 2 and 3, the driver circuit MIC includes at least two output pins OUTP, a data pin DataP, an address pin Di_in, a relay pin Di_out, a ground pin GNDP, and a chip power supply pin VCCP. Referring to Figures 4 to 6, the driver circuit MIC can drive the connected device unit EC by the driving method shown in the following steps S110 to S140, thereby driving the array board.

[0094] In step S110, during the power-on phase T1, the chip power supply voltage VCC is received. In this step, the external circuit can apply the chip power supply voltage VCC to the chip power supply line VCCL, and the chip power supply voltage VCC can be loaded onto the driver circuit MIC via the chip power supply pin VCCP, thereby supplying power to the driver circuit MIC. In this way, the driver circuit MIC is in the power-on state.

[0095] Optionally, when the display device of this disclosure is in operation, an external circuit may simultaneously load the chip power supply voltage VCC onto each chip power supply line VCCL, thereby simultaneously powering on each driver circuit MIC on the array board.

[0096] Optionally, when the display device is started and an external circuit (e.g., the circuit board of the drive array board) is powered on, the external circuit can load the chip power supply voltage VCC onto the chip power supply line VCCL, thereby synchronizing the power-on of the driver circuit MIC with the startup of the display device.

[0097] In step S120, during the address placement stage T2, the address signal is received, the address information of the driver circuit MIC is placed based on the address signal, and a relay signal is generated and output. The relay signal can be the address signal of the next stage driver circuit MIC (i.e., the connected driver circuit MIC). Here, the driver circuit MIC can receive the address signal on the address line ADDRL connected via the address pin Di_in. If the address line ADDRL is electrically connected to an external circuit, the address signal may be the address signal loaded into the address line ADDRL by the external circuit. If the address line ADDRL is electrically connected to the previous stage driver circuit MIC, the address signal on the address line ADDRL may be the relay signal output from the previous stage driver circuit MIC. Here, the driver circuit MIC can output the relay signal via the relay pin Di_out.

[0098] Illustratively, referring to Figure 5, in a cascaded driver circuit MIC, Di_out(n-1) is the relay pin Di_out of the (n-1)th stage driver circuit MIC. Di_in(n) is the address pin Di_in of the nth stage driver circuit MIC. Di_out(n) is the relay pin Di_out of the nth stage driver circuit MIC. Di_in(n+1) is the address pin Di_in of the (n+1)th stage driver circuit MIC. Referring to Figure 5, in the addressing stage T2, the same signal is loaded into Di_out(n-1) and Di_in(n), i.e., the relay signal output from the (n-1)th stage driver circuit MIC is used as the address signal of the nth stage driver circuit MIC. The same signal is loaded into Di_out(n) and Di_in(n+1), i.e., the relay signal output from the nth stage driver circuit MIC is used as the address signal of the (n+1)th stage driver circuit MIC. In this example, 2 ≤ n ≤ n-1. Here, n is a positive integer, and N is the total number of driver circuits MICs that have a cascaded connection relationship.

[0099] In step S120, in a series of cascaded driver circuit MICs, the external circuit can load an address signal into the first-stage driver circuit MIC, thereby causing the first-stage driver circuit MIC to place the address information. Next, the preceding driver circuit MIC outputs a relay signal to the next-stage driver circuit MIC, which then places the address information, and this process continues until the last driver circuit MIC places the address information, thus achieving the placement of address information in each driver circuit MIC.

[0100] In step S130, during the drive placement stage T3, the drive placement signal is received, and the driver circuit MIC is initialized based on the drive placement signal. Here, the external circuit can load the drive placement signal onto the drive data line DataL, and the driver circuit MIC can load the drive placement signal via the data pin DataP.

[0101] Selectively, each driver circuit MIC connected to the same drive data line DataL can simultaneously receive the drive placement signal and perform initialization placement.

[0102] Optionally, the external circuit can simultaneously load a drive placement signal onto each drive data line (DataL), allowing each driver circuit (MIC) to simultaneously receive the drive placement signal and complete its initialization, thereby reducing the time it takes for the array board to perform the initialization on the driver circuits (MIC).

[0103] In step S140, during the device control stage T4, the driver circuit MIC receives drive data Data and generates a drive control signal that corresponds one-to-one with each output pin OUTP based on the drive data Data. The drive control signal is used to control the current flowing through the corresponding output pin OUTP. In this way, the driver circuit MIC can control the current flowing through the device unit EC by the action of the device power supply voltage VLED loaded onto the device power supply line VLEDL, thereby achieving the objective of driving each connected device unit EC based on the drive data Data. In step S140, the external circuit can load drive data Data onto the drive data line DataL, and the driver circuit MIC receives the drive data Data via the data pin DataP.

[0104] In one embodiment of this disclosure, the drive data includes address information and drive information. When the address information of the drive data matches the address information of the driver circuit MIC, the drive information of the drive data is obtained, and a drive control signal is generated based on the drive information of the drive data.

[0105] Optionally, the method for driving the driver circuit MIC may further include step S150, in which the driver circuit MIC is in a power-down state and does not operate during the power-down phase T5. Optionally, the chip power supply voltage VCC may not be applied to the chip power supply line VCCL, thereby putting the driver circuit MIC into a power-down state. Further optionally, the driver circuit IC powers down when the external circuit driving the array board powers down. In other words, when the display device is shut down, the driver circuit IC powers down and enters the power-down phase.

[0106] Selectively, Figure 7 is a schematic diagram of the drive process of the array substrate. Referring to Figure 7, when the array substrate is operating, it may further include applying the device power supply voltage VLED to the device power supply line VLEDL before the device control step T4. In this way, the device unit EC can operate under the control of the driver circuit MIC, and for example, the light-emitting element can emit light under the control of the driver circuit MIC.

[0107] In some embodiments of the present disclosure, the number of output pins OUTP is four, and the driver circuit MIC further includes a data pin DataP, an address pin Di_in, a relay pin Di_out, a ground pin GNDP, and a chip power supply pin VCCP. Thus, in the device control region row BB, the array substrate may be provided with a drive data line DataL electrically connected to the data pin DataP, an address line ADDRL electrically connected to the address pin Di_in or relay pin Di_out, a ground voltage line GNDL electrically connected to the ground pin GNDP, a chip power supply line VCCL electrically connected to the chip power supply pin VCCP, and a device power supply line VLEDL for applying the device power supply voltage VLED to the device unit EC.

[0108] In this embodiment, the pins of the driver circuit MIC may be arranged in multiple rows, which is advantageous for the manufacture of the driver circuit MIC. For example, the pins of the driver circuit MIC may be arranged in three rows (three pins per row) or in two rows.

[0109] In one embodiment of the present disclosure, each pin of the driver circuit MIC (including, for example, the ground pin GNDP, the chip power pin VCCP, the data pin DataP, the address pin Di_in, the relay pin Di_out, and the output pin OUTP) is arranged in two pin rows, each pin row containing a plurality of pins arranged in a straight line, and at least one pin row containing five pins. In other words, one of the pin rows may contain five pins, and the other pin row may contain the remaining pins. Here, all four output pins OUTP are located at the ends of the pin rows, which is advantageous for the four output pins OUTP to be electrically connected to four device units EC, respectively.

[0110] Optionally, the driver circuit MIC has two ground pins GNDP. In this way, the driver circuit MIC has 10 pins, with each pin row containing 5 pins, which is advantageous for the uniformity of each pin and facilitates the manufacture of the driver circuit MIC. Furthermore, the two ground pins GNDP are located in the same pin row to facilitate wiring. Moreover, the two ground pins GNDP are placed adjacent to each other. Alternatively, the driver circuit MIC may have one ground pin GNDP, resulting in a driver circuit MIC with 9 pins. Furthermore, a pin row containing a ground pin GNDP has 4 pins.

[0111] Optionally, the chip power pin VCCP and the data pin DataP may be located on different pin rows. Thus, the chip power pin VCCP and the data pin DataP may be located on opposite sides of the ground voltage line GNDL. Of course, the chip power pin VCCP and the data pin DataP may also be located on the same pin row. Thus, the chip power line VCCL and the drive data line DataL may be located on the same side of the ground voltage line GNDL.

[0112] Optionally, the address pin Di_in and the relay pin Di_out are located on the same pin row. In this way, when the relay pin Di_out of the preceding driver circuit MIC and the address pin Di_in of the subsequent driver circuit MIC are connected to the same address line ADDRL, the wiring of the array board becomes easier, the overlapping area between lines can be reduced, and the yield of the array board can be improved.

[0113] For example, in one embodiment of this disclosure, with reference to Figure 2, one pin row may include the address pin Di_in, the chip power supply pin VCCP, and the relay pin Di_out, arranged in order. Another pin row may include the data pin DataP and the ground pin GNDP. This example is merely one form of pin arrangement for the driver circuit MIC, and the pins of the driver circuit MIC may be arranged in other forms as well. For example, the address pin Di_in, the data pin DataP, and the relay pin Di_out may be placed on one pin row, and the chip power supply pin VCCP and the ground pin GNDP may be placed on another pin row.

[0114] Optionally, the distance between the pins of the driver circuit MIC and the edges of the driver circuit MIC may be 25 to 40 micrometers, which facilitates the manufacture of the driver circuit and avoids increasing the area of ​​the driver circuit due to an excessively large distance.

[0115] In this disclosure, the direction of pin arrangement in a pin row may be defined as the first direction, and the direction of arrangement of two pin rows may be defined as the second direction. Optionally, the distance between two adjacent pins in the same pin row may be 0.8 to 1.2 times the pin size in the first direction. In this way, on the one hand, the process window for binding pins to chip pads can be expanded, reducing binding defects due to misalignment, and on the other hand, the driver circuit area that would increase due to excessive spacing between two pins can be avoided, further reducing the driver circuit area and thus lowering the cost of the array substrate. Exemplarily, the pin size of the driver circuit in the first direction may be in the range of 80 to 120 micrometers, and the pitch between two adjacent pins in the first direction may be in the range of 80 to 100 micrometers.

[0116] Optionally, the distance between two adjacent pin rows may be 0.8 to 1.2 times the pin size in the second direction. In this way, on the one hand, the process window for binding the pins to the chip pads can be expanded, reducing binding defects due to misalignment, and on the other hand, the driver circuit area that would increase due to excessive spacing between two pins can be avoided, further reducing the driver circuit area and thus lowering the cost of the array substrate. Exemplaryly, the pin size of the driver circuit in the second direction may be in the range of 120 to 150 micrometers, and the pitch between two adjacent pins in the second direction may be in the range of 130 to 170 micrometers.

[0117] Figure 12 is an example of a driver circuit MIC of the present disclosure. In this example, only the first modulation module PWMM1 is shown, and other modulation modules are not shown. Referring to Figure 12, in this example, the driver circuit MIC may include a voltage regulation circuit C310, a low dropout regulator C330, an oscillator C340, a control logic module CLM, an address driver C360, a dimming circuit C370, a transistor C375, and a brightness control circuit C380. In various embodiments, the driver circuit MIC may include additional, fewer, or different components.

[0118] The voltage regulating circuit C310 adjusts the chip power supply voltage VCC, received at the chip power supply pin VCCP, to obtain the DC component of the chip power supply voltage VCC, thereby generating the feed voltage. In an exemplary embodiment, the voltage regulating circuit C310 includes a primary RC filter followed by an active follower. The feed voltage is supplied to a low-dropout regulator C330. The low-dropout regulator C330 converts the feed voltage into a regulated DC voltage (which may be gradually stepped down) to supply power to the oscillator C340, the control logic module CLM, and other components (not shown). In an exemplary embodiment, the regulated DC voltage may be 1.8 volts. The oscillator C340 provides a clock signal, the maximum frequency of which may be, for example, about 10 MHz.

[0119] The control logic module CLM receives drive data Data from the data pin DataP, a DC voltage from the low-dropout regulator C330, and a clock signal from the oscillator C340. Depending on the operating stage of the array board, the control logic module CLM can also receive digital data from the address signal received at the address pin Di_in. The control logic module CLM can output an enable signal C352, an incremented data signal C354, a PWM clock selection signal C356, and a maximum current signal C358. During the address placement stage, the control logic module CLM activates the enable signal C352 to enable the address driver C360. The control logic module CLM receives the address signal via the address pin Di_in, stores the address, and provides the address driver C360 with an incremented data signal C354 representing the outgoing address. When the enable signal C352 is activated during the address placement stage, the address driver C360 buffers the incremented data signal C354 at the relay pin Di_out. The control logic module CLM can control the dimming circuit C370 to turn off transistor C375 during the addressing stage, effectively blocking the current path from the device unit.

[0120] During the device control and drive placement phases, the control logic module CLM deactivates the enable signal C352, and the output of the address driver C360 is tristate, effectively disconnecting it from the relay pin Di_out. During the device control phase, the PWM clock selection signal C356 specifies the duty cycle for controlling PWM dimming by the PWM dimming circuit C370. The PWM dimming circuit C370 controls the on and off timing of transistor C375 based on the selected duty cycle. While transistor C375 is on, a current path is established through transistor C375 from the output pin OUTP (coupled to the device unit, with Out1 as an example in Figure 12) to the ground pin GNDP, and the brightness control circuit C380 aggregates the driver current through the functional elements of the device unit. While transistor C375 is off, the current path is blocked, preventing current from flowing through the device unit. When transistor C375 is conducting, the brightness control circuit C380 receives a maximum current signal C358 from the control logic module CLM and controls the current level flowing through the functional element (from the output pin OUTP to the ground pin GNDP). During the device control phase, the control logic module CLM controls the duty cycle of the PWM dimming circuit C370 and the maximum current C358 of the brightness control circuit C380 to set the LED in the device unit to the desired brightness.

[0121] The driver circuit MIC may further include a voltage-controlled constant current circuit (not shown), the input reference voltage and input reference current of the voltage-controlled constant current circuit can be generated by the chip power supply voltage VCC received at the chip power supply pin VCCP. The voltage-controlled constant current circuit can be electrically connected to the brightness control circuit C380.

[0122] Referring to Figure 12, a short-circuit detector and an open-circuit detector are installed in the modulation module. Here, the open-circuit detector consists of an operational amplifier connected using a virtual open-circuit method and is used to detect whether or not an open-circuit has occurred between the device unit and the driver circuit MIC, where the Vopen terminal may be a floating signal terminal. The short-circuit detector consists of an operational amplifier connected using a virtual short-circuit method and is used to detect whether or not a short circuit has occurred between the device unit and the driver circuit MIC, where the potential of Vshort may be the same as the potential of the power supply voltage VLED transmitted by the device power supply line VLEDL.

[0123] Information such as short circuits or open circuits occurring between each device unit and the driver circuit MIC in any signal channel is aggregated in the corresponding driver circuit MIC's control logic module CLM, then transmitted stepwise through the driver circuit MIC's relay pin Di_out (for example, information is sequentially appended to the data signal C354 according to encoding rules), continuing until output from the final stage driver circuit MIC's relay pin Di_out, and connected to an external circuit via a feedback line FBL. The external circuit can then timely detect abnormalities in the driver circuit MIC or device unit EC in response to the feedback information.

[0124] In some embodiments, during the power-on and / or addressing phases, CRC (Cyclic Redundancy Check Code) check information on the signal channel is output in a similar manner from the relay pin Di_out of the final-stage driver circuit MIC and connected to an external circuit via the feedback line FBL. The external circuit responds to the feedback information and can timely detect abnormalities in the driver circuit MIC or device unit EC.

[0125] In some embodiments, as shown in Figure 12, the driver circuit MIC further includes a data selector MUX and an analog-to-digital converter ADC. When the driver circuit MIC forms a signal circuit with the corresponding connected device unit EC and device power supply line VLEDL via multiple output pins OutP, it transmits the electrical signals of the multiple signal circuits to the data selector MUX, processes them sequentially in time division via the analog-to-digital converter ADC, and then transmits them to the control logic module CLM, then transmits them stepwise via the relay pin Di_out of the driver circuit MIC (e.g., the electrical signals of the multiple signal circuits are sequentially appended to the data signal C354 according to coding rules) until it is output from the relay pin Di_out of the final stage driver circuit MIC, and connects to an external circuit via a feedback line FBL. The external circuit can respond to the feedback information and adjust the output signal level (e.g., the level of the device power supply voltage VLED) to reduce the power consumption of the array board.

[0126] Referring to Figure 12, a thermal shutdown delay sensor TSD and a thermal shutdown controller TS may also be installed in the driver circuit MIC. The thermal shutdown delay sensor TSD is used to detect the internal temperature of the driver circuit MIC. When the internal temperature of the driver circuit MIC reaches a preset protection temperature (generally set between 150°C and 170°C), the thermal shutdown delay controller TS operates to shut off the output of the driver circuit MIC, reducing the power consumption of the driver circuit MIC and thereby lowering the internal temperature of the driver circuit MIC. When the internal temperature of the driver circuit MIC drops to a preset restart temperature (restart temperature = protection temperature - delay temperature), the driver circuit MIC resumes output. Here, the delay temperature is usually set within the range of 15 to 30°C. The thermal shutdown delay controller TS may also be connected to a data selector MUX, and abnormal information may be fed back to the control logic module CLM via the data selector MUX to control the operating state of the driver circuit MIC.

[0127] In some embodiments, the external circuitry of the display device may further include a control circuit D110 for driving the array board. Referring to Figure 13, the control circuit D110 generates address signals ADDR and drive data Data for controlling the array board and provides these signals to the driver circuit MIC via drive lines (e.g., VLEDL / ADDRL / GNDL / DataL). The control circuit D110 may also include a timing controller D210 and a bridge D220. In various embodiments, the control circuit D110 may include additional, fewer, or different components. For example, in some embodiments, the control circuit D110 may be implemented using a field-programmable gate array (FPGA) and / or PHY block. The control circuit D110 is powered by an input voltage (VP) and connected to ground (GND). The control circuit D110 may control the display device using an active matrix (AM) drive scheme or a passive matrix (PM) drive scheme.

[0128] The timing controller D210 generates an image control signal D215 that specifies the values ​​and timings for driving the pixels on the array substrate. For example, the timing controller D210 controls the timing of an image frame or video frame and the timing for driving each of the device units (which may be LEDs located within an LED light zone) in the image frame or video frame. Furthermore, the timing controller D210 controls the brightness for driving each of the LED light zones in a given image frame or video frame. The image control signal D215 is provided to the bridge D220 by the timing controller D210.

[0129] Bridge D220 converts the image control signal D215 into driver control signals for the address signal ADDR and drive data Data. For example, according to the control method described above, Bridge D220 can generate the address signal ADDR for the first driver circuit MIC in the driver circuit MIC group in addressing mode.

[0130] From the viewpoint of the film layer structure, referring to Figure 10, the array substrate may include a base substrate 11, a driver circuit layer 200, and a device layer 300 that are stacked in order. Binding pads may be provided on the driver circuit layer, for example, device pads for binding functional elements, chip pads for binding driver circuit MICs, and circuit board pads for binding external circuits. The device layer includes each functional element and each driver circuit MIC, with each functional element being connected by binding to a device pad, and each driver circuit MIC being connected by binding to a chip pad. In this disclosure, a chip pad for binding to each pin of the same driver circuit MIC can constitute a single chip pad group. Thus, the driver circuit layer of the array substrate may include multiple chip pad groups, and each chip pad group is connected by binding in a one-to-one correspondence with each driver circuit MIC.

[0131] In some embodiments of this disclosure, the driver circuit MIC may include at least two output pins OUTP, an address pin Di_in, a relay pin Di_out, a chip power supply pin VCCP, a data pin DataP, and a ground pin GNDP. Accordingly, a group of chip pads may include output pads for binding to each output pin OUTP, an address pad for binding to the address pin Di_in, a relay pad for binding to the relay pin Di_out, a chip power supply pad for binding to the chip power supply pin VCCP, a data pad for binding to the data pin DataP, a ground pad for binding to the ground pin GNDP, and so on. Furthermore, in the driver circuit MIC, there are two ground pins GNDP, and they are located adjacent to each other. Accordingly, there are two ground pins, and they are located adjacent to each other. In this way, sufficient electrical connection (e.g., having a larger connection area and smaller contact resistance, smaller impedance, etc.) can be ensured between the ground pin GNDP and the ground voltage line GNDL, improving the stability of the ground voltage GND loaded into the driver circuit MIC. Furthermore, installing two ground pins (GNDP) avoids the need to install a ground pin with an excessively large surface area, and also avoids the problem of insufficient coupling strength between the ground pin and the other ground pins due to the large surface area of ​​the ground pin.

[0132] In an array substrate, the method of installing chip pads in a group of chip pads can be based on the pin arrangement method of the driver circuit MIC, and the present disclosure is not particularly limited to this, provided that the binding between the driver circuit MIC and the group of chip pads is satisfied.

[0133] In this disclosure, the base substrate 11 may be a base substrate made of an inorganic material, a base substrate made of an organic material, or a base substrate formed by laminating an organic material and an inorganic material. For example, in one embodiment of this disclosure, the material of the base substrate may be a glass material such as soda-lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. In another embodiment of this disclosure, the material of the base substrate may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0134] Optionally, referring to Figures 10 and 11, the driver circuit layer 200 may include a drive line layer 102, a first insulating layer 117, and a metal wiring layer 105, which are sequentially laminated on one side of the base substrate 11. Here, the drive line layer 102 may have drive lines for loading signals (e.g., ground voltage line GNDL, device power line VLEDL, address line ADDRL, drive data line DataL, chip power line VCCL, feedback line FBL, etc.). The metal wiring layer 105 may have binding pads (e.g., 101 / 107) and wiring lines WW. Here, the wiring lines WW can be used for electrical connections between binding pads (e.g., between device pads corresponding to each functional element of the device unit EC), and between binding pads and drive lines (e.g., between chip pads and drive lines, and between device pads and drive lines). Here, the connection between the drive lines and the wiring lines can be electrically made through through holes penetrating the first insulating layer 117. In one embodiment of the present disclosure, the thickness of the drive line layer may be greater than that of the metal wiring layer, thereby reducing the sheet resistance of the drive line and reducing the voltage drop of the signal in the drive line.

[0135] Optionally, the thickness of the drive line layer 102 is approximately 1.5 μm to 7 μm, and its material can include copper. For example, a MoNb / Cu / MoNb laminate can be formed by sputtering. The material on one side of the laminate that is close to the base substrate is MoNb, with a thickness of approximately 300 Å, and is mainly used to improve the adhesion between the film layer and the base substrate. The intermediate layer material of the laminate is Cu, which is a suitable material for electrical signal transmission channels. The material on the other side that is away from the base substrate is MoNb, with a thickness of approximately 200 Å, and is used to protect the intermediate layer and prevent oxidation from occurring due to the exposure of the surface of the intermediate layer, which has low resistivity. Since the thickness of a single sputtering generally does not exceed 1 μm, if a drive line layer exceeding 1 μm is to be manufactured, it is necessary to form it by sputtering multiple times. Furthermore, the drive line layer may be formed by electroplating. Specifically, a seed layer may be formed first using MoNiTi to improve the nucleation density of metal crystal grains in the subsequent electroplating process, followed by the production of low-resistivity copper by electroplating, and then an oxidation prevention layer, the material of which may be MoNiTi. Optionally, one side of the drive line layer that is separated from the base substrate may be covered with a first insulating layer to ensure the reliability and stability of the electrical pathway.

[0136] Optionally, the metal wiring layer 105 is provided with pads for binding to electronic elements (e.g., functional elements, driver circuit MICs, and external circuits) (e.g., device pads for binding functional elements, chip pads for binding driver circuit MICs, and circuit board pads for binding external circuits). The thickness of the metal wiring layer is approximately 6000 Å. In order to prevent oxidation problems that may occur due to the pads being exposed to air during the manufacturing process from the array substrate manufacturing process to the manufacturing process for setting electronic elements on the substrate, an anti-oxidation material layer can be installed only on the surface area where the pads are exposed; that is, the surface of the pad area has a more layered structure than the area where the wiring lines are located. Alternatively, the entire metal wiring layer can be arranged in a laminated structure of at least two layers, where the film layer material away from the base substrate is an oxidation-resistant metal or alloy material, specifically, for example, a MoNb / Cu / CuNi laminated structure. In the laminate, the bottom layer material MoNb is mainly used to improve adhesion, the intermediate layer Cu is mainly used to transmit electrical signals due to its low resistivity, and the top layer CuNi not only prevents oxidation of the intermediate layer but also ensures robustness of the connection with electronic elements. The surface on one side of the wiring line away from the base substrate is covered with a second insulating layer 108 to ensure the reliability and stability of the electrical path.

[0137] For example, in the drive wiring layer, the drive lines may include the device power line VLEDL, the ground voltage line GNDL, the address line ADDRL, the chip power line VCCL, the drive data line DataL, etc. Here, the following connections are electrically connected by wiring lines: between the output pin OUTP and the device pad of the device unit EC, between the address pad and the address line ADDRL, between the chip power pad and the chip power line VCCL, between the data pad and the drive data line DataL, between the device pad of the device unit EC and the device power line VLEDL, and between some address pads and the address line ADDRL.

[0138] In some embodiments, the ground pad and the ground voltage line GNDL can be electrically connected via a wiring line. Of course, in other embodiments of this disclosure, the ground pad and the ground voltage line GNDL may be directly connected via a through hole.

[0139] Optionally, the array substrate further includes a buffer layer 109 located between the base substrate 11 and the drive line layer 102, a first flat layer 110 located between the first insulating layer 117 and the metal wiring layer 105, a second flat layer 111 and a reflective layer 112 located on one side of the second insulating layer 108 away from the metal wiring layer, a transparent electrode 113 located on the binding pad 107 in the peripheral region, and an anisotropic conductive adhesive 114 located between the transparent electrode 113 and an external circuit (e.g., a flexible printed circuit board (FPC)). Here, the buffer layer 109 can prevent impurities in the base substrate from affecting the conductivity of the drive line layer, the first flat layer 110 can provide a flat surface for the manufacture of the second conductive layer 105, the second flat layer 111 can provide a flat surface for the binding of subsequent functional elements FE and driver circuits MIC, the material of the reflective layer 112 may be white ink and is used to improve the reflectivity of the array substrate and reduce light loss, and the transparent electrode 113 and anisotropic conductive adhesive 114 are used to realize electrical connection between the binding pads 107 in the peripheral region (e.g., circuit board binding pads) and the flexible circuit board FPC. The material of the base substrate may be glass, quartz, plastic, polyimide, PET, PMMA, etc.

[0140] Figure 11 is a schematic diagram of the structure of several other embodiments of the array substrate of the present disclosure. Each functional element and driver circuit is not shown in Figure 11. Referring to Figure 11, the array substrate may include a base substrate 11, a buffer layer 109 located on the base substrate 11, a drive line layer 102 located on one side of the buffer layer 109 away from the base substrate, a first insulating layer 117 located on one side of the drive line layer 102 away from the base substrate, a first flat layer 110 located on one side of the first insulating layer 117 away from the base substrate, a second conductive layer 105 located on one side of the first flat layer 110 away from the base substrate, a second insulating layer 116 located on one side of the second conductive layer 105 away from the base substrate, and a second flat layer 111 located on one side of the second insulating layer 116 away from the base substrate.

[0141] As shown in Figure 11, the second insulating layer 116 is located between the first flat layer 110 and the second flat layer 111. If the material of the second flat layer 111 is an organic insulating material, a plurality of exhaust holes 1160 can be installed in the second insulating layer 116. Each of these exhaust holes 1160 exposes a portion of the first flat layer 110 located below it. During the manufacturing process of the array substrate, gas accumulated in the first flat layer 110 can be released through the exhaust holes 1160, thereby preventing problems such as warping and delamination of the film layer of the array substrate, and thereby improving the product yield.

[0142] For example, in the embodiment shown in Figure 11, a plurality of exhaust ports 1160 are provided, but this is merely illustrative and does not limit the embodiments of the present disclosure. In other embodiments, a larger or smaller number of exhaust ports may be provided.

[0143] In some embodiments of the present disclosure, with reference to Figure 10, the array substrate may further include a sealing layer 13 located on one side away from the base substrate of the device layer. The sealing layer 13 includes a laminated structure for sealing the functional elements FE to the base substrate. In some exemplary embodiments, a sealing adhesive is applied to the surface of the functional elements FE on the array substrate, and the sealing layer 13 is formed after drying. The material of the sealing adhesive may include a transparent photocurable or thermosetting resin, i.e., the material of the sealing layer 13 may be a transparent protective adhesive. In some embodiments, the sealing layer 13 may include a plurality of transparent protective structures 30.

[0144] Referring to Figure 10, each pin of the functional element FE is connected to a device pad 101 via solder paste T, and each device pad 101 is also connected based on the position of the functional element in the electrical circuit.

[0145] Although the various steps of the driver circuit driving method described herein are shown in a specific order in the drawings, this does not require or imply that the steps must be performed in a specific order, or that all shown steps must be performed, in order to achieve the desired result. Additionally or alternatively, some steps may be omitted, some steps may be combined into one, and / or one step may be divided into several steps.

[0146] Those skilled in the art will readily acquire other embodiments of the invention through understanding the specification and practicing the inventions described herein. This application includes any modifications, uses, or adaptive changes to the disclosure, and such modifications, uses, or adaptive changes are intended to include prior art knowledge or common technical means not disclosed herein, in accordance with the general principles of the disclosure. The specification and examples are merely illustrative, and the true scope and spirit of the disclosure are indicated by the following claims. [Explanation of symbols]

[0147] AA device control area BB Device Control Area Column MIC driver circuit OUTP output pin Out1 First output pin Out2 is the second output pin. Out3 Third Output Pin Out4 (Fourth Output Pin) DataP (Data Pin) DataL Driven Dataline VLEDL Device Power Line Di_in Address Pin Di_out relay pin ADDRL Address Line FBL Feedback Line GNDP Ground pin GNDL Ground voltage line VCCP chip power pins VCCL chip power line CTR Logic Control Module PWMM1 First Modulation Module PWMM2 Second Modulation Module PWNM3 Third Modulation Module PWMM4 Fourth Modulation Module PWMM5 Fifth Modulation Module

Claims

1. Array substrate, Includes multiple device control areas installed in the array, In any of the device control regions, a driver circuit is installed on the array substrate, and a device unit is installed that is connected in a one-to-one correspondence to each output pin of the driver circuit. Any of the device units includes a plurality of electrically connected functional elements, each of which is an LED, MicroLED, or miniLED. The driver circuit includes a logic control module, data pins, and at least two output pins, the data pins being used to receive drive data, the logic control module being configured to generate drive control signals that correspond one-to-one with each of the output pins based on the drive data, and the drive control signals being used to control the current flowing through the corresponding output pins. The array substrate includes a base substrate, a driver circuit layer, and a device layer, which are stacked in order. The driver circuit layer has binding pads for binding the functional elements and binding pads for binding the driver circuit, respectively. The device layer includes the functional elements and the driver circuit, with the functional elements connected by binding to chip pads, and the driver circuit connected by binding to chip pads. The chip pads for binding and connecting to each pin of the same driver circuit constitute a single chip pad group, the driver circuit layer includes a plurality of such chip pad groups, and the chip pad groups are bound and connected to the driver circuit in a one-to-one correspondence. The driver circuit layer includes a metal wiring layer, on which device pads, chip pads, and wiring lines are provided, and the device pads and chip pads corresponding to the functional elements are electrically connected via the wiring lines. The device control regions are arranged in a plurality of rows of device control regions, each row of device control regions includes a plurality of device control regions arranged sequentially along the row direction, and in each row of device control regions, a device power line extending along the row direction is provided on the array substrate, and the device pads and device power lines corresponding to one functional element of each device unit are electrically connected by the wiring lines. An array substrate characterized by the following features.

2. The aforementioned drive data includes address information and drive information, The logic control module is further configured to acquire the drive information of the drive data and generate the drive control signal based on the drive information of the drive data when the address information of the drive data matches the address information of the driver circuit. The array substrate according to claim 1.

3. The driver circuit further includes an address pin and a relay pin, The address pin can receive an address signal. The logic control module is further configured to arrange the address information of the driver circuit based on the address signal and to generate a relay signal. The relay signal can be the address signal of the connected driver circuit. The relay pin is used to output the relay signal. The array substrate according to feature 2.

4. The number of output pins is four. The driver circuit further includes a ground pin and a chip power supply pin. The aforementioned ground pin is used to apply a ground voltage to the driver circuit. The aforementioned chip power supply pins are used to apply the chip power supply voltage to the driver circuit to drive the operation of the driver circuit. Each pin of the driver circuit is arranged in two pin rows, and each pin row includes a plurality of pins arranged linearly. At least one of the aforementioned pin rows includes five pins, The four output pins are all located at the ends of the pin row. The chip power pins and data pins are located in different pin rows. The address pin and the relay pin are located in the same pin row. The array substrate according to claim 3.

5. In any of the device control region rows, a drive data line extending along the row direction is installed on the array substrate, One end of the device unit is electrically connected to the device power line, and the other end is electrically connected to the corresponding output pin. The data pin is electrically connected to the drive data line. The array substrate according to claim 1.

6. Each of the driver circuits located in the same device control area column is cascaded in sequence. The driver circuit further includes an address pin and a relay pin, In any of the device control region rows, a plurality of address lines corresponding one-to-one with each of the driver circuits are provided on the array substrate, and each of the address lines extends along the row direction. The address pins of the driver circuit are electrically connected to the corresponding address lines, and the relay pins of the preceding driver circuit are electrically connected to the address lines corresponding to the next driver circuit. The array substrate according to claim 5.

7. In any of the aforementioned device control region rows, the array substrate is further provided with chip power lines and ground voltage lines extending along the row direction. The driver circuit further includes a chip power pin and a ground pin, the chip power pin being used to apply a chip power voltage to the driver circuit to drive the operation of the driver circuit. The chip power line is electrically connected to the chip power pins, The ground pin is used to apply a ground voltage to the driver circuit, and the ground pin is electrically connected to the ground voltage line. The array substrate according to claim 6.

8. In any of the device control region columns, the device units are arranged in two device unit columns, and each of the device unit columns includes a plurality of device units arranged sequentially along the column direction. In any of the above-mentioned device control region sequences, the number of device power lines is two, The two device power lines are located on either side of the ground voltage line and are installed in a one-to-one correspondence with the two device unit rows. Each of the device units in the aforementioned array of device units is electrically connected to the corresponding device power line. The array substrate according to feature 7.

9. In any of the device control region sequences, the address line, the drive data line, and the chip power line are all located between the device power line and the ground voltage line. The array substrate according to feature 8.

10. In at least one of the device control region rows, the array substrate is further provided with a feedback line. In the aforementioned device control region sequence, the relay pin of the final stage driver circuit is electrically connected to the feedback line. The feedback line is located between the device power line and the ground voltage line. The array substrate according to feature 8.

11. In two adjacent rows of the device control regions, two adjacent device power lines are connected to each other to form a single line. The array substrate according to feature 8.

12. The driver circuit layer includes, in order, a drive line layer, a first insulating layer, and a metal wiring layer, which are laminated on the base substrate. The thickness of the drive line layer is greater than the thickness of the metal wiring layer. The ground voltage line, the device power line, the chip power line, the drive data line, and the address line are located in the drive line layer. Device pads, chip pads, and wiring lines are installed on the metal wiring layer. The functional element and the driver circuit are located in the device layer. The functional element is connected by binding to the device pad, the driver circuit is connected by binding to the chip pad, and the device pad and the chip pad and the drive line layer are electrically connected by the wiring lines. The array substrate according to feature 8.

13. In any of the device units, all of the functional elements are connected in series in sequence. Each of the functional elements on the array substrate is arranged in a plurality of element rows, each element row is arranged at equal intervals along the column direction, and each element row includes a plurality of functional elements arranged at equal intervals along the row direction; each of the functional elements on the array substrate is arranged in a plurality of element columns, each element column is arranged at equal intervals along the row direction, and each element column includes a plurality of functional elements arranged at equal intervals along the column direction. The array substrate according to claim 1.

14. A method for driving a driver circuit, The driver circuit is the driver circuit described in any one of claims 1 to 13. The driver circuit includes at least two output pins, The method for driving the driver circuit includes, in the device control stage, receiving drive data, generating a drive control signal that corresponds one-to-one with each of the output pins based on the drive data, and using the drive control signal to control the current flowing through the corresponding output pin. A method for driving a driver circuit, characterized by the following features.

15. The aforementioned drive data includes address information and drive information, The method for driving the driver circuit further includes, in the address placement stage, receiving an address signal, arranging the address information of the driver circuit based on the address signal, and generating and outputting a relay signal. The relay signal can be the address signal of the connected driver circuit. Generating a drive control signal that corresponds one-to-one with each output pin based on the drive data includes, when the address information of the drive data matches the address information of the driver circuit, acquiring the drive information of the drive data and generating the drive control signal based on the drive information of the drive data. A method for driving a driver circuit according to feature 14.

16. A display device, The array substrate is as described in any one of claims 1 to 13, wherein the display device is a liquid crystal display device and includes a stacked liquid crystal display module and a backlight module, the array substrate is the backlight of the backlight module, and the material of the base substrate is glass or metal. A display device characterized by the following features.

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