Data processing method and data processing device

Abstract

The embodiment of the present application discloses a data processing method and a data processing device. The method in the embodiment of the present application includes the following steps: separately performing convolutional interleaving on n lane data streams to obtain n first data streams, where n>1, and a first FEC encoding is performed on all of the n lane data streams. All a codewords obtained by the first FEC encoding are distributed into b lane data streams, where a≦b≦n and a≧1. Each z consecutive symbols of the first data stream are from z different codewords, where z>1. Then, all K first data streams of the n first data streams are multiplexed to obtain one second data stream, and a total of m second data streams are obtained. The n first data streams include G first data stream subsets, and the symbols in different first data stream subsets are from different codewords, where m=n / K, K>1, and G>1. The y consecutive symbols in each second data stream are from y different codewords, where y>z.

Description

[Technical Field]

[0001] This application is a compilation of the following patent applications: Chinese Patent Application No. 202210109956.X titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the China National Intellectual Property Administration on January 28, 2022; Chinese Patent Application No. 202210290887.7 titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the China National Intellectual Property Administration on March 23, 2022; Chinese Patent Application No. 202211065772.4 titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the China National Intellectual Property Administration on September 1, 2022; and "DATA PROCESSING METHOD AND DATA PROCESSING" filed with the China National Intellectual Property Administration on October 24, 2022. This invention claims priority to Chinese Patent Application No. 202211305113.3, titled “APPARATUS”, and Chinese Patent Application No. 202211448533.7, titled “DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS”, filed with the China National Intellectual Property Administration on 18 November 2022, which is incorporated herein by reference in its entirety.

[0002] This application relates to the field of communications, and more particularly to data processing methods and data processing devices. [Background technology]

[0003] With the continued proliferation of 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are evolving towards features such as high capacity and ultra-high speed. Forward error correction (FEC) coding is used to correct transmitted data, resolve errors in transmitted bits, and reconstruct the original data transmitted by the transmitter from the received data.

[0004] Currently, a concatenated FEC transmission solution has been proposed. In this solution, the transmitting device is connected to a transmitting processing module via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the data obtained by the first FEC encoding to the transmitting processing module. The transmitting processing module performs a second FEC encoding on the data obtained by the first FEC encoding and sends the data obtained by the second FEC encoding to the data receiver via a channel. Specifically, the transmitting processing module receives multiple data streams, first performs convolutional interleaving on the multiple data streams separately, and then performs a second FEC encoding on each data stream obtained by the convolutional interleaving. It should be understood that, in order to improve performance, one data stream involved in the second FEC encoding must be from multiple codewords obtained by the first FEC encoding. However, this must be done by using convolutional interleaving, which involves long latency, and the application is not ideal in scenarios requiring low latency. [Overview of the Initiative]

[0005] Embodiments of this application provide a data processing method and a data processing device. In low-latency scenarios, better performance of the concatenated FEC solution can be obtained. [Means for solving the problem]

[0006] According to a first aspect, the present application provides a data processing method. The method includes the following steps: First, convolutional interleaving is performed separately on n lane data streams to obtain n first data streams, where n is an integer greater than 1, and a first FEC coding is performed on all of the n lane data streams. The data obtained by the first FEC coding a piece The codewords are distributed across b lane data streams, where a ≤ b ≤ n, where n is exactly divisible by b, and a is an integer greater than or equal to 1. Each of the z consecutive symbols in the first data stream comes from z distinct codewords, where z is an integer greater than 1. Then, the n first data streams... every K The first data stream is multiplexed to obtain one second data stream, resulting in a total of m second data streams. The n first data streams contain G first data stream subsets, where the symbols in different first data stream subsets come from different codewords, m = n / K, where K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream come from y different codewords, where y > z. If K ≤ G, then each of the K first data streams comes from K first data stream subsets. If K > G, then each of the K first data streams contains K / G first data streams within each first data stream subset.

[0007] In this embodiment, all n lane data streams are externally coded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by the convolutional interleaving to obtain m second data streams, after which internal code coding is performed. According to the data interleaving and multiplexing processing solution provided in this application, the following case can be implemented with low latency: multiple symbols output sequentially from the m multiplexed data streams are from multiple different external codewords, and as a result, the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, in this application, the combined solution of convolutional interleaving and data multiplexing can reduce the overall latency of the concatenated FEC solution and is more applicable to scenarios requiring low latency.

[0008] In some possible embodiments, the step of performing a convolutional interleave on a lane data stream to obtain a first data stream includes: delaying a lane data stream based on p delay lines to obtain a first data stream, where p is an integer greater than 1 and each delay line has a different number of storage units. A delay line having the fewest number of storage units includes 0 storage units, Every twoThe difference between the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store d symbols, with z = p*d. Symbols in each lane data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, with d symbols input into each delay line once and d symbols output from each delay line once, so that p*d consecutive symbols in the first data stream include the d symbols output from the delay lines. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. This embodiment provides a specific embodiment of convolutional interleaving, thereby improving the practicality of this solution.

[0009] In some possible embodiments, the delay line with the highest sequence number among p delay lines contains 0 memory units. d(p*Q+1)≧a*N / b, where d≦a, N is the length of the codeword, and z consecutive symbols in each first data stream may come from z different codewords.

[0010] In some possible embodiments, the delay line having the smallest sequence number among p delay lines contains 0 memory units. d(p*Q-1)≧a*N / b, d≦a, where N is the length of the codeword, and z consecutive symbols in each first data stream may come from z different codewords.

[0011] In some possible embodiments, if K ≤ G, then y = K * z; or if K > G, then y = G * z. Such multiplexing is used to ensure that y > z can be implemented in multiple different application scenarios, and that the concatenated FEC solution can be implemented with better performance and lower latency.

[0012] In some possible embodiments, each second data stream contains multiple second data stream symbol subsets, each second data stream symbol subset contains K symbol groups, and each symbol group contains Δ symbols. Two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets. If K ≤ G, Δ is a divisor of z; or if K > G, Δ = z.

[0013] In this embodiment, since two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets, y consecutive symbols in the second data stream obtained by multiplexing are from y different codewords, where y > z (y = K*z or y = G*z). It should be understood that when only convolutional interleaving is performed, a long latency is required to implement the case where y consecutive symbols in the output data stream are from y different codewords. In this solution, the duration of convolutional interleaving is reduced, but equivalent performance can still be achieved by combining convolutional interleaving with multiplexing. Alternatively, by combining convolutional interleaving with multiplexing, the duration of multiplexing can be shorter, and equivalent performance can be achieved with lower latency.

[0014] In some possible embodiments, each j-th symbol group in a second data stream symbol subset is from the j-th first data stream of the K first data streams involved in multiplexing, where 0 ≤ j ≤ K-1. In the above form, rules are provided for selecting the K first data streams involved in multiplexing to ensure that two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets.

[0015] In some possible embodiments, if K > G, two adjacent first data streams among the K first data streams involved in multiplexing are from different subsets of first data streams. In the form described above, the K > G scenario provides a rule for selecting the K first data streams involved in multiplexing, ensuring that y = G * z.

[0016] In some possible embodiments, if K > G, then multiplexing is involved. G pieces The consecutive first data streams are from different subsets of first data streams. In the above form, in the scenario K > G, a rule is provided for selecting the K first data streams involved in the multiplexing, further ensuring that y = G * z.

[0017] In some possible embodiments, n=32 and K=2, 4, or 8. The above form provides several specific types of multiplexers, extending the application scenarios of this solution.

[0018] In some possible embodiments, n=32, p=2, 3, 4, 6, or 8, and d=1 or 2. In the above form, several specific types of convolutional interleavers are provided, extending the application scenarios of this solution.

[0019] In some possible embodiments, a=1 or 2, and b=4, 8, or 16. The above forms provide several distribution patterns for the lane data stream, extending the application scenarios of this solution.

[0020] In some possible embodiments, prior to the step of performing convolutional interleaving separately on n lane data streams to obtain n first data streams, the method further includes the step of performing lane sorting on the n lane data streams so that the n lane data streams are arranged in a pre-configured sequence.

[0021] In some possible embodiments, prior to the step of performing convolutional interleaving separately on n lane data streams to obtain n first data streams, the method further includes the step of performing lane deskue on the n lane data streams. This embodiment provides a specific embodiment of lane data alignment, thereby improving the feasibility of this solution.

[0022] In some possible embodiments, the method further includes the step of aligning the n lane data streams so that the symbols in the n lane data streams are aligned, before performing convolutional interleaving separately on the n lane data streams to obtain the n first data streams. In this embodiment, another specific embodiment of lane data alignment is provided, thereby increasing the flexibility of this solution.

[0023] In some possible embodiments, after a total of m second data streams have been obtained, the method further includes the step of performing a second FEC encoding separately on the m second data streams. The length of the information bits of the second FEC encoding is less than or equal to y symbols.

[0024] According to a second aspect, the present application provides a data processing device. The data processing device includes a convolutional interleaver and a multiplexer. The convolutional interleaver is configured to obtain n first data streams by separately performing convolutional interleaving on n lane data streams, where n is an integer greater than 1, and the first FEC coding is performed on all of the n lane data streams. a pieceThe codewords are distributed across b lane data streams, where a ≤ b ≤ n, where n is exactly divisible by b, and a is an integer greater than or equal to 1. Each of the z consecutive symbols in the first data stream comes from z distinct codewords, where z is an integer greater than 1. The multiplexer takes n first data streams to obtain a total of m second data streams. every K The system is configured to multiplex a first data stream to obtain a single second data stream. Each n first data stream contains G first data stream subsets, where the symbols in different first data stream subsets come from different codewords, m = n / K, where K is an integer greater than 1, and G is an integer greater than 1. Each y consecutive symbols in the second data stream come from y different codewords, where y > z. If K ≤ G, each of the K first data streams comes from K first data stream subsets. If K > G, each of the K first data streams contains K / G first data streams within each first data stream subset.

[0025] In some possible embodiments, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to acquire one first data stream, where p is an integer greater than 1, and each delay line contains a different number of memory units. The delay line with the fewest number of memory units contains 0 memory units, Every twoThe difference between the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store d symbols, with z = p*d. Symbols in each lane data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, with d symbols input into each delay line once and d symbols output from each delay line once. The p*d consecutive symbols in the first data stream include the d symbols output from the delay lines, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0026] In some possible embodiments, among p delay lines, the delay line having the largest sequence number contains 0 memory units, d(p*Q+1)≧a*N / b, where N is the length of the codeword and d≦a.

[0027] In some possible embodiments, among p delay lines, the delay line having the smallest sequence number contains 0 memory units, d(p*Q-1)≧a*N / b, where N is the length of the codeword and d≦a.

[0028] In some possible embodiments, if K ≤ G, then y = K * z; or if K > G, then y = G * z.

[0029] In some possible embodiments, each second data stream contains multiple second data stream symbol subsets, each second data stream symbol subset contains K symbol groups, and each symbol group contains Δ symbols. Two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets. If K ≤ G, Δ is a divisor of z; or if K > G, Δ = z.

[0030] In some possible embodiments, each j-th symbol group of the second data stream symbol subset is from the j-th first data stream of the K first data streams involved in multiplexing, where 0 ≤ j ≤ K-1.

[0031] In some possible embodiments, if K > G, then two adjacent first data streams among the K first data streams involved in multiplexing are from different subsets of first data streams.

[0032] In some possible embodiments, if K > G, then multiplexing is involved. G pieces The consecutive first data streams are derived from different subsets of the first data stream.

[0033] In some possible embodiments, n=32 and K=2, 4, or 8.

[0034] In some possible embodiments, n=32, p=2, 3, 4, 6, or 8, and d=1 or 2.

[0035] In some possible embodiments, a = 1 or 2, and b = 4, 8, or 16.

[0036] In some possible embodiments, the data processing unit further includes a lane sorting unit. Before convolutional interleaving is performed separately on the n lane data streams to obtain n first data streams, the lane sorting unit is configured to perform lane sorting on the n lane data streams so that the n lane data streams are arranged in a pre-configured sequence.

[0037] In some possible embodiments, the data processing unit further includes a lane data alignment unit. The lane data alignment unit is configured to perform lane deskue on the n lane data streams before convolutional interleaving is performed separately on the n lane data streams to obtain the n first data streams.

[0038] In some possible embodiments, the data processing device further includes a lane data alignment unit. Before convolutional interleaving is performed separately on the n lane data streams to obtain the n first data streams, the lane data alignment unit is configured to align the n lane data streams so that the symbols in the n lane data streams are aligned.

[0039] In some possible embodiments, the data processing device further includes an encoder. After a total of m second data streams have been acquired, the encoder is configured to perform a second FEC encoding separately on the m second data streams, where the length of the information bits of the second FEC encoding is less than or equal to y symbols.

[0040] According to a third aspect, the present application provides a data processing method. The method includes the following steps: performing interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4; performing first forward error correction FEC coding on all n lane data streams, and obtaining the data obtained by the first FEC coding a pieceThe codewords are distributed across b lane data streams, where a ≤ b ≤ n, and n can be divided exactly by b. F consecutive symbols in each target data stream come from F distinct codewords, where F > a. F consecutive symbols in each target data stream come from at least K1 distinct lane data streams, and F consecutive symbols in each target data stream come from up to K2 symbols in n aligned symbols across n lane data streams, where K1 and K2 are divisors of n, and K2 is a divisor of K1. Up to K3 symbols in each target data stream come from the same lane data stream.

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[0041] In some possible embodiments, K1 = n / 4 and K2 = n / 16.

[0042] In some possible embodiments, the steps include: performing interleaving on n lane data streams to obtain m target data streams; performing convolutional interleaving separately on n lane data streams to obtain n first data streams, where z consecutive symbols in each of the first data streams come from at least e different codewords, z is an integer greater than 1, a ≤ e ≤ F, e*k² ≥ F, and at most k1 / k² symbols in each of the z consecutive symbols in the first data streams come from the same codeword; and obtaining the sum of m target data streams from the n first data streams Each KA step of performing block interleaving on a first data stream to obtain S target data streams, where S is an integer greater than or equal to 1, m = S*n / K1, S ≥ k1 / k2, and the n first data streams contain K1 first data stream groups, within the same first data stream group Every two The symbols of the first data streams are from the same codeword, and each of the K1 first data streams is from a group of K1 first data streams, including the step.

[0043] In some possible embodiments, the step of performing a convolutional interleave on one lane data stream to obtain one first data stream is the step of delaying one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1, p*a ≥ F / k², and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units including 0 memory units. Every 2 The difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store d symbols, with z = p * d, including a step. Symbols in each lane data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, with d symbols input into each delay line once and d symbols output from each delay line once, so that p * d consecutive symbols in the first data stream include the d symbols output from the delay lines, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d ≤ a.

[0044] In some possible embodiments, among the p delay lines, the delay line with the largest sequence number contains 0 memory units and d(p*Q+1)≧K4.

[0045] In some possible embodiments, the delay line having the smallest sequence number among the p delay lines contains 0 memory units, and d(p*Q - 1) ≥ K4.

[0046] In some possible embodiments, the K first data streams involved in block interleaving include a first symbol matrix, the first symbol matrix includes symbols in K rows and B columns, B = R*p*d, R is an integer greater than or equal to 1, the S target data streams obtained by block interleaving include a second symbol matrix, the second symbol matrix includes symbols in S rows and F columns, and K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and the maximum R*K1 / K2 symbols in the first symbol matrix are from the same codeword.

[0047] In some possible embodiments, the F symbols in each row of the second symbol matrix are from at least

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[0048] In some possible embodiments, the symbols in each row of the second symbol matrix from the odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix. The symbols in each row of the second symbol matrix from the even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

[0049] In some possible embodiments, the symbols are output from delay lines having the same delay value, and each symbol in each row of the second symbol matrix is ​​from a different row of the first symbol matrix.

[0050] In some possible embodiments, up to K3 symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K3 symbols are output from two delay lines whose delay difference is greater than or equal to 2*Q*d.

[0051] In some possible embodiments, the steps include: performing interleaving on n lane data streams to obtain m target data streams, a first block interleaving on n lane data streams to obtain T first data streams, wherein C consecutive symbols in each of the first data streams come from at least E different codewords, T = n / K1, C is a multiple of a, and E ≥ K2*a; performing convolution interleaving on T first data streams to obtain T second data streams, wherein H consecutive symbols in each of the second data streams come from at least F different codewords, F ≥ E, and up to K1 / K2 symbols in the H consecutive symbols in each of the second data streams come from the same codeword; and performing a second block interleaving on each of the T second data streams to obtain S target data streams to obtain a sum of m target data streams, where m = T*S, and S ≥ k1 / K2.

[0052] In some possible embodiments, the n lane data streams involved in the first block interleave include a third symbol matrix, the third symbol matrix includes symbols in n rows and A columns, where A is a multiple of a, and the T first data streams obtained by the first block interleave include a fourth symbol matrix, the fourth symbol matrix includes symbols in T rows and C columns, where T is a divisor of n, and n*A=T*C. In one column of the third symbol matrix T pieces A sequence of symbols is a symbol submatrix, and each T symbol in each column of the fourth symbol matrix corresponds one-to-one with each symbol submatrix in the third symbol matrix.

[0053] In some possible embodiments, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix contain the first to (n / T) symbol submatrices arranged in the first sequence, and the (n / T) symbol submatrices of the preceding column and the first symbol submatrices of the following column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remainder can be inferred by analogy until the T symbols in the Cth column of the fourth symbol matrix are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices; or the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the third symbol matrix Each row T The first to A columns of the symbol matrix contain the first to A symbol submatrices arranged in the second sequence, the A symbol submatrices of the first T row and the first symbol submatrices of the second T row of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, the T symbols in the first column of the fourth symbol matrix are arranged in the second sequence and come from the first symbol submatrices in the third symbol matrix, and the remainder can be inferred by analogy until the T symbols in the C column of the fourth symbol matrix are arranged in the second sequence and come from the last symbol submatrices in the third symbol matrix.

[0054] In some possible embodiments, the step of performing a convolutional interleave on a first data stream to obtain a second data stream is the step of delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, p*E ≥ F, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units including 0 memory units. Every 2The difference in the number of memory units of adjacent delay lines is Q, each memory unit is configured to store C symbols, p*C = H, the symbols in each first data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, C symbols are input into each delay line once, C symbols are output from the delay line once, the p*C consecutive symbols in the second data stream include the C symbols output from the delay line, and Q is an integer greater than or equal to 1. The step includes:

[0055] In some possible embodiments, the delay line having the largest sequence number among the p delay lines includes 0 memory units, and C(p*Q + 1) ≥ K1*K4.

[0056] In some possible embodiments, the delay line having the smallest sequence number among the p delay lines includes 0 memory units, and C(p*Q - 1) ≥ K1*K4.

[0057] In some possible embodiments, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from the p delay lines respectively, the symbols in each symbol set are from at least F different codewords, each target data stream includes F symbols, R*p*C = S*F, and R is an integer greater than or equal to. The F symbols in the target data stream are from at least

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[0058] In some possible embodiments, F symbols in the target data stream include a first symbol group from a first symbol subset and a second symbol group from a second symbol subset, the first and second symbol subsets belong to the same symbol set, the first and second symbol subsets are output from two adjacent delay lines, the symbols in the first symbol subset and the symbols in the second symbol subset are arranged separately and sequentially, the ranking of the first symbol group in the first symbol subset is the ranking of the second symbol group in the second symbol subset The ranking is different from that of the fourth symbol group in the fourth symbol subset; or F symbols in the target data stream include a third symbol group from a third symbol subset and a fourth symbol group from a fourth symbol subset, the third and fourth symbol subsets belong to different symbol sets, the third and fourth symbol subsets are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are arranged separately and sequentially, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

[0059] In some possible embodiments, the maximum number of F symbols in each target data stream

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[0060] In some possible embodiments, after the sum of m target data streams is obtained, the method further includes the step of performing a second FEC encoding separately on the m target data streams, wherein the length of the information bits of the second FEC encoding is equal to the F symbol.

[0061] According to a fourth aspect, the present application provides a data processing device, the data processing device including an interleaving module. The interleaving module is configured to perform interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4, and a first forward error correction FEC coding is performed on all n lane data streams and obtained via the first FEC coding. a piece All codewords are distributed across b lane data streams, where a ≤ b ≤ n, and n can be divided exactly by b. F consecutive symbols in each target data stream come from F distinct codewords, where F > a. F consecutive symbols in each target data stream come from at least K1 distinct lane data streams, and F consecutive symbols in each target data stream come from up to K2 symbols in n aligned symbols of n lane data streams, where K1 and K2 are divisors of n, and K2 is a divisor of K1. Up to K3 symbols in each target data stream come from the same lane data stream.

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[0062] In some possible embodiments, K1 = n / 4 and K2 = n / 16.

[0063] In some possible embodiments, the interleaving module includes a convolutional interleaver and a block interleaver. The convolutional interleaver is configured to perform convolutional interleaving separately on n lane data streams to obtain n first data streams, where each z consecutive symbols of the first data streams are from at least e different codewords, where z is an integer greater than 1, a ≤ e ≤ F, e*k² ≥ F, and at most k1 / k² symbols in each z consecutive symbols of the first data streams are from the same codeword. The block interleaver is configured to perform block interleaving for every K1 first data streams of n first data streams in order to obtain the sum of m target data streams, where S is an integer greater than or equal to 1, m = S * n / K1, S ≥ k1 / k2, where n first data streams contain K1 first data stream groups, where the symbols for every two first data streams within the same first data stream group are from the same codeword, and each of the K1 first data streams is from a K1 first data stream group.

[0064] In some possible embodiments, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to acquire one first data stream, where p is an integer greater than 1, p*a ≥ F / k², and each delay line contains a different number of memory units, with the delay line having the fewest memory units containing zero memory units. Every twoThe difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store d symbols, with z = p * d. Symbols in each lane data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, with d symbols input into each delay line once and d symbols output from each delay line once. The p * d consecutive symbols in the first data stream include the d symbols output from the delay lines, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d ≤ a.

[0065] In some possible embodiments, the delay line with the largest sequence number among the p delay lines contains 0 memory units and d(p*Q+1)≧K4.

[0066] In some possible embodiments, among the p delay lines, the delay line having the smallest sequence number contains 0 memory units and d(p*Q-1)≧K4.

[0067] In some possible embodiments, the K first data streams involved in the block interleaving include a first symbol matrix containing K rows and B columns of symbols, where B = R*p*d, and R is an integer greater than or equal to 1. The S target data streams obtained by the block interleaving include a second symbol matrix containing S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and up to R*K1 / K2 symbols in the first symbol matrix are from the same codeword.

[0068] In some possible embodiments, the F symbols in each row of the second symbol matrix are at least the first symbol matrix.

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[0069] In some possible embodiments, in each row of the second symbol matrix, the symbols from the odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and in each row of the second symbol matrix, the symbols from the even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

[0070] In some possible embodiments, the symbols are output from delay lines having the same delay value, and each symbol in each row of the second symbol matrix is ​​from a different row of the first symbol matrix.

[0071] In some possible embodiments, up to K3 symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K3 symbols are output from two delay lines whose delay difference is greater than or equal to 2*Q*d.

[0072] In some possible embodiments, the convolutional interleave module includes a first block interleave, a convolutional interleave, and a second block interleave. The first block interleave is configured to perform a first block interleave on n lane data streams to obtain T first data streams, where each C consecutive symbols in the first data streams are from at least E different codewords, T = n / K1, C is a multiple of a, and E ≥ K2*a. The convolutional interleave is configured to perform a convolutional interleave on the T first data streams to obtain T second data streams, where each H consecutive symbols in the second data streams are from at least F different codewords, F ≥ E, and up to K1 / K2 symbols in each H consecutive symbols in the second data streams are from the same codeword. The second block interleaver is configured to obtain S target data streams by performing the second block interleave on each of T second data streams in order to obtain the sum of m target data streams, where m = T * S and S ≥ k1 / K2.

[0073] In some possible embodiments, the n lane data streams involved in the first block interleave include a third symbol matrix, the third symbol matrix includes symbols in n rows and A columns, where A is a multiple of a, and the T first data streams obtained by the first block interleave include a fourth symbol matrix, the fourth symbol matrix includes symbols in T rows and C columns, where T is a divisor of n, and n*A=T*C. In one column of the third symbol matrix T piecesA sequence of symbols is a symbol submatrix, and each T symbol in each column of the fourth symbol matrix corresponds one-to-one with each symbol submatrix in the third symbol matrix.

[0074] In some possible embodiments, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix contain the first to (n / T) symbol submatrices arranged in the first sequence, and the (n / T) symbol submatrices of the preceding column and the first symbol submatrices of the following column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and the T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remainder can be inferred by analogy until the T symbols in the Cth column of the fourth symbol matrix are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices; or the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the third symbol matrix Each row T The first to A columns of the symbol matrix contain the first to A symbol submatrices arranged in the second sequence, the A symbol submatrices of the first T row and the first symbol submatrices of the second T row of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, the T symbols in the first column of the fourth symbol matrix are arranged in the second sequence and come from the first symbol submatrices in the third symbol matrix, and the remainder can be inferred by analogy until the T symbols in the C column of the fourth symbol matrix are arranged in the second sequence and come from the last symbol submatrices in the third symbol matrix.

[0075] In some possible embodiments, the convolutional interleaver is specifically configured to delay one first data stream based on p delay lines in order to obtain one second data stream, where p is an integer greater than 1, p*E ≥ F, and each delay line contains a different number of memory units, with the delay line having the fewest memory units containing zero memory units. Every two The difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store C symbols, with p*C=H. Symbols in each first data stream are sequentially input into p delay lines based on the sequence numbers of the p delay lines, with C symbols input into each delay line once and C symbols output from each delay line once. p*C consecutive symbols in the second data stream include the C symbols output from the delay lines, where Q is an integer greater than or equal to 1.

[0076] In some possible embodiments, among the p delay lines, the delay line with the largest sequence number contains 0 memory units and C(p*Q+1)≧K1*K4.

[0077] In some possible embodiments, among the p delay lines, the delay line having the smallest sequence number contains 0 memory units and C(p*Q-1)≧K1*K4.

[0078] In some possible embodiments, each second data stream contains R symbol sets, each symbol set contains p symbol subsets, each symbol subset contains C symbols, the p symbol subsets are output from p delay lines, the symbols in each symbol set are from at least F different codewords, each target data stream contains F symbols, R*p*C=S*F, where R is more than or equal to an integer. The F symbols in the target data stream are at least

number

number

number

[0079] In some possible embodiments, F symbols in the target data stream include a first symbol group from a first symbol subset and a second symbol group from a second symbol subset, the first and second symbol subsets belong to the same symbol set, the first and second symbol subsets are output from two adjacent delay lines, the symbols in the first symbol subset and the symbols in the second symbol subset are arranged separately and sequentially, the ranking of the first symbol group in the first symbol subset is the ranking of the second symbol group in the second symbol subset The ranking is different from that of the fourth symbol group in the fourth symbol subset; or F symbols in the target data stream include a third symbol group from a third symbol subset and a fourth symbol group from a fourth symbol subset, the third and fourth symbol subsets belong to different symbol sets, the third and fourth symbol subsets are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are arranged separately and sequentially, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

[0080] In some possible embodiments, the maximum number of F symbols in each target data stream

number

number

[0081] In some possible embodiments, the data processing device further includes an encoder. After a total of m target data streams have been acquired, the encoder is configured to perform a second FEC encoding separately on the m target data streams, the length of the information bits of the second FEC encoding being equal to F symbols.

[0082] According to a fifth aspect, the present application provides a data processing method. The method includes the following steps: First, in order to obtain a total of m first data streams, n lane data streams every t items Block interleaving is performed on the lane data stream to obtain s first data streams, where n=q*t, m=q*s, where n is an integer greater than 1, n can be exactly divided by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. First forward error correction FEC coding is performed on all n lane data streams, and obtained by the first FEC coding a piece The codeword is distributed across b lane data streams, where a ≤ b ≤ n, n can be exactly divided by b, and a is an integer greater than or equal to 1. a piece The consecutive symbols are from different codewords, and within each lane data stream... Each L The consecutive symbols are from at least one different codeword, and L1 = N*a / b, where N is the length of the codeword. The t lane data streams are ,each Consecutive symbols within a lane data stream Therefore, a total of t*a symbols The symbols include t*a symbols ,each The Δ bit of the symbol, D = Δ*t*a Regarding the total D bits,The D bits are included, and the D bits are consecutive in any one of the s first data streams, such that Δ = M / s, where M represents the number of bits contained in one symbol. Next, convolutional interleaving is performed separately on the m first data streams to obtain m second data streams.

[0083] In some possible embodiments, within each first data stream every d The consecutive symbols are from v different codewords, each within the first data stream. Every 2 L The consecutive symbols are from at least v different codewords, where v can be divided exactly by a, and L2 = t / s * L1, and d = D / M.

[0084] In some possible embodiments, n=32, and the 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, the 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

[0085] In some possible embodiments, t=2, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing a block interleave on a lane data stream is: a step of performing a block interleave on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain a first data stream, where 0 ≤ i < 16. Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via the block interleave, and in the first data stream obtained via the block interleave every four The sequence of symbols comes from four different codewords.

[0086] In some possible embodiments, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the (

number

number

number

[0087] In some possible embodiments, t=2, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing a block interleave on a lane data stream includes: the step of performing a block interleave on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain a first data stream, where 0 ≤ i < 16. The jth consecutive β-bit group in the (2*i)th lane data stream and the jth consecutive β-bit group in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via the block interleave, where j ≥ 0 and β is 1, 2, 4, 5, 10, or 20 in the first data stream obtained via the block interleave. every four The sequence of symbols comes from four different codewords.

[0088] In some possible embodiments, t=2, s=2, and n lane data streams are used to obtain s first data streams. every t items The step of performing a block interleave on a lane data stream includes the step of performing a block interleave on the (2*i) lane data stream and the (2*i+1) lane data stream in order to obtain the (2*i) first data stream and the (2*i+1) first data stream, wherein 0 ≤ i < 16. 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream 5 bits in each of them, for a total of 20 bits. The first (2*i) data stream is continuous, and in the first (2*i) data stream every 20 The consecutive bits are from four different codewords, 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream The other 5 bits in each of them, for a total of 20 bits.The first (2*i+1) data stream is continuous, and in the first (2*i+1) data stream every 20 The consecutive bits come from four different codewords.

[0089] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0090] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0091] In some possible embodiments, t=4, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing block interleaving on lane data streams is to perform block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream in order to obtain one first data stream, where 0 ≤ i ≤ 7. 4 Two consecutive symbols are included in each of the two lane data streams. There are a total of eight symbols. However, it is continuous in the first data stream obtained by block interleaving, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0092] In some possible embodiments, t=4, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing block interleaving on lane data streams is to perform block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream in order to obtain one first data stream, where 0 ≤ i ≤ 7. 4The j-th two consecutive symbol groups to be included in each of the lane data streams There are a total of eight symbols. However, in the first data stream obtained by block interleaving, two consecutive symbol groups of the jth order, which are included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0093] In some possible embodiments, t=4, s=1, and n lane data streams every t items The step of performing block interleaving on lane data streams to obtain s first data streams is to perform block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream in order to obtain one first data stream, where 0 ≤ i ≤ 7. 4 The jth symbol to be included in each of the two lane data streams There are a total of four symbols.However, they are continuous in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every four The sequence of symbols, including the step, is derived from four different codewords.

[0094] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing a block interleave on a lane data stream is to perform a block interleave on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream in order to obtain one first data stream, wherein 0 ≤ i ≤ 3 and in the first data stream obtained by the block interleave 8 Two consecutive symbols are included in each of the two lane data streams. A total of 16 symbols These are consecutive, and in the first data stream obtained by block interleaving... every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are from different codewords, including the step.

[0095] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing block interleaving on the lane data stream is: A step of performing block interleaving on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, in order to obtain one first data stream, wherein 0 ≤ i ≤ 3, in the first data stream obtained by block interleaving 8 The jth two consecutive symbol groups to be included in each of the lane data streams A total of 16 symbols The two consecutive symbol groups of the jth order, which are included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are from different codewords, including the step.

[0096] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing block interleaving on lane data streams is to perform block interleaving on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream in order to obtain one first data stream, wherein 0 ≤ i ≤ 3, 8 The jth symbol to be included in each of the two lane data streams There are a total of eight symbols.However, in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The consecutive symbols are from four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0097] In some possible embodiments, n=32, and 16 consecutive lane data streams sorted before n lane data streams are from the same codeword, 16 consecutive lane data streams sorted after n lane data streams are from the same codeword, and 16 consecutive lane data streams sorted before n lane data streams and 16 consecutive lane data streams sorted after n lane data streams are from different codewords.

[0098] In some possible embodiments, t=2, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing a block interleave on a lane data stream is: a step of performing a block interleave on the i-th lane data stream and the (i+16)-th lane data stream to obtain a first data stream, where 0 ≤ i < 16. Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream are consecutive in the first data stream obtained via the block interleave, and in the first data stream obtained via the block interleave every four The sequence of symbols comes from four different codewords.

[0099] In some possible embodiments, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the (

number

number

number

[0100] In some possible embodiments, t=2, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing a block interleave on a lane data stream is: a step of performing a block interleave on the i-th lane data stream and the (i+16)-th lane data stream to obtain a first data stream, where 0 ≤ i < 16. The j-th consecutive β-bit group in the i-th lane data stream and the j-th consecutive β-bit group in the (i+16)-th lane data stream are consecutive in the first data stream obtained via the block interleave, where j ≥ 0 and β is 1, 2, 4, 5, 10, or 20 in the first data stream obtained via the block interleave. every four The sequence of symbols comes from four different codewords.

[0101] In some possible embodiments, t=2, s=2, and n lane data streams are used to obtain s first data streams. every t items The step of performing a block interleave on a lane data stream is: a step of performing a block interleave on the i-th lane data stream and the (i+16) lane data stream in order to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, wherein 0 ≤ i < 16. 4 Two symbols : Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16th) lane data stream 5 bits in each of them, for a total of 20 bits. The first (2*i) data stream is continuous, and in the first (2*i) data stream every 20 The consecutive bits are from four different codewords, 4 Two symbols : Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16th) lane data stream The other 5 bits in each of them, for a total of 20 bits.The first (2*i+1) data stream is continuous, and in the first (2*i+1) data stream every 20 The consecutive bits come from four different codewords.

[0102] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0103] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0104] In some possible embodiments, t=4, s=1, and n lane data streams are used to obtain s first data streams. every t itemsThe step of performing block interleaving on lane data streams is to perform block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream in order to obtain one first data stream, where 0 ≤ i ≤ 7. 4 Two consecutive symbols are included in each of the two lane data streams. There are a total of eight symbols. However, it is continuous in the first data stream obtained by block interleaving, and in the first data stream obtained by block interleaving every 8 The consecutive symbols are from at least four different codewords, and all 272 consecutive symbols are from at least four different codewords, and in the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0105] In some possible embodiments, t=4, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing block interleaving on lane data streams is to perform block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream in order to obtain one first data stream, where 0 ≤ i ≤ 7. 4The j-th two consecutive symbol groups to be included in each of the lane data streams There are a total of eight symbols. However, in the first data stream obtained by block interleaving, two consecutive symbol groups of the jth order, which are included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0106] In some possible embodiments, t=4, s=1, and n lane data streams every t items The step of performing block interleaving on lane data streams to obtain s first data streams is to perform block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, where 0 ≤ i ≤ 7. 4 The jth symbol to be included in each of the two lane data streams There are a total of four symbols.However, they are continuous in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every four The sequence of symbols, including the step, is derived from four different codewords.

[0107] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing a block interleave on a lane data stream is to perform a block interleave on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream in order to obtain one first data stream, wherein 0 ≤ i ≤ 3 and in the first data stream obtained by the block interleave 8 Two consecutive symbols are included in each of the two lane data streams. A total of 16 symbols These are consecutive, and in the first data stream obtained by block interleaving... every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are from different codewords, including the step.

[0108] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing a block interleave on a lane data stream is to perform a block interleave on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream in order to obtain one first data stream, wherein 0 ≤ i ≤ 3 and in the first data stream obtained by the block interleave 8 The jth two consecutive symbol groups to be included in each of the lane data streams A total of 16 symbols The two consecutive symbol groups of the jth order, which are included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are from different codewords, including the step.

[0109] In some possible embodiments, t=8, s=1, and n lane data streams are used to obtain s first data streams. every t items The step of performing block interleaving on lane data streams is to perform block interleaving on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream in order to obtain one first data stream, wherein 0 ≤ i ≤ 3, 8 The jth symbol to be included in each of the two lane data streams There are a total of eight symbols.However, in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is from at least four different codewords and is within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords, including the step.

[0110] In some possible embodiments, the step of performing a convolutional interleave on a first data stream to obtain a second data stream is the step of delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units including 0 memory units. Every 2 The difference in the number of memory units of adjacent delay lines is Q, each memory unit is configured to store d symbols, the symbols in each lane data stream are sequentially input into p delay lines based on the sequence number of the p delay lines, d symbols are input into each delay line once, and d symbols are output from the delay line once, and p*d consecutive symbols in the second data stream include the d symbols output from the delay lines, with Q being an integer greater than or equal to 1, including steps.

[0111] In some possible embodiments, the delay line with the largest sequence number among the p delay lines contains 0 memory units, d(p*Q+1)≧L2, and L2=t / s*L1; or the delay line with the smallest sequence number among the p delay lines contains 0 memory units, d(p*Q-1)≧L2, and L2=t / s*L1.

[0112] In some possible embodiments, after the step of performing convolutional interleaving separately on m first data streams to obtain m second data streams, the method further includes the step of performing second FEC coding separately on the m second data streams to obtain m coded data streams. In each coded data stream, the information data having length K symbols is from at most K different codewords, where K ≥ p*d.

[0113] In some possible embodiments, the step of performing a convolutional interleave on a first data stream to obtain a second data stream is the step of delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units including 0 memory units. Every 2 The difference in the number of memory units of adjacent delay lines is Q, each memory unit is configured to store 4 symbols, the symbols in each lane data stream are sequentially input into p delay lines based on the sequence number of the p delay lines, 4 symbols are input into each delay line once, and 4 symbols are output from the delay line once, so that p*4 consecutive symbols in the second data stream include the 4 symbols output from the delay lines, and Q includes steps that satisfy 4(p*Q-1)≧272, 4(p*Q-1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

[0114] In some possible embodiments, the method further includes the step of performing a convolutional interleave separately on m first data streams to obtain m second data streams, followed by the step of performing a second FEC coding separately on the m second data streams to obtain m coded data streams, wherein the information data in each coded data stream is of length K symbols and comes from at most K different codewords, where K ≥ p * 4.

[0115] In some possible embodiments, the step of performing a convolutional interleave on a first data stream to obtain a second data stream is the step of delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units including 0 memory units. Every 2 The difference in the number of memory units of adjacent delay lines is Q, including a step, where each memory unit is configured to store 34 bits, the bits in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, 34 bits are input to each delay line once, and 34 bits are output from each delay line once, so that p*34 consecutive bits in one second data stream include the output of 34 bits output from the delay lines; or each memory unit is configured to store 68 bits, the bits in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, 68 bits are input to each delay line once, and 68 bits are output from each delay line once, so that p*68 consecutive bits in one second data stream include the output of 68 bits output from the delay lines.

[0116] In some possible embodiments, p=2 and each memory unit is configured to store 68 bits, or p=4 and each memory unit is configured to store 34 bits.

[0117] According to a sixth aspect, the present application provides a data processing device. The data processing device includes a block interleaver and a convolutional interleaver. The block interleaver takes n lane data streams to obtain a total of m first data streams. every t items The lane data streams are configured to perform block interleaving against block interleaving, where n=q*t, m=q*s, where n is an integer greater than 1, n can be exactly divided by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. The first forward error correction FEC coding is performed on all n lane data streams, and the results obtained by the first FEC coding are a piece The codeword is distributed across b lane data streams, where a ≤ b ≤ n, n can be exactly divided by b, and a is an integer greater than or equal to 1. a piece Consecutive symbols are from different codewords, and all L1 consecutive symbols in each lane data stream are from at least one different codeword, where L1 = N*a / b, and N is the length of the codeword. t lane data streams are each Consecutive symbols within a lane data stream Therefore, a total of t*a symbols The symbols include t*a symbols each The Δ bit of the symbol, D = Δ*t*a The total is D bits. The D bits are contiguous in any one of the s first data streams, and Δ = M / s, where M represents the number of bits contained in one symbol. The convolutional interleaver is configured to perform convolutional interleaving separately on m first data streams to obtain m second data streams.

[0118] In some possible embodiments, within each first data stream every d The consecutive symbols are from v different codewords, each within the first data stream. Every 2 LThe consecutive symbols are from at least v different codewords, where v can be divided exactly by a, and L2 = t / s * L1, and d = D / M.

[0119] In some possible embodiments, n=32, and the 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, the 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

[0120] In some possible embodiments, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream such that 0≦i<16. Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via block interleaving, and in the first data stream obtained via block interleaving every four The sequence of symbols comes from four different codewords.

[0121] In some possible embodiments, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the (

number

number

number

[0122] In some possible embodiments, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream such that 0≦i<16. The jth consecutive β-bit group in the (2*i)th lane data stream and the jth consecutive β-bit group in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via block interleaving, where j≧0, β is 1, 2, 4, 5, 10, or 20, and in the first data stream obtained via block interleaving. every four The sequence of symbols comes from four different codewords.

[0123] In some possible embodiments, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, such that 0≦i<16. 4 Two symbols : Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream 5 bits in each of them, for a total of 20 bits. The first (2*i) data stream is continuous, and in the first (2*i) data stream every 20 The consecutive bits are from four different codewords, 4 Two symbols :Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream The other 5 bits in each of them, for a total of 20 bits. The first (2*i+1) data stream is continuous, and in the first (2*i+1) data stream every 20 The consecutive bits come from four different codewords.

[0124] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0125] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0126] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, where 0≦i≦7. 4 Two consecutive symbols are included in each of the two lane data streams. There are a total of eight symbols. However, it is continuous in the first data stream obtained by block interleaving, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0127] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, where 0≦i≦7. 4 The j-th two consecutive symbol groups to be included in each of the lane data streams There are a total of eight symbols.However, in the first data stream obtained by block interleaving, two consecutive symbol groups of the jth order, which are included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0128] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, where 0≦i≦7. 4 The jth symbol to be included in each of the two lane data streams There are a total of four symbols. However, they are continuous in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every four The sequence of symbols is specifically constructed to be derived from four different codewords.

[0129] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of eight lane data streams to obtain one first data stream: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleave. 8 Two consecutive symbols are included in each of the two lane data streams. A total of 16 symbols These are consecutive, and in the first data stream obtained by block interleaving... every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0130] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of eight lane data streams to obtain one first data stream: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleave. 8 The jth two consecutive symbol groups to be included in each of the lane data streams A total of 16 symbols The two consecutive symbol groups of the jth, provided in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving. every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0131] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of 8 lane data streams to obtain one first data stream: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, where 0≦i≦3. 8 The jth symbol to be included in each of the two lane data streams There are a total of eight symbols. However, in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The consecutive symbols are from four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0132] In some possible embodiments, n=32, and 16 consecutive lane data streams sorted before n lane data streams are from the same codeword, 16 consecutive lane data streams sorted after n lane data streams are from the same codeword, and 16 consecutive lane data streams sorted before n lane data streams and 16 consecutive lane data streams sorted after n lane data streams are from different codewords.

[0133] In some possible embodiments, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain one first data stream such that 0≦i<16. Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream are consecutive in the first data stream obtained via block interleaving, and in the first data stream obtained via block interleaving every four The sequence of symbols comes from four different codewords.

[0134] In some possible embodiments, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the (

number

number

number

[0135] In some possible embodiments, t=2, s=1, and the block interleaver is specifically configured to perform block interleaving on the i-th lane data stream and the (i+16th) lane data stream to obtain one first data stream such that 0≦i<16. The j-th consecutive β-bit group in the i-th lane data stream and the j-th consecutive β-bit group in the (i+16th) lane data stream are consecutive in the first data stream obtained via block interleaving, such that j≧0, β is 1, 2, 4, 5, 10, or 20, and in the first data stream obtained via block interleaving every four The sequence of symbols comes from four different codewords.

[0136] In some possible embodiments, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, such that 0≦i<16. 4 Two symbols : Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16th) lane data stream 5 bits in each of them, for a total of 20 bits. The first (2*i) data stream is continuous, and in the first (2*i) data stream every 20 The consecutive bits are from four different codewords, 4 Two symbols : Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16th) lane data stream The other 5 bits in each of them, for a total of 20 bits.The first (2*i+1) data stream is continuous, and in the first (2*i+1) data stream every 20 The consecutive bits come from four different codewords.

[0137] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0138] In some possible embodiments, the fth bit of the 20 consecutive bits in the first (2*i+g) data stream is the (

number

number

[0139] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, where 0≦i≦7. 4 Two consecutive symbols are included in each of the two lane data streams. There are a total of eight symbols.However, it is continuous in the first data stream obtained by block interleaving, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0140] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, where 0≦i≦7. 4 The j-th two consecutive symbol groups to be included in each of the lane data streams There are a total of eight symbols. However, in the first data stream obtained by block interleaving, two consecutive symbol groups of the jth order, which are included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is derived from at least four different codewords. Every 272The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0141] In some possible embodiments, t=4, s=1, and the block interleaver performs block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, where 0≦i≦7. 4 The jth symbol to be included in each of the two lane data streams There are a total of four symbols. However, they are continuous in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every four The sequence of symbols is specifically constructed to be derived from four different codewords.

[0142] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of eight lane data streams to obtain one first data stream: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleave. 8 Two consecutive symbols are included in each of the two lane data streams. A total of 16 symbols These are consecutive, and in the first data stream obtained by block interleaving... every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0143] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of eight lane data streams to obtain one first data stream: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleave. 8 The jth two consecutive symbol groups to be included in each of the lane data streams A total of 16 symbols The two consecutive symbol groups of the jth order, which are included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 16 The consecutive symbols are from at least four different codewords, Every 544 The consecutive symbols are from at least four different codewords and are within the first data stream obtained by block interleaving. every 16 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16The eighth, ninth, tenth, and eleventh symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 16 The 12th, 13th, 14th, and 15th symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0144] In some possible embodiments, t=8, s=1, and the block interleaver performs block interleaving on a total of 8 lane data streams to obtain one first data stream: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19th) lane data stream, where 0≦i≦3. 8 The jth symbol to be included in each of the two lane data streams There are a total of eight symbols. However, in the first data stream obtained by block interleaving, j≧0, and in the first data stream obtained by block interleaving every 8 The sequence of symbols is from at least four different codewords and is within the first data stream obtained by block interleaving. every 8 The 0th, 1st, 2nd, and 3rd symbols in the sequence of symbols are from different codewords and are within the first data stream obtained by block interleaving. every 8 The fourth, fifth, sixth, and seventh symbols in the sequence of symbols are specifically constructed to be from different codewords.

[0145] In some possible embodiments, the convolutional interleaver delays one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line contains a different number of memory units, with the delay line having the fewest memory units containing zero memory units. Every two The difference in the number of memory units of adjacent delay lines is Q, each memory unit is configured to store d symbols, the symbols in each lane data stream are sequentially input into p delay lines based on the sequence number of the p delay lines, d symbols are input into each delay line once, and d symbols are output from the delay line once, and p*d consecutive symbols in the second data stream include the d symbols output from the delay lines, and Q is specifically configured to be an integer greater than or equal to 1.

[0146] In some possible embodiments, the delay line with the largest sequence number among the p delay lines contains 0 memory units, d(p*Q+1)≧L2, and L2=t / s*L1; or the delay line with the smallest sequence number among the p delay lines contains 0 memory units, d(p*Q-1)≧L2, and L2=t / s*L1.

[0147] In some possible embodiments, the data processing device further includes an encoder. After m second data streams have been acquired, the encoder is configured to perform a second FEC encoding separately on the m second data streams to obtain m encoded data streams. In each encoded data stream, the information data, having a length of K symbols, comes from at most K different codewords, where K ≥ p*d.

[0148] In some possible embodiments, the convolutional interleaver delays one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line contains a different number of memory units, with the delay line having the fewest memory units containing zero memory units. Every two The difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store 4 symbols, and the symbols in each lane data stream are sequentially input into p delay lines based on the sequence number of the p delay lines, 4 symbols are input into each delay line once, and 4 symbols are output from the delay line once, and p*4 consecutive symbols in the second data stream include the 4 symbols output from the delay line, and Q is specifically configured to satisfy 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

[0149] In some possible embodiments, the data processing device further includes an encoder. After m second data streams have been acquired, the encoder is configured to separately perform a second FEC encoding on the m second data streams in order to acquire m encoded data streams, wherein the information data in each encoded data stream is of length K symbols and comes from at most K different codewords, where K ≥ p * 4.

[0150] In some possible embodiments, a convolutional interleaver delays one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and the number of memory units included in each delay line varies, with the delay line having the fewest memory units containing zero memory units. Every 2The difference in the number of memory units of adjacent delay lines is specifically configured to be Q, each memory unit is configured to store 34 bits, the bits in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, 34 bits are input to each delay line once, and 34 bits are output from each delay line once, so that p*34 consecutive bits in one second data stream include the 34 bits output from the delay lines; or each memory unit is configured to store 68 bits, the bits in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, 68 bits are input to each delay line once, and 68 bits are output from each delay line once, so that p*68 consecutive bits in one second data stream include the 68 bits output from the delay lines.

[0151] In some possible embodiments, p=2 and each memory unit is configured to store 68 bits, or p=4 and each memory unit is configured to store 34 bits.

[0152] According to the seventh aspect, the present application provides a data processing method. The method comprises the following steps: First, in order to obtain n first data streams, n lane data streams are separately delayed based on p delay lines. A first forward error correction FEC coding is performed on all n lane data streams, where p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units containing 0 memory units. Every twoThe difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store U bits. The bits in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, with each U bit being input to each delay line once and each U bit being output from the delay line once. p*U consecutive bits in one second data stream include the U bits output from the delay lines, where Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. Next, to obtain n second data streams, the second FEC coding is performed separately on the n first data streams. The information data of each codeword in the second data stream obtained by the second FEC coding is p*U bits, output once from the p delay lines.

[0153] In some possible embodiments, p*U = 120, 136, or 160.

[0154] According to the eighth aspect, the present application provides a data processing device comprising a convolutional interleaver and an encoder. The convolutional interleaver is configured to separately delay n lane data streams based on p delay lines in order to obtain n first data streams. A first forward error correction FEC coding is performed on all of the n lane data streams, where p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units containing 0 memory units. Every twoThe difference in the number of memory units of adjacent delay lines is Q, and each memory unit is configured to store U bits. The bits in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, with each U bit being input to each delay line once and each U bit being output from the delay line once. p*U consecutive bits in one second data stream include the U bits output from the delay lines, where Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. The encoder is then configured to separately perform the second FEC coding on n first data streams to obtain n second data streams. The information data for each codeword in the second data streams obtained by the second FEC coding is p*U bits, which are output once from the p delay lines.

[0155] In some possible embodiments, p*U = 120, 136, or 160.

[0156] According to the ninth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by hardware, some or all of the steps of any of the first, third, fifth, or seventh aspects of the method may be performed.

[0157] In the embodiments of this application, all n lane data streams are externally code-encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by the convolutional interleaving to obtain m second data streams, after which internal code encoding is performed. According to the data interleaving and multiplexing processing solution provided in this application, the following case can be implemented with low latency: multiple symbols output sequentially from the m multiplexed data streams are from multiple different external codewords, and as a result the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, in this application, the combined solution of convolutional interleaving and data multiplexing can reduce the overall latency of the concatenated FEC solution and is more applicable to application scenarios requiring low latency. [Brief explanation of the drawing]

[0158] [Figure 1] This is a schematic diagram of a communication system according to an embodiment of the present application. [Figure 2] Figure 1 is a schematic diagram of the data transmission process in the communication system shown. [Figure 3a] This is a schematic diagram of the first type of data processing by the transmitting processing module according to an embodiment of the present application. [Figure 3b] This is a schematic diagram of a second type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 3c] This is a schematic diagram of a third type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 3d] This is a schematic diagram of a fourth type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 3e] This is a schematic diagram of lane data alignment according to an embodiment of the present application. [Figure 3f]This is a schematic diagram of a fifth type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 3g] This is a schematic diagram of a sixth type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 3h] This is a schematic diagram of a seventh type of data processing by a transmitting processing module according to an embodiment of the present application. [Figure 3i] This is a schematic diagram of an eighth type of data processing by a transmitting-side processing module according to an embodiment of the present application. [Figure 4a] This is a schematic diagram of the first type of data processing by the receiving processing module according to an embodiment of the present application. [Figure 4b] This is a schematic diagram of a second type of data processing by a receiving-side processing module according to an embodiment of the present application. [Figure 4c] This is a schematic diagram of a third type of data processing by a receiving-side processing module according to an embodiment of the present application. [Figure 5] This is a schematic diagram of the 32 PCS lane data streams corresponding to the 1 x 800G interface used by the transmitting device. [Figure 6] This is a schematic diagram of the 32 PCS lane data streams corresponding to the 2 x 400G interface used by the transmitting device. [Figure 7] This is a schematic diagram of the 32 PCS lane data streams corresponding to the 4x200G interface used by the transmitting device. [Figure 8] This is a schematic diagram of the 32 FEC lane data streams corresponding to the 8x100G interface used by the transmitting device. [Figure 9] This is another schematic diagram of the 32 FEC lane data streams corresponding to the 8x100G interface used by the transmitting device. [Figure 10] This is a schematic flowchart of the data processing method according to the embodiment of this application. [Figure 11]This is a schematic diagram of a structure in which convolutional interleaving is performed separately for n lane data streams according to an embodiment of the present application. [Figure 12a] This is a schematic diagram of the first structure of a convolutional interleaver according to an embodiment of the present application. [Figure 12b] This is a schematic diagram of the second structure of a convoluted interleaver according to an embodiment of the present application. [Figure 13] This is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application. [Figure 14] This is a schematic diagram of the first structure of a multiplexer according to an embodiment of the present application. [Figure 15] This is a schematic diagram of a structure in which FEC coding is performed on m second data streams according to an embodiment of the present application. [Figure 16a] This is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application. [Figure 16b] This is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 17a] This is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application. [Figure 17b] This is a schematic diagram of a third structure of a multiplexer according to an embodiment of the present application. [Figure 17c] This is a schematic diagram of a fourth structure of a multiplexer according to an embodiment of the present application. [Figure 18a] This is a schematic diagram of a fifth structure of a convoluted interleaver according to an embodiment of the present application. [Figure 18b] This is a schematic diagram of a sixth structure of a convoluted interleaver according to an embodiment of the present application. [Figure 19a] This is a schematic diagram of the seventh structure of a convoluted interleaver according to an embodiment of the present application. [Figure 19b] This is a schematic diagram of the eighth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 20]This is a schematic diagram of the ninth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 21] This is a schematic diagram of the tenth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 22] This is a schematic diagram of a fifth structure of a multiplexer according to an embodiment of the present application. [Figure 23] This is a schematic diagram of the 11th structure of a convolutional interleaver according to an embodiment of the present application. [Figure 24] This is a schematic diagram of a sixth structure of a multiplexer according to an embodiment of the present application. [Figure 25] This is a schematic diagram of the twelfth structure of a convolutional interleaver according to an embodiment of the present application. [Figure 26] This is a schematic diagram of the 13th structure of a convolutional interleaver according to an embodiment of the present application. [Figure 27a] This is a schematic diagram of the 14th structure of a convoluted interleaver according to an embodiment of the present application. [Figure 27b] This is a schematic diagram of the 15th structure of a convoluted interleaver according to an embodiment of the present application. [Figure 28a] This is a schematic diagram of the 16th structure of a convoluted interleaver according to an embodiment of the present application. [Figure 28b] This is a schematic diagram of the 17th structure of a convoluted interleaver according to an embodiment of the present application. [Figure 29a] This is a schematic diagram of the 18th structure of a convolutional interleaver according to an embodiment of the present application. [Figure 29b] This is a schematic diagram of the 19th structure of a convolutional interleaver according to an embodiment of the present application. [Figure 30a] This is a schematic diagram of a 20th structure of a convolutional interleaver according to an embodiment of the present application. [Figure 30b] This is a schematic diagram of the 21st structure of a convoluted interleaver according to an embodiment of the present application. [Figure 31a] This is a schematic diagram of the 22nd structure of a convolutional interleaver according to an embodiment of the present application. [Figure 31b]This is a schematic diagram of the 23rd structure of a convolutional interleaver according to an embodiment of the present application. [Figure 32a] This is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application. [Figure 32b] This is a schematic diagram of the structure of a block interleaver according to an embodiment of the present application. [Figure 33] This is a schematic diagram of the structure of a data processing device according to an embodiment of this application. [Figure 34] This is a schematic flowchart of interleaving according to the embodiment of this application. [Figure 35] This is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application. [Figure 36] This is a schematic diagram of an embodiment in which block interleaving is performed according to the embodiment of this application. [Figure 37] This is a schematic diagram of the lane-aligned data stream format for a 2x400GbE host interface. [Figure 38] This is a schematic diagram of an embodiment of block interleaving. [Figure 39] This is a schematic diagram of another embodiment of block interleaving. [Figure 40] This is a schematic diagram of another embodiment of block interleaving. [Figure 41] This is a schematic diagram of another embodiment of block interleaving. [Figure 42] This is another schematic flowchart of interleaving according to the embodiments of this application. [Figure 43] This is a schematic diagram of an embodiment of the first block interleaving according to the embodiments of this application. [Figure 44a] This is a schematic diagram of an embodiment of performing a second block interleaving according to the embodiments of this application. [Figure 44b]This is a schematic diagram of a specific embodiment of performing a second block interleaving according to the embodiments of this application. [Figure 45a] This is a schematic diagram of a first embodiment of block interleaving. [Figure 45b] This is a schematic diagram of an embodiment of convolutional interleaving. [Figure 45c] This is a schematic diagram of another embodiment of convolutional interleaving. [Figure 45d] This is a schematic diagram of a second embodiment of block interleaving. [Figure 46a] This is a schematic diagram of another embodiment of convolutional interleaving. [Figure 46b] This is a schematic diagram of another embodiment of convolutional interleaving. [Figure 46c] This is a schematic diagram of another embodiment of the second block interleaving. [Figure 47] This is a schematic diagram of another embodiment of the second block interleaving. [Figure 48] This is a schematic diagram of another embodiment of the second block interleaving. [Figure 49] This is a schematic diagram of another embodiment of the first block interleaving. [Figure 50a] This is a schematic diagram of another structure of the data processing device according to an embodiment of this application. [Figure 50b] This is a schematic diagram of another structure of the data processing device according to an embodiment of this application. [Figure 51] This is a schematic flowchart of the data processing method according to the embodiment of this application. [Figure 52] This is a schematic diagram of a structure in which block interleaving is performed on n lane data streams according to an embodiment of this application. [Figure 53] This is a schematic diagram illustrating the application scenario of block interleaving according to the embodiment of this application. [Figure 54] This is a schematic diagram of several specific embodiments of block interleaving according to the embodiments of this application. [Figure 55]This is a schematic diagram of another application scenario of block interleaving according to the embodiments of this application. [Figure 56] This is a schematic diagram of several specific embodiments of block interleaving according to the embodiments of this application. [Figure 57] This is a schematic diagram of another application scenario of block interleaving according to the embodiments of this application. [Figure 58] This is a schematic diagram of another application scenario of block interleaving according to the embodiments of this application. [Figure 59] This is a schematic diagram of another application scenario of block interleaving according to the embodiments of this application. [Figure 60] This is a schematic diagram of another application scenario of block interleaving according to the embodiments of this application. [Figure 61] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 62] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 63] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 64] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 65] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 66] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 67] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 68] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 69] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 70] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 71] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 72] This is a schematic diagram of yet another application scenario of block interleaving according to the embodiments of this application. [Figure 73] This is a schematic diagram of a structure in which convolutional interleaving is performed separately for m first data streams according to an embodiment of the present application. [Figure 74] This is a schematic diagram of an embodiment of a convolutional interleaver according to the present application. [Figure 75] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 76] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 77] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 78] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 79] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 80] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 81] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 82] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 83] This is a schematic diagram of another embodiment of the convolutional interleaver according to the embodiments of this application. [Figure 84] This is a schematic diagram of an embodiment of internal code encoding according to the embodiments of this application. [Figure 85]This is a schematic diagram of the structure of a data processing device according to an embodiment of this application. [Figure 86] This is another schematic flowchart of the data processing method according to the embodiment of this application. [Figure 87] This is a schematic diagram of another structure of the data processing device according to an embodiment of this application. [Figure 88] This is a schematic diagram of another structure of the data processing device according to an embodiment of this application. [Modes for carrying out the invention]

[0159] Embodiments of this application provide data processing methods and data processing devices such that better performance of a linked FEC solution can be achieved in low-latency scenarios. Note that in the specification, claims, and accompanying drawings of this application, terms such as “first,” “second,” etc., are intended to distinguish similar subjects but do not necessarily indicate a specific order or sequence. The aforementioned terms are interchangeable in appropriate contexts, and therefore, the embodiments described in this application may be carried out in an order other than that described herein. Furthermore, terms such as “include,” “have,” or any other variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units may include, but is not limited to, any other steps and units not explicitly listed or specific to the process, method, product, or device.

[0160] Figure 1 is a schematic diagram of a communication system according to an embodiment of the present application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. For example, the communication system is a data center network. The transmitting device 01 and the receiving device 05 may be devices such as switches or routers, the transmitting device 01 is also called a host chip located in the transmitter, the receiving device 05 is also called a host chip located in the receiver, and the channel transmission medium 03 may be an optical fiber. The host chip is also called a host device. The transmitting device 01 may be connected to the transmitting processing module 02 via an attachment unit interface (AUI), and the receiving device 05 may be connected to the receiving processing module 04 via an AUI. The transmitting processing module 02 and the receiving processing module 04 may each be an optical module, an electrical module, a connector, or another module that processes data in the data transmission process. For example, the processing module may be an 800LR module (which is a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in the communication system may all support bidirectional or unidirectional transmission. This is not specifically limited herein.

[0161] Figure 2 is a schematic diagram of the data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from a transmitting device 01 to a receiving device 05, the transmitting device 01 is configured to perform external code encoding on the data and then transmit the externally code encoded data to a transmitting processing module 02. The transmitting processing module 02 is configured to perform internal code encoding on the externally code encoded data to obtain the externally code encoded and internally code encoded data and transmit the externally code encoded and internally code encoded data to a channel transmission medium 03. The channel transmission medium 03 is configured to transmit the externally code encoded and internally code encoded data to a receiving processing module 04. The receiving processing module 04 is configured to perform internal code decoding on the externally code encoded and internally code encoded data and transmit the internally code decoded data to a receiving device 05. The receiving device 05 is configured to perform external code decoding on the internally code decoded data.

[0162] It should be understood that the distinction between "internal" in internal code and "external" in external code is based solely on the distance between the execution body that performs operations on the data and the channel transmission medium 03. The execution body that performs operations on internal code is close to the channel transmission medium, while the execution body that performs operations on external code is far from the channel transmission medium. In the embodiments of this application, data is transmitted from the transmitting device 01 to the channel transmission medium 03 via the transmitting processing module 02, and then transmitted from the channel transmission medium 03 to the receiving device 05 via the receiving processing module 04. The distance over which the data encoded by the transmitting device 01 travels to the channel transmission medium 03 is longer than the distance over which the data encoded by the transmitting processing module 02 travels, and the distance over which the data decoded by the receiving device 05 travels to the channel transmission medium 03 is longer than the distance over which the data decoded by the receiving processing module 04 travels. Therefore, data encoded by the transmitting device 01 is called external code-encoded data, data encoded by the transmitting processing module 02 is called internal code-encoded data, data decoded by the receiving device 05 is called external code-decoded data, and data decoded by the receiving processing module 04 is called internal code-decoded data. In possible embodiments, both internal and external code encoding use the FEC encoding style to form a concatenated FEC transmission solution. For example, the transmitting device 01 may perform external code encoding using RS code, and the transmitting processing module 02 may perform internal code encoding using Hamming code. As another example, the transmitting device 01 may perform external code encoding using RS code, and the transmitting processing module 02 may perform internal code encoding using Bose-Chaudhuri-Hocquenghem (BCH) code.

[0163] It should be noted that the foregoing is an illustrative description of application scenarios for the data interleaving method provided in the embodiments of this application and does not constitute any limitation to the application scenarios of the data interleaving method. Those skilled in the art will know that as service requirements change, the application scenarios for the data interleaving method may be adjusted based on the requirements being applied. The embodiments of this application do not list one application scenario at a time.

[0164] In the aforementioned concatenated FEC transmission solution, a data processing solution including "convolutional interleaving" and "multiplexing" is designed in this application to achieve good performance and low latency for the entire concatenated FEC solution. Thus, the concatenated FEC transmission solution can be applied to multiple transmission scenarios and is particularly applicable to transmission scenarios requiring low transmission latency, such as low-latency data center interconnection scenarios. Data processing is performed via the aforementioned transmission-side processing module 02.

[0165] Figure 3(a) is a schematic diagram of a first type of data processing by a transmitting processing module according to an embodiment of the present application. As shown in Figure 3(a), after processing data from multiple client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting processing module can acquire n external code-encoded physical coding sublayer (PCS) or FEC lane data streams and perform alignment lock and lane data alignment to acquire n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on alignment markers so that the n lanes of data can be arranged in a specified sequence. The n lane data streams acquired by lane reordering are sent to a designed processor including convolutional interleaving and muxing for data sequence irregularization, and then to an internal code encoder for internal code encoding. After data processing is performed on the internally coded data stream, the processed data stream is sent to the channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0166] Figure 3(b) is a schematic diagram of a second type of data processing by a transmitting processing module according to an embodiment of the present application. As shown in Figure 3(b), in some practical application scenarios, n aligned lane data streams obtained by lane data alignment are already arranged in a specified sequence. In this case, lane reordering does not need to be performed, and the n aligned lane data streams are sent directly to a designed processor that includes convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an internal code encoder for internal code encoding.

[0167] In some possible embodiments, unlike the data processing procedures described in Figures 3(a) and 3(b), the n aligned lane data streams obtained by lane data alignment may instead not be convolutionally interleaved, but may be directly multiplexed and sent to an internal code encoder for internal code encoding.

[0168] Figure 3(c) is a schematic diagram of a third type of data processing by the transmitting processing module according to an embodiment of the present application. As shown in Figure 3(c), unlike the data processing procedure shown in Figure 3(a), the n lane data streams obtained by lane reordering are directly multiplexed without convolutional interleaving and sent to an internal code encoder for internal code encoding.

[0169] Figure 3(d) is a schematic diagram of a fourth type of data processing by the transmitting processing module according to an embodiment of the present application. As shown in Figure 3(d), unlike the data processing procedure shown in Figure 3(b), the n lane data streams acquired by lane data alignment are directly multiplexed without convolutional interleaving and sent to the internal code encoder for internal code encoding.

[0170] Figure 3(e) is a schematic diagram of lane data alignment according to an embodiment of the present application. It should be understood that the aforementioned “lane data alignment” may be a lane de-skew as defined in existing standards, and may be used to ensure that the data in n lane data streams output via the lane data alignment is perfectly aligned. Alternatively, the above “lane data alignment” may simply be lane symbol alignment, where the data in n lane data streams output via the lane data alignment is aligned based on external code symbols. Specifically, the data may be aligned based on one or more external code symbols. Figure 3(e) uses two lane data streams as an example to illustrate the specific operation of “lane data alignment.” It is assumed that the external code is an RS code, and that the length of one RS code symbol is 10 bits. Scenario (a) in Figure 3(e) shows a 75-bit deviation between the two lane data streams, with AM 0 and AM 1 being the alignment markers for lane data stream 0 and lane data stream 1, respectively. In scenario (b) of Figure 3(e), lane de-skew as defined in existing standards is used, so there is no deviation between output lane data stream 0 and output lane data stream 1. In scenario (c) of Figure 3(e), one RS symbol-based alignment is performed, aligning one RS symbol for output lane data stream 0 and one RS symbol for output lane data stream 1. In this case, a 70-bit deviation still exists between the two lanes. In scenario (d) of Figure 3(e), two RS symbol-based alignments are performed, aligning two RS symbols for output lane data stream 0 and two RS symbols for output lane data stream 1. In this case, a 60-bit deviation still exists between the two lanes.

[0171] Figure 3(f) is a schematic diagram of a fifth type of data processing by a transmitting processing module according to an embodiment of the present application. As shown in Figure 3(f), after processing data from multiple client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting processing module can acquire n Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment lock and lane data alignment to acquire n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on alignment markers so that the n lanes of data are arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and block interleaving, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0172] Figure 3(g) is a schematic diagram of a sixth type of data processing by a transmitting processing module according to an embodiment of the present application. As shown in Figure 3(g), after processing data from multiple synchronous client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting processing module may acquire n Physical Coding Sublayer (PCS) or FEC lane data streams, the PCS lane data streams and FEC lane data streams collectively referred to as lane data streams, and may perform alignment lock and lane data alignment to acquire n aligned lane data streams. Next, lane reorder is performed on the n lanes of data based on alignment markers, so that the n lanes of data are arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a designed processor that includes a first block interleaving, convolutional interleaving, and a second block interleaving for interleaving and data sequence irregularization, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internal code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0173] Figure 3(h) is a schematic diagram of a seventh type of data processing by a transmitting processing module according to an embodiment of the present application. As shown in Figure 3(h), after processing data from multiple client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting processing module can acquire n Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment lock and lane data alignment to acquire n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on alignment markers so that the n lanes of data are arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a processor designed for interleaving and data sequence irregularization, including block interleaving and convolutional interleaving, and then to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0174] Figure 3(i) is a schematic diagram of an eighth type of data processing by a transmitter processing module according to an embodiment of the present application. As shown in Figure 3(i), after processing data from n synchronous client lanes, such as an AUI-n interface, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module can acquire n externally code-encoded lane data streams. The PMA sublayer herein only needs to perform signal recovery operations such as clock data recovery (CDR) and PAM4 symbol demodulation on the data from each client lane to acquire one lane data stream, and does not need to perform other complex operations such as AM locking, lane deskew, and lane reordering. The n lane data streams are sent to a designed processor, including convolutional interleaving, for interleaving and data sequence irregularization, and then to an internal code encoder for internal code encoding. After data processing is performed on the internally code-encoded data streams, the processed data streams are sent to a channel transmit medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, and DSP framing. In this specification, n is a positive integer greater than 1.

[0175] In some practical application scenarios, RS external code coding means that after coding is performed using two encoders, interleaving such as two-way interleaving is performed so that RS symbols on lane data streams with even sequence numbers are transmitted in the form "ABABA B..." and RS symbols on lane data streams with odd sequence numbers are transmitted in the form "BABAB A...", where A and B are two RS symbols generated by different encoders. In the case of two RS symbol-based alignment, the effect of the embodiment is that RS symbols on all lane data streams with even sequence numbers are generated by the same encoder at the same moment, and RS symbols on all lane data streams with odd sequence numbers are generated by another same encoder at the same moment; or the effect of another embodiment is that RS symbols on all lane data streams are generated by the same encoder at the same moment. Specific forms are not limited herein.

[0176] Figure 4(a) is a schematic diagram of a first type of data processing by a receiver processing module according to an embodiment of the present application. As shown in Figure 4(a), the receiver processing module receives a data stream from a channel transmitting medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing is performed on the data stream from the transmitter processing module, the receiver processing module first performs the corresponding inverse data processing and then sends the data stream to an internal code decoder for decoding. After internal code decoding, the data stream is sent to a processor including convolutional deinterleaving and demultiplexing for processing to obtain n lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to the receiver device for external code decoding. Convolutional de-interleaving and de-muxing in the receiving processing module are the reverse operations of convolutional interleaving and de-muxing in the transmitting processing module. Convolutional de-interleaving is the reverse operation of convolutional interleaving in the transmitting processing module, and de-muxing is the reverse operation of multiplexing in the transmitting processing module. Convolutional interleaving and de-muxing in the transmitting processing module will be described in detail below. Convolutional de-interleaving and de-muxing in the receiving processing module are the reverse operations of convolutional interleaving and multiplexing in the transmitting processing module shown in Figures 3(a) and 3(b). This is well known to those skilled in the art and is not described herein.

[0177] Figure 4(b) is a schematic diagram of a second type of data processing by a receiver processing module according to an embodiment of the present application. As shown in Figure 4(b), the receiver processing module receives a data stream from a channel transmitting medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing is performed on the data stream from the transmitter processing module, the receiver processing module first performs the corresponding inverse data processing and then sends the data stream to an internal code decoder for decoding. After internal code decoding, the data stream is sent to a processor for processing, including block deinterleaving and convolutional deinterleaving, to obtain n lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to the receiver device for external code decoding. In this specification, block deinterleaving and convolution deinterleaving in the receiving processing module are the reverse operations of block interleaving and convolution interleaving in the transmitting processing module shown in Figure 3(f). Convolution deinterleaving is the reverse operation of convolution interleaving in the transmitting processing module, and block deinterleaving is the reverse operation of block interleaving in the transmitting processing module.

[0178] Figure 4(c) is a schematic diagram of a third type of data processing by a receiver processing module according to an embodiment of the present application. As shown in Figure 4(c), the receiver processing module receives a data stream from a channel transmitting medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing is performed on the data stream from the transmitter processing module, the receiver processing module first performs the corresponding inverse data processing and then sends the data stream to an internal code decoder for decoding. After internal code decoding, the data stream is sent for processing to a second block deinterleave, a convolutional deinterleave, and a first block deinterleave to obtain n lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to the receiver device for external code decoding. In this specification, the first block deinterleave, convolutional deinterleave, and second block deinterleave in the receiving processing module are the reverse operations of the first block interleave, convolutional interleave, and second block interleave in the transmitting processing module shown in Figure 3(g), respectively. The first block interleave, convolutional interleave, and second block interleave in the transmitting processing module will be described in detail below. The first block deinterleave, convolutional deinterleave, and second block deinterleave in the receiving processing module are the reverse operations of the first block interleave, convolutional interleave, and second block interleave in the transmitting processing module, respectively. This is well known to those skilled in the art and is not described herein.

[0179] The following provides several specific scenarios to which embodiments of this application may apply. Note that, for ease of explanation, the following specific scenarios will be illustrated using the example where "lane data alignment" is lane deskew.

[0180] Figure 5 is a schematic diagram of 32 PCS lane data streams corresponding to a 1 x 800G interface used by the transmitting device. As shown in Figure 5, the transmitting device performs external code encoding of KP4 RS(544,514) code for one channel of the 800GbE service data stream to be transmitted in order to obtain the 32 PCS lane data streams. Every 68 The consecutive symbols form a total of 16 * 68 = 1088 symbols, each containing two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols in the same location within two adjacent PCS lane data streams are from different RS codewords. Similarly, in each of the PCS lane data streams 16 to 31 Every 68 The consecutive symbols form a total of 16 * 68 = 1088 symbols, each containing two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols in the same location within two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmitting processing module via the mounting unit interface 800GAUI-8.

[0181] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the lane data stream based on the known alignment markers of the PCS lanes. The known alignment markers for the 32 lanes are different (see "Ethernet Technology Consortium 800G Specification"). The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers, a lane reorder is performed on the data of the n=32 lanes so that the data of the n=32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from 0 to 31 from top to bottom, which is the same as shown in Figure 5.

[0182] Figure 6 is a schematic diagram of 32 PCS lane data streams corresponding to the 2×400G interface used by the transmitting device. As shown in Figure 6, the transmitting device performs external code encoding of KP4 RS(544,514) code for two channels of the 400GbE service data stream to be transmitted. P Two channels of CS lane data stream A total of 32 PCS lane data streams The data is obtained, and each channel contains 16 PCS lane data streams. Each of the PCS lane data streams 0 to 15 or PCS lane data streams 16 to 31 Every 68The consecutive symbols form a total of 16 * 68 = 1088 symbols, each containing two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols in the same location within two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmitting processing module via the mounting unit interface 2x400GAUI-4.

[0183] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on 16 lane data streams based on known alignment markers for PCS lanes 0 through 15 or PCS lanes 16 through 31. PCS lanes 0 through 15 may be considered as PCS lanes 0 through 15 of the 0th channel of the 400G, and PCS lanes 16 through 31 may be considered as PCS lanes 0 through 15 of the 1st channel of the 400G. The known alignment markers for 16 lanes in the 0th channel of the 400G are the same as the known alignment markers for 16 lanes in the 1st channel of the 400G. The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in PCS lanes 0 through 15 or PCS lanes 16 through 31, a lane reorder is performed on the data in the 16 lanes so that the data in the 16 lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as shown in Figure 6.

[0184] Figure 7 is a schematic diagram of 32 PCS lane data streams corresponding to the 4×200G interface used by the transmitting device. As shown in Figure 7, the transmitting device performs external code encoding of KP4 RS(544,514) code for the four channels of the 200GbE service data stream to be transmitted. P Four channels of the CS lane data stream A total of 32 The PCS lane data stream is acquired, and each channel contains 8 PCS lane data streams. PCS lane data streams 0 to 7, PCS lane data streams 8 to 15, PCS lane data streams 16 to 23, or PCS lane data streams 24 to 31 Every 136 The consecutive symbols form a total of 8 * 136 = 1088 symbols, each containing two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols in the same location within two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmitting processing module via the mounting unit interface 4x200GAUI-2.

[0185] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on eight lane data streams based on known alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. To this specification, PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channel of the 200G, respectively. The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in PCS lanes 0 through 7, 8 through 15, 16 through 23, or 24 through 31, a lane reorder is performed on the data in the eight lanes so that the data in the eight lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as shown in Figure 7.

[0186] Figure 8 is a schematic diagram of 32 FEC lane data streams corresponding to the 8×100G interface used by the transmitting device. As shown in Figure 8, the transmitting device performs external code encoding of KP4RS(544,514) code for the eight channels of the 100GbE service data stream to be transmitted. F EC Lane (FEC lane) 8 channels of data stream This consists of a total of 32 FEC lane data streams.Upon acquisition, each channel contains four FEC lane data streams. In the "100G RS-FEC-Int" mode of two KP4 RS(544,514) codeword-based interleaves, consecutive FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31 are obtained. Every 272 The symbols form a total of 4 * 272 = 1088 symbols, each containing two RS codewords. Two adjacent symbols within each FEC lane data stream are from different RS codewords, and two symbols in the same location within two adjacent FEC lane data streams are from different RS codewords. After PMA processing, the 32 FEC lane data streams are sent to the transmitting processing module via the mounting unit interface 8 × 100 GAUI-1.

[0187] Figure 9 is another schematic diagram of the 32 FEC lane data streams corresponding to the 8×100G interface used by the transmitting device. As shown in Figure 9, unlike the scenario in Figure 8, in this scenario the transmitting device uses “100G RS-FEC” mode and each of the FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31 Every 136 The symbols form a total of 4*136=544 symbols, each containing one RS codeword. After PMA processing, 32 FEC lane data streams are sent to the transmitting processing module via the mounting unit interface 8×100GAUI-1.

[0188] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the four lane data streams based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31 can be considered as FEC lanes 0 through 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channels of 100G, respectively. The transmitting processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31, a lane reorder is performed on the data in the four lanes so that the data in the four lanes can be arranged in a specified sequence. Finally, the data in all 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figures 8 and 9.

[0189] Figure 10 is a schematic flowchart of the data processing method according to the embodiment of this application.

[0190] 1001: Perform convolutional interleaving separately on n lane data streams to obtain n first data streams.

[0191] In this embodiment, the lane data stream may be a PCS lane data stream or an FEC lane data stream. This is not specifically limited herein. All n lane data streams are data streams obtained by the first FEC coding, i.e., the aforementioned external code coding data streams, where n is an integer greater than 1. For example, the external code coding may be performed using RS coding, and the n external code coding data streams may include multiple RS codewords. In practical applications, a different coding scheme may be used to perform the external code coding. For ease of explanation, RS codewords will be used below to represent the codewords generated by the external code coding. a piece It should be understood that the codeword is distributed across b lane data streams, where a ≤ b ≤ n, where n can be exactly divided by b, and a is an integer greater than or equal to 1. In the different application scenarios shown in Figures 5 through 9, the values ​​of a and b can also be different. The application scenario shown in Figure 5 is used as an example, where n=32, a=2, and b=16, in other words, Every two The codeword is distributed across 16 lane data streams. The values ​​of a and b in the application scenarios in Figures 6 to 9 can be estimated by referring to the attached drawings, which are again not described in detail herein. Note that in this application, the code length of the external code is measured in symbols, and a symbol may contain one or more bits. For example, the external code used is the KP4 RS(544,514) code, the code length is N=544 symbols, and one symbol contains 10 bits.

[0192] The example shows that when a=1, no interleaving is performed for the codeword acquired by the transmitting device 01 via external code encoding, and the codeword is directly distributed across b lane data streams. As shown in Figure 9, when a=1, no interleaving is performed for the codeword with N=544 symbols acquired by the transmitting device 01 via external code KP4 encoding, and the codeword is directly distributed across b=4 lane data streams. The 544 symbols in one dashed box shown in Figure 9 are from the same KP4 codeword, and the N / b=544 / 4=136 consecutive symbols in one lane data stream within each dashed box are from the same KP4 codeword.

[0193] In another example, when a>1, the codewords obtained by external code encoding by the transmitting device 01 are first interleaved and then distributed into b lane data streams. As shown in Figure 8, when a=2, two-way symbol interleaving is first performed on two codewords with a total of a*N=2*544=1088 symbols obtained by external code KP4 encoding by the transmitting device 01, and then the two codewords are distributed into b=4 lane data streams. One dashed box shown in Figure 8 contains 1088 symbols from a=2 KP4 codewords, and 2*N / b=2*544 / 4=272 consecutive symbols in one lane data stream within each dashed box are from a=2 KP4 codewords, and two adjacent symbols are from different KP4 codewords. As shown in Figure 5, bidirectional symbol interleaving is first performed on two codewords with a=2 and a total of a*N=2*544=1088 symbols obtained by external code KP4 coding by the transmitting device 01, and then the two codewords are distributed into lane data streams with b=16. One dashed box shown in Figure 5 contains 1088 symbols from a=2 KP4 codewords, and 2*N / b=2*544 / 16=68 consecutive symbols in one lane data stream within each dashed box are from a=2 KP4 codewords, and two adjacent symbols are from different KP4 codewords.

[0194] Note that after convolutional interleaving, each of the z consecutive symbols in the first data stream comes from z different codewords, where z is an integer greater than 1. Specific embodiments of convolutional interleaving are described below.

[0195] Figure 11 is a schematic diagram of a structure according to an embodiment of the present application in which convolutional interleaving is performed separately for n lane data streams. As shown in Figure 11, convolutional interleaving may be performed separately for n lane data streams via n convolutional interleavers, and after convolutional interleaving is performed for each lane data stream, a first data stream, which is an irregular data sequence, may be obtained. Note that in this embodiment, each convolutional interleaver performs convolutional interleaving on the input lane data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays the input lane data stream based on the p delay lines to obtain the first data stream. p is an integer greater than 1, and the number of memory units included in each delay line is different, with the delay line having the fewest number of memory units containing 0 memory units, and the difference in the number of memory units of all two adjacent delay lines is Q. Each memory unit is configured to store d symbols, and z = p * d. Symbols in each lane data stream are sequentially input to p delay lines based on the sequence number of the p delay lines, with d symbols input to each delay line once and d symbols output from each delay line once. p*d consecutive symbols in the first data stream include the d symbols output from the delay lines. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, the p delay lines each contain 0 storage units, Q storage units, 2Q storage units, ..., (p-1)Q storage units, and each storage unit is configured to store d symbols. In this case, each p delay line corresponds to a delay value of p, and the delay value includes 0 symbols, Q×d symbols, 2Q×d symbols, ..., (p-1)Q×d symbols. Note that in this application, the delay value is measured in symbols, and a symbol can contain one or more bits. A greater number of symbols in the delay value of a delay line indicates a longer delay (also called latency) in the data stream's delay line.If the delay line does not contain a memory unit, the delay of the delay line is 0 symbols, meaning that a transparent transmission without delay is performed.

[0196] The specific structure of the convolutional interleaver will be described below with reference to the attached drawings.

[0197] Figure 12(a) is a schematic diagram of the first structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 12(a), the number of memory units in the p delay lines is in descending order based on the sequence number of the p delay lines. Specifically, delay line 0 has (p-1)Q memory units, and the Q memory units are sequentially reduced in each delay line, so delay line (p-1) has 0 memory units. Figure 12(b) is a schematic diagram of the second structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 12(b), the number of memory units in the p delay lines is in ascending order based on the sequence number of the p delay lines. Specifically, delay line 0 has 0 memory units, and the Q memory units are sequentially increased in each delay line, so delay line (p-1) has (p-1)Q memory units.

[0198] Note that the input and output switches of the convolutional interleaver are simultaneously located on the same delay line. After d symbols are input to the current delay line once and d symbols are output from the current delay line once, the switch positions are updated to the next delay line, and symbols in each lane data stream are sequentially input to p delay lines based on the sequence numbers of the p delay lines, ensuring that p*d consecutive symbols in the first data stream include the d symbols output from each delay line. The specific data read / write operations are as follows: d symbols are read from the memory unit closest to the output port and located on the current delay line. The d symbols stored in each memory unit on the current delay line are transferred to the next memory unit. Next, d symbols are written to the memory unit closest to the input port and located on the current delay line. Then, a switch to the next delay line is performed, and the above operations are repeated, with the remainder being inferred by analogy. In a possible embodiment, when the convolutional interleaver shown in Figure 12(a) is used, the parameters of the convolutional interleaver satisfy d(p*Q+1)≧a*N / b, where N is the length of the codeword, and p*d consecutive symbols in the first data stream output by the convolutional interleaver come from p*d different external codewords, and d≦a. In another possible embodiment, when the convolutional interleaver shown in Figure 12(b) is used, the parameters of the convolutional interleaver satisfy d(p*Q-1)≧a*N / b, where N is the length of the codeword, and p*d consecutive symbols in the first data stream output by the convolutional interleaver come from p*d different external codewords, and d≦a.

[0199] It should be understood that the convolutional interleaving in Figure 12(a) and the convolutional interleaving in Figure 12(b) are inverse operations of each other when the same parameters p, Q, and d are used. In other words, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving in the receiving processing module uses the structure shown in Figure 12(b). Similarly, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving in the receiving processing module uses the structure shown in Figure 12(a).

[0200] It should be further understood that any one of the n convolutional interleavers may use the structure shown in Figure 12(a) or Figure 12(b). In practical applications, all n convolutional interleavers may use the structure shown in Figure 12(a); all n convolutional interleavers may use the structure shown in Figure 12(b); or some convolutional interleavers may use the structure shown in Figure 12(a) and the remaining convolutional interleavers may use the structure shown in Figure 12(b).

[0201] Note that in some specific application scenarios, n=32 is used as an example, and the value of p can be 2, 3, 4, 6, or 8, and the value of d can be 1 or 2.

[0202] For ease of explanation, the following embodiments relating to convolutional interleaves will be described using an example in which n convolutional interleaves all use the structure shown in Figure 12(a). Naturally, this example may simply be extended to other structures described above, the specific embodiments of which may be known to those skilled in the art and are not described in detail herein.

[0203] In some possible embodiments, lane sorting may be performed on the n lane data streams before convolutional interleaving is performed separately on the n lane data streams to obtain n first data streams, so that the n data streams are arranged in a pre-defined sequence. For example, 32 data streams are used. The 32 data streams can be sorted from 0 to 31 from top to bottom. Naturally, this example can simply be extended to sorting in a different sequence, specific embodiments of which will be known to those skilled in the art and are not described in detail herein.

[0204] In some possible embodiments, convolutional interleaving may be performed separately on the n lane data streams to obtain the n first data streams, after which lane data alignment may be performed on the n lane data streams. Lane data alignment may be a lane de-skew as defined in existing standards, ensuring that the data in the n lane data streams output via the lane data alignment is fully aligned. Alternatively, the above "lane data alignment" may simply be a lane symbol alignment, ensuring that the data in the n lane data streams output via the lane data alignment is aligned based on external code symbols. Specifically, the data may be aligned based on one external code symbol or based on multiple external code symbols. For a detailed explanation of lane data alignment, see the relevant explanation in Figure 3(e). Further details are not provided herein.

[0205] 1002: To obtain a total of m second data streams, n first data streams every K The first data stream is multiplexed to obtain a single second data stream.

[0206] FIG. 13 is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application. As shown in FIG. 13, m multiplexers are used and multiplexing can be performed. Specifically, among the n first data streams every K one of the first data streams is input to one multiplexer, and the multiplexer outputs one second data stream. The m multiplexers output a total of m second data streams, where m = n / K, and K is an integer greater than 1. For ease of explanation, in this embodiment of the present application, an example in which the integer n can be exactly divided by K is used for explanation. The n first data streams include G first data stream subsets, where G is an integer greater than 1, and note that symbols in different first data stream subsets are from different codewords. In a possible embodiment, when K ≤ G, one first data stream is selected from each of any K first data stream subsets. In other words, the K first data streams input to one multiplexer are each from K first data stream subsets. In another possible embodiment, when K > G, K / G first data streams are selected from each first data stream subset. In other words, the K first data streams input to one multiplexer include K / G first data streams within each first data stream subset. For example, when n = 32, G = 2, K = 4, and m = 8, since K > G, in order to obtain the four first data streams input to the multiplexer, two first data streams need to be selected from each of the two first data stream subsets. In another example, when n = 32, G = 4, K = 2, and m = 8, since K < G, in order to obtain the two first data streams input to the multiplexer, two first data stream subsets need to be selected from the four first data stream subsets, and one first data stream needs to be selected from each of the two first data stream subsets.

[0207] Note that in some specific application scenarios, n=32 is used as an example, and the value of K can be 2, 4, or 8.

[0208] It should be understood that the concept of a first data stream subset is introduced simply for the sake of ease of explanation. In practical application, the n first data streams are the whole without division, and each first data stream subset can be considered as one or more data streams within the n first data streams.

[0209] Note that since z consecutive symbols in each first data stream involved in multiplexing come from z different codewords, y consecutive symbols in each second data stream obtained by multiplexing come from y different codewords, and y > z. In a possible embodiment, if K ≤ G, then y = K * z. In another possible embodiment, if K > G, then y = G * z.

[0210] The following describes specific embodiments of multiplexing. For ease of explanation, the K first data streams input to the multiplexer will be denoted as multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, ..., multiplexed input data stream (K-1).

[0211] Figure 14 is a schematic diagram of the first structure of a multiplexer according to an embodiment of this application. As shown in Figure 14,

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[0212] Note that since two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets, y consecutive symbols in the second data stream obtained by multiplexing are from y different codewords, and y > z (y = K*z or y = G*z). Understand that when only convolutional interleaving is performed, a long latency is required to handle the case where y consecutive symbols in the output data stream are from y different codewords. In this solution, the duration of convolutional interleaving is reduced, but equivalent performance can still be achieved by combining convolutional interleaving with multiplexing. Alternatively, by combining convolutional interleaving with multiplexing, equivalent performance can be achieved with a shorter multiplexing duration and lower latency.

[0213] It should be understood that the concept of a second data stream symbol subset is merely introduced for the sake of ease of explanation. In practical application, the symbols within the second data stream are an undivided whole, and each second data stream symbol subset can be considered as multiple symbols within the second data stream.

[0214] Figure 14 is used as an example.

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[0215] In other words, in the above configuration, the multiplexer outputs the data from the K input data streams to a second data stream in a polling manner for every Δ symbols, or in other words, it generates a second data stream by sequentially outputting Δ symbols from each of the multiplexed input data streams 0 to the multiplexed input data stream (K-1), and the data sequence corresponding to the second data stream is,

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[0216] 1003: Perform second FEC encoding separately on m second data streams to obtain encoded data streams.

[0217] FIG. 15 is a schematic diagram of a structure in which FEC encoding is performed on m second data streams according to an embodiment of the present application. As shown in FIG. 15, second FEC encoding, that is, the above-described inner code encoding, is performed separately on m second data streams, and the length of the information bits of the inner code encoding is less than or equal to y RS symbols. After data processing is performed on the inner code encoded data stream, the data processed data stream is transmitted to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, in order to improve the ability of the system to withstand burst errors, the inner code encoded data stream may be interleaved and then transmitted.

[0218] In the embodiments of this application, all n lane data streams are externally code-encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n convolutionally interleaved data streams to obtain m second data streams, after which internal code encoding is performed. According to the data interleaving and multiplexing processing solution provided in this application, the following case can be implemented with low latency: multiple symbols output sequentially from the m multiplexed data streams are from multiple different external codewords, and the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, in this application, the combined solution of convolutional interleaving and data multiplexing enables a lower overall latency for the concatenated FEC solution, making it more applicable to application scenarios requiring low latency.

[0219] The following describes the procedure of the data processing method explained in Figure 10, with reference to several specific embodiments.

[0220] Embodiment 1: The application scenario is a 1x800G interface, the internal code encoding information bit length is 120 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and a lane deskue is used.

[0221] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the lane data stream based on the known alignment markers of the PCS lanes. The known alignment markers for the 32 lanes are different (see "Ethernet Technology Consortium 800G Specification"). The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 fully aligned lane data streams. Then, based on the alignment markers, a lane reorder is performed on the data of the n=32 lanes so that the data of the n=32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from 0 to 31 from top to bottom, which is the same as in Figure 5.

[0222] The n=32 lane data streams on which lane reordering is performed are sent to a processor designed for convolutional interleaving and multiplexing, and then to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc.

[0223] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and the convolutional interleaving is separately executed for n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0224] FIG. 16(a) is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 16(a), p = 3 delay lines are included. The p = 3 delay lines respectively include 2Q storage units, Q storage units, and 0 storage units, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, that is, there is no delay.

[0225] As shown in FIG. 16(a), C r (.) represents one RS symbol in the lane data stream r (0 ≤ r ≤ n - 1). For example, C r (6t) and C r (6t + 1) represent two RS symbols in the lane data stream r that are currently input into delay line 0, and C r (6t - 12Q) and C r (6t - 12Q + 1) are two RS symbols output from delay line 0; C r (6t + 2) and C r (6t + 3) represent two RS symbols in the lane data stream that are subsequently input into delay line 1, and C r (6t - 6Q + 2) and C r (6t - 6Q + 3) are two RS symbols output from delay line 1; C r (6t + 4) and C r (6t + 5) represent two RS symbols in the lane data stream that are subsequently input into delay line 2, and C r(6t+4) and C r (6t+5) is the two RS symbols output from delay line 2; C r (6t+6) and C r (6t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 0, and also C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 5, when 6Q+2≧68, i.e., Q≧11, a total of six RS symbols C are output by the convolutional interleave. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be understood that (6t+5) comes from six different RS code words.

[0226] Figure 16(b) is a schematic diagram of a fourth structure of the convolutional interleaver according to an embodiment of the present application. As shown in Figure 16(b), in a possible embodiment, Q=11 is selected, and the specific structure of the convolutional interleaver is shown in Figure 16(b). The interleaving rate corresponding to the convolutional interleaver is approximately 22*2*3 / 2 = 66 RS symbols. The convolutional interleaver shown in Figure 16(b) performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 5. It is not difficult to understand that any RS symbols in the first data streams 0 to 15 and any RS symbols in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams contain G = 2 subsets of the first data streams, where first data streams 0 through 15 constitute first data stream subset 0, and first data streams 16 through 31 constitute first data stream subset 1. Referring to Figure 16(a), The Six output symbols C that belong to any data stream r_0 within data stream subset 0 of 1 r_0 (6t-12Q), C r_0 (6t-12Q+1), C r_0 (6t-12Q+1), C r_0 (6t-6Q+3), C r_0 (6t+4), and C r_0 (6t+5), as well as six output symbols C that belong to any data stream r_1 within the first data stream subset 1. r_1 (6t-12Q), C r_1 (6t-12Q+1), C r_1 (6t-6Q+2), C r_1 (6t-6Q+3), C r_1 (6t+4), and C r_1 (6t+4) A total of 12 RS symbols It is not difficult to understand that these are derived from 12 different RS codewords.

[0227] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=2, K=2, and m=16. Sixteen second data streams are generated, and sixteen 2:1 multiplexing processing modules are included. Any first data stream selected from the first data stream subset 0 and any first data stream selected from the first data stream subset 1 are used as inputs to the 2:1 multiplexer.

[0228] Figure 17(a) is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application. As shown in Figure 17(a), the two input data streams of the 2:1 multiplexer i (0 ≤ i ≤ 15) are the first data stream i and the first data stream (i + 16). In the figure,

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[0229] Another possible embodiment of the multiplexing shown in Figure 13 of this embodiment is as follows: G=2, K=4, m=8, eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from the first data stream subset 0 and any two first data streams selected from the first data stream subset 1 are used as inputs to the 4:1 multiplexers.

[0230] Figure 17(b) is a schematic diagram of a third structure of the multiplexer according to an embodiment of the present application. As shown in Figure 17(b), the multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0 ≤ i ≤ 7) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), and the first data stream (i+24), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different subsets of the first data stream. In the figure,

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[0231] Another possible embodiment of the multiplexing shown in Figure 13 of this embodiment is as follows: G=2, K=8, m=4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from the first data stream subset 0 and any four first data streams selected from the first data stream subset 1 are used as inputs to the 8:1 multiplexers.

[0232] Figure 17(c) is a schematic diagram of a fourth structure of the multiplexer according to an embodiment of the present application. As shown in Figure 17(c), the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0 ≤ i ≤ 3) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), the first data stream (i+24), the first data stream (i+4), the first data stream (i+20), the first data stream (i+12), and the first data stream (i+28), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different subsets of the first data stream. Note that the multiplexed input data streams 0 through 7 of the 8:1 multiplexer i (0 ≤ i ≤ 3) may alternatively correspond to the first data stream i, the first data stream (i+16), the first data stream (i+4), the first data stream (i+20), the first data stream (i+8), the first data stream (i+24), the first data stream (i+12), and the first data stream (i+28), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different subsets of the first data stream. In the figure,

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[0233] Internal code encoding is performed separately for 16 second data streams, 8 second data streams, or 4 second data streams, with an information bit length of 120 bits for the internal code encoding. Specifically, the internal code encoder separately adds redundancy to the total of 120 bits in 12 consecutive RS symbols within each second data stream in order to obtain the codeword data stream of the internal code. In a possible embodiment, internal code encoding is performed by using Hamming(128,120) to obtain a 128-bit codeword, with 8 bits of redundancy added to the total of 120 bits in 12 consecutive RS symbols within each second data stream. In another possible embodiment, internal code encoding is performed by using BCH(136,120), with 16 bits of redundancy added to the total of 120 bits in 12 consecutive RS symbols within each second data stream to obtain a 136-bit codeword.

[0234] After data processing is performed on the internally coded data stream, the processed data stream is transmitted to the channel transmission medium. Data processing may include modulation and mapping, channel interleaving, polarization distribution, and DSP framing. For example, the internally coded data stream may be interleaved to improve the system's ability to withstand burst errors.

[0235] By using the data interleaving and coding scheme of Embodiment 1, the concatenated code KP4 RS(544,514)+Hamming(128,120) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, and the performance approximates the optimal performance of a concatenated FEC scheme.

[0236] Embodiment 2: The application scenario is a 1×800G interface, the internal code encoding information bit length is 120 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane symbol alignment is used.

[0237] The main difference between Embodiment 2 and Embodiment 1 is that in Embodiment 2, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

[0238] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the lane data stream based on known alignment markers of the PCS lanes. Next, the transmitting processing module performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Then, based on the alignment markers, a lane reorder is performed on the data of the 32 lanes so that the data of the 32 lanes can be arranged in a specified sequence. One arrangement sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 3(a). Another arrangement sequence is that, in the 32 lanes output through the top-down "lane reorder," the first 16 lane data streams contain PCS lane data streams 0 to 15, and the second 16 lanes contain PCS lane data streams 16 to 31. In this case, please understand that the specific sequence of the first 16-lane data stream is not limited, nor is the specific sequence of the second 16-lane data stream. That is, lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

[0239] The 32 lane data streams on which lane reordering is performed are sent to a processor designed to include convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission. It should be understood that all convolutional interleaving, multiplexing, and internal code encoding schemes used in this embodiment utilize the solutions of Embodiment 1.

[0240] By using the data interleaving and coding scheme of Embodiment 2, the concatenated code KP4 RS(544,514)+Hamming(128,120) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, with performance equivalent to that of the solution of Embodiment 1 and lower overall latency. However, the solution of Embodiment 2 is less resilient to system burst errors compared to the solution of Embodiment 1. This solution is applicable to several scenarios requiring lower latency.

[0241] Embodiment 3: The application scenario is a 1x800G interface, the internal code encoding information bit length is 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and a lane deskue is used.

[0242] Based on Embodiment 1, in this embodiment, an internal code having a code length of 160 bits is conceivable, and a newly designed convolutional interleaver is used accordingly.

[0243] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0244] Figure 18(a) is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 18(a), p = four delay lines are included. The four delay lines each contain 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0245] As shown in Figure 18(a), C r (.) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in the lane data stream r that are currently input to delay line 0, and C r (8t-24Q) and C r (8t-24Q+1) is the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and C r (8t-16Q+2) and C r (8t-16Q+3) is the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents two RS symbols in the lane data stream that are input following delay line 2, and C r (8t-8Q+4) and C r (8t-8Q+5) is the two RS symbols output from delay line 2; C r (8t+6) and C r (8t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 3, and C r (8t+6) and C r(8t+7) are the two RS symbols output from delay line 3; and so on. Referring to Figure 5, when 8Q+2≧68, i.e., Q≧9, a total of eight RS symbols, C, are output via the convolutional interleave. r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r (8t+7) can be understood as being derived from eight different RS code words.

[0246] Figure 18(b) is a schematic diagram of a sixth structure of the convolutional interleaver according to an embodiment of the present application. As shown in Figure 18(b), in a possible embodiment, Q=9 is selected, and the specific structure of the convolutional interleaver is shown in Figure 18(b). The interleaving latency corresponding to the convolutional interleaver is approximately 27*2*4 / 2 = 108 RS symbols. The convolutional interleaver shown in Figure 18(b) performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 5. It is not difficult to understand that any RS symbols in the first data streams 0 to 15 and any RS symbols in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams contain G = 2 subsets of the first data streams, where first data streams 0 through 15 constitute first data stream subset 0, and first data streams 16 through 31 constitute first data stream subset 1. Referring to Figure 18(a), The Eight output symbols C of any data stream r_0 within data stream subset 0 of 1 r_0 (8t-24Q), C r_0 (8t-24Q+1), C r_0(8t-16Q+2), C r_0 (8t-16Q+3), C r_0 (8t-8Q+4), C r_0 (8t-8Q+5), C r_0 (8t+6), and C r_0 (8t+7), as well as the eight output symbols C of any data stream r_1 in the first data stream subset 1. r_1 (8t-24Q), C r_1 (8t-24Q+1), C r_1 (8t-16Q+2), C r_1 (8t-16Q+3)

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[0247] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=2, K=2, and m=16. Sixteen second data streams are generated, and sixteen 2:1 multiplexing processing modules are included. Any first data stream selected from the first data stream subset 0 and any first data stream selected from the first data stream subset 1 are used as inputs to the 2:1 multiplexer. A corresponding specific embodiment of the 2:1 multiplexer is shown in Figure 17(a). The two input data streams of the 2:1 multiplexer i (0≦i≦15) are the first data stream i and the first data stream (i+16). In the figure,

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[0248] In this embodiment, another possible embodiment of the multiplexing shown in Figure 13 is as follows: G=2, K=4, and m=8. Eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from the first data stream subset 0 and any two first data streams selected from the first data stream subset 1 are used as inputs to the 4:1 multiplexers. A corresponding specific embodiment of the 4:1 multiplexer is shown in Figure 17(b). The multiplexing input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0≦i≦7) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), and the first data stream (i+24), respectively, i.e., any two consecutive multiplexing input data of the multiplexer are from different first data symbol subsets. In the figure,

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[0249] Another possible embodiment of the multiplexing shown in Figure 13 of this embodiment is as follows: G=2, K=8, m=4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from the first data stream subset 0 and any four first data streams selected from the first data stream subset 1 are used as inputs to the 8:1 multiplexers. A corresponding specific embodiment of the 8:1 multiplexer is shown in Figure 17(c). The multiplexing input data streams 0 to 7 of the 8:1 multiplexer i (0≦i≦3) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+4), the first data stream (i+20), the first data stream (i+8), the first data stream (i+24), the first data stream (i+12), and the first data stream (i+28), respectively. In the figure,

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[0250] Internal code encoding is performed separately for 16 second data streams, 8 second data streams, or 4 second data streams, with an information bit length of 160 bits for the internal code encoding. Specifically, the internal code encoder separately adds redundancy to the total of 160 bits in 16 consecutive RS symbols within the second data stream to obtain an internal code word data stream. In a possible embodiment, internal code encoding is performed by using Hamming(170,160) to obtain a 170-bit codeword, with 10 bits of redundancy added to the total of 160 bits in 16 consecutive RS symbols within each second data stream. In another possible embodiment, internal code encoding is performed by using BCH(176,160), with 16 bits of redundancy added to the total of 160 bits in 16 consecutive RS symbols within each second data stream to obtain a 176-bit codeword. After data processing is performed on the internally code encoded data stream, the processed data stream is sent to the channel transmission medium for transmission.

[0251] By using the data interleaving and coding scheme in this embodiment, when Hamming(170,160) is used as the internal code, the concatenated code KP4 RS(544,514)+Hamming(170,160) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, and the performance approximates the optimal performance of a concatenated FEC scheme. When BCH(176,160) is used as the internal code, the concatenated code KP4 RS(544,514)+BCH(176,160) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, and the performance approximates the optimal performance of a concatenated FEC scheme.

[0252] Embodiment 4: The application scenario is a 1×800G interface, the internal code encoding information bit length is 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane symbol alignment is used.

[0253] The main difference between Embodiment 4 and Embodiment 3 is that in Embodiment 4, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

[0254] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the lane data stream based on known alignment markers of the PCS lanes. Next, the transmitting processing module performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Then, based on the alignment markers, a lane reorder is performed on the data of the 32 lanes so that the data of the 32 lanes can be arranged in a specified sequence. One arrangement sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 3(a). Another arrangement sequence is that, in the 32 lanes output through the top-down "lane reorder," the first 16 lane data streams contain PCS lane data streams 0 to 15, and the second 16 lanes contain PCS lane data streams 16 to 31. In this case, please understand that the specific sequence of the first 16-lane data stream is not limited, nor is the specific sequence of the second 16-lane data stream. That is, lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

[0255] The 32 lane data streams on which lane reordering is performed are sent to a processor designed to include convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission. It should be understood that all convolutional interleaving, multiplexing, and internal code encoding schemes used in this embodiment utilize the solutions of Embodiment 3.

[0256] By using the data interleaving and coding scheme of Embodiment 4, the concatenated code KP4 RS(544,514)+Hamming(160,120) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, with performance equivalent to that of the solution in Embodiment 3 and lower overall latency. However, the solution in Embodiment 4 is less resilient to system burst errors compared to the solution in Embodiment 3. This solution is applicable to several scenarios requiring lower latency.

[0257] By using the data interleaving and coding scheme of Embodiment 4, when Hamming(170,160) is used as the internal code, the concatenated code of KP4 RS(544,514)+Hamming(170,160) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, and the performance approximates the optimal performance of a concatenated FEC scheme. When BCH(176,160) is used as the internal code, the concatenated code of KP4 RS(544,514)+BCH(176,160) in the scheme is below AWGN, and the corresponding pre-FEC BER for achieving a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, and the performance approximates the optimal performance of a concatenated FEC scheme. While the performance of the solution in Embodiment 4 is the same as that of the solution in Embodiment 3 when the same internal coding scheme is used, it should be understood that the solution in Embodiment 4 has poorer tolerance to system burst errors. This solution is applicable to several scenarios requiring lower latency.

[0258] Embodiment 5: The application scenario is a 2x400G interface, the internal code encoding information bit length is 120 or 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane dispatch is used.

[0259] Unlike Embodiments 1 to 4, in this embodiment, the host interface is considered to be a 2 x 400G interface with 100 Gb / s per lane. For details of the interface, please refer to IEEE Std 802.3ck™ / D3.0.

[0260] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on 16 lane data streams based on known alignment markers in PCS lanes 0 through 15 or PCS lanes 16 through 31. Next, the transmitting processing module performs a lane de-skew on 32 lane data streams to obtain 32 aligned lane data streams. Then, a lane reorder is performed on the data of the 16 lanes based on the alignment markers in PCS lanes 0 through 15 or PCS lanes 16 through 31, so that the data of the 16 lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 6.

[0261] The 32 lane data streams on which lane reordering is performed are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and multiplexing, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

[0262] In possible embodiments, if the processor, including the convolutional interleaving and multiplexing used in Embodiment 5, as well as the internal code coding, is the same as that of the solution in Embodiment 1, then the performance and latency of the concatenated FEC solution are the same as those of Embodiment 1.

[0263] In another possible embodiment, if the processor, including the convolutional interleaving and multiplexing used in Embodiment 5, as well as the internal code coding, is the same as that of the solution in Embodiment 3, then the performance and latency of the concatenated FEC solution are the same as those of Embodiment 3.

[0264] Embodiment 6: The application scenario is a 2×400G interface, the internal code encoding information bit length is 120 or 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, lane symbol alignment is used, and lane reordering is not performed.

[0265] Based on the solution of Embodiment 5, Embodiment 6 provides a lower latency embodiment solution.

[0266] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(b), the transmitting processing module performs alignment lock on 16 lane data streams based on known alignment markers in PCS lanes 0 through 15 or PCS lanes 16 through 31. The transmitting processing module then performs alignment on 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are sent directly to a designed processor that includes convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to the channel transmission medium for transmission.

[0267] In possible embodiments, if the processor, including the convolutional interleaving and multiplexing used in Embodiment 6, as well as the internal code coding, is the same as that of the solution in Embodiment 2, then the performance and latency of the concatenated FEC solution are the same as those of Embodiment 2.

[0268] In another possible embodiment, if the processor, including the convolutional interleaving and multiplexing used in Embodiment 6, as well as the internal code coding, is the same as that of the solution in Embodiment 4, then the performance and latency of the concatenated FEC solution are the same as those of Embodiment 4.

[0269] Embodiment 7: The application scenario is a 4×200G interface, the internal code encoding information bit length is 120 or 160 bits, a 4:1 or 8:1 multiplexer is used, and lane deskews are used.

[0270] In this embodiment, the host interface is considered to be a 4x200G interface with 100Gb / s per lane. For details of the interface, please refer to IEEE Std 802.3ckTM / D3.0.

[0271] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on eight lane data streams based on known alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. To this specification, PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channel of the 200G, respectively. The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in PCS lanes 0 through 7, 8 through 15, 16 through 23, or 24 through 31, a lane reorder is performed on the data in the eight lanes, allowing the data in the eight lanes to be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 7.

[0272] The 32 lane data streams on which lane reordering is performed are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and multiplexing, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

[0273] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0274] Figure 19(a) is a schematic diagram of the seventh structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 19(a), p = 2 delay lines are included. The two delay lines include Q memory units and 0 memory units, respectively, and each memory unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0275] As shown in Figure 19(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (4t) and C r (4t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C r (4t+2) and C r(4t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and also C r (4t+2) and C r (4t+3) is the two RS symbols output from delay line 1; C r (4t+4) and C r (4t+5) represents two RS symbols in the lane data stream that are input following delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are two RS symbols output from delay line 0; and so on. Referring to Figure 7, when 4Q+2≧136, i.e., Q≧34, there are a total of four consecutive RS symbols output via the convolutional interleave: Cr(4t-4Q), Cr(4t-4Q+1), C r (4t+2), and C r It can be understood that (4t+3) comes from four different RS code words.

[0276] Figure 19(b) is a schematic diagram of an eighth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 19(b), in a possible embodiment, Q=34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 19(b). The corresponding interleaving latency is approximately 34*2*2 / 2 = 68 RS symbols. The convolutional interleaver shown in Figure 19(b) performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 7. It is not difficult to understand that any RS symbols in first data streams 0 to 7, any RS symbols in first data streams 8 to 15, any RS symbols in first data streams 16 to 23, and any RS symbols in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams contain G=4 subsets of the first data streams, where first data streams 0 through 7 constitute first data stream subset 0, first data streams 8 through 15 constitute first data stream subset 1, first data streams 16 through 23 constitute first data stream subset 2, and first data streams 24 through 31 constitute first data stream subset 3.

[0277] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=4, K=4, and m=8. It includes eight 4:1 multiplexers. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. Any first data stream selected from first data stream subset 0, any first data stream selected from first data stream subset 1, any first data stream selected from first data stream subset 2, and any first data stream selected from first data stream subset 3 are used as inputs to the 4:1 multiplexers.

[0278] A corresponding specific embodiment of the 4:1 multiplexer is shown in Figure 17(b). The multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0 ≤ i ≤ 7) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), and the first data stream (i+24), respectively. Note that the multiplexed input data streams 0, 1, 2, and 3 of the 4:1 multiplexer i (0 ≤ i ≤ 7) may alternatively correspond to the first data stream i, the first data stream (i+8), the first data stream (i+16), and the first data stream (i+24), respectively. This embodiment is shown in Figure 17(b).

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[0279] In this embodiment, another possible embodiment of the multiplexing shown in Figure 13 is as follows: G=4, K=8, and m=4. It includes four 8:1 multiplexers. Each multiplexer multiplexes eight first data streams to obtain one second data stream, generating a total of four second data streams. Any two first data streams selected from first data stream subset 0, any two first data streams selected from first data stream subset 1, any two first data streams selected from first data stream subset 2, and any two first data streams selected from first data stream subset 3 are used as inputs to the 8:1 multiplexers.

[0280] A corresponding specific embodiment of the 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0 ≤ i ≤ 3) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), the first data stream (i+24), the first data stream (i+4), the first data stream (i+20), the first data stream (i+12), and the first data stream (i+28), respectively, that is, any Q = 4 consecutive multiplexed input data streams of the multiplexer are from different subsets of the first data stream. Note that the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0 ≤ i ≤ 3) may alternatively correspond to the first data stream i, the first data stream (i+8), the first data stream (i+16), the first data stream (i+24), the first data stream (i+4), the first data stream (i+12), the first data stream (i+20), and the first data stream (i+28), respectively. In the figure,

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[0281] Internal code encoding is performed separately for the eight or four second data streams mentioned above. The internal code encoding scheme may be the one provided in Embodiment 1 to obtain performance equivalent to Embodiment 1; or the one provided in Embodiment 3 may be used to obtain performance equivalent to Embodiment 3, details of which are not described herein.

[0282] Embodiment 8: The application scenario is a 4x200G interface, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and lane dispatch is used.

[0283] Based on Embodiment 7, in this embodiment, the use of a 2:1 multiplexer is conceivable, and a newly designed convolutional interleaver is used accordingly.

[0284] Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on eight lane data streams based on known alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 as herein may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channels of the 200G, respectively. The transmitting processing module then performs a lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in PCS lanes 0 through 7, 8 through 15, 16 through 23, or 24 through 31, a lane reorder is performed on the data in the eight lanes, allowing the data in the eight lanes to be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 7.

[0285] The 32 lane data streams on which lane reordering is performed are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and multiplexing, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

[0286] In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, and the convolutional interleaving is separately performed on n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2,..., convolutional interleaver 31 use the same interleaving structure. FIG. 16(a) shows the configuration of a convolutional interleaver including p = 3 delay lines. The three delay lines respectively include 2Q storage units, Q storage units, and 0 storage units, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, that is, no delay.

[0287] As shown in FIG. 16(a), C r (·) represents one RS symbol in the lane data stream r (0 ≤ r ≤ n - 1). For example, C r (6t) and C r (6t + 1) represent two RS symbols in the lane data stream that are currently input to delay line 0, and also C r (6t - 12Q) and C r (6t - 12Q + 1) are two RS symbols output from delay line 0; C r (6t + 2) and C r (6t + 3) represent two RS symbols in the lane data stream that are subsequently input to delay line 1, and also C r (6t - 6Q + 2) and C r (6t - 6Q + 3) are two RS symbols output from delay line 1; C r (6t + 4) and C r (6t + 5) represent two RS symbols in the lane data stream that are subsequently input to delay line 2, and also C r (6t + 4) and C r (6t + 5) are two RS symbols output from delay line 2; C r(6t+6) and C r (6t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 0, and also C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 7, when 6Q+2≧136, in other words Q≧23, a total of six RS symbols C are output by the convolutional interleave. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be understood that (6t+5) comes from six different RS code words.

[0288] Figure 20 is a schematic diagram of the ninth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 20, in a possible embodiment, Q=23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 20. The latency of the corresponding interleave is approximately 46*2*3 / 2 = 138 RS symbols. The convolutional interleaver shown in Figure 20 performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 7. It is not difficult to understand that any RS symbols in the first data streams 0 to 7, any RS symbols in the first data streams 8 to 15, any RS symbols in the first data streams 16 to 23, and any RS symbols in the first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams contain G=4 subsets of the first data streams, where first data streams 0 through 7 constitute first data stream subset 0, first data streams 8 through 15 constitute first data stream subset 1, first data streams 16 through 23 constitute first data stream subset 2, and first data streams 24 through 31 constitute first data stream subset 3.

[0289] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=4, K=2, and m=16. It includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. The Any first data stream selected from any two of the following: data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3. These are two first data streams.is used as an input to a 2:1 multiplexer. A corresponding specific embodiment of the 2:1 multiplexer is shown in FIG. 17(a). The multiplexed input data streams 0 and 1 of the 2:1 multiplexer i (0 ≦ i ≦ 15) respectively correspond to the first data stream i and the first data stream (i + 16). In the figure,

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[0290] Internal code encoding is separately performed for the above-mentioned sixteen second data streams, and the internal code encoding method of the sixteen second data streams can use the encoding method provided in Embodiment 1 to obtain performance equivalent to that of Embodiment 1. Details are not described in this specification.

[0291] Embodiment 9: The application scenario is a 4 × 200G interface, the information bit length of the internal code encoding is 160 bits, a 2:1 multiplexer is used, and lane despooling is used.

[0292] Based on Embodiment 8, in this embodiment, an internal code having a code length of 160 bits is conceivable, and a newly designed convolutional interleaver is used accordingly.

[0293] Specifically, in this embodiment, the convolutional interleaver structure shown in Figure 18(a) is used, and p = 4 delay lines are included. The four delay lines each contain 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0294] As shown in Figure 18(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in the lane data stream that are currently input to delay line 0, and also C r (8t-24Q) and C r (8t-24Q+1) is the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and also C r (8t-16Q+2) and C r (8t-16Q+3) is the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents two RS symbols in the lane data stream that are input following delay line 2, and also C r (8t-8Q+4) and C r (8t-8Q+5) is the two RS symbols output from delay line 2; C r (8t+6) and Cr (8t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 3, and also C r (8t+6) and C r (8t+7) is the two RS symbols output from delay line 3; C r (8t+8) and C r (8t+9) represents two RS symbols in the lane data stream that are subsequently input to delay line 0, and also C r (8t-24Q+8) and C r (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to Figure 7, when 8Q+2≧136, in other words Q≧17, a total of eight RS symbols, C, are output by the convolutional interleave. r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), and C r (8t+7) can be understood as being derived from eight different RS code words.

[0295] Figure 21 is a schematic diagram of a tenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 21, in a possible embodiment, Q=17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 21. The latency of the corresponding interleave is approximately 51*2*4 / 2 = 204 RS symbols.

[0296] The convolutional interleaver shown in Figure 21 performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 7. It is not difficult to understand that any RS symbols in first data streams 0 through 7, any RS symbols in first data streams 8 through 15, any RS symbols in first data streams 16 through 23, and any RS symbols in first data streams 24 through 31 are from different RS codewords. Thus, the 32 first data streams contain G=4 first data stream subsets, where first data streams 0 through 7 are first data stream subset 0, first data streams 8 through 15 are first data stream subset 1, first data streams 16 through 23 are first data stream subset 2, and first data streams 24 through 31 are first data stream subset 3.

[0297] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=4, K=2, and m=16. It includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. The Any first data stream selected from any two of the following: data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3. These are two first data streams. This is used as the input to a 2:1 multiplexer. A corresponding specific embodiment of the 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0 ≤ i ≤ 15) correspond to the first data stream i and the first data stream (i + 16), respectively. In the figure,

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[0298] Inner code encoding is separately performed for the aforementioned 16 second data streams, and the inner code encoding method of the 16 second data streams can use the encoding method provided in Embodiment 3 to obtain performance equivalent to that of Embodiment 3. Details are not described herein.

[0299] Embodiment 10: The application scenario is a 4×200G interface, the information bit length of the inner code encoding is 160 bits, and lane symbol alignment is used.

[0300] Based on any one of Embodiments 7 to 9, this embodiment provides a solution for an embodiment with lower latency.

[0301] Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(d), the transmitting processing module performs an alignment lock on eight lane data streams based on known alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. To this specification, PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 may be considered as PCS lanes 0 to 7 of the 0th, 1st, 2nd, or 3rd channels of 200G, respectively. The transmitting processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are sent directly to a processor designed for processing, including multiplexing, and then to an internal code encoder for internal code encoding. After data processing is performed on the internally coded data stream, the processed data stream is sent to the channel transmission medium for transmission.

[0302] In possible embodiments, when both the multiplexing and internal code encoding schemes of this embodiment use the solution of Embodiment 7, the concatenated codes in the scheme are below AWGN, the performance is equivalent to that of the solution of Embodiment 7, and the overall latency is lower. However, the solution of this embodiment is less resilient to system burst errors compared to the solution of Embodiment 7. This solution is applicable to several scenarios requiring lower latency.

[0303] In another possible embodiment, when both the multiplexing and internal code encoding scheme of this embodiment use the solution of Embodiment 8, the concatenated code in the scheme is below AWGN, the performance is equivalent to the solution of Embodiment 8, and the overall latency is lower. However, the solution of this embodiment is less resilient to system burst errors compared to the solution of Embodiment 8. This solution is applicable to several scenarios requiring lower latency.

[0304] In yet another possible embodiment, when both the multiplexing and internal code encoding scheme of this embodiment use the solution of Embodiment 9, the concatenated code in the scheme is below AWGN, the performance is equivalent to the solution of Embodiment 9, and the overall latency is lower. However, the solution of this embodiment is less resilient to system burst errors compared to the solution of Embodiment 9. This solution is applicable to several scenarios requiring lower latency.

[0305] Embodiment 11: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane dispatch is used.

[0306] In this embodiment, the host interface is an 8x100G interface with 100Gb / s per lane, and it is assumed that the "100G RS-FEC-Int" mode is used. For details of the interface, please refer to IEEE Std 802.3ckTM / D3.0.

[0307] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(c), the transmitting processing module performs an alignment lock on the four lane data streams based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31 can be considered as FEC lanes 0 through 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channels of 100G, respectively. The transmitting processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31, a lane reorder is performed on the data of four lanes so that the data of the four lanes can be arranged in a specified sequence. Finally, the data of 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom from 0 to 31, which is the same as in Figure 11. The 32 lane data streams on which the lane reorder is performed are not convolutionally interleaved but are directly multiplexed to obtain a total of 16 second data streams, which are sent to the internal code encoder for internal code encoding.After data processing is performed on the internally coded data stream, the processed data stream is sent to the channel transmission medium for transmission.

[0308] Refer to the PCS lane data streams shown in Figure 8. It is not difficult to understand that any RS symbols in lane data streams 0 to 3, any RS symbols in lane data streams 4 to 7, any RS symbols in lane data streams 8 to 11, any RS symbols in lane data streams 12 to 15, any RS symbols in lane data streams 16 to 19, any RS symbols in lane data streams 20 to 23, any RS symbols in lane data streams 24 to 27, and any RS symbols in lane data streams 28 to 31 all come from different RS codewords. Since no convolutional interleaving is performed on the lane data streams, lane data streams 0 to 31 are equivalent to the first data streams 0 to 31. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0309] The multiplexable embodiment shown in Figure 13 used in this embodiment is as follows: G=8, K=8, m=4, and multiplexing is performed on 32 lane data streams to obtain four second data streams. As eight input data streams for the 8:1 multiplexer i (0≦i≦3), The One data stream in Data Stream Subset 0, one data stream in Data Stream Subset 1, one data stream in Data Stream Subset 2, one data stream in Data Stream Subset 3, one data stream in Data Stream Subset 4, one data stream in Data Stream Subset 5, one data stream in Data Stream Subset 6, and one data stream in Data Stream Subset 7 This consists of a total of eight lane data streams. The following is used. A specific embodiment is shown in Figure 17(c). The multiplexer i (0≦i≦3) uses the first data stream i, the first data stream (i+16), the first data stream (i+8), the first data stream (i+24), the first data stream (i+4), the first data stream (i+20), the first data stream (i+12), and the first data stream (i+28) to correspond to the multiplexed input data streams 0 through 7 of the 8:1 multiplexer, respectively. In the figure,

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[0310] Figure 22 is a schematic diagram of a fifth structure of the multiplexer according to an embodiment of the present application. As shown in Figure 22, the multiplexer i (0 ≤ i ≤ 3) corresponds to the multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively, using the first data stream i, the first data stream (i+4), the first data stream (i+8), the first data stream (i+12), the first data stream (i+16), the first data stream (i+20), the first data stream (i+24), and the first data stream (i+28). In the figure,

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[0311] Internal code encoding is performed separately for the four second data streams mentioned above. The internal code encoding scheme may be the one provided in Embodiment 1 to obtain performance equivalent to Embodiment 1; or the one provided in Embodiment 3 may be used to obtain performance equivalent to Embodiment 3, details of which are not described herein.

[0312] Embodiment 12: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits or 160 bits, a 4:1 multiplexer is used, and lane dispatch is used.

[0313] Based on the solution of Embodiment 11, this embodiment provides a second low-latency embodiment solution when a 4:1 multiplexer is used for multiplexing.

[0314] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the four lane data streams based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31 can be considered as FEC lanes 0 through 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channels of 100G, respectively. The transmitting processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31, a lane reorder is performed on the data in the four lanes so that the data in the four lanes can be arranged in a specified sequence. Finally, the data in all 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 11.

[0315] The 32 lane data streams on which lane reordering is performed are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and multiplexing, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

[0316] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 19(a) shows the configuration of a convolutional interleaver including p=2 delay lines. The two delay lines each contain Q memory units and 0 memory units, and each memory unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0317] As shown in Figure 19(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (4t) and C r (4t+1) represents the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C r (4t+2) and C r (4t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and also C r (4t+2) and C r (4t+3) is the two RS symbols output from delay line 1; Cr (4t+4) and C r (4t+5) represents two RS symbols in the lane data stream that are input following delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are two RS symbols output from delay line 0; and so on. Referring to Figure 8, when 4Q+2≧272, i.e., Q≧68, it can be seen that the four consecutive RS symbols output via the convolutional interleave, Cr(4t-4Q), Cr(4t-4Q+1), Cr(4t+2), and Cr(4t+3), are from four different RS codewords.

[0318] Figure 23 is a schematic diagram of the 11th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 23, in a possible embodiment, Q=68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 23. The latency of the corresponding interleave is approximately 68*2*2 / 2 = 136 RS symbols.

[0319] The convolutional interleaver shown in Figure 23 performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 8. It is not difficult to understand that any RS symbols in lane data streams 0 to 3, any RS symbols in lane data streams 4 to 7, any RS symbols in lane data streams 8 to 11, any RS symbols in lane data streams 12 to 15, any RS symbols in lane data streams 16 to 19, any RS symbols in lane data streams 20 to 23, any RS symbols in lane data streams 24 to 27, and any RS symbols in lane data streams 28 to 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0320] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=8, K=4, and m=8. It includes eight 4:1 multiplexers. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. The Any first data stream selected from any four of the data stream subsets 0 through 7 of 1 These are the four first data streams.This is used as the input to a 4:1 multiplexer. A specific embodiment is shown in Figure 17(b). The multiplexed input data streams 0 to 3 of the 4:1 multiplexer i (0 ≤ i ≤ 7) correspond to the first data stream i, the first data stream (i+16), the first data stream (i+8), and the first data stream (i+24), respectively. In the figure,

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[0321] Figure 24 is a schematic diagram of a sixth structure of the multiplexer according to an embodiment of the present application. As shown in Figure 24, the multiplexer i (0 ≤ i ≤ 3) corresponds to the multiplexed input data streams 0 to 3 of the 4:1 multiplexer, respectively, using the first data stream i, the first data stream (i+8), the first data stream (i+16), and the first data stream (i+24). In the figure,

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[0322] Internal code encoding is performed separately for the eight second data streams mentioned above. The internal code encoding scheme may be the one provided in Embodiment 1 to obtain performance equivalent to Embodiment 1; or the one provided in Embodiment 3 may be used to obtain performance equivalent to Embodiment 3, details of which are not described herein.

[0323] Embodiment 13: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and lane dispatch is used.

[0324] Based on Embodiment 12, in this embodiment, a 2:1 multiplexer and an internal code having a 120-bit information length are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are used accordingly.

[0325] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 16(a) shows the configuration of a convolutional interleaver including p=3 delay lines. The three delay lines include 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

[0326] As shown in Figure 16(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (6t) and C r (6t+1) represents the two RS symbols in the lane data stream that are currently input to delay line 0, and also C r (6t-12Q) and C r (6t-12Q+1) is the two RS symbols output from delay line 0; C r (6t+2) and C r (6t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and also C r (6t-6Q+2) and C r (6t-6Q+3) is the two RS symbols output from delay line 1; C r (6t+4) and C r (6t+5) represents two RS symbols in the lane data stream that are input following delay line 2, and also C r (6t+4) and C r (6t+5) is the two RS symbols output from delay line 2; C r(6t+6) and C r (6t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 0, and also C r (6t-12Q+6) and C r (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, when 6Q+2≧272, in other words Q≧45, a total of six RS symbols C are output by the convolutional interleave. r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), and C r It can be understood that (6t+5) comes from six different RS code words.

[0327] Figure 25 is a schematic diagram of the twelfth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 25, in a possible embodiment, Q=45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 25. The latency of the corresponding interleave is approximately 90*2*3 / 2 = 270 RS symbols.

[0328] The convolutional interleaver shown in Figure 25 performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 8. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0329] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=8, K=2, and m=16. It includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. The Any first data stream selected from any two of the data stream subsets 0 through 7 of 1 These are two first data streams.This is used as the input to a 2:1 multiplexer. A corresponding specific embodiment of the 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0 ≤ i ≤ 15) correspond to the first data stream i and the first data stream (i + 16), respectively. In the figure,

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[0330] A solution for encoding the 16 second data streams output by multiplexing can use the solution of Embodiment 1 and achieve performance equivalent to that of Embodiment 1, which will not be described in detail here again.

[0331] Embodiment 14: The application scenario is an 8×100G interface, the internal code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and lane dispatch is used.

[0332] Based on Embodiment 12, in this embodiment, a 2:1 multiplexer and an internal code having a 160-bit information length are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are used accordingly.

[0333] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 18(a) shows the configuration of a convolutional interleaver including p=4 delay lines. The four delay lines each contain 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0334] As shown in Figure 18(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (8t) and C r (8t+1) represents the two RS symbols in the lane data stream that are currently input to delay line 0, and also C r (8t-24Q) and C r (8t-24Q+1) is the two RS symbols output from delay line 0; C r (8t+2) and C r (8t+3) represents two RS symbols in the lane data stream that are input following delay line 1, and also C r (8t-16Q+2) and C r(8t-16Q+3) is the two RS symbols output from delay line 1; C r (8t+4) and C r (8t+5) represents two RS symbols in the lane data stream that are input following delay line 2, and also C r (8t-8Q+4) and C r (8t-8Q+5) is the two RS symbols output from delay line 2; C r (8t+6) and C r (8t+7) represents two RS symbols in the lane data stream that are subsequently input to delay line 3, and also C r (8t+6) and C r (8t+7) is the two RS symbols output from delay line 3; C r (8t+8) and C r (8t+9) represents two RS symbols in the lane data stream that are subsequently input to delay line 0, and also C r (8t-24Q+8) and C r (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, when 8Q+2≧272, in other words Q≧34, a total of eight RS symbols C are output by the convolutional interleave. r (8t-24Q), C r (8t-24Q+1), C r (8t-24Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), and C r (8t+7) can be understood as being derived from eight different RS code words.

[0335] Figure 26 is a schematic diagram of a thirteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 26, in a possible embodiment, Q=34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 26. The latency of the corresponding interleave is approximately 102*2*4 / 2 = 408 RS symbols.

[0336] The convolutional interleaver shown in Figure 26 performs convolutional interleaving separately on 32 PCS lane data streams to obtain 32 first data streams. Refer to the PCS lane data streams shown in Figure 8. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0337] In this embodiment, the multiplexable embodiment shown in Figure 13 is as follows: G=8, K=2, and m=16. It includes 16 2:1 multiplexers. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. The Any first data stream selected from any two of the data stream subsets 0 through 7 of 1 These are two first data streams. This is used as the input to a 2:1 multiplexer. A corresponding specific embodiment of the 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0 ≤ i ≤ 15) correspond to the first data stream i and the first data stream (i + 16), respectively. In the figure,

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[0338] The method for performing internal code encoding on the 16 second data streams output by multiplexing may use the internal code encoding method of Embodiment 3, achieving performance equivalent to that of Embodiment 3, which will not be described in detail again herein.

[0339] Embodiment 15: The application scenario is an 8×100G interface, and lane symbol alignment is used.

[0340] Based on any one of embodiments 11 to 14, this embodiment provides a lower latency embodiment solution.

[0341] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(b), the transmitting processing module performs alignment lock on four lane data streams based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. The transmitting processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, and the second data streams are sent to the internal code encoder for internal code encoding. After data processing is performed on the internally coded data stream, the processed data stream is sent to the channel transmission medium for transmission.

[0342] In this embodiment, if the processor including convolutional interleaving, multiplexing, and internal code coding is the same as that of the solution in Embodiment 11, the concatenated code in the scheme is under AWGN, and the performance is equivalent to the solution in Embodiment 11, but the solution in this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios that require lower latency.

[0343] In this embodiment, if the processor and internal code coding, including convolutional interleaving and multiplexing, are the same as those in the solution of Embodiment 12, the concatenated code in the scheme is below AWGN, and the performance is equivalent to that of the solution of Embodiment 12, however the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios requiring lower latency.

[0344] In this embodiment, if the processor and internal code coding, including convolutional interleaving and multiplexing, are the same as those in the solution of Embodiment 13, the concatenated code in the scheme is below AWGN, and the performance is equivalent to that of the solution of Embodiment 13, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios that require lower latency.

[0345] In this embodiment, if the processor and internal code coding, including convolutional interleaving and multiplexing, are the same as those in the solution of Embodiment 14, the concatenated code in the scheme is below AWGN, and the performance is equivalent to that of the solution of Embodiment 14, however the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios requiring lower latency.

[0346] Embodiment 16: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane dispatch is used.

[0347] In this embodiment, the host interface is an 8x100G interface with 100Gb / s per lane, and it is assumed that the "100G RS-FEC" mode is used. For details of the interface, please refer to IEEE Std 802.3ckTM / D3.0.

[0348] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs an alignment lock on the four lane data streams based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31 can be considered as FEC lanes 0 through 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th channels of 100G, respectively. The transmitting processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers in FEC lanes 0 through 3, 4 through 7, 8 through 11, 12 through 15, 16 through 19, 20 through 23, 24 through 27, or 28 through 31, a lane reorder is performed on the data in the four lanes so that the data in the four lanes can be arranged in a specified sequence. Finally, the data in all 32 lanes can be arranged in a specified sequence. One sequence is that the lane data streams are sorted from top to bottom, from 0 to 31, which is the same as in Figure 9.

[0349] The 32 lane data streams on which lane reordering is performed are sent to a processor designed for interleaving and data sequence irregularization, including convolutional interleaving and multiplexing, and then sent to an internal code encoder for internal code encoding. After data processing is performed on the internally code encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

[0350] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 FEC lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0351] Figure 27(a) is a schematic diagram of a 14th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 27(a), p = includes two delay lines. The two delay lines include Q memory units and 0 memory units, respectively, and each memory unit is configured to store d = 1 symbol. That is, the delay value of delay line 0 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0352] As shown in Figure 27(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (2t) represents one RS symbol in the lane data stream that is currently input to delay line 0, and C r (2t-2Q) is a single RS symbol output from delay line 0; C r (2t+1) represents one RS symbol in the lane data stream that was input following delay line 1, and C r(2t+1) is one RS symbol output from delay line 1; C r (2t+2) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, and also C r (2t-2Q+2) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, when 2Q+1≧136, i.e., Q≧68, two consecutive RS symbols, C, are output via the convolutional interleave. r (2t-2Q) and C r It can be understood that (2t+1) comes from two different RS code words.

[0353] Figure 27(b) is a schematic diagram of a 15th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 27(b), in a possible embodiment, Q=68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 27(b). The latency of the corresponding interleave is approximately 68*2 / 2=68 RS symbols.

[0354] The convolutional interleaver shown in Figure 27(b) performs convolutional interleaving separately on 32 FEC lane data streams to obtain 32 first data streams. Refer to the FEC lane data streams shown in Figure 9. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0355] In this embodiment, the 8:1 multiplexing processing structure of Embodiment 11 is used, and four second data streams may be acquired, where all 16 consecutive RS symbols in each second data stream are from 16 different RS codewords.

[0356] Internal code encoding is performed separately for the four second data streams mentioned above. The internal code encoding scheme may be the one provided in Embodiment 1 to obtain performance equivalent to Embodiment 1; or the one provided in Embodiment 3 may be used to obtain performance equivalent to Embodiment 3, details of which are not described herein.

[0357] Embodiment 17: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits, a 4:1 multiplexer is used, and lane dispatch is used.

[0358] Based on the solution of Embodiment 16, in this embodiment, when the length of the internal code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0359] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0360] Figure 28(a) is a schematic diagram of the 16th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 28(a), it includes p=3 delay lines. The p=3 delay lines include 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 2Q symbols, the delay value of delay line 1 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0361] As shown in Figure 28(a), C rThe (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, Cr(3t) represents a single RS symbol in the lane data stream currently input to delay line 0, and Cr(3t-6Q) is a single RS symbol output from delay line 0; Cr(3t+1) represents a single RS symbol in the lane data stream subsequently input to delay line 1, and Cr(3t-3Q+1) is a single RS symbol output from delay line 1; Cr(3t+2) represents a single RS symbol in the lane data stream subsequently input to delay line 2, and Cr(3t+2) is a single RS symbol output from delay line 2; Cr(3t+3) represents a single RS symbol in the lane data stream subsequently input to delay line 0, and Cr(3t-6Q+3) is a single RS symbol output from delay line 0; and so on. Referring to Figure 9, when 3Q+1≧136, i.e., Q≧45, it can be seen that the total of three RS symbols output via the convolutional interleave, Cr(3t-6Q), Cr(3t-3Q+2), and Cr(3t+2), are from three different RS codewords.

[0362] Figure 28(b) is a schematic diagram of the 17th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 28(b), in a possible embodiment, Q=45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 28(b). The latency of the corresponding interleave is approximately 90 * 3 / 2 = 135 RS symbols.

[0363] The convolutional interleaver shown in Figure 28(b) performs convolutional interleaving separately on 32 FEC lane data streams to obtain 32 first data streams. Refer to the FEC lane data streams shown in Figure 9. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0364] In this embodiment, the multiplexing processing structure of Embodiment 12 is used, and when Δ=1 or 3, eight second data streams may be obtained, and all 12 consecutive RS symbols in each second data stream are from 12 different RS codewords.

[0365] A solution for encoding the eight second data streams output by multiplexing can use the solution of Embodiment 1 and achieve performance equivalent to that of Embodiment 1, which will again not be described in detail herein.

[0366] Embodiment 18: The application scenario is an 8×100G interface, the internal code encoding information bit length is 160 bits, a 4:1 multiplexer is used, and lane dispatch is used.

[0367] Based on the solution of Embodiment 16, this embodiment provides a second low-latency embodiment solution in which the length of the internal code information is 160 bits and a 4:1 multiplexer is used for multiplexing, with a newly designed interleaver and multiplexing used accordingly.

[0368] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0369] Figure 29(a) is a schematic diagram of the 18th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 29(a), it includes p=4 delay lines. The p=4 delay lines include 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 3Q symbols, the delay value of delay line 1 is 2Q symbols, the delay value of delay line 2 is Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0370] As shown in Figure 29(a), C r(·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (4t) represents one RS symbol in the lane data stream currently input to delay line 0, and Cr(4t-12Q) is one RS symbol output from delay line 0; C r (4t+1) represents one RS symbol in the lane data stream that is input following delay line 1, and Cr(4t-8Q+1) is one RS symbol output from delay line 1; C r (4t+2) represents one RS symbol in the lane data stream that is subsequently input to delay line 2, and Cr(4t-4Q+2) is one RS symbol that is output from delay line 2; C r (4t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, C r (4t+3) is one RS symbol output from delay line 3; C r (4t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, Cr(4t-12Q+4) is one RS symbol output from delay line 0, and so on. Referring to Figure 9, when 4Q+1≧136, i.e., Q≧34, a total of four RS symbols, C, are output consecutively by the convolutional interleave. r (4t-12Q), C r (4t-8Q+1), C r (4t-4Q+2), and C r It can be understood that (4t+3) comes from four different RS code words.

[0371] Figure 29(b) is a schematic diagram of the 19th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 29(b), in a possible embodiment, Q=34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 29(b). The latency of the corresponding interleave is approximately 102*4 / 2 = 204 RS symbols.

[0372] The convolutional interleaver shown in Figure 29(b) performs convolutional interleaving separately on 32 FEC lane data streams to obtain 32 first data streams. Refer to the FEC lane data streams shown in Figure 9. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0373] In this embodiment, the multiplexing processing structure of Embodiment 13 is used, and when Δ=1, 2, or 4, eight second data streams may be acquired, and all 16 consecutive RS symbols in each second data stream are from 16 different RS codewords.

[0374] Internal code encoding is performed separately for the eight second data streams mentioned above, and the internal code encoding scheme for the eight second data streams can be used to achieve performance equivalent to that of Embodiment 3, using the internal code encoding scheme provided in Embodiment 3. Details are not described herein.

[0375] Embodiment 19: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and lane dispatch is used.

[0376] Based on the solution of Embodiment 16, in this embodiment, when the length of the internal code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0377] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0378] Figure 30(a) is a schematic diagram of the 20th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 30(a), it includes p=6 delay lines. The p=6 delay lines include 5Q memory units, 4Q memory units, 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 5Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 3Q symbols, the delay value of delay line 3 is 2Q symbols, the delay value of delay line 4 is Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay.

[0379] As shown in Figure 30(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (6t) represents one RS symbol in the lane data stream that is currently input to delay line 0, C r (6t-30Q) is a single RS symbol output from delay line 0; C r (6t+1) represents one RS symbol in the lane data stream that was input following delay line 1, and C r (6t-24Q+1) is one RS symbol output from delay line 1; C r (6t+2) represents one RS symbol in the lane data stream that is subsequently input to delay line 2, C r (6t-18Q+2) is one RS symbol output from delay line 2; C r (6t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, C r (6t-12Q+3) is one RS symbol output from delay line 3; C r (6t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 4, C r (6t-6Q+4) is one RS symbol output from delay line 4; C r (6t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, C r (6t+5) is one RS symbol output from delay line 5; C r (6t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, C r (6t-30Q+6) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, when 6Q+1≧136, i.e., Q≧23, a total of six RS symbols, C, are output consecutively by the convolutional interleave. r (6t-30Q), C r(6t-24Q+1), C r It can be understood that (6t-18Q+2) is derived from six different RS code words.

[0380] Figure 30(b) is a schematic diagram of the 21st structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 30(b), in a possible embodiment, Q=23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 30(b). The latency of the corresponding interleave is approximately 23*5*6 / 2 = 345 RS symbols.

[0381] The convolutional interleaver shown in Figure 30(b) performs convolutional interleaving separately on 32 FEC lane data streams to obtain 32 first data streams. Refer to the FEC lane data streams shown in Figure 9. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0382] In this embodiment, the multiplexing processing structure of Embodiment 13 is used, and when Δ=1, 2, 3, or 6, 16 second data streams may be obtained, and all 12 consecutive RS symbols in each second data stream are from 12 different RS codewords.

[0383] Internal code encoding is performed separately for the aforementioned 16 second data streams, and the encoding scheme for the 16 second data streams can be performed using the internal code encoding scheme provided in Embodiment 1 to achieve performance equivalent to that of Embodiment 1. Details are not described herein.

[0384] Embodiment 20: The application scenario is an 8×100G interface, the internal code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and lane dispatch is used.

[0385] Based on the solution of Embodiment 16, in this embodiment, when the length of the internal code information is 160 bits and a 2:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

[0386] In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately for n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

[0387] Figure 31(a) is a schematic diagram of the 22nd structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 31(a), it includes p=8 delay lines. The p=8 delay lines include 7Q memory units, 6Q memory units, 5Q memory units, 4Q memory units, 3Q memory units, 2Q memory units, Q memory units, and 0 memory units, respectively, and each memory unit is configured to store d=1 symbols. That is, the delay value of delay line 0 is 7Q symbols, the delay value of delay line 1 is 6Q symbols, the delay value of delay line 2 is 5Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 3Q symbols, the delay value of delay line 5 is 2Q symbols, the delay value of delay line 6 is Q symbols, and the delay value of delay line 7 is 0 symbols, i.e., no delay.

[0388] As shown in Figure 31(a), C r (·) represents a single RS symbol in the lane data stream r (0 ≤ r ≤ n-1). For example, C r (8t) represents one RS symbol in the lane data stream that is currently input to delay line 0, C r (8t-56Q) is a single RS symbol output from delay line 0; C r (8t+1) represents one RS symbol in the lane data stream that was input following delay line 1, and C r (8t-48Q+1) is one RS symbol output from delay line 1; C r (8t+2) represents one RS symbol in the lane data stream that is subsequently input to delay line 2, C r (8t-40Q+2) is one RS symbol output from delay line 2; C r (8t+3) represents one RS symbol in the lane data stream that is subsequently input to delay line 3, C r (8t-32Q+3) is one RS symbol output from delay line 3; C r(8t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 4, C r (8t-24Q+4) is one RS symbol output from delay line 4; C r (8t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, C r (8t-16Q+5) is one RS symbol output from delay line 5; C r (8t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 6, C r (8t-8Q+6) is one RS symbol output from delay line 6; C r (8t+7) represents one RS symbol in the lane data stream that is subsequently input to delay line 7, C r (8t+7) is one RS symbol output from delay line 7; C r (8t+8) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, C r (8t-56Q+8) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, when 8Q+1≧136, i.e., Q≧17, a total of eight RS symbols C are output consecutively via the convolutional interleave. r (8t-56Q), C r (8t-48Q+1), C r (8t-40Q+2), C r (8t-32Q+3), C r (8t-24Q+4), C r (8t-16Q+5), C r (8t-8Q+6), and C r (8t+7) can be understood as being derived from eight different RS code words.

[0389] Figure 31(b) is a schematic diagram of a 23rd structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 31(b), in a possible embodiment, Q=17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 31(b). The latency of the corresponding interleave is approximately 17*7*8 / 2 = 476 RS symbols.

[0390] The convolutional interleaver shown in Figure 31(b) performs convolutional interleaving separately on 32 FEC lane data streams to obtain 32 first data streams. Refer to the FEC lane data streams shown in Figure 9. It is not difficult to understand that any RS symbols in the first data streams 0 through 3, any RS symbols in the first data streams 4 through 7, any RS symbols in the first data streams 8 through 11, any RS symbols in the first data streams 12 through 15, any RS symbols in the first data streams 16 through 19, any RS symbols in the first data streams 20 through 23, any RS symbols in the first data streams 24 through 27, and any RS symbols in the first data streams 28 through 31 are from different RS codewords. Therefore, the 32 first data streams contain G=8 first data stream subsets, where first data streams 0 to 3 constitute first data stream subset 0, first data streams 4 to 7 constitute first data stream subset 1, first data streams 8 to 11 constitute first data stream subset 2, first data streams 12 to 15 constitute first data stream subset 3, first data streams 16 to 19 constitute first data stream subset 4, first data streams 20 to 23 constitute first data stream subset 5, first data streams 24 to 27 constitute first data stream subset 6, and first data streams 28 to 31 constitute first data stream subset 7.

[0391] In this embodiment, the multiplexing processing structure of Embodiment 13 is used, and when Δ=1, 2, 3, or 8, 16 second data streams may be acquired, and all 16 consecutive RS symbols in each second data stream are from 16 different RS codewords.

[0392] Internal code encoding is performed separately for the aforementioned 16 second data streams, and the internal code encoding scheme for the 16 second data streams can achieve performance equivalent to that of Embodiment 3 by using the internal code encoding scheme provided in Embodiment 3. Details are not described herein.

[0393] Embodiment 21: The application scenario is an 8×100G interface, the internal code encoding information bit length is 120 bits or 160 bits, and lane symbol alignment is used.

[0394] Based on the solutions in any of embodiments 16 to 20, this embodiment provides a lower latency embodiment solution.

[0395] Based on the schematic data processing diagram of the transmitting processing module shown in Figure 3(d), the transmitting processing module performs alignment lock on four lane data streams based on known alignment markers in FEC lanes 0 to 3, 4 to 7, 8 to 11, 12 to 15, 16 to 19, 20 to 23, 24 to 27, or 28 to 31. Next, the transmitting processing module performs one symbol-based alignment on the 32 lane data streams to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, and the second data streams are sent to the internal code encoder for internal code encoding. After data processing is performed on the internally coded data stream, the processed data stream is sent to the channel transmission medium for transmission.

[0396] It should be understood that both the multiplexing and internal code encoding schemes used in this embodiment utilize the solutions provided in any one of embodiments 16 to 20.

[0397] In this embodiment, if the processor and internal code coding, including multiplexing, are the same as those in the solution of Embodiment 16, the concatenated code in the scheme is below AWGN, and the performance is equivalent to that of the solution of Embodiment 16, although the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios that require lower latency.

[0398] In this embodiment, if the processor and internal code coding, including multiplexing, are the same as those in the solution of Embodiment 17, the concatenated code in the scheme is below AWGN, and the performance is equivalent to that of the solution of Embodiment 17, however the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to several scenarios requiring lower latency.

[0399] In this embodiment, if the processor and internal code coding, including multiplexing, are the same as those in the solution of Embodiment 18, the concatenated code in...

Claims

1. A data processing method, The steps of obtaining s first data streams by performing block interleaving on every t lane data streams of n lane data streams in order to obtain a total of m first data streams, wherein n = q * t, m = q * s, n is an integer greater than 1, n can be divided exactly by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2, s is an integer greater than or equal to 1, all of the n lane data streams are first forward error correction FEC encoded, a codeword every a is distributed in b lane data streams of the n lane data streams, a ≤ b ≤ n, n can be divided exactly by b, a is an integer greater than or equal to 2, and each lane data stream Each a sequence of symbols in a lane comes from a different codeword, and each L1 sequence of symbols in each lane data stream comes from at least a different codewords, where L1 is an integer, L1 = N * a / b, where N is the length of the codeword; the t lane data streams comprise t * a symbols, each of which comprises Δ bits from each of the t * a symbols, and D bits, where D = Δ * t * a, where D bits are consecutive in any one of the s first data streams, where Δ is an integer, Δ = M / s, where M is the number of bits provided in one symbol; A step of separately performing convolution interleaving on the m first data streams in order to obtain m second data streams, A data processing method comprising the following features.

2. The data processing method according to claim 1, wherein every d consecutive symbols in each first data stream come from v different codewords, every L2 consecutive symbols in each first data stream come from at least v different codewords, v can be divided exactly by a, L2 is an integer such that L2 = t / s * L1, d is an integer such that d = D / M.

3. The method according to claim 1, wherein n = 32, the 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, the 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

4. The step of performing block interleaving on every t lane data stream of n lane data streams in order to obtain s first data streams, where t = 8 and s = 1, The step of performing a block interleave on a total of eight lane data streams to obtain one first data stream: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, wherein 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleave, there are a total of 16 consecutive symbols, each of the eight lane data streams having two consecutive symbols, and every 16 consecutive symbols in the first data stream obtained by the block interleave come from at least four different codewords, and every 544 consecutive symbols come from at least four different codewords The first, second, and third symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the fourth, fifth, sixth, and seventh symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the eighth, ninth, tenth, and eleventh symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the twelfth, thirteenth, fourteenth, and fifteenth symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, step The method according to claim 3, comprising:

5. The step of performing block interleaving on every t lane data stream of n lane data streams in order to obtain s first data streams, where t = 8 and s = 1, A step of performing a block interleave on a total of eight lane data streams to obtain one first data stream: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, wherein 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleave, there are a total of 16 symbols in sequence, which are the j-th two consecutive symbol groups provided in each of the eight lane data streams, and the j-th two consecutive symbol groups provided in each of the eight lane data streams are in sequence in the first data stream obtained by the block interleave, and j ≥ 0, and in the first data stream obtained by the block interleave, every 16 consecutive symbols The symbols are from at least four different codewords, every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are,Steps from different codewords, The method according to claim 3, comprising:

6. The step of performing block interleaving on every t lane data streams of n lane data streams in order to obtain the s first data streams, where t = 8 and s = 1, The step of performing a block interleave on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, wherein a total of eight symbols, 0 ≤ i ≤ 3 and the j-th symbol present in each of the eight lane data streams, are obtained by the block interleave of the first data stream. Step The method according to claim 3, comprising:

7. The method according to claim 1, wherein n = 32, the 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted at the rear of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the rear of the n lane data streams are from different codewords.

8. The step of obtaining s first data streams by performing block interleaving on every t lane data streams of n lane data streams, where t = 2 and s = 1, is as follows: A step of performing a block interleave on the i-th lane data stream and the (i+16)-th lane data stream to obtain a first data stream, wherein 0 ≤ i < 16, and two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream are consecutive in the first data stream obtained by the block interleave, and every four consecutive symbols in the first data stream obtained by the block interleave are from four different codewords. The method according to claim 7, comprising:

9. The step of obtaining s first data streams by performing block interleaving on every t lane data streams of n lane data streams, where t = 2 and s = 1, is as follows: A step of performing a block interleave on the i-th lane data stream and the (i+16th) lane data stream to obtain a first data stream, wherein 0 ≤ i < 16, the j-th group of consecutive β bits in the i-th lane data stream and the j-th group of consecutive β bits in the (i+16th) lane data stream are consecutive in the first data stream obtained by the block interleave, j ≥ 0, β is 1, 2, 4, 5, 10, or 20, and every four consecutive symbols in the first data stream obtained by the block interleave are from four different codewords. The method according to claim 7, comprising:

10. The step of obtaining s first data streams by performing block interleaving on every t lane data streams of n lane data streams, where t = 2 and s = 2, is as follows: A step of performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, wherein 0 ≤ i < 16, and in the (2*i)-th first data stream, there are 20 consecutive bits totaling 4 symbols: 5 bits each of 2 consecutive symbols in the i-th lane data stream and 2 consecutive symbols in the (i+16)-th lane data stream, and every 20 consecutive bits in the (2*i)-th first data stream are from 4 different codewords, and in the (2*i+1)-th first data stream, there are 20 consecutive bits totaling 4 symbols: 5 bits each of 2 consecutive symbols in the i-th lane data stream and 2 consecutive symbols in the (i+16)-th lane data stream, and every 20 consecutive bits in the (2*i+1)-th first data stream are from 4 different codewords. The method according to claim 7, comprising:

11. The step of performing block interleaving on every t lane data stream of n lane data streams in order to obtain s first data streams, where t = 8 and s = 1, The step of performing a block interleave on a total of eight lane data streams to obtain one first data stream: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, wherein 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleave, there are a total of 16 consecutive symbols, each of the eight lane data streams having two consecutive symbols, and every 16 consecutive symbols in the first data stream obtained by the block interleave come from at least four different codewords, and every 544 consecutive symbols come from at least four different codewords. The first, second, and third symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleave are from a different codeword, the fourth, fifth, sixth, and seventh symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleave are from a different codeword, the eighth, ninth, tenth, and eleventh symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleave are from a different codeword, and the twelfth, thirteenth, fourteenth, and fifteenth symbols in every sixteen consecutive symbols in the first data stream obtained by the block interleave are from a different codeword, step The method according to claim 7, comprising:

12. The step of performing block interleaving on every t lane data stream of n lane data streams in order to obtain s first data streams, where t = 8 and s = 1, A step of performing block interleaving on a total of eight lane data streams to obtain one first data stream: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, wherein 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleaving, there are a total of 16 symbols in sequence, which are two j-th consecutive symbol groups provided in each of the eight lane data streams, and the two j-th consecutive symbol groups provided in each of the eight lane data streams are consecutive in the first data stream obtained by the block interleaving, and j ≥ 0, and every 16 consecutive symbols in the first data stream obtained by the block interleaving The symbols are from at least four different codewords, every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are,Steps from different codewords, The method according to claim 7, comprising:

13. The step of performing block interleaving on every t lane data streams of n lane data streams in order to obtain the s first data streams, where t = 8 and s = 1, A step of performing a block interleave on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, wherein a total of eight symbols, 0 ≤ i ≤ 3 and the j-th symbol present in each of the eight lane data streams, are obtained by the block interleave in the first data stream. The data stream is continuous, j≧0, and every eight consecutive symbols in the first data stream obtained by the block interleaving are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, step The method according to claim 7, comprising:

14. The step of performing a convolution interleave on a first data stream to obtain a second data stream is, A step of obtaining a second data stream by delaying a first data stream based on p delay lines, where p is an integer greater than 1, each delay line has a different number of memory units, the delay line with the fewest number of memory units has 0 memory units, the difference in the number of memory units for every two adjacent delay lines is Q, each memory unit is configured to store d symbols, symbols in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, d symbols are input to each delay line once, d symbols are output from the delay line once, p*d consecutive symbols in the second data stream comprise the d symbols output from the delay lines, and Q is an integer greater than or equal to 1. The method according to claim 1, comprising:

15. The step of performing a convolution interleave on a first data stream to obtain a second data stream is, A step of obtaining a second data stream by delaying a first data stream based on p delay lines, where p is an integer greater than 1, each delay line has a different number of memory units, the delay line with the fewest number of memory units has 0 memory units, the difference in the number of memory units for every two adjacent delay lines is Q, each memory unit is configured to store 4 symbols, symbols in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, 4 symbols are input to each delay line once, 4 symbols are output from the delay line once, p*4 consecutive symbols in the second data stream comprise the 4 symbols output from the delay lines, and Q satisfies 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544. The method according to claim 1, comprising:

16. After the step of performing convolution interleaving separately on the m first data streams to obtain m second data streams, the method proceeds as follows: A step of obtaining m encoded data streams by separately performing a second FEC encoding on the m second data streams, wherein the information data in each encoded data stream, having a length of K symbols, comes from a maximum of K different codewords, and K ≥ p * 4. The method according to claim 15, further comprising:

17. The step of performing a convolution interleave on a first data stream to obtain a second data stream is, A step of delaying a first data stream based on p delay lines to obtain a second data stream, wherein p is an integer greater than 1, each delay line has a different number of memory units, the delay line with the fewest number of memory units has 0 memory units, and the difference in the number of memory units of every two adjacent delay lines is Q. The method according to claim 1, wherein each storage unit is configured to store 34 bits, the bits in each lane data stream are sequentially input to the p delay lines based on the sequence numbers of the p delay lines, 34 bits are input to each delay line once, and 34 bits are output from each delay line once, and p*34 consecutive bits in one second data stream comprise the output of the 34 bits output from the delay lines; or the method according to claim 1, wherein each storage unit is configured to store 68 bits, the bits in each lane data stream are sequentially input to the p delay lines based on the sequence numbers of the p delay lines, 68 bits are input to each delay line once, and 68 bits are output from each delay line once, and p*68 consecutive bits in one second data stream comprise the output of the 68 bits output from the delay lines.

18. The method according to claim 1, wherein t is 2, 4, or 8.

19. The method according to claim 1, wherein s is 1.

20. A data processing device comprising a block interleaver and a convolutional interleaver, The block interleaver is configured to obtain s first data streams by performing block interleaving on every t lane data streams of n lane data streams in order to obtain a total of m first data streams, where n = q * t, m = q * s, where n is an integer greater than 1, n can be divided exactly by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2, s is an integer greater than or equal to 1, all of the n lane data streams are first forward error correction FEC encoded, a codeword for every a is distributed across b lane data streams of the n lane data streams, where a ≤ b ≤ n, n can be divided exactly by b, a is an integer greater than or equal to 2, and each lane Each a sequence of symbols in a data stream comes from a different codeword, and each L1 sequence of symbols in each lane data stream comes from at least a different codewords, where L1 is an integer, L1 = N * a / b, where N is the length of the codeword; the t lane data streams comprise t * a symbols, each of which comprises Δ bits from each of the t * a symbols, and D bits, where D = Δ * t * a, where D bits are consecutive in any one of the s first data streams, where Δ is an integer, Δ = M / s, where M is the number of bits provided in one symbol; The convolutional interleaver is configured to perform convolutional interleaving separately on the m first data streams in order to obtain m second data streams, in a data processing device.

21. The data processing apparatus according to claim 20, wherein every d consecutive symbols in each first data stream are from v different codewords, and every L2 consecutive symbols in each first data stream are from at least v different codewords, where v can be divided exactly by a, L2 is an integer such that L2 = t / s * L1, and d is an integer such that d = D / M.

22. The data processing apparatus according to claim 20, wherein n = 32, the 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, the 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

23. t = 8, s = 1, and the block interleaver is, To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, where 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleaving, there are a total of 16 consecutive symbols, each of the eight lane data streams having two consecutive symbols, and every 16 consecutive symbols in the first data stream obtained by the block interleaving come from at least four different codewords, and every 544 consecutive symbols come from at least four different codewords. The 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. The data processing apparatus according to claim 22, specifically configured as described above.

24. t = 8, s = 1, and the block interleaver is, To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleaving, there are a total of 16 symbols in sequence, which are the jth of two consecutive symbol groups present in each of the eight lane data streams, and the jth of two consecutive symbol groups present in each of the eight lane data streams are in sequence in the first data stream obtained by the block interleaving, where j≧0, and every 16 consecutive symbols in the first data stream obtained by the block interleaving are Every 544 consecutive symbols are from at least four different codewords, and every 16 consecutive symbols in the first data stream obtained by the block interleaving are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are,They are from different codewords. The data processing apparatus according to claim 22, specifically configured as described above.

25. t = 8, s = 1, and the block interleaver is, To obtain a first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i) lane data stream, the (8*i+1) lane data stream, the (8*i+2) lane data stream, the (8*i+3) lane data stream, the (8*i+4) lane data stream, the (8*i+5) lane data stream, the (8*i+6) lane data stream, and the (8*i+7) lane data stream, and a total of eight symbols, where 0 ≤ i ≤ 3 and the j-th symbol present in each of the eight lane data streams, are obtained from the first data obtained by the block interleaving. The stream is contiguous, j≧0, and every eight consecutive symbols in the first data stream obtained by the block interleaving are from four different codewords, and the 0th, 1st, 2nd, and 3rd symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. The data processing apparatus according to claim 22, specifically configured as described above.

26. The data processing device according to claim 20, wherein n = 32, the 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted at the rear of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the rear of the n lane data streams are from different codewords.

27. t = 2, s = 1, and the block interleaver is, Block interleaving is performed on the i-th lane data stream and the (i+16th) lane data stream to obtain a first data stream such that 0 ≤ i < 16, and two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16th) lane data stream are consecutive in the first data stream obtained by the block interleaving, and every four consecutive symbols in the first data stream obtained by the block interleaving are from four different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

28. t = 2, s = 1, and the block interleaver is, Perform a block interleave on the i-th lane data stream and the (i+16)-th lane data stream to obtain a first data stream such that 0 ≤ i < 16, the j-th group of consecutive β bits in the i-th lane data stream and the j-th group of consecutive β bits in the (i+16)-th lane data stream are consecutive in the first data stream obtained by the block interleave, j ≥ 0, β is 1, 2, 4, 5, 10, or 20, and every four consecutive symbols in the first data stream obtained by the block interleave are from four different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

29. t=2, s=2, and the block interleaver is, Perform a block interleave on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, where 0 ≤ i < 16, and four symbols: 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, totaling 20 bits that are consecutive in the (2*i)-th first data stream, where every 20 consecutive bits in the (2*i)-th first data stream come from four different codewords, and four symbols: the other 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, totaling 20 bits that are consecutive in the (2*i+1)-th first data stream, where every 20 consecutive bits in the (2*i+1)-th first data stream come from four different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

30. t = 8, s = 1, and the block interleaver is, To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, where 0 ≤ i ≤ 3, and in the first data stream obtained by the block interleaving, there are a total of 16 consecutive symbols, each of the eight lane data streams having two consecutive symbols, and every 16 consecutive symbols in the first data stream obtained by the block interleaving come from at least four different codewords, and every 544 consecutive symbols come from at least four different codewords The 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

31. t = 8, s = 1, and the block interleaver is, To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, where 0≦i≦3, and in the first data stream obtained by the block interleaving, there are a total of 16 symbols in sequence, which are the jth of two consecutive symbol groups present in each of the eight lane data streams, and the jth of two consecutive symbol groups present in each of the eight lane data streams are in sequence in the first data stream obtained by the block interleaving, where j≧0, and every 16 consecutive symbols in the first data stream obtained by the block interleaving The symbols are from at least four different codewords, every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols in every 16 consecutive symbols in the first data stream obtained by the block interleaving are,They are from different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

32. t = 8, s = 1, and the block interleaver is, To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i) lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, the (4*i+3) lane data stream, the (4*i+16) lane data stream, the (4*i+17) lane data stream, the (4*i+18) lane data stream, and the (4*i+19) lane data stream, and a total of eight symbols, where 0 ≤ i ≤ 3 and the j-th symbol present in each of the eight lane data streams, are obtained as the first data obtained by the block interleaving. The stream is contiguous, j≧0, and every eight consecutive symbols in the first data stream obtained by the block interleaving are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols in every eight consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. The data processing apparatus according to claim 26, specifically configured as described above.

33. The aforementioned convolutional interleaver is To obtain a second data stream, a first lane data stream is delayed based on p delay lines, where p is an integer greater than 1, and each delay line has a different number of memory units, with the delay line having the fewest memory units having 0, and the difference in the number of memory units for every two adjacent delay lines is Q, and each memory unit is configured to store d symbols, and the symbols in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, with d symbols being input to each delay line once, and d symbols being output from the delay line once, and p*d consecutive symbols in the second data stream comprise the d symbols output from the delay lines, where Q is an integer greater than or equal to 1. The data processing apparatus according to claim 20, specifically configured as described above.

34. The aforementioned convolutional interleaver is To obtain a second data stream, one first lane data stream is delayed based on p delay lines, where p is an integer greater than 1, and each delay line has a different number of memory units, the delay line with the fewest memory units has 0 memory units, and the difference in the number of memory units for every two adjacent delay lines is Q, and each memory unit is configured to store 4 symbols, and the symbols in each lane data stream are sequentially input to the p delay lines based on the sequence number of the p delay lines, with 4 symbols being input to each delay line once and 4 symbols being output from the delay line once, and p*4 consecutive symbols in the second data stream comprise the 4 symbols output from the delay lines, where Q satisfies 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544. A data processing apparatus according to claim 20, configured as described above.

35. The data processing device further comprises an encoder, and after the m second data streams have been acquired, the encoder To obtain m encoded data streams, a second FEC encoding is performed separately on the m second data streams, and the information data in each of the encoded data streams, having a length of K symbols, comes from a maximum of K different codewords, where K ≥ p * 4. A data processing apparatus according to claim 34, configured as described above.

36. The aforementioned convolutional interleaver, A first data stream is delayed based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line has a different number of memory units, the delay line with the fewest memory units has 0 memory units, and the difference in the number of memory units for every two adjacent delay lines is Q. The data processing apparatus according to claim 20, wherein each storage unit is configured to store 34 bits, and the bits in each lane data stream are sequentially input to the p delay lines based on the sequence numbers of the p delay lines, with 34 bits input to each delay line once and 34 bits output from each delay line once, and p*34 consecutive bits in one second data stream comprise the output of the 34 bits output from the delay lines; or each storage unit is configured to store 68 bits, and the bits in each lane data stream are sequentially input to the p delay lines based on the sequence numbers of the p delay lines, with 68 bits input to each delay line once and 68 bits output from each delay line once, and p*68 consecutive bits in one second data stream comprise the output of the 68 bits output from the delay lines.

37. The data processing apparatus according to claim 20, wherein t is 2, 4, or 8.

38. The data processing apparatus according to claim 20, wherein s is 1.

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