Data sampling circuit and data transmitter circuit

Abstract

The data sampling circuit may include a pattern detection circuit that detects a pattern of multi-bit data containing input data and generates a slow signal; and a sampling circuit that samples the input data during the activation period of a sampling clock and slows down the operating speed when the slow signal is activated.

Description

Technology Field

[0001] This patent document relates to a transmission circuit used to transmit data (signals) in various integrated circuits. Background Technology

[0003] Various integrated circuit chips do not operate independently but function by exchanging data (signals) with surrounding chips. For example, memory chips such as DRAM and Flash exchange data with a memory controller, and the CPU also exchanges data with various chips on the motherboard. Furthermore, signal transmission does not occur only between chips; it also takes place between circuit A and circuit B within a single integrated circuit chip (where A and B represent arbitrary circuits). A circuit that transmits data (signals) is called a transmitter circuit or an output driver.

[0004] As the operating speed of integrated circuits increases and the data rate of data (signals) transmitted by transmission circuits increases, there is an increasing demand to perform various operations to improve the quality of the data (signals) transmitted by transmission circuits.

[0005] A data sampling circuit used in a data system that samples and transmits data is described in Korean published patent KR10-2007-0015094, disclosed on February 1, 2007, under the name “Pre-emphasis circuit”. The problem to be solved

[0006] Embodiments of the present invention can provide a technology that improves the quality of transmitted data using a simple structure without increasing current consumption. means of solving the problem

[0008] A data sampling circuit according to one embodiment of the present invention may include: a pattern detection circuit that detects a pattern of multi-bit data including input data and generates a slow signal; and a sampling circuit that samples the input data during the activation period of a sampling clock and slows down the operating speed when the slow signal is activated.

[0009] A data transmission circuit according to another embodiment of the present invention may include: a plurality of pattern detection circuits that detect a pattern of multi-bit data and generate a plurality of slow signals; a plurality of sampling circuits that sample data corresponding to themselves among the multi-bit data during the activation period of the sampling clock corresponding to themselves among the plurality of sampling clocks, and slow down the operating speed when the slow signal corresponding to themselves among the plurality of slow signals is activated; and a parallel-to-serial conversion circuit for converting data sampled by the plurality of sampling circuits into a parallel-to-serial format and outputting it to an output node.

[0010] A data transmission circuit according to another embodiment of the present invention may include: first to fourth pattern detection circuits that generate first to fourth slow signals using multi-bit data corresponding to itself among first to fourth data; a first sampling circuit that samples the first data in the activation interval of a first sampling clock and slows down the operating speed when the first slow signal is activated; a second sampling circuit that samples the second data in the activation interval of a second sampling clock and slows down the operating speed when the second slow signal is activated; a third sampling circuit that samples the third data in the activation interval of a third sampling clock and slows down the operating speed when the third slow signal is activated; a fourth sampling circuit that samples the fourth data in the activation interval of a fourth sampling clock and slows down the operating speed when the first slow signal is activated; and a parallel-to-serial conversion circuit for converting data sampled by the first to fourth sampling circuits into a parallel-to-serial format and outputting it to an output node. Effects of the invention

[0012] According to embodiments of the present invention, the quality of transmitted data can be improved while using a simple structure and without increasing current consumption. Brief explanation of the drawing

[0014] FIG. 1 is a configuration diagram of a data transmission circuit (100) according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an exemplary embodiment of the sampling clock generation circuit (110) of FIG. 1. FIG. 3 is a timing diagram to explain the operation of FIG. 2. FIG. 4 is a configuration diagram of an exemplary embodiment of the data sampling circuits (120) of FIG. 1. FIG. 5 is a configuration diagram of an exemplary embodiment of the parallel-to-serial conversion circuit (130) of FIG. 1. FIG. 6 is a timing diagram for explaining the operation of FIG. 4 and FIG. 5. FIG. 7 is a diagram showing pre-amplification driving at the output stage (DATA_OUT). Specific details for implementing the invention

[0015] Hereinafter, in order to provide a detailed explanation that enables a person skilled in the art to easily implement the technical concept of the present invention, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings. In describing the present invention, known components unrelated to the gist of the invention may be omitted. It should be noted that in assigning reference numbers to the components of each drawing, identical components are assigned the same number as much as possible, even if they are shown in different drawings.

[0017] FIG. 1 is a configuration diagram of a data transmission circuit (100) according to an embodiment of the present invention. The data transmission circuit (100) can be used to transmit data (signals) between different integrated circuit chips or within a single integrated circuit chip.

[0018] Referring to FIG. 1, the data transmission circuit (100) may include a sampling clock generation circuit (110), first to fourth data sampling circuits (120_0 to 120_3) and a parallel-to-serial conversion circuit (130).

[0019] The first to fourth data (DIIN, DQIN, DIBIN, DQBIN), which are parallel data, may be data to be transmitted by the data transmission circuit (100). The first to fourth clocks (CLKI, CLKQ, CKKIB, CLKQB) may be clocks for strobing the first to fourth data (DIIN, DQIN, DIBIN, DQBIN). The first to fourth clocks (CLKI, CLKQ, CLKIB, CLKQB) may have different phases. That is, the first to fourth clocks (CLKI, CLKQ, CKKIB, CLKQB) may have a phase difference of 90° from each other.

[0020] The sampling clock generation circuit (110) can generate first to fourth sampling clocks (SCI, SCQ, SCIB, SCQB) using first to fourth clocks (CLKI, CLKQ, CLKIB, CLKQB). The first to fourth sampling clocks (SCI, SCQ, SCIB, SCQB) may be clocks used by first to fourth data sampling circuits (120_0~120_3) to sample first to fourth data (DIIN, DQIN, DIBIN, DQBIN).

[0021] The first to fourth data sampling circuits (120_0 to 120_3) can sample the first to fourth data (DIIN, DQIN, DIBIN, DQBIN) using the first to fourth sampling clocks (SCI, SCQ, SCIB, SCQB). The first to fourth data sampling circuits (120_0 to 120_3) can detect the pattern of the first to fourth data (DIIN, DQIN, DIBIN, DQBIN) and slow down their sampling speed in the section where it is determined that pre-emphasis is required, so that pre-emphasis is implemented at the output terminal (DATA_OUT) of the data transmission circuit. The data (IOUT, IOUTB, QOUT, QOUTB, IBOUT, IBOUTB, QBOUT, QBOUTB) sampled by the first to fourth data sampling circuits (120_0 to 120_3) can be output in a differential form. In FIG. 1, DIN represents a terminal where the data to be sampled is input, SC represents a terminal where the sampling clock is input, DIN_P0 represents a terminal where the data immediately preceding the data input to DIN is input, DIN_P1 represents a terminal where the data immediately preceding the data input to DIN_P0 is input, and OUT and OUTB represent terminals where the sampled differential data is output. By referring to DIN, SC, DIN_P0, and DIN_P1 in FIG. 1, it is possible to determine what signals the first to fourth data sampling circuits (120_0 to 120_3) receive.

[0022] Depending on the system including the data transmission circuit (100), the sampling circuits (120_0 to 120_3) may perform the role of a level shifter. For example, signals input to the sampling circuits (120_0 to 120_3) may swing to a level between ground voltage and the first power supply voltage (VDD1), and signals output from the sampling circuits (120_0 to 120_3) may swing to a level between ground voltage and the second power supply voltage (VDD2). Here, the levels of the first power supply voltage (VDD1) and the second power supply voltage (VDD2) may be different from each other.

[0023] The parallel-to-serial conversion circuit (130) can convert the data (IOUT, IOUTB, QOUT, QOUTB, IBOUT, IBOUTB, QBOUT, QBOUTB) sampled by the first to fourth data sampling circuits (120_0~120_3) into parallel-to-serial and output it to the output terminal (DATA_OUT).

[0024] In FIG. 1, it is illustrated that there are 4 data sampling circuits (120_0 to 120_3) and a 4:1 parallel-to-serial conversion operation is performed by the parallel-to-serial conversion circuit (130), but this is merely an example, and it is obvious that the number of data sampling circuits (120) is N (N is an integer greater than or equal to 2) and the parallel-to-serial conversion circuit (130) can perform an N:1 parallel-to-serial conversion operation.

[0026] FIG. 2 is a configuration diagram of an exemplary embodiment of the sampling clock generation circuit (110) of FIG. 1, and FIG. 3 is a timing diagram for explaining the operation thereof.

[0027] Referring to FIG. 2, the sampling clock generation circuit (110) may include inverters (211–218) and AND gates (221–224). The first to fourth clocks (CLKI, CLKQ, CLKIB, CLKQB) swing between the ground voltage and the first power supply voltage (VDD1), and the sampling clock generation circuit (110) may operate using the ground voltage and the first power supply voltage (VDD1).

[0028] Inverters (211, 212) can delay the first clock (CLKI). The delay value of the inverters (211, 212) is denoted as D0. The AND gate (221) can generate a first sampling clock (SCI) that is activated to '1' during the interval when the first clock (CLKI) and the fourth clock (CLKQB), which are delayed by the inverters (211, 212), are '1' (high). Referring to FIG. 3, it can be seen that the rising edge of the first sampling clock (SCI) is delayed by D0 compared to the rising edge of the first clock (CLKI), and that the falling edge of the first sampling clock (SCI) and the falling edge of the fourth clock (CLKQB) are at the same time. In addition, with reference to FIG. 3, the relationship between the first to fourth data (DIIN, DQIN, DIBIN, DQBIN) and the first to fourth clocks (CLKI, CLKQ, CLKIB, CLKQB) can also be seen.

[0029] Inverters (213, 214) can delay the second clock (CLKQ). The delay value of the inverters (213, 214) is denoted as D0. The AND gate (222) can generate a second sampling clock (SCQ) that is activated as '1' in the interval where the second clock (CLKQ) delayed by the inverters (213, 214) and the first clock (CLKI) are '1'. Referring to FIG. 3, it can be seen that the rising edge of the second sampling clock (SCQ) is delayed by D0 compared to the rising edge of the second clock (CLKQ), and that the falling edge of the second sampling clock (SCQ) and the falling edge of the first clock (CLKI) are at the same time.

[0030] Inverters (215, 216) can delay the third clock (CLKIB). The delay value of the inverters (215, 216) is denoted as D0. The AND gate (223) can generate a third sampling clock (SCIB) that is activated as '1' in the interval where the third clock (CLKIB) and the second clock (CLKQ) delayed by the inverters (215, 216) are '1'. Referring to FIG. 3, it can be seen that the rising edge of the third sampling clock (SCIB) is delayed by D0 compared to the rising edge of the third clock (CLKIB), and that the falling edge of the third sampling clock (SCIB) and the falling edge of the second clock (CLKQ) are at the same time.

[0031] Inverters (217, 218) can delay the fourth clock (CLKQB). The delay value of the inverters (217, 218) is denoted as D0. The AND gate (224) can generate a fourth sampling clock (SCQB) that is activated as '1' in the interval where the fourth clock (CLKQB) and the third clock (CLKIB) delayed by the inverters (217, 218) are '1'. Referring to FIG. 3, it can be seen that the rising edge of the fourth sampling clock (SCQB) is delayed by D0 compared to the rising edge of the fourth clock (CLKQB), and that the falling edge of the fourth sampling clock (SCQB) and the falling edge of the third clock (CLKIB) are at the same time.

[0033] FIG. 4 is a configuration diagram of an exemplary embodiment of the data sampling circuits (120) of FIG. 1. Since the signals input to the terminals are different for each of the data sampling circuits (120_0 to 120_3) of FIG. 1, FIG. 4 will be described based on the terminals.

[0034] Referring to FIG. 4, the data sampling circuit (120) may include a pattern detection circuit (410) and a sampling circuit (420).

[0035] The pattern detection circuit (410) can activate the slow signal (SLOWB) to '0' when the data of terminal (DIN) and the data of terminal (DIN_P0) are different, and when the data of terminal (DIN_P0) and the data of terminal (DIN_P1) are different. The pattern detection circuit (410) may include XOR gates (411, 412) and a NAND gate (413). When the data of terminals (DIN, DIN_P0) are different, the output of the XOR gate (411) becomes '1', and when the data of terminals (DIN_P0, DIN_P1) are different, the output of the XOR gate (412) can become '1'. And when the outputs of both XOR gates (411, 412) are '1', the slow signal (SLOWB) output from the NAND gate (413) can be activated to '0'. That is, the pattern detection circuit (410) can activate the slow signal (SLOWB) to '0' when the data pattern of DIN_P1, DIN_P0, DIN is (0, 1, 0) or (1, 0, 1). The pattern detection circuit (410) can operate using the ground voltage and the first power supply voltage (VDD1).

[0036] The pattern detection circuit (410) of the first data sampling circuit (120_0) can activate the slow signal (SLOWB) to '0' when the pattern of the third, fourth, and first data (DIBIN, DQBIN, DIIN) is (0, 1, 0) or (1, 0, 1). Additionally, the pattern detection circuit (410) of the second data sampling circuit (120_1) can activate the slow signal (SLOWB) to '0' when the pattern of the fourth, first, and second data (DQBIN, DIIN, DQIN) is (0, 1, 0) or (1, 0, 1). Additionally, the pattern detection circuit (410) of the third data sampling circuit (120_2) can activate the slow signal (SLOWB) to '0' when the pattern of the first, second, and third data (DIIN, DQIN, DIBIN) is (0, 1, 0) or (1, 0, 1). Additionally, the pattern detection circuit (410) of the fourth data sampling circuit (120_3) can activate the slow signal (SLOWB) to '0' when the pattern of the second, third, and fourth data (DQIN, DIBIN, DQBIN) is (0, 1, 0) or (1, 0, 1).

[0037] The sampling circuit (420) samples and amplifies data from terminal (DIN) while the sampling clock of terminal (SC) is '1', and can be reset while the sampling clock of terminal (SC) is '0'. The sampling circuit (420) can increase the amount of operating current while the slow signal (SLOWB) is disabled as '1', and decrease the amount of operating current while the slow signal (SLOWB) is enabled as '0'. That is, the sampling circuit (420) can operate at a relatively fast speed while the slow signal (SLOWB) is disabled as '1', and operate at a relatively slow speed while the slow signal (SLOWB) is enabled as '0'. Meanwhile, the sampling circuit (420) can reset the output terminals (OUT, OUTB) to the level of the second power supply voltage (VDD2) while the sampling clock of terminal (SC) is '0'. The sampling circuit (420) can operate using the ground voltage and the second power supply voltage (VDD2). Therefore, the data of the output terminals (OUT, OUTB) of the sampling circuit (420) can swing to a level of 0 to VDD2.

[0038] The sampling circuit (420) may include a positive input section (421), a negative input section (422), a first pull-up driving section (423), a second pull-up driving section (424), a first sinking section (425), a second sinking section (428), and transistors (431, 432, 433) for a reset operation.

[0039] The positive input section (421) can sink current from the terminal (OUTB), where negative output data is output, to the common source node (CS) in response to data input to the terminal (DIN). Therefore, the higher the voltage of the terminal (DIN), the lower the voltage of the terminal (OUTB) can be. The positive input section (421) may be an NMOS transistor.

[0040] The auxiliary input section (422) can sink current from the terminal (OUT), where the positive output data is output in response to the data of the terminal (DINB), to the common source node (CS). Here, the data of the terminal (DINB) may be data obtained by inverting the data of the terminal (DIN). The higher the voltage of the terminal (DINB), the lower the voltage of the terminal (OUT) may be. The auxiliary input section (422) may be an NMOS transistor.

[0041] The first pull-up driver (423) can pull up the terminal (OUT) in response to the voltage level of the terminal (OUTB), and the second pull-up driver (424) can pull up the terminal (OUTB) in response to the voltage level of the terminal (OUT). The voltages of the terminals (OUT, OUTB) can be differentially amplified by the operation of the first pull-up driver (423) and the second pull-up driver (424). Each of the first pull-up driver (423) and the second pull-up driver (424) may be a PMOS transistor.

[0042] The first sinking unit (425) can sink current from the common source node (CS) to the ground terminal. The first sinking unit (425) can be activated when the sampling clock of the terminal (SC) is '1' and deactivated when the sampling clock of the terminal (SC) is '0'. The first sinking unit (425) may include two NMOS transistors (426, 427) connected in series. The NMOS transistor (426) can be turned on when the sampling clock of the terminal (SC) is '1' and turned off when it is '0'. The NMOS transistor (427) receives an activation signal (EN), which is a signal that always maintains a level of '1' when the sampling circuit (420) is operating. Therefore, the NMOS transistor (427) can always be turned on.

[0043] The second sinking unit (428) can sink current from the common source node (CS) to the ground terminal when the slow signal (SLOWB) is disabled as '1'. The second sinking unit (425) can be activated when the sampling clock of the terminal (SC) is '1' and disabled when the sampling clock of the terminal (SC) is '0'. The second sinking unit (428) may include two NMOS transistors (429, 430) connected in series. The NMOS transistor (429) can be turned on when the sampling clock of the terminal (SC) is '1' and turned off when it is '0'. The NMOS transistor (430) can be turned on when the slow signal (SLOWB) is disabled as '1' and turned off when it is enabled as '0'. That is, the second sinking unit (428) can sink current from the common source (CS) to the ground terminal when the slow signal (SLOWB) is deactivated to '1' and the sampling clock of the terminal (SC) is '1'. Since the second sinking unit (428) performs the sinking operation only when the slow signal (SLOWB) is deactivated to '1', the amount of operating current of the sampling circuit (420) can be increased when the slow signal (SLOWB) is deactivated to '1', and the amount of operating current of the sampling circuit (420) can be decreased when the slow signal (SLOWB) is activated to '0'.

[0044] The PMOS transistor (431) can reset the negative output terminal (OUTB) to the level of the second power supply voltage (VDD2) when the sampling clock of the terminal (SC) is '0', and the PMOS transistor (432) can reset the positive output terminal (OUT) to the level of the second power supply voltage (VDD2) when the sampling clock of the terminal (SC) is '0'. Additionally, the PMOS transistor (433) can equalize the positive output terminal (OUT) and the negative output terminal (OUTB) when the sampling clock of the terminal (SC) is '0'.

[0045] Referring to FIG. 6, it can be seen that the data sampling circuit (120_0) samples the first data (DIIN) when the first sampling clock (SCI) is '1' and generates the resulting output data (IOUT, IOUTB). It can be seen that the output data (IOUT, IOUTB) has a level corresponding to the first data (DIIN) while the first sampling clock (SCI) is '1', and is reset to '1' while the first sampling clock (SCI) is '0'. Likewise, in FIG. 6, it can be seen that the second to fourth data sampling circuits (120_1 to 120_3) sample the second to fourth data (DQIN, DIBIN, DQBIN) when the second to fourth sampling clocks (SCQ, SCIB, SCQB) are '1', and generate the resulting output data (QOUT, QOUTB, IBOUT, IBOUTB, QBOUT, QBOUTB).

[0047] FIG. 5 is a configuration diagram of an exemplary embodiment of the parallel-to-serial conversion circuit (130) of FIG. 1.

[0048] The parallel-to-serial conversion circuit (130) can perform a parallel-to-serial conversion operation that sequentially outputs the sampling data of the first to fourth data sampling circuits (120_0 to 120_3) to the output terminal (DATA_OUT).

[0049] The parallel-to-serial conversion circuit (130) may include NAND gates (501–504), inverters (505–516, 527), PMOS transistors (517, 519, 521, 523, 528), NMOS transistors (518, 520, 522, 524, 529) and latches (525, 526).

[0050] NAND gate (501) receives sampled data (IOUT, IBOUT) and generates data (IDATA), NAND gate (502) receives sampled data (QOUT, QBOUT) and generates data (QDATA), NAND gate (503) receives sampled data (IOUTB, IBOUTB) and generates data (IBDATA), and NAND gate (504) receives sampled data (QOUTB, QBOUTB) and generates data (QDATA).

[0051] Inverters (505, 508, 511, 514)) can invert data (IDATA, QDATA, IBDATA, QBDATA) to generate data (IDATA_B, QDATA_B, IBDATA_B, QBDATA_B). And inverters (506, 507, 509, 510, 512, 513, 515, 516) can generate data (IDATA_D, QDATA_D, IBDATA_D, QBDATA_D) having the same logic level as data (IDATA, QDATA, IBDATA, QBDATA).

[0052] PMOS transistors (517, 519) can pull up the input terminal of the latch (525) in response to data (IDATA_B, QDATA_B). Additionally, PMOS transistors (521, 523) can pull up the input terminal of the latch (526) in response to data (IBDATA_B, QBDATA_B).

[0053] The NMOS transistors (518, 520) can pull down the input terminal of the latch (525) in response to data (IBDATA_D, QBDATA_D). Additionally, the NMOS transistors (522, 524) can pull down the input terminal of the latch (526) in response to data (IDATA_D, QDATA_D).

[0054] The inverter (527) inverts the signal of the output terminal (RDOI) of the latch (525), and the PMOS transistor (528) can pull up the output terminal (DATA_OUT) in response to the output signal of the inverter (527). And the NMOS transistor (529) can pull down the output terminal (DATA_OUT) in response to the signal of the output terminal (FDOI) of the latch (526).

[0055] FIG. 6 illustrates the data (IDATA, QDATA, IBDATA, QBDATA), the signals of the output terminals (RDOI, FDOI) of the latches (525, 526), ​​and the data of the output terminal (DATA_OUT). Referring to FIG. 6, it can be understood that the first to fourth data (DIIN, DQIN, DIBIN, DQBIN) are sampled by the first to fourth data sampling circuits (120_0 to 120_3), and that the sampled data (IOUT, IOUTB, QOUT, QOUTB, IBOUT, IBOUTB, QBOUT, QBOUTB) becomes the data (IDATA, QDATA, IBDATA, QBDATA) and is finally output serially to the output terminal (DATA_OUT). In S0b, S1b, etc. in FIG. 6, b may represent inversion. For example, S0b may be the inverted data of S0.

[0057] Figure 7 is a diagram showing pre-emphasis driving at the output stage (DATA_OUT). In Figure 7, we will examine how pre-emphasis driving is performed when the data (S0~S7) is (0, 1, 0, 1, 0, 0, 1, 0).

[0058] Data (S2) is sampled by the second data sampling circuit (120_1), and since the pattern of the data (S0~S2) is (0, 1, 0), the slow signal (SLOWB) of the second data sampling circuit (120_1) can be activated to '0'. As a result, the data (S2) is sampled slowly by the second data sampling circuit (120_1), and as a result, the transition from data (S1) to data (S2) at the output terminal (DATA_OUT) can be slowed down as shown by the solid line.

[0059] Data (S3) is sampled by the third data sampling circuit (120_2), and since the pattern of data (S1~S3) is (1, 0, 1), the slow signal (SLOWB) of the third data sampling circuit (120_2) can be activated to '0'. As a result, data (S3) is sampled slowly by the third data sampling circuit (120_2), and as a result, the transition from data (S2) to data (S3) at the output terminal (DATA_OUT) can be slowed down as shown by the solid line.

[0060] Data (S4) is sampled by the fourth data sampling circuit (120_3), and since the pattern of data (S2~S4) is (0, 1, 0), the slow signal (SLOWB) of the fourth data sampling circuit (120_3) can be activated to '0'. As a result, data (S4) is sampled slowly by the fourth data sampling circuit (120_3), and as a result, the transition from data (S3) to data (S4) at the output terminal (DATA_OUT) can be slowed down as shown by the solid line.

[0061] Data (S7) is sampled by the third data sampling circuit (120_2), and since the pattern of the data (S5~S7) is (0, 1, 0), the slow signal (SLOWB) of the third data sampling circuit (120_2) can be activated to '0'. As a result, the data (S7) is sampled slowly by the third data sampling circuit (120_2), and as a result, the transition from data (S6) to data (S7) at the output terminal (DATA_OUT) can be slowed down as shown by the solid line.

[0062] It can be observed that at the output stage (DATA_OUT), there is no change in the eye size of the data (S0, S2, S3, S5, S7), while the eye size of the data (S1, S6) increases and the eye size of the data (S4) decreases. In other words, it can be confirmed that time-domain pre-emphasis driving is taking place, in which the eye size of the data (S1, S6) increases. Since the point at which pre-emphasis driving is required is when the data (DATA_OUT) changes from a low frequency to a high frequency (the output time of S1, S6), it can be seen that pre-emphasis driving is performed at the time when pre-emphasis driving is necessary. Although the eye size of the data (S4) decreases, since the output time of the data (S4) is when the data (DATA_OUT) changes from a high frequency to a low frequency, sufficient margin can be secured at the receiving stage, so this may not be a problem.

[0064] According to embodiments of the present invention, pre-emphasis driving at the output stage can be implemented by controlling the data sampling rate with a simple configuration. Furthermore, since the data sampling rate is only slowed down in the section where pre-emphasis driving is required, the quality of transmitted data can be improved without increasing current consumption.

[0065] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the aforementioned embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0067] 100: Data transmission circuit 110: Sampling clock generation circuit 120_0~120_3: Data Sampling Circuits 130: Parallel-to-series conversion circuit

Claims

Claim 1 A pattern detection circuit that detects a pattern of multi-bit data including input data and generates a slow signal; and a data sampling circuit that samples the input data during the activation period of a sampling clock and slows down the operating speed when the slow signal is activated. Claim 2 A data sampling circuit in which the operating current of the sampling circuit is reduced when the slow signal is activated in claim 1. Claim 3 In claim 1, the pattern detection circuit is a data sampling circuit that generates the slow signal when the pattern of the multi-bit data matches one of the preset patterns. Claim 4 In claim 3, the preset patterns are a data sampling circuit including a toggling pattern. Claim 5 In claim 1, the sampling circuit comprises: a positive input section that sinks current from a negative output node to a common source node in response to the input data; a negative input section that sinks current from a positive output node to the common source node in response to inverted data obtained by inverting the input data; a first pull-up driving section that pulls up the positive output node in response to the voltage level of the negative output node; a second pull-up driving section that pulls up the negative output node in response to the voltage level of the positive output node; a first sinking section for sinking current from the common source node to a ground terminal; and a second sinking section that is activated when the slow signal is deactivated and sinks current from the common source node to the ground terminal. Claim 6 In claim 5, the first pull-up driving unit, the second pull-up driving unit, the first sinking unit, and the second sinking unit are a data sampling circuit that is activated during the activation period of the sampling clock. Claim 7 In claim 6, the data sampling circuit in which the positive output node and the negative output node are equalized during the deactivation period of the sampling clock. Claim 8 A data transmission circuit comprising: a plurality of pattern detection circuits that detect a pattern of multi-bit data and generate a plurality of slow signals; a plurality of sampling circuits that sample data corresponding to each of the multi-bit data during the activation period of a sampling clock corresponding to each of the plurality of sampling clocks, and slow down the operation speed when a slow signal corresponding to each of the plurality of slow signals is activated; and a parallel-to-serial conversion circuit for converting data sampled by the plurality of sampling circuits into a parallel-to-serial format and outputting it to an output node. Claim 9 In claim 8, each of the plurality of sampling circuits is a data transmission circuit in which the amount of operating current is reduced when the slow signal corresponding to each of the plurality of slow signals is activated. Claim 10 In claim 8, each of the plurality of sampling circuits comprises: a positive input unit that sinks current from a negative output node to a common source node in response to input data corresponding to each of the multi-bit data; a negative input unit that sinks current from a positive output node to a common source node in response to inverted data obtained by inverting the input data corresponding to each of the multi-bit data; a first pull-up driving unit that pulls up the positive output node in response to the voltage level of the negative output node; a second pull-up driving unit that pulls up the negative output node in response to the voltage level of the positive output node; a first sinking unit for sinking current from the common source node to a ground terminal; and a second sinking unit that is activated when a slow signal corresponding to each of the plurality of slow signals is deactivated and sinks current from the common source node to the ground terminal. Claim 11 In claim 10, the first pull-up driving unit, the second pull-up driving unit, the first sinking unit, and the second sinking unit are a data transmission circuit that is activated during the activation period of a sampling clock corresponding to each of the plurality of sampling clocks. Claim 12 In claim 11, the data transmission circuit in which the positive output node and the negative output node are equalized during the deactivation period of the sampling clock corresponding to each of the plurality of sampling clocks. Claim 13 A data transmission circuit comprising: first to fourth pattern detection circuits for generating first to fourth slow signals using multi-bit data corresponding to each of the first to fourth data; a first sampling circuit that samples the first data in the activation interval of the first sampling clock and slows down the operating speed when the first slow signal is activated; a second sampling circuit that samples the second data in the activation interval of the second sampling clock and slows down the operating speed when the second slow signal is activated; a third sampling circuit that samples the third data in the activation interval of the third sampling clock and slows down the operating speed when the third slow signal is activated; a fourth sampling circuit that samples the fourth data in the activation interval of the fourth sampling clock and slows down the operating speed when the first slow signal is activated; and a parallel-to-serial conversion circuit for converting data sampled by the first to fourth sampling circuits into a parallel-to-serial format and outputting it to an output node. Claim 14 In claim 13, the data transmission circuit wherein the first pattern detection circuit activates the first slow signal when the first data and the fourth data are different and the fourth data and the third data are different, the second pattern detection circuit activates the second slow signal when the second data and the first data are different and the first data and the fourth data are different, the third pattern detection circuit activates the third slow signal when the third data and the second data are different and the second data and the first data are different, and the fourth pattern detection circuit activates the fourth slow signal when the fourth data and the third data are different and the third data and the second data are different. Claim 15 In Clause 13, the first to fourth sampling clocks are a data transmission circuit in which the activation intervals do not overlap. Claim 16 In claim 13, each of the first to fourth sampling circuits is a data transmission circuit in which the amount of operating current is reduced when the slow signal corresponding to each of the first to fourth slow signals is activated. Claim 17 In claim 13, the swing widths of the first to fourth data and the first to fourth sampling clocks are different from the swing widths of the data sampled by the first to fourth sampling circuits, in a data transmission circuit. Claim 18 In claim 13, each of the first to fourth sampling circuits comprises: a positive input unit that sinks current from a negative output node to a common source node in response to input data corresponding to each of the first to fourth data; a negative input unit that sinks current from a positive output node to a common source node in response to inverted data obtained by inverting the input data corresponding to each of the first to fourth data; a first pull-up driving unit that pulls up the positive output node in response to the voltage level of the negative output node; a second pull-up driving unit that pulls up the negative output node in response to the voltage level of the positive output node; a first sinking unit for sinking current from the common source node to a ground terminal; and a second sinking unit that is activated when a slow signal corresponding to each of the first to fourth slow signals is deactivated and sinks current from the common source node to the ground terminal. Claim 19 In claim 18, the first pull-up driving unit, the second pull-up driving unit, the first sinking unit, and the second sinking unit are a data transmission circuit that is activated during the activation period of a sampling clock corresponding to each of the first to fourth sampling clocks. Claim 20 In claim 19, the data transmission circuit in which the positive output node and the negative output node are equalized during the deactivation period of the sampling clock corresponding to each of the first to fourth sampling clocks.

Images