Display panel and display device including the display panel

Abstract

The embodiments relate to a display device comprising: a display panel including a pixel array and a bezel area surrounding the pixel array; a display panel driving circuit that outputs a driving signal for driving the display panel; and a compensation unit that compensates for noise generated by the driving signal in the display panel or the display panel driving circuit, wherein the compensation unit comprises: an inversion unit that inverts the phase of the driving signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel; and a phase compensation unit that delays the phase of the driving signal by an arbitrary amount of time so that the phases of the driving signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device including the same. Background Technology

[0002] Display devices include liquid crystal displays and electroluminescent displays, and electroluminescent displays can be classified into inorganic light-emitting displays and organic light-emitting diode displays depending on the material of the light-emitting layer.

[0003] As the resolution of display devices gradually increases, higher frequencies and more signals are required to drive them, leading to problems such as signal distortion and EMI (electromagnetic interference) noise.

[0004] To solve these problems, a phase cancellation method is applied that uses a phase-inverted signal with the same magnitude and opposite polarity as the driving signal (e.g., an electromagnetic signal) as a noise compensation signal. However, this method requires separate wiring and pins to apply the noise compensation signal from an external control unit to the panel, which can increase component costs. Additionally, in general phase cancellation methods, there is a problem in that the phase cannot be completely canceled because there is a delay between the driving signal and the phase-inverted signal. The problem to be solved

[0005] The embodiments provide a display panel with improved noise, such as EMI within the display panel, and a display device including the same.

[0006] The embodiments provide a display panel capable of self-eliminating noise within the display panel without the application of an external signal, and a display device including the same. means of solving the problem

[0007] A display device according to one embodiment may include a display panel comprising a pixel array and a bezel area surrounding the pixel array, a display panel driving circuit that outputs a driving signal for driving the display panel, and a compensation unit that compensates for noise generated by the driving signal in the display panel or the display panel driving circuit.

[0008] The above compensation unit may include an inversion unit that inverts the phase of the driving signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel, and a phase compensation unit that delays the phase of the driving signal by an arbitrary amount of time so that the phases of the driving signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel.

[0009] The above display panel driving circuit may include a GIP (Gate-In-Panel) mounted in the bezel area of ​​the display panel and comprising a gate driver and a light-emitting driver, a multiplexer array in the bezel area of ​​the display panel, and a level shifter that transmits the driving signal to the gate driver, the light-emitting driver, and the multiplexer array.

[0010] The above compensation unit may be mounted in the bezel area of ​​the display panel and positioned adjacent to the GIP and the multiplexer array.

[0011] It may further include a compensation GIP disposed adjacent to the above GIP and applying a signal output from the compensation unit to the pixel array, and a compensation multiplexer array disposed adjacent to the above multiplexer array and applying a signal output from the compensation unit to the pixel array.

[0012] The above driving signal is composed of n (n is a natural number) pulse signals, and the inversion unit may include at least one logic gate that outputs an inverted phase of the n pulse signals.

[0013] The above inversion unit may include at least one of a NAND gate and an XOR gate that logically synthesizes the n pulse signals to output a phase-inverted signal.

[0014] The above compensation unit further includes a determination unit that outputs a first signal if the pulses of the n pulse signals overlap each other and outputs a second signal having a different level from the first signal if they do not overlap and are non-overlapping signals, and the inversion unit can output the output signal of the XOR gate as the phase inversion signal in response to the first signal and output the output signal of the NAND gate as the phase inversion signal in response to the second signal.

[0015] The above inversion unit may include n NOT gates that output a phase inversion signal for each of the n pulse signals.

[0016] The phase compensation unit includes a resistor and a transistor connected in series between a gate high voltage and a gate low voltage, the transistor is controlled to turn on and turn off by the driving signal, and the output terminal of the phase compensation unit can be connected between the resistor and the transistor.

[0017] The above phase compensation unit can output the phase compensation signal having the same waveform as the driving signal but delayed by the arbitrary time, depending on the on / off delay time of the transistor.

[0018] The above compensation unit may further include an output buffer that amplifies the signal output from the inversion unit and the phase compensation unit and outputs it to the pixel array.

[0019] In the above display panel, electromagnetic interference (EMI) noise generated by the phase compensation signal can be eliminated by the field cancellation effect of the phase inversion signal.

[0020] A display device according to one embodiment may include a display panel comprising a pixel array and a bezel area surrounding the pixel array, a gate driver and a light-emitting driver that respectively apply a gate signal and a light-emitting signal to the pixels, a level shifter that applies a gate clock signal to the gate driver and the light-emitting driver, and a compensation unit that compensates for noise generated by the gate clock signal in the display panel.

[0021] The compensation unit may include an inversion unit that inverts the phase of the gate clock signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel, and a phase compensation unit that delays the phase of the gate clock signal by an arbitrary amount of time so that the phases of the gate clock signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel.

[0022] The above inversion unit may include a NAND gate that logically synthesizes n pulse signals constituting the gate clock signal to output a single phase-inverted signal.

[0023] A display device according to one embodiment may include a display panel comprising a pixel array and a bezel area surrounding the pixel array, a multiplexer array for applying a data signal to the pixels, a level shifter for applying a multiplexer array to a multiplexer array, and a compensation unit for compensating for noise generated by the driving signal in the display panel or the display panel driving circuit.

[0024] The compensation unit may include an inversion unit that inverts the phase of the multiplexer control signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel, and a phase compensation unit that delays the phase of the multiplexer control signal by an arbitrary amount of time so that the phases of the multiplexer control signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel.

[0025] The above inversion unit may include an XOR gate that logically synthesizes n pulse signals constituting the multiplexer control signal to output a single phase-inverted signal. Effects of the invention

[0026] A display panel according to the embodiments and a display device including the same can reduce component costs by reducing the number of wires and pins.

[0027] The display panel according to the embodiments can be applied to various models of display devices regardless of timing changes of the GIP or multiplexer array.

[0028] The display panel and display device according to the embodiments can effectively eliminate noise generated in the display panel by compensating for the phase delay of the phase inversion signal. Brief explanation of the drawing

[0029] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment. FIG. 2 is a diagram showing signal wiring between a timing control unit and a level shifter in a display device according to one embodiment. FIG. 3 is a timing diagram showing a gate clock signal and a noise compensation signal according to one embodiment. Figure 4 is a diagram showing the arrangement relationship of the GIP, level shifter, and compensation part mounted on the display panel. FIG. 5 is a block diagram showing the configuration of a compensation unit according to one embodiment. Figure 6 is a drawing showing an example in which a compensation unit is mounted on a display panel. Figure 7 is a circuit diagram showing one embodiment of the inversion section. FIG. 8 is a timing diagram showing an example of a non-overlapping clock signal. FIG. 9 is a circuit diagram showing another embodiment of the inversion section. FIG. 10 is a timing diagram showing one embodiment of an overlapping clock signal. Figure 11 is a circuit diagram showing the connection relationship between the inversion section and the judgment section. FIG. 12 is a circuit diagram showing an example of a judgment unit. FIG. 13 is a circuit diagram showing one embodiment of a phase compensation unit. FIG. 14 is a timing diagram showing an example of a phase compensation signal. FIG. 15 is a circuit diagram showing another embodiment of the phase compensation unit. FIG. 16 is a circuit diagram showing one embodiment of an output buffer. FIG. 17 is a graph showing the noise improvement effect according to an embodiment of the present invention. Specific details for implementing the invention

[0030] Specific details of other embodiments are included in the detailed description and drawings.

[0031] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various different forms. Furthermore, when a part is described as being connected to another part in the following description, this includes not only cases where they are directly connected but also cases where they are electrically connected with other elements interposed between them. Additionally, parts unrelated to the present invention in the drawings have been omitted to clarify the description of the invention, and similar parts throughout the specification are given the same reference numerals.

[0033] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment.

[0034] Referring to FIG. 1, the display device (1) includes a display panel (100) and a display panel driving circuit.

[0035] A display panel (100) includes a pixel array (AA) that displays pixel data of an input image. Pixel data of the input image is displayed on the pixels of the pixel array (AA). The pixel array (AA) includes a plurality of data lines (DL), a plurality of gate lines (GL) that intersect the data lines (DL), and pixels (P) arranged in a matrix form. In addition to the matrix form, the arrangement of pixels may be a form sharing pixels that emit the same color, a stripe form, a diamond form, etc.

[0036] When the resolution of the pixel array (AA) is n*m, the pixel array (AA) includes n pixel columns and m pixel rows that intersect the pixel columns. A pixel column includes pixels arranged along the y-axis direction. A pixel row includes pixels arranged along the x-axis direction. One horizontal period is the time divided by the total number of pixel lines for one frame period. During one horizontal period, pixel data is simultaneously written to the pixels of one pixel line.

[0037] Each pixel may include a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each pixel may further include a white subpixel. Each subpixel includes a pixel circuit and a light-emitting element. The pixel circuit includes a pixel electrode, a plurality of Thin Film Transistors (TFTs), and a capacitor. The pixel circuit is connected to a corresponding data line (DL) and a gate line (GL). The pixel circuit can write pixel data to control the amount of driving current flowing through the light-emitting element.

[0038] The display panel driving circuit generates and outputs driving signals for driving the display panel (100). The display panel driving circuit includes a gate driving unit (110), a data driving unit (120), and a timing control unit (130) for controlling the operation timing of these. Under the control of the timing control unit (130), the display panel driving circuit writes data of an input image to the pixels of the display panel (100).

[0039] The gate driver (110) applies a gate signal to pixels (P) through gate lines (GL). The gate signal applied to the gate lines (GL) turns on the switching TFTs provided in the subpixels to sequentially select the row of pixels to be charged with data voltage.

[0040] In one embodiment, the gate driver (110) can generate a gate signal based on a gate timing control signal received from a level shifter (140) provided in the display device (1). The level shifter (140) converts a logic high voltage (or high potential input voltage) of an input signal received from the timing control unit (130) into a gate high voltage and converts a logic low voltage (or low potential input voltage) of an input signal into a gate low voltage. The level shifter (140) can output clock signals that swing between the gate high voltage and the gate low voltage. The output signal of the level shifter (140) can be transmitted to at least one of a multiplexer array (121) and a gate driver (110).

[0041] The gate driver (110) can sequentially shift the gate timing control signal output from the level shifter (140) and sequentially output it to the gate lines (GL). The gate signal thus generated may be a pulse signal that swings between a gate high voltage and a gate low voltage.

[0042] In one embodiment, the gate driver (110) is positioned in a bezel area surrounding a pixel array (AA) of a display panel (100) and can be implemented in the form of a Gate-In-Penel (GIP).

[0043] The data driver (120) supplies the data voltage of the input image to the pixels (P) through the data lines (DL). The data driver (120) converts the pixel data (DATA) of the input image, which is received as a digital signal from the timing control unit (130) for every frame, into an analog gamma compensation voltage and outputs a data signal. The data driver (120) can generate the data signal using a digital to analog converter (DAC) that converts the digital signal into an analog gamma compensation voltage. The data signal is supplied to the data lines (DL).

[0044] The data driving unit (120) can be mounted on a COF (Chip on film) in the form of a data drive IC (DIC) and connected between an external device and a display panel (100).

[0045] The display panel driving circuit may further include a multiplexer array (121) positioned between the data driving unit (120) and the data lines (DL).

[0046] The multiplexer array (121) can reduce the number of channels of the data driver (120) by sequentially connecting one channel of the data driver (120) to a plurality of data lines (DL) and distributing the data signal output from one channel of the data driver (120) to the data lines (DL) in a time-division manner.

[0047] The timing control unit (130) receives pixel data of an input image and a timing signal synchronized therewith from an external host system. The timing control unit (130) transmits the pixel data of the input image to the data driving unit (120). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE), etc.

[0048] The timing control unit (130) can output a data timing control signal for controlling the data driver (120) based on a timing signal received from the host system, a gate timing control signal for controlling the gate driver (110), and a multiplexer control signal for controlling the switch elements of the multiplexer array (121). The gate timing control signal may include a start pulse, a shift clock, etc. The start pulse defines the start timing of the gate driver (110) for each frame period. The shift clock defines the shift timing of the gate signal output from the gate driver (110). The timing control unit (130) can further output a control signal for controlling the level shifter (140).

[0049] The timing control unit (130) is provided in the form of a flexible printed circuit board (FPCB) and can be connected to a COF on which a DIC is mounted. The timing control unit (130) can be electrically connected to a DIC and a display panel (100) through wiring formed on the COF. Other components, such as a level shifter (140), can be mounted together on the flexible printed circuit board on which the timing control unit (130) is placed.

[0050] In one embodiment, the display device (1) further includes a light-emitting driving unit (150). The light-emitting driving unit (150) applies a light-emitting signal through light-emitting lines (EL). The light-emitting signal applied to the light-emitting lines (EL) can turn on a switching TFT provided in the subpixels to form a current path flowing from a high-potential driving voltage through a light-emitting element to a low-potential driving voltage.

[0051] In one embodiment, the light-emitting driving unit (150) can generate a light-emitting signal based on a light-emitting timing control signal received from a level shifter (140) provided in the display device (1).

[0052] In one embodiment, the light-emitting driver (150) may be placed in the bezel area of ​​the display panel (100) in the form of a Gate-In-Penel (GIP) together with the gate driver (110).

[0053] In the present embodiment, the display device (1) further includes a compensation unit (160). The compensation unit (160) generates a noise compensation signal to remove noise generated in the display device (1) and applies it to the display panel (100) or the display panel driving circuit. The noise may be signal distortion and / or EMI noise generated by the driving signal applied to the display panel (100) or the display panel driving circuit.

[0055] FIG. 2 is a diagram showing signal wiring between a timing control unit and a level shifter in a display device according to one embodiment. FIG. 3 is a timing diagram showing a gate clock signal and a noise compensation signal according to one embodiment.

[0056] Referring to FIG. 2, the control board (170) can be connected to the source PCB (171) via a flexible circuit board, for example, a Flexible Flat Cable (FFC, 180). A data drive IC (190a) is connected between the source PCB (171) and the display panel (100).

[0057] The timing control unit (130) and the level shifter (140) may be mounted on the control board (170). In this case, the input terminals of the level shifter (140) are connected to the timing control unit (130) through wiring formed on the control board (170). The output terminals of the level shifter (140) may be connected to the GIP (195) through wiring connecting the FFC (180), the source PCB (171), the COF (190b), and the GIP (195) on the display panel (100). Additionally, the output terminals of the level shifter (140) may be connected to the multiplexer array (121) through wiring connecting the FFC (180), the source PCB (171), the COF (190b), and the multiplexer array (121) on the display panel (100).

[0058] The timing control unit (130) can output a control signal for controlling the display panel driving circuit. For example, the timing control unit (130) can output a control signal for controlling the operation timing of the gate driving unit (110) and the light-emitting driving unit (150) through the first to third control lines (G1, G2, EM), and can output a control signal for controlling the operation timing of the multiplexer array (121) through the fourth control line (MUX).

[0059] The level shifter (140) converts control signals output from the timing control unit (130) into clock signals and transmits them to the GIP (195) and the multiplexer array (121). For example, the level shifter (140) can generate a gate clock signal from the control signal output from the timing control unit (130) and transmit it to the gate driver (110) and light-emitting driver (150) embedded in the GIP (195). Additionally, the level shifter (140) can generate a multiplex signal from the control signal output from the timing control unit (130) and transmit it to the multiplexer array (121).

[0060] The clock signal generated by the level shifter (140) may be a pulse signal in which a pulse of gate low voltage (or gate high voltage) is output at a timing indicated by a control signal. For example, the gate clock signal may be four four-phase gate clock signals (GCLK1 to GCLK4) having the same pulse width and a phase delayed by 1 / 4 period, as shown in FIG. 3. However, the present embodiment is not limited thereto. For example, the gate clock signals may be n pulse signals having the same pulse width and a phase delayed by 1 / n period.

[0061] The level shifter (140) can output gate clock signals (GCLK1 to GCLK4) through corresponding control lines (G1, G2, EM). When the gate clock signals (GCLK1 to GCLK4) are applied, pulses are generated sequentially between the control lines (G1, G2, EM). EMI noise may occur as pulses are generated at different timings between adjacent control lines (G1, G2, EM). If EMI noise occurs, the smooth output state of the level shifter (140) cannot be guaranteed, and the reliability of the gate clock signals (GCLK1 to GCLK4) may be reduced.

[0062] To eliminate noise, the timing control unit (130) may further output a noise compensation signal (GCLK') for compensating for EMI noise, as shown in FIG. 3. The noise compensation signal (GCLK') is output to a compensation line (CL) placed adjacent to each control line (G1, G2, EM, MUX) through a level shifter (140). As shown in FIG. 3, the noise compensation signal (GCLK') is a phase-inverted signal that has the same magnitude and opposite polarity for the gate clock signals (GCLK1~GCLK4). When the phase-inverted signal is applied to the compensation line (CL), a field cancellation effect occurs between the control line (G1, G2, EM, MUX) and the compensation line (CL), so that EMI noise can be minimized.

[0063] Ideally, EMI noise should be completely canceled out by the noise compensation signal, but in actual driving environments, the noise compensation signal has a time delay with respect to EMI noise, so it is difficult to expect effective improvement of EMI noise. In addition, when the timing control unit (130) generates the noise compensation signal and applies it to the display panel (100), separate wiring is required for this, which increases manufacturing costs and may generate additional EMI noise.

[0064] Below, an embodiment is described that generates a noise compensation signal with improved time delay in the display panel (100) itself to solve this problem.

[0066] Figure 4 is a diagram showing the arrangement relationship of the GIP, level shifter, and compensation part mounted on the display panel.

[0067] The display panel (100) includes a pixel array (AA) that displays pixel data of an input image. Pixel data of the input image is displayed on the pixels of the pixel array (AA).

[0068] GIPs (195) are arranged on both the left and right sides of the display panel (100). A gate driver (110) and a light-emitting driver (150) may be mounted within the GIP (195). In the illustrated embodiment, one GIP (195) is provided on each of the left and right sides of the display panel (100). However, the present embodiment is not limited thereto, and the GIPs (195) may be arranged on any one or multiple sides of the display panel in various ways.

[0069] A multiplexer array (121) is placed on the upper side of the display panel (100).

[0070] The compensation unit (160) is positioned between the level shifter (140) and the GIP (195), and between the level shifter (140) and the multiplexer array (121). The compensation unit (160) may be positioned adjacent to the GIP (195) and the multiplexer array (121) at the edge of the display panel (100). For example, the compensation unit (160) may be positioned at the corner of the display panel (100), with one side positioned adjacent to the GIP (195) and the other side positioned adjacent to the multiplexer array (121).

[0071] As illustrated, when the GIP (195) is positioned on both the left and right sides of the display panel, multiple compensation units (160) may be provided on both the left and right sides of the display panel (100). Through this arrangement, the length of the wiring connecting the compensation units (160) and the GIP (195) and the signal delay can be minimized.

[0072] The compensation unit (160) can generate a noise compensation signal for the clock signal output from the level shifter (140) and output the clock signal and the noise compensation signal. The compensation unit (160) can apply the generated noise compensation signal to the display panel (100) through the GIP (195) and / or multiplexer array (121).

[0073] In one embodiment, the display panel (100) may include a separate compensation GIP (195') and / or compensation multiplexer array (121') to apply a noise compensation signal to the display panel (100). The compensation GIP (195') and the compensation multiplexer array (121') may each have the same configuration as the GIP (195) and the multiplexer array (121). The compensation GIP (195') and the compensation multiplexer array (121') may each be positioned adjacent to the GIP (195) and the multiplexer array (121), and may be positioned closer to the edge of the display panel (100) than the GIP (195) and the multiplexer array (121). In this embodiment, the compensation unit (160) processes the clock signal received from the level shifter (140) and outputs it to the GIP (195) and / or multiplexer array (121), and can output a noise compensation signal to the compensation GIP (195') and / or compensation multiplexer array (121').

[0075] FIG. 5 is a block diagram showing the configuration of a compensation unit according to one embodiment.

[0076] Referring to FIG. 5, the compensation unit (160) generates a noise compensation signal, and the generated noise compensation signal can be applied to a display panel driving circuit. In one embodiment, the noise compensation signal may be a signal for compensating for EMI noise of driving signals applied from the level shifter (140) shown in FIG. 4 to the GIP (195) and / or multiplexer array (121). The driving signals may include a gate clock signal (GCLK) and / or a multiplexer control signal (MUX).

[0077] In one embodiment, the compensation unit (160) may include an inversion unit (161) that generates a phase inversion signal (GCLK', MUX') for a driving signal (GCLK, MUX) and a phase compensation unit (163) that compensates for the phase delay of the phase inversion signal.

[0078] The inversion unit (161) inverts the phase of the driving signal (GCLK, MUX) to generate a phase-inverted signal. The inversion unit (161) may include a phase-inverting circuit, for example, an inverter or a logic gate. In one embodiment, the inversion unit (161) may have a 1:1 structure that receives one driving signal (GCLK, MUX) and outputs one phase-inverted signal (GCLK', MUX'). In another embodiment, the inversion unit (161) may have an N:1 structure that receives two or more driving signals (GCLK, MUX) and logically synthesizes them to output one phase-inverted signal (GCLK', MUX').

[0079] The inversion unit (161) can be configured with logic gates suitable for the timing characteristics of the input driving signals (GCLK, MUX). Specifically, when the driving signals (GCLK, MUX) are multiple pulse signals (clock signals), the inversion unit (161) can be configured with logic gates suitable for generating the correct phase inversion signal (GCLK', MUX') depending on whether the pulses overlap or not.

[0080] In this way, to apply different logical operations according to the timing characteristics of the driving signals (GCLK, MUX), the compensation unit (160) may include a judgment unit (162). The judgment unit (162) may be configured to determine whether the pulses overlap or not when the input driving signals (GCLK, MUX) are pulse signals, and to output a corresponding signal.

[0081] The phase compensation unit (163) can compensate for the phase delay of the phase inversion signal (GCLK', MUX') output from the inversion unit (161). The phase inversion signal (GCLK', MUX') output from the inversion unit (161) has a certain phase delay with respect to the driving signal (GCLK, MUX) while passing through the signal processing stage inside the inversion unit (161). The phase compensation unit (163) can match the phases of the driving signal (GCLK, MUX) and the phase inversion signal (GCLK', MUX') by delaying the phase of the driving signal (GCLK, MUX) by a preset time and outputting it by the amount of the phase delay occurring in the inversion unit (161).

[0082] As described above, since the phase of the phase inversion signal (GCLK', MUX') output from the inversion unit (161) and the phase compensation signal (CGCLK, CMUX) output from the phase compensation unit (163) are matched, the EMI noise generated by the driving signal (GCLK, MUX) can be effectively eliminated by the field cancellation effect of the phase inversion signal.

[0083] In one embodiment, the compensation unit (160) may further include an output buffer (164). The output buffer (164) outputs the signal output from the inversion unit (161) and the phase compensation unit (163) to the pixel array (AA).

[0084] An output buffer (164) is provided to prevent the magnitude of the original signal from being attenuated due to an increase in load caused by the inversion unit (161) and the phase compensation unit (163). The output buffer (164) can stabilize the signal output from the inversion unit (161) and the phase compensation unit (163) and amplify it by a preset gain to output it. Depending on the implementation, the output buffer (164) may be omitted.

[0085] The phase inversion signal generated in the inversion unit (161) can be output as a noise compensation signal through the output buffer (164) to the compensation GIP (195') and / or compensation multiplexer array (121') shown in FIG. 4. The phase-delayed driving signal (phase compensation signal) through the phase compensation unit (163) can be output to the GIP (195) and multiplexer array (121) through the output buffer (164).

[0087] Figure 6 is a drawing showing an example in which a compensation unit is mounted on a display panel.

[0088] Referring to FIG. 6, the compensation unit (160) is mounted on the display panel (100). The compensation unit (160) is connected to the level shifter (140) and the timing control unit (130) as shown in FIG. 2 through control lines (G1, G2, EM, MUX) formed on the COF (190b). Additionally, the compensation unit (160) is further connected to the GIP (195) and the multiplexer array (141) through control lines (G1, G2, EM, MUX) formed on the display panel (100).

[0089] The compensation unit (160) may include an inversion unit (161) and a phase compensation unit (163) connected to control lines (G1, G2, EM, MUX). In one embodiment, the compensation unit (160) may include a pair of inversion units (161) and phase compensation units (163) connected to each control line (G1, G2, EM, MUX). Accordingly, the compensation unit (160) can generate independent noise compensation signals suitable for the characteristics of the clock signal applied to each control line (G1, G2, EM, MUX).

[0090] Although the city is omitted in FIG. 6, the judgment unit (162) and output buffer (164) described with reference to FIG. 5 may be further mounted on the display panel (100).

[0092] FIG. 7 is a circuit diagram showing an embodiment of an inversion unit. FIG. 8 is a timing diagram showing an embodiment of a non-overlapping clock signal. In FIG. 7, the illustration of the phase compensation unit is omitted to more explicitly explain various embodiments of the inversion unit (261) in the compensation unit according to an embodiment.

[0093] Referring to FIG. 7, the inversion unit (261) is mounted on the display panel (200). The inversion unit (261) receives a driving signal through control lines (G1, G2, EM, MUX) formed on the COF (290b). The driving signal may be a gate clock signal (GCLK) applied through the control lines (G1, G2, EM) and a multiplexer control signal (MUX) applied through the control line (MUX).

[0094] In one embodiment, the driving signal (e.g., the multiplexer control signal (MUX)) may include n pulse signals (three in FIG. 7) as shown in FIG. 8. Here, the pulse signals may be non-overlapping signals in which the pulses do not overlap each other. The inversion unit (261) may include a logic gate for generating a phase-inverted signal (GCLK', MUX') by inverting the phase of the gate clock signal (GCLK) and the multiplexer control signal (MUX) composed of non-overlapping signals.

[0095] In one embodiment, the inversion unit (261) may include at least one NAND gate for inverting the phase of the gate clock signal (GCLK). In this embodiment, the inversion unit (261) may be an N:1 structure that receives n pulse signals constituting the gate clock signal (GCLK) and logically synthesizes them to output a single phase-inverted signal.

[0096] In one embodiment, the inversion unit (261) may include at least one NOT gate for inverting the phase of the multiplexer control signal (MUX). In this embodiment, the inversion unit (261) may be a 1:1 structure that independently inverts each of the n pulse signals constituting the multiplexer control signal (MUX) to output n phase-inverted signals.

[0098] FIG. 9 is a circuit diagram showing another embodiment of the inversion unit. FIG. 10 is a timing diagram showing one embodiment of the superimposed clock signal. In FIG. 9, the illustration of the phase compensation unit is omitted to more explicitly explain various embodiments of the inversion unit (361) in the compensation unit according to one embodiment.

[0099] Compared to the embodiments of FIGS. 7 and 8, the n (three in FIG. 10) pulse signals in this embodiment may be superimposed signals in which the pulses overlap each other, as shown in FIG. 10. For example, the multiplexer control signal (MUX) may be a superimposed signal as shown in FIG. 10.

[0100] In the case of a superimposed signal, the inversion unit (361) may include at least one XOR gate for inverting the phase of the multiplexer control signal (MUX). Even when pulses are superimposed through the XOR gate, phase-inverted pulses corresponding to each pulse can be correctly generated as shown in FIG. 10.

[0101] As described above, the inversion unit (361) may be composed of different logic gates depending on the timing characteristics of the driving signal, that is, whether the driving signal is a superposition signal or a non-superposition signal. Below, an embodiment is described in which a phase-inverted signal can be generated in a single inversion unit (361) by considering the timing characteristics of the driving signal.

[0103] FIG. 11 is a circuit diagram showing the connection relationship between the inversion unit and the judgment unit. FIG. 12 is a circuit diagram showing an example of the judgment unit.

[0104] Referring to FIG. 11, the compensation unit (460) includes a judgment unit (462) that determines the timing characteristics of a driving signal and an inversion unit (461) that selectively outputs a phase inversion signal generated by one of a plurality of logic gates in response to a signal output from the judgment unit (462). This compensation unit (460) may be, for example, a compensation unit (460) for generating a phase inversion signal of a multiplexer control signal (MUX).

[0105] The judgment unit (462) is configured to output a first signal (e.g., a logic high signal) when the driving signal is a superposition signal and to output a second signal (e.g., a logic low signal) when the driving signal is a non-superposition signal.

[0106] For example, the judgment unit (462) may include a first logic gate (4621) and a second logic gate (4622) as illustrated in FIG. 12. The first logic gate (4621) outputs a logic high signal (or logic low signal) when any two of the multiple pulse signals (MUX1 to MUX3) constituting the multiple control signal (MUX) have the same voltage level. Multiple first logic gates (4621) may be provided so as to select all possible combinations of the pulse signals (MUX1 to MUX3) constituting the multiple control signal (MUX) and perform a logic operation. When the multiple control signal (MUX) has a gate low voltage pulse, the first logic gate (4621) may be configured as a NOR gate.

[0107] The second logic gate (4622) outputs a logic high signal (or a logic low signal) when all signals output from the first logic gate (4621) are logic high signals. That is, the second logic gate (4622) outputs a logic high signal when the pulse signals (MUX1 to MUX3) are superimposed signals having the same voltage level at any given time. When the pulse signals (MUX1 to MUX3) are non-superimposed signals having no same voltage level at any given time, the second logic gate (4622) outputs a logic low signal. In one embodiment, the second logic gate (4622) may be configured as an AND gate.

[0108] In another embodiment, the second logic gate (4622) may be configured as an OR gate. In this embodiment, the second logic gate (4622) may output a logic high signal by determining that at least two of the pulse signals (MUX1 to MUX3) have the same voltage level at any given time as a superposition signal.

[0109] The inversion unit (461) is configured to selectively output a phase inversion signal generated by any one of a plurality of logic gates in response to a signal output from the judgment unit (462).

[0110] For example, the inversion unit (461) includes a NOR gate and an XOR gate, each of which outputs a phase-inverted signal of the multiplexer control signal (MUX). Different types of switching transistors (TFT1, TFT2) are connected to the output terminals of each logic gate. For example, a P-type switching transistor (TFT1) may be connected to the output terminal of the NOR gate, and an N-type switching transistor (TFT2) may be connected to the output terminal of the XOR gate.

[0111] The gate electrodes of the switching transistors (TFT1, TFT2) are connected to the output terminal of the judgment unit (462). The switching transistors (TFT1, TFT2) are turned on or turned off in response to a signal output from the judgment unit (462).

[0112] When a logic high signal is output from the judgment unit (462) (i.e., when the multiplexer control signal (MUX) is a superposition signal), the P-type switching transistor (TFT1) is turned off and the N-type switching transistor (TFT2) is turned on. Accordingly, a phase inversion signal generated by an XOR gate is output. Conversely, when a logic low signal is output from the judgment unit (462) (i.e., when the multiplexer control signal (MUX) is a non-superposition signal), the P-type switching transistor (TFT1) is turned on and the N-type switching transistor (TFT2) is turned off. Accordingly, a phase inversion signal generated by a NOR gate is output.

[0114] FIG. 13 is a circuit diagram showing one embodiment of a phase compensation unit. FIG. 14 is a timing diagram showing one embodiment of a phase compensation signal.

[0115] Referring to FIG. 13, a phase compensation unit (563) according to one embodiment includes a resistor (R) and a transistor (TFT) connected in series between a gate high voltage (VGH) and a gate low voltage (VGL). In the illustrated embodiment, the resistor (R) is shown as being connected between the gate high voltage (VGH) and the transistor (TFT), but in other embodiments, the resistor (R) may be connected between the transistor (TFT) and the gate low voltage (VGL).

[0116] The gate electrode of the transistor (TFT) receives a driving signal. In the illustrated embodiment, the gate electrode of the transistor (TFT) receives a gate clock signal (GCLK). The output terminal of the phase compensation unit (563) is connected between the resistor and the transistor (TFT).

[0117] When the gate clock signal (GCLK) is at the gate high voltage, the transistor (TFT) is turned off, and the gate high voltage (VGH) is output to the output terminal via the resistor (R). Also, when the gate clock signal (GCLK) is at the gate low voltage, the transistor (TFT) is turned on, and the gate low voltage (VGL) is output to the output terminal.

[0118] That is, as illustrated in FIG. 14, the phase compensation signals (CGCLK1~CGCLK4) output from the phase compensation unit (563) follow the waveform of the original signal, the gate clock signals (GCLK1~GCLK4). However, because an on / off delay time occurs depending on the operating characteristics of the circuit in which the transistor (TFT) and the resistor (R) are connected in series, the phase compensation signals (CGCLK1~CGCLK4) are delayed in phase by an arbitrary time (Δt) compared to the gate clock signals (GCLK1~GCLK4).

[0119] If the delay characteristic of the transistor (TFT) of the phase compensation unit (563) is designed to correspond to the response delay characteristic of the logic gate provided in the inversion units (161, 261, 361, 461) described above, the timing of the phase delay signal (CGCLK1~CGCLK4) output from the phase compensation unit (563) and the phase inversion signal (GCLK') output from the inversion units (161, 261, 361, 461) can be matched.

[0121] FIG. 15 is a circuit diagram showing another embodiment of the phase compensation unit.

[0122] Referring to FIG. 15, the phase compensation unit (663) according to another embodiment, compared with the embodiment of FIG. 13, is configured as a two-stage structure further comprising a second resistor (R2) and a second transistor (TFT2) connected in series between the gate high voltage (VGH) and the gate low voltage (VGL). The gate electrode of the second transistor (TFT2) is connected to an output terminal between the first resistor (R1) and the first transistor (TFT1). An output terminal of the phase compensation unit (663) is connected between the second resistor (R2) and the second transistor (TFT2).

[0123] The second stage, comprising a second resistor (R2) and a second transistor (TFT2), has the same configuration as the first stage, comprising a first resistor (R1) and a first transistor (TFT1). Accordingly, the phase compensation signal (CGCLK) output in this embodiment has the same waveform as the original signal (GCLK) as described in the embodiment of FIG. 13. However, in this embodiment, longer turn-on and turn-off delay times may occur due to the two transistors (TFT1, TFT2) provided in each of the two stages. That is, the phase compensation signal (CGCLK) according to this embodiment has a larger phase delay compared to the embodiment of FIG. 13.

[0124] In this way, by adjusting the number of stages constituting the phase compensation unit (663), the magnitude of the phase delay of the phase compensation signal (CGCLK) output from the phase compensation unit (663) can be easily controlled.

[0126] FIG. 16 is a circuit diagram showing one embodiment of an output buffer.

[0127] Referring to FIG. 16, an output buffer (764) according to one embodiment includes a resistor (R) and a transistor (TFT) connected in series between a gate high voltage (VGH) and a gate low voltage (VGL). The gate electrode of the transistor (TFT) receives a driving signal. For example, the gate electrode of the transistor (TFT) receives gate clock signals (GCLK1 to GCLK4) and a phase inversion signal (GCLK') output from an inversion unit (not shown). In one embodiment, the gate clock signals (GCLK1 to GCLK4) may be clock signals whose phase is delayed by a phase compensation unit (not shown). The output terminal of the output buffer (764) is connected between the resistor and the transistor (TFT).

[0128] The transistors (TFTs) are turned off or turned on in response to a driving signal. When the transistor (TFT) is turned on, the gate low voltage (VGL) is output to the output terminal, and when the transistor (TFT) is turned off, the gate high voltage (VGH) is output to the output terminal.

[0129] This output buffer (764) converts a signal with the same waveform as the original signal into a gate high voltage (VGH) and a gate low voltage (VGL) and outputs it. That is, the output buffer (764) can amplify and stabilize a driving signal, whose magnitude has been attenuated due to increased load caused by an inversion unit and a phase compensation unit placed in the previous stage, back to the original required magnitude and output it.

[0131] FIG. 17 is a graph showing the noise improvement effect according to an embodiment of the present invention.

[0132] Referring to FIG. 17, compared to a phase cancellation method (a) that uses a separate noise compensation signal provided externally but does not consider the delay of the phase inversion signal, the average peak noise is significantly reduced in a method (b) in which the display panel itself generates and provides a noise compensation signal that considers the phase delay according to the embodiments described above.

[0133] In other words, according to the embodiments described above, EMI noise generated in the display panel can be effectively improved. The embodiments described above reduce component costs by reducing the number of wires and pins, and can be applied to various models of display devices regardless of timing changes of the GIP or multiplexer array.

[0135] A person skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0136] 1: Display device 100: Display panel 110: Gate drive unit 120: Data driver 121: Multiplexer Array 130: Timing control unit 140: Level Shifter 150: Light-emitting driving unit 160: Compensation signal generator

Claims

Claim 1 A display device comprising: a display panel including a pixel array and a bezel area surrounding the pixel array; a display panel driving circuit that outputs a driving signal for driving the display panel; and a compensation unit that compensates for noise generated by the driving signal in the display panel or the display panel driving circuit, wherein the compensation unit includes: an inversion unit that inverts the phase of the driving signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel; and a phase compensation unit that delays the phase of the driving signal by an arbitrary amount of time so that the phases of the driving signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel as a phase compensation signal, wherein the phase compensation unit includes a resistor and a transistor connected in series and delays the phase of the driving signal by an amount of time determined by the on / off delay time of the transistor. Claim 2 A display device according to claim 1, wherein the display panel driving circuit comprises: a GIP (Gate-In-Panel) mounted in the bezel area of ​​the display panel and including a gate driving unit and a light-emitting driving unit; a multiplexer array in the bezel area of ​​the display panel; and a level shifter that transmits the driving signal to the gate driving unit, the light-emitting driving unit and the multiplexer array, and the compensation unit is mounted in the bezel area of ​​the display panel and disposed adjacent to the GIP and the multiplexer array. Claim 3 A display device according to claim 2, further comprising: a compensation GIP disposed adjacent to the GIP and applying a signal output from the compensation unit to the pixel array; and a compensation multiplexer array disposed adjacent to the multiplexer array and applying a signal output from the compensation unit to the pixel array. Claim 4 A display device according to claim 1, wherein the driving signal is composed of n (n is a natural number) pulse signals, and the inversion unit includes at least one logic gate that inverts the phase of the n pulse signals and outputs it. Claim 5 In paragraph 4, the inversion unit comprises at least one of a NAND gate and an XOR gate that logically synthesizes the n pulse signals to output a phase-inverted signal, in a display device. Claim 6 In claim 5, the compensation unit further includes a determination unit that outputs a first signal if the pulses of the n pulse signals overlap each other and outputs a second signal having a different level from the first signal if they do not overlap and are non-overlapping signals, and the inversion unit outputs the output signal of the XOR gate as the phase inversion signal in response to the first signal and outputs the output signal of the NAND gate as the phase inversion signal in response to the second signal. Claim 7 In paragraph 4, the inversion unit comprises n NOT gates that output a phase inversion signal for each of the n pulse signals, a display device. Claim 8 A display device according to claim 1, wherein the phase compensation unit comprises the resistor and the transistor connected in series between the gate high voltage and the gate low voltage, the transistor being turned on and turned off by the driving signal, and the output terminal of the phase compensation unit being connected between the resistor and the transistor. Claim 9 In claim 8, the phase compensation unit outputs a phase compensation signal having the same waveform as the driving signal according to the on / off delay time of the transistor, but delayed by a time determined by the on / off delay time, a display device. Claim 10 A display device according to claim 1, wherein the compensation unit further comprises an output buffer that amplifies a signal output from the inversion unit and the phase compensation unit and outputs it to the pixel array. Claim 11 A display device according to claim 1, wherein in the display panel, electromagnetic interference (EMI) noise generated by the phase compensation signal is eliminated by the field cancellation effect of the phase inversion signal. Claim 12 A display device comprising: a display panel including a pixel array and a bezel area surrounding the pixel array; a gate driver and a light-emitting driver that respectively apply a gate signal and a light-emitting signal to the pixels; a level shifter that applies a gate clock signal to the gate driver and the light-emitting driver; and a compensation unit that compensates for noise generated by the gate clock signal in the display panel, wherein the compensation unit includes: an inversion unit that inverts the phase of the gate clock signal to generate a phase-inverted signal and outputs the phase-inverted signal to the display panel; and a phase compensation unit that delays the phase of the gate clock signal by an arbitrary amount of time so that the phases of the gate clock signal and the phase-inverted signal are matched and outputs the phase compensation signal to the display panel as a phase compensation signal, wherein the phase compensation unit includes a resistor and a transistor connected in series and delays the phase of the gate clock signal by a amount of time determined by the on / off delay time of the transistor. Claim 13 In claim 12, the inversion unit comprises a NAND gate that logically synthesizes n pulse signals constituting the gate clock signal to output a single phase-inverted signal, a display device. Claim 14 A display device comprising: a display panel including a pixel array and a bezel area surrounding the pixel array; a multiplexer array for applying a data signal to the pixels; a level shifter for applying a multiplexer array to a multiplexer array; and a compensation unit for compensating for noise generated by the multiplexer control signal in the display panel, wherein the compensation unit comprises: an inversion unit that inverts the phase of the multiplexer control signal to generate a phase inversion signal and outputs the phase inversion signal to the display panel; and a phase compensation unit that delays the phase of the multiplexer control signal by an arbitrary amount of time so that the phases of the multiplexer control signal and the phase inversion signal are matched and outputs the phase compensation signal to the display panel as a phase compensation signal, wherein the phase compensation unit comprises a resistor and a transistor connected in series and delays the phase of the multiplexer control signal by an amount of time determined by the on / off delay time of the transistor. Claim 15 In claim 14, the inversion unit comprises an XOR gate that logically synthesizes n pulse signals constituting the multiplex control signal to output a single phase inversion signal, a display device.

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