Semiconductor devices and method for manufacturing semiconductor devices

The semiconductor device design addresses reliability issues by using a separation structure with varying hardness and density to facilitate stable contact structure formation, enhancing the device's performance and integrity.

KR103014308B1Active Publication Date: 2026-09-04SAMSUNG ELECTRONICS CO LTD
7 Cites 0 Cited by

Patent Information

Application Number
KR1020210039595
Authority / Receiving Office
KR · KR
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-03-26
Publication Date
2026-09-04
Estimated Expiration
2041-03-26

AI Technical Summary

Technical Problem

The challenge in manufacturing semiconductor devices with fine patterns and three-dimensional channel structures is to enhance the reliability of the devices while maintaining stable contact structures during the manufacturing process.

Method used

A semiconductor device design featuring gate structures with a gate capping layer and a separation structure of differing hardness and density, allowing for stable formation of contact structures through a planarization process that removes the intermediate insulating layer, ensuring the separation structure's upper surface is lower than the gate capping layer.

Benefits of technology

This design enhances the reliability of semiconductor devices by stabilizing the formation of contact structures, improving the overall performance and integrity of the device.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

A semiconductor device according to an embodiment of the present invention comprises: an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from each other perpendicularly on the active region; gate structures extending in a second direction intersecting the active region and the plurality of channel layers on the substrate, each including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on the upper surface of the gate electrode; source / drain regions disposed on the active region at least one side of each of the gate structures and in contact with the plurality of channel layers; a separation structure extending in the second direction intersecting the active region on the substrate and disposed between the source / drain regions adjacent to each other; and contact structures in contact with the source / drain regions on the source / drain regions, wherein the upper surface of the separation structure is disposed at a height lower than the upper surface of the gate capping layer in a direction perpendicular to the upper surface of the substrate.
Need to check novelty before this filing date? Find Prior Art