Lamination inductor
The lamination inductor design addresses the issue of stray capacitance by strategically positioning the loop conductor layer relative to the outer terminal electrodes, enhancing self-resonant frequency and maintaining a higher Q-value in high frequency regions through optimized gap dimensions.
Patent Information
- Application Number
- US17/233321
- Authority / Receiving Office
- US · United States
- Patent Type
- Patents(United States)
- Current Assignee / Owner
- Priority Date
- 2016-05-31
- Filing Date
- 2021-04-16
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2036-10-04
AI Technical Summary
Lamination inductors with larger inside diameters of the coil conductor experience increased stray capacitance between the outer terminal electrodes and the coil conductor, leading to a lower self-resonant frequency and decreased Q-value in high frequency regions.
The design includes a lamination inductor with a coil conductor having a helically extended shape, where the loop conductor layer's outer edge is positioned to create a specific gap with the outer terminal electrodes, with oblique side portions and a lower side portion of defined lengths to minimize stray capacitance, ensuring the inside diameter is maximized without compromising self-resonant frequency.
This configuration effectively suppresses stray capacitance, increasing the self-resonant frequency and maintaining a higher Q-value in high frequency regions by optimizing the dimensions of the intervals between the outer terminal electrodes and the loop conductor layer.