Pixel drive circuit and drive method therefor, and display panel and display apparatus

Abstract

A pixel drive circuit and a drive method therefor, and a display panel and a display apparatus. The pixel drive circuit comprises a drive circuit (10) and a first control circuit (20), wherein the drive circuit (10) is connected to a first node, a second node and a third node, and the drive circuit (10) is used for providing, in response to a voltage signal of the first node, a drive current by using a voltage difference between the second node and the third node; and the first control circuit (20) is connected to the second node, a first power source end and an enable signal end, and the first control circuit (20) is used for transmitting a voltage signal of the first power source end to the second node in response to a signal of the enable signal end. By means of adjusting a conduction duration of an enable signal, the duration of providing a voltage signal for a second node by a first power-source end is adjusted by using the first control circuit (20), such that a pixel drive circuit has a PWM function, the display uniformity of a display panel at a low grayscale can be improved, and the display image quality is improved.

Description

Pixel driving circuit and its driving method, display panel, display device

[0001] [Corrected according to Rule 91, 2010.2023] Cross-reference

[0002] [Amended 20.10.2023 in accordance with Rule 91] This disclosure claims priority to Chinese Patent Application No. 202211139247.2, filed on September 19, 2022, entitled “Pixel Driving Circuit and Driving Method Thereof, Display Panel, Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] [Revised according to Rule 91, 20.10.2023] This disclosure relates to the field of display technology, and more specifically, to a pixel driving circuit and driving method thereof, a display panel, and a display device. Background Technology

[0004] [Corrected according to Rule 91, October 20, 2023] Organic Light Emitting Diode (OLED) is an active-matrix display device with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, and flexibility. Currently, OLED displays are increasingly widely used. However, a problem with OLED displays is the poor uniformity of low grayscale display.

[0005] [Revised according to Rule 91, 20.10.2023] It should be noted that the information disclosed in the above background section is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0006] [Revised according to Article 91, October 2023] Summary of the Invention

[0007] [Revised according to Article 91, 20.10.2023] The purpose of this disclosure is to overcome the shortcomings of the prior art described above and to provide a pixel driving circuit and driving method thereof, a display panel, and a display device.

[0008] [Correction 20.10.2023 according to Rule 91] According to one aspect of this disclosure, a pixel driving circuit is provided, comprising: a driving circuit connected to a first node, a second node, and a third node, the driving circuit being configured to provide a driving current using the voltage difference between the second node and the third node in response to a voltage signal of the first node; and a first control circuit connected to the second node, a first power supply terminal, and an enable signal terminal, the first control circuit being configured to transmit a voltage signal from the first power supply terminal to the second node in response to a signal from the enable signal terminal.

[0009] [Revised according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the conduction level of the drive circuit has the same polarity as the conduction level of the first control circuit.

[0010] [Revised according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the driving circuit includes: a driving transistor, a first terminal connected to the second node, a second terminal connected to the third node, and a gate connected to the first node, the driving transistor being used to provide a driving current by utilizing the voltage difference between the second node and the third node in response to a voltage signal from the first node; the first control circuit includes: a fifth transistor, a first terminal connected to the second node, a second terminal connected to the first power supply terminal, and a gate connected to the enable signal terminal, the fifth transistor being used to transmit the voltage signal from the first power supply terminal to the second node in response to a signal from the enable signal terminal.

[0011] [Revised according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, both the driving transistor and the fifth transistor are N-type transistors.

[0012] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the device further includes: a first reset circuit connected to the third node, a third gate signal terminal, and a first initial signal terminal, the first reset circuit being configured to transmit a signal from the first initial signal terminal to the third node in response to a signal from the third gate signal terminal; a second reset circuit connected to the first node, a second initial signal terminal, and a second gate signal terminal, the second reset circuit being configured to transmit a signal from the second initial signal terminal to the first node in response to a signal from the second gate signal terminal; a data writing circuit connected to the first node, a first gate signal terminal, and a data signal terminal, the data writing circuit being configured to transmit a signal from the data signal terminal to the first node in response to a signal from the first gate signal terminal; and a coupling circuit connected between the first node and the third node.

[0013] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the first reset circuit includes: a fourth transistor, with a first terminal connected to a first initial signal terminal, a second terminal connected to the third node, and a gate connected to a third gate signal terminal, the fourth transistor being used to transmit a signal from the first initial signal terminal to the third node in response to a signal from the third gate signal terminal; the second reset circuit includes: a second transistor, with a first terminal connected to the second initial signal terminal, a second terminal connected to the first node, and a gate connected to a second gate signal terminal, the second transistor being used to transmit a signal from the second initial signal terminal to the first node in response to a signal from the second gate signal terminal; the data writing circuit includes: a first transistor, with a first terminal connected to the data signal terminal, a second terminal connected to the first node, and a gate connected to the first gate signal terminal, the first transistor being used to transmit a signal from the data signal terminal to the first node in response to a signal from the first gate signal terminal; the coupling circuit includes: a storage capacitor, with a first terminal connected to the first node and a second terminal connected to the third node.

[0014] [Revised according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the fourth transistor, the second transistor, and the first transistor are all N-type transistors.

[0015] [Corrected according to Rule 91 20.10.2023] According to a second aspect of this disclosure, a pixel driving circuit driving method is also provided for driving the pixel driving circuit described in any embodiment of this disclosure. The method includes: during the light emission stage, providing a conduction level signal with a preset duty cycle to the enable signal terminal to control the conduction of the first control circuit for a preset duration, using the first control circuit to transmit a signal from the first power supply terminal to the second node, and controlling the driving circuit to provide a driving current using the voltage difference between the second node and the third node.

[0016] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the method includes: in an initialization phase, transmitting a signal from a first initial signal terminal to the third node using a first reset circuit, and transmitting a signal from a second initial signal terminal to a first node using a second reset circuit; in a data writing phase, transmitting a signal from a data signal terminal to the first node using the data writing circuit; and in a light-emitting phase, controlling the first control circuit to conduct for a preset duration, transmitting a signal from the first power supply terminal of the first control circuit to the second node, and controlling the driving circuit to provide a driving current using the voltage difference between the second node and the third node.

[0017] [Corrected according to Rule 91, 20.10.2023] According to a third aspect of this disclosure, a display panel is also provided, including a plurality of pixel driving circuits as described in any embodiment of this disclosure. The plurality of pixel driving circuits are arrayed along a first direction and a second direction. Each pixel driving circuit includes a fifth transistor and a driving transistor. The first electrode of the fifth transistor is connected to a second node, the second electrode is connected to a first power supply terminal, and the gate is connected to an enable signal terminal. The first electrode of the driving transistor is connected to the second node. The pixel driving circuit is used to drive a light-emitting unit to emit light. The display panel further includes: a substrate; an active layer located on one side of the substrate, the active layer including: a third active portion extending along the second direction in the orthographic projection of the substrate, the third active portion being used to form a channel region of the driving transistor; a fifth active portion located on one side of the third active portion, being used to form a channel region of the fifth transistor; and a fifteenth active portion connected between the third active portion and the fifth active portion, being used to form the first electrode of the driving transistor and the fifth active portion. The fifth transistor has a first electrode; a sixteenth active portion connected to the fifth active portion on the side away from the fifteenth active portion, used to form the second electrode of the fifth transistor; a third conductive layer located on the side of the active layer away from the substrate, the third conductive layer including: a first conductive portion corresponding to the third active portion, the orthographic projection of the first conductive portion on the substrate covering the orthographic projection of the third active portion on the substrate, the first conductive portion used to form the gate of the driving transistor; a first enable signal line extending along the first direction on the orthographic projection of the substrate and covering the orthographic projection of the fifth active portion on the substrate, a portion of the structure of the first enable signal line used to form the top gate of the fifth transistor; and a fourth conductive layer located on the side of the third conductive layer away from the substrate, the fourth conductive layer including: a first power line extending along the second direction on the orthographic projection of the substrate and intersecting the orthographic projection of the sixteenth active portion on the substrate, the first power line being connected to the sixteenth active portion at a corresponding position via a via.

[0018] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, the first terminal of which is connected to a first initial signal terminal, the second terminal of which is connected to a third node, and the gate of which is connected to a third gate signal terminal; the second terminal of the driving transistor is connected to the third node; the active layer further includes: a fourth active portion located on the side of the third active portion away from the fifth active portion, for forming a channel region of the fourth transistor; an eighteenth active portion connected between the fourth active portion and the third active portion, for forming the second terminal of the fourth transistor and the second terminal of the driving transistor; and a seventeenth active portion connected on the side of the fourth active portion away from the eighteenth active portion. The third conductive layer further includes: a third gate signal line extending along the first direction in the orthographic projection of the substrate and covering the orthographic projection of the fourth active portion on the substrate, wherein a portion of the structure of the third gate signal line is used to form the top gate of the fourth transistor; a first initial signal line extending along the first direction in the orthographic projection of the substrate and located on the side of the orthographic projection of the third gate signal line on the substrate away from the orthographic projection of the third active portion on the substrate; the fourth conductive layer further includes: a fourth bridging portion extending along the second direction in the orthographic projection of the substrate, wherein the fourth bridging portion connects the first initial signal line and the seventeenth active portion respectively through vias.

[0019] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor, the first electrode of the second transistor being connected to a second initial signal line, the second electrode being connected to a first node, and the gate being connected to a second gate signal line; the gate of the driving transistor is connected to the first node; the active layer further includes: a second active portion extending along the second direction in the orthographic projection of the substrate, the second active portion being used to form a channel region of the second transistor; a thirteenth active portion connected to the side of the second active portion away from the third active portion, used to form the first electrode of the second transistor; a fourteenth active portion connected to the side of the second active portion close to the third active portion, used to form the second electrode of the second transistor; the third conductive layer further includes: a second gate signal line extending along the first direction in the orthographic projection of the substrate and located at... The first enable signal line is projected onto the substrate on a side away from the projection of the third active portion onto the substrate. The projection of the second gate signal line onto the substrate covers the projection of the second active portion onto the substrate. A portion of the structure of the second gate signal line is used to form the top gate of the second transistor. The second initial signal line extends along the first direction in the projection of the second gate signal line onto the substrate. The second initial signal line is located on the side of the second gate signal line away from the first enable signal line. The fourth conductive layer further includes: a first bridging portion, which connects the fourteenth active portion and the first conductive portion through vias to connect the second electrode of the second transistor to the gate of the driving transistor; and a second bridging portion, which connects the thirteenth active portion and the second initial signal line through vias to connect the first electrode of the second transistor to the second initial signal line.

[0020] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, the first electrode of the first transistor being connected to a data signal terminal, the second electrode being connected to a first node, and the gate being connected to a first gate signal line; the active layer further includes: a first active portion for forming a channel region of the first transistor; a first eleventh active portion connected to one side of the first active portion for forming a first electrode of the first transistor; a twelfth active portion connected to the other side of the first active portion for forming a second electrode of the first transistor, the twelfth active portion being connected to the first bridging portion through a via; the third conductive layer further includes: a first gate signal line extending along the first direction in the orthographic projection of the substrate and covering the orthographic projection of the first active portion on the substrate, the first gate signal line being located between the second gate signal line and the first enable signal line; the fourth conductive layer further includes: a data signal line extending along the second direction in the orthographic projection of the substrate and located on the side of the orthographic projection of the third active portion on the substrate away from the orthographic projection of the first power line on the substrate, the data signal line being connected to the eleventh active portion through a via.

[0021] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a storage capacitor, the first terminal of which is connected to the first node, and the second terminal of which is connected to the third node; the first conductive portion includes a first main body portion and a first extension portion, the first main body portion extending along the second direction in the orthographic projection of the substrate and covering the orthographic projection of the third active portion on the substrate, the first extension portion being connected to the side of the first main body portion away from the first power line, and the first extension portion extending along the first direction in the orthographic projection of the substrate; the display panel further includes: a first conductive layer located between the substrate and the active layer, the first conductive layer including: a second conductive portion corresponding to the first conductive portion, the second conductive portion being used to form the first terminal of the storage capacitor and connected to the first extension portion through a via; a second conductive layer located between the first conductive layer and the active layer, the first conductive layer being... The second conductive layer includes: a third conductive portion for forming the second electrode of the storage capacitor; the third conductive portion includes a second main body portion and a second additional portion; the second main body portion extends along the second direction in the orthographic projection of the substrate and overlaps with the orthographic projection of the second conductive portion in the substrate; the second additional portion is located between the orthographic projection of the second main body portion in the substrate and the orthographic projection of the third gate signal line in the substrate in the orthographic projection of the substrate. The fourth conductive layer further includes: a third bridging portion extending along the first direction in the orthographic projection of the substrate; the third bridging portion connects the second additional portion and the eighteenth active portion respectively through vias; wherein the second main body portion has an opening for exposing a portion of the second conductive portion; the orthographic projection of the first additional portion in the substrate is located within the orthographic projection of the opening in the substrate; the portion of the second conductive portion facing the opening is connected to the first additional portion through a via.

[0022] [Corrected according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, the second conductive layer further includes: a first gate line extending along the first direction in the orthographic projection of the substrate and overlapping with a portion of the orthographic projection of the first gate signal line on the substrate, the orthographic projection of the first gate line on the substrate covering the orthographic projection of the first active portion on the substrate, and a portion of the structure of the first gate line being used to form the bottom gate of the first transistor; a second gate line extending along the first direction in the orthographic projection of the substrate and overlapping with a portion of the orthographic projection of the second gate signal line on the substrate, the orthographic projection of the second gate line on the substrate covering the orthographic projection of the second active portion on the substrate, and a portion of the structure of the second gate line being used to form the bottom gate of the second transistor; and a third gate line extending along the first direction in the orthographic projection of the substrate and overlapping with a portion of the orthographic projection of the third gate signal line on the substrate, the orthographic projection of the third gate line on the substrate covering the orthographic projection of the fourth active portion on the substrate, and a portion of the structure of the third gate line being used to form the bottom gate of the fourth transistor.

[0023] [Corrected according to Rule 91 20.10.2023] In an exemplary embodiment of this disclosure, the first direction is a row direction and the second direction is a column direction; the display panel includes a plurality of repeating units distributed along the row and column directions, the repeating unit includes two adjacent pixel driving circuits in the row direction, and each column of pixel driving circuits is provided with a first power line; in the same repeating unit, the two first power lines are connected.

[0024] [Revised according to Rule 91, 20.10.2023] In an exemplary embodiment of this disclosure, two pixel driving circuits that are adjacent in the row direction in the same repeating unit are mirror images of each other.

[0025] [Revised according to Rule 91, 20.10.2023] According to a fourth aspect of this disclosure, a display device is also provided, including the display panel described in any embodiment of this disclosure.

[0026] [Revised according to Rule 91, 20.10.2023] The pixel driving circuit provided in this disclosure provides a first control circuit between the second node and the first power supply terminal. The first control circuit can provide a voltage signal from the first power supply terminal to the second node in response to the signal of the enable signal terminal. Thus, the duration of the voltage signal provided from the first power supply terminal to the second node can be adjusted by adjusting the conduction duration of the enable signal, so that the pixel driving circuit has a PWM function, which can improve the display uniformity of the display panel at low gray levels and improve the display quality.

[0027] [Revised according to Rule 91 20.10.2023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] [Revised according to Rule 91, October 20, 2023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and that other drawings can be obtained by those skilled in the art from these drawings without inventive effort.

[0029] [Correction 20.10.2023 according to Rule 91] Figure 1 is a schematic diagram of the structure of a pixel driving circuit according to an embodiment of the present disclosure;

[0030] [Corrected according to Rule 91 20.10.2023] Figure 2 is a timing diagram of each node of the pixel driving circuit in Figure 1;

[0031] [Corrected according to Rule 91 20.10.2023] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in the reset phase according to an embodiment of the present disclosure;

[0032] [Corrected according to Rule 91 20.10.2023] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in the data writing stage according to an embodiment of the present disclosure;

[0033] [Corrected according to Rule 91 20.10.2023] Figure 5 is an equivalent circuit diagram of a pixel driving circuit in the light-emitting stage according to an embodiment of the present disclosure;

[0034] [Correction 20.10.2023 based on Rule 91] Figure 6 is a structural layout of a display panel according to an embodiment of the present disclosure;

[0035] [Corrected according to Rule 91, 20.10.2023] Figure 7 is the structural layout of the active layer in Figure 6;

[0036] [Corrected according to Rule 91, 20.10.2023] Figure 8 is a structural layout of the third conductive layer in Figure 6;

[0037] [Corrected according to Rule 91, 20.10.2023] Figure 9 is a structural layout of the fourth conductive layer in Figure 8;

[0038] [Corrected according to Rule 91, 20.10.2023] Figure 10 is a structural layout of the first conductive layer in Figure 6;

[0039] [Corrected according to Rule 91, 20.10.2023] Figure 11 is a structural layout of the second conductive layer in Figure 6;

[0040] [Correction 20.10.2023 based on Rule 91] Figure 12 is a structural layout of a display panel according to another embodiment of this disclosure;

[0041] [Corrected according to Rule 91 20.10.2023] Figure 13 is a cross-sectional view along the AA direction in Figure 6. Detailed Implementation

[0042] [Correction 20.10.2023 based on Rule 91] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0043] [Correction based on Rule 91, 20.10.2023] Although relative terms such as “upper” and “lower” are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used in this specification only for convenience, such as the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped so that it is upside down, the component described as “upper” will become the component described as “lower.” When a structure is “upper” than another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” mounted on the other structure, or that the structure is “indirectly” mounted on the other structure through another structure.

[0044] [Corrected according to Rule 91 20.10.2023] The terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0045] [Corrected according to Rule 91, 20.10.2023] Figure 1 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in Figure 1, the pixel driving circuit may include a driving circuit 10 and a first control circuit 20. The driving circuit 10 is connected to a first node N1, a second node N2 and a third node N3. The driving circuit 10 can be used to provide a driving current by utilizing the voltage difference between the second node N2 and the third node N3 in response to the voltage signal of the first node N1. The first control circuit 20 is connected to the second node N2, a first power supply terminal VDD and an enable signal terminal EM. The first control circuit 20 can be used to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM.

[0046] [Correction 20.10.2023 according to Rule 91] The pixel driving circuit provided in this disclosure provides a first control circuit 20 between the second node N2 and the first power supply terminal VDD. The first control circuit 20 can provide a voltage signal from the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM. Thus, the duration of the voltage signal provided from the first power supply terminal VDD to the second node N2 can be adjusted by adjusting the conduction duration of the enable signal, so that the pixel driving circuit has a PWM function, which can improve the display uniformity of the display panel at low gray levels and improve the display quality.

[0047] [Correction 20.10.2023 based on Rule 91] The pixel driving circuit of this disclosure, having a first control circuit 20, can adjust the refresh rate of the image to be displayed by adjusting the duty cycle of the enable signal EM, thereby improving the display uniformity of the display panel. For example, if the current image to be displayed is a low grayscale display, the driver integrated circuit DIC can increase the grayscale voltage based on the grayscale voltage corresponding to the current grayscale value, i.e., use a higher grayscale voltage to display the current low grayscale image. Simultaneously, the driver integrated circuit DIC can decrease the duty cycle of the enable signal EM to reduce the refresh rate of the current image. Thus, by combining the adjustment of the grayscale voltage and the refresh rate, the display uniformity of the display panel at low grayscale levels is improved. It can be seen that the pixel driving circuit of this disclosure can control the driving current provided by the driving transistor through the first control circuit 20, providing the possibility for adjusting the driving current. It should be understood that in other embodiments, the first control circuit 20 can also be used in other ways to improve display uniformity, which will not be detailed here.

[0048] [Corrected according to Rule 91, 20.10.2023] As shown in FIG1, in an exemplary embodiment, the driving circuit 10 and the first control circuit 20 can be implemented by transistors. Exemplarily, the driving circuit 10 may include a driving transistor T3, the first terminal of which is connected to the second node N2, the second terminal of which is connected to the third node N3, and the gate of which is connected to the first node N1. The driving transistor T3 can be used to provide a driving current using the voltage difference between the second node N2 and the third node N3 in response to a voltage signal from the first node N1. The first control circuit 20 may include a fifth transistor T5, the first terminal of which is connected to the second node N2, the second terminal of which is connected to the first power supply terminal VDD, and the gate of which is connected to the enable signal terminal EM. The fifth transistor T5 can be used to transmit the voltage signal of the first power supply terminal VDD to the second node N2 in response to a signal from the enable signal terminal EM. For example, during the light-emitting stage, the fifth transistor T5 is turned on under the control of the enable signal output from the enable signal terminal EM, thereby transmitting the voltage signal of the first power supply terminal VDD to the second node N2. The driving transistor T3 is turned on under the control of the voltage signal of the first node N1, so that the driving transistor T3 can use the voltage difference between the second node N2 and the third node N3 to provide driving current to the light-emitting device connected thereto, driving the light-emitting device to emit light. In this exemplary embodiment, because there is a fifth transistor T5 between the first power supply terminal VDD and the second node N2, the duty cycle of the signal applied to the gate of the fifth transistor T5 can be adjusted. In one frame of data, the duty cycle of the conduction time of the fifth transistor T5 in one frame of data can be controlled, thereby enabling PWM adjustment of the driving current. This allows the pixel driving circuit provided in this disclosure to actively adjust the grayscale brightness of the light-emitting device, thereby improving the problem of poor uniformity of the display panel at low grayscale levels.

[0049] [Correction 20.10.2023 based on Rule 91] As shown in FIG1, in an exemplary embodiment, both the driving transistor T3 and the fifth transistor T5 can be N-type transistors. For example, they can both be N-type oxide thin-film transistors, which can reduce the leakage current effect of the first node N1 and the second node N2, thus helping to ensure the voltage stability of the aforementioned main nodes of the driving circuit 10 at low refresh frequencies. Of course, in other embodiments, the driving circuit 10 and the first control circuit 20 can also be implemented by other circuits.

[0050] [Corrected according to Rule 91, 20.10.2023] As shown in FIG1, in an exemplary embodiment, the pixel driving circuit may further include a first reset circuit 30, a second reset circuit 40, a data writing circuit 50, and a coupling circuit 60. The first reset circuit 30 is connected to a third node N3, a third gate signal terminal Gate3, and a first initial signal terminal Vinit1. The first reset circuit 30 can be used to transmit the signal of the first initial signal terminal Vinit1 to the third node N3 in response to the signal of the third gate signal terminal Gate3. The second reset circuit 40 is connected to a first node N1, a second initial signal terminal Vinit2, and a second gate signal terminal Gate2. The second reset circuit 40 can be used to transmit the signal of the second initial signal terminal Vinit2 to the first node N1 in response to the signal of the second gate signal terminal Gate2. The data writing circuit 50 is connected to a first node N1, a first gate signal terminal Gate1, and a data signal terminal Data. The data writing circuit 50 can be used to transmit the signal of the data signal terminal Data to the first node N1 in response to the signal of the first gate signal terminal Gate1. The coupling circuit 60 is connected between the first node N1 and the third node N3. The first reset circuit 30 can reset the third node N3 during the initialization phase, that is, reset the anode of the light-emitting device to eliminate the influence of the previous frame of data. The second reset circuit 40 can input the voltage of the shutdown drive circuit 10 to the first node N1 to prevent abnormal light emission of the light-emitting device. The data writing circuit 50 can write the data signal of the data signal terminal Data to the first node N1 during the data writing phase.

[0051] [Corrected according to Rule 91, 20.10.2023] Similarly, the first reset circuit 30, the second reset circuit 40, and the data writing circuit 50 described in this disclosure can all be implemented using transistors. For example, the first reset circuit 30 may include a fourth transistor T4, the first terminal of which is connected to the first initial signal terminal Vinit1, the second terminal of which is connected to the third node N3, and the gate of which is connected to the third gate signal terminal Gate3. The fourth transistor T4 can be used to transmit the signal from the first initial signal terminal Vinit1 to the third node N3 in response to the signal from the third gate signal terminal Gate3. The second reset circuit 40 may include a second transistor T2, the first terminal of which is connected to the second initial signal terminal Vinit2, and the second terminal of which is connected to the first node N1. The gate of the second transistor T2 is connected to the second gate signal terminal Gate2. The second transistor T2 can be used to transmit the signal of the second initial signal terminal Vinit2 to the first node N1 in response to the signal of the second gate signal terminal Gate2. The data writing circuit 50 may include a first transistor T1. The first terminal of the first transistor T1 is connected to the data signal terminal Data, the second terminal of the first transistor T1 is connected to the first node N1, and the gate of the first transistor T1 is connected to the first gate signal terminal Gate1. The first transistor T1 can be used to transmit the signal of the data signal terminal Data to the first node N1 in response to the signal of the first gate signal terminal Gate1. The first transistor T1, the second transistor T2, and the fourth transistor T4 can all be N-type transistors, such as N-type oxide thin-film transistors. Of course, in other embodiments, the first reset circuit 30, the second reset circuit 40, and the data writing circuit 50 may also have other circuit structures, which will not be detailed here.

[0052] [Correction 20.10.2023 according to Rule 91] As shown in FIG1, in an exemplary embodiment, the coupling circuit 60 may include a storage capacitor C, which can couple the voltage of each node at different stages.

[0053] [Corrected according to Rule 91, 20.10.2023] Figure 2 is a timing diagram of each node of the pixel driving circuit in Figure 1. In the figure, EM represents the timing of the enable signal terminal EM, Gate1 represents the timing of the first gate signal terminal Gate1, Gate2 represents the timing of the second gate signal terminal Gate2, Gate3 represents the timing of the third gate signal terminal Gate3, and Data represents the timing of the data signal terminal Data. As shown in Figure 2, the driving method of this pixel driving circuit may include: a reset stage t1, a data writing stage t2, and a light emission stage t3. The driving method of the pixel driving terminal circuit of this disclosure will be specifically described below with reference to the timing diagram.

[0054] [Corrected according to Rule 91, 20.10.2023] Figure 3 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure during the reset phase. As shown in Figure 3, during the reset phase t1, the third gate signal terminal Gate3 and the second gate signal terminal Gate2 output high levels successively, and the fourth transistor T4 and the second transistor T2 are turned on successively. The fourth transistor T4 transmits the initialization signal of the first initial signal terminal Vinit1 to the third node N3, resetting the anode of the light-emitting device. The second transistor T2 transmits the second initialization signal of the second initial signal terminal Vinit2 to the first node N1, resetting the first node N1.

[0055] [Corrected according to Rule 91, 20.10.2023] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure during the data writing stage. As shown in Figure 4, during the data writing stage t2, both the second gate signal terminal Gate2 and the third gate signal terminal Gate3 output low levels, and the fourth transistor T4 and the second transistor T2 are turned off. The first gate signal terminal Gate1 outputs a high-level signal, and the first transistor T1 is turned on, transmitting the data signal from the data signal terminal Data to the first node N1. The voltage of the first node N1 becomes Vdata, and the voltage of the third node N3 becomes V... N3 =Vinit2-Vth.

[0056] [Corrected according to Rule 91, 20.10.2023] Figure 5 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure in the light-emitting stage. As shown in Figure 5, in the light-emitting stage t3, the first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off, the enable signal terminal EM outputs a high-level signal, the fifth transistor T5 is turned on, and the voltage signal of the first power supply terminal VDD is written into the second node N2, thereby driving the transistor T3 to turn on under the action of the data signal of the first node N1. The voltage difference between the first power supply terminal VDD and the second power supply terminal VSS is used to provide driving current to the light-emitting device, driving the light-emitting device to emit light. V N1 =V Data +Voled+Vss-Vinit2+Vth, V N3 =Voled + Vss, according to the formula for the output current of the driving transistor I = (μWCox / 2L)(Vgs - Vth) 2 Where μ is the carrier mobility; Cox is the gate storage capacity per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of this disclosure, the output current I of the driving transistor is I = (μWCox / 2L)(V Data –Vinit2) 2This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0057] [Revised according to Rule 91, 20.10.2023] This disclosure also provides a display panel that may include a plurality of pixel driving circuits as described in any embodiment of this disclosure. The plurality of pixel driving circuits are arrayed along a first direction X and a second direction Y, where the first direction X may be, for example, a row direction and the second direction Y may be, for example, a column direction. Figure 6 is a structural layout of a display panel according to an embodiment of the present disclosure, Figure 7 is a structural layout of the active layer in Figure 6, Figure 8 is a structural layout of the third conductive layer in Figure 6, and Figure 9 is a structural layout of the fourth conductive layer in Figure 8. As shown in Figures 6 to 9, the display panel may include a substrate, an active layer 3, a third conductive layer 4, and a fourth conductive layer 5. The active layer 3 is located on one side of the substrate and may include a third active portion 33, a fifth active portion 35, a fifteenth active portion 315, and a sixteenth active portion 316. The third active portion 33 is used to form the channel region of the driving transistor T3; the fifth active portion 35 is used to form the channel region of the fifth transistor T5; the fifteenth active portion 315 is connected between the third active portion 33 and the fifth active portion 35 and may be used to form the first electrode of the driving transistor T3 and the first electrode of the fifth transistor T5; the sixteenth active portion 316 is connected to the side of the fifth active portion 35 away from the fifteenth active portion 315, and the tenth active portion 316 is connected to the side of the fifth active portion 35 away from the fifteenth active portion 315. The sixth active portion 316 can be used to form the second electrode of the fifth transistor T5; the third conductive layer 4 is located on the side of the active layer 3 away from the substrate. The third conductive layer 4 may include a first conductive portion 41 and a first enable signal line EM. The first conductive portion 41 is correspondingly disposed with the third active portion 33. The orthographic projection of the first conductive portion 41 on the substrate covers the orthographic projection of the third active portion 33 on the substrate. The first conductive portion 41 can be used to form the gate of the driving transistor T3. The orthographic projection of the first enable signal line EM on the substrate may extend along the first direction X and cover the orthographic projection of the fifth active portion 35 on the substrate. Part of the structure of the first enable signal line EM can be used to form the top gate of the fifth transistor T5; the fourth conductive layer 5 is located on the side of the third conductive layer 4 away from the substrate. The fourth conductive layer 5 may include a first power line Vdd. The orthographic projection of the first power line Vdd on the substrate may extend along the second direction Y. The first power line Vdd is connected to the sixteenth active portion 316 at the corresponding position through a via.

[0058] [Revised according to Rule 91, 20.10.2023] The display panel of this disclosure, by forming a fifth transistor T5, can adjust the conduction duration of the fifth transistor T5 during the light-emitting stage by adjusting the duty cycle of the first enable signal line EM, thereby adjusting the magnitude of the driving current provided by the pixel driver. This allows for active control of the pixel driver circuit during the light-emitting stage, making it possible to adjust the grayscale voltage of the image displayed on the display panel. In other words, because the display panel of this disclosure has a fifth transistor T5, it is possible to adjust the grayscale value of the displayed image during the light-emitting stage.

[0059] [Correction 20.10.2023 according to Rule 91] As shown in Figures 6 and 7, in an exemplary embodiment, the structure formed by the sequential connection of the sixteenth active part 316, the fifth active part 35, the fifteenth active part 315, and the third active part 33 can be extended along the second direction Y in the orthogonal projection of the substrate, so that the fifth transistor T5 is located on one side of the driving transistor T3 along the column direction.

[0060] [Corrected according to Rule 91 20.10.2023] It should be understood that, in this disclosure, a structure A extending along direction B means that A may include a main part and a secondary part connected to the main part, the main part being a line, line segment or strip shape, the main part extending along direction B, and the length of the main part extending along direction B being greater than the length of the secondary part extending along other directions.

[0061] [Revised according to Rule 91, 20.10.2023] This disclosure allows the active layer 3 to be made conductive by using the third conductive layer 4 as a mask. That is, the area of ​​the active layer 3 covered by the third conductive layer 4 can form the channel region of the transistor, and the area of ​​the active layer 3 not covered by the third conductive layer 4 forms a conductor structure.

[0062] [Corrected according to Rule 91 20.10.2023] The first enable signal line EM can be used to provide the enable signal terminal EM in FIG1. ​​The orthographic projection of the first enable signal line EM onto the substrate can extend along the first direction X, so that a portion of the structure of the first enable signal line EM covers the fifth active portion 35, thereby forming the channel region of the fifth transistor T5.

[0063] [Corrected according to Rule 91, 20.10.2023] As shown in Figures 6 and 7, in an exemplary embodiment, the first conductive portion 41 in the third conductive layer 4 may include a first main body portion 411 and a first extension portion 412. The orthographic projection of the first main body portion 411 onto the substrate may extend along the second direction Y and cover the orthographic projection of the third active portion 33 onto the substrate. The first main body portion 411 may be used to form the gate of the driving transistor T3. The first extension portion 412 may be connected to one side of the first main body portion 411 along the first direction X. The first extension portion 412 may be connected to the first terminal of the storage capacitor C through a via, thereby connecting the gate of the driving transistor T3 to the first terminal of the storage capacitor C.

[0064] [Corrected according to Rule 91 20.10.2023] The first power line Vdd can provide the first power terminal VDD in FIG1. ​​The first power line Vdd extends along the second direction Y in the orthographic projection of the substrate. The first power line Vdd can be connected to the sixteenth active part 316 through a via, thereby connecting the second terminal of the fifth transistor T5 to the first power terminal VDD.

[0065] [Corrected according to Rule 91 20.10.2023] It should be understood that the orthographic projection of a certain structure A onto the substrate of this disclosure covering the orthographic projection of another structure B onto the substrate can be understood as the outline of the projection of B onto the plane of the substrate being completely inside the outline of the projection of A onto the same plane.

[0066] [Corrected according to Rule 91, 20.10.2023] Furthermore, as shown in FIG6, the display panel of this disclosure may further include a first conductive layer 1 and a second conductive layer 2, wherein the substrate, the first conductive layer 1, the second conductive layer 2, the active layer 3, the third conductive layer 4, and the fourth conductive layer 5 are sequentially stacked, and an insulating layer may be disposed between the above functional layers. The first conductive layer 1 may be a first gate metal layer (Gate1 layer), the second conductive layer 2 may be a second gate metal layer (Gate2 layer), the third conductive layer 4 may be a third gate metal layer (Gate3 layer), and the fourth conductive layer 5 may be a first metal trace layer (SD1 layer). FIG10 is a structural layout diagram of the first conductive layer in FIG6, and FIG11 is a structural layout diagram of the second conductive layer in FIG6.

[0067] [Corrected according to Rule 91 20.10.2023] As shown in Figures 6 and 10, in an exemplary embodiment, the first conductive layer 1 may include a second conductive portion 12. The second conductive portion 12 may be used to form the first electrode of the storage capacitor C. The orthographic projection of the second conductive portion 12 on the substrate may cover the orthographic projection of the first addition portion 412 on the substrate, so that the second conductive portion 12 may be directly connected to the first addition portion 412 through a via at the corresponding position, and the first electrode of the storage capacitor C may be connected to the gate of the driving transistor T3.

[0068] [Corrected according to Rule 91, 20.10.2023] As shown in Figures 6 and 11, the second conductive layer 2 may include a third conductive portion 23. The third conductive portion 23 can be used to form the second electrode of the storage capacitor C. The third conductive portion 23 may include a second main body portion 231 and a second extension portion 232. The orthographic projection of the second main body portion 231 onto the substrate may extend along the second direction Y and overlap with the orthographic projection of the second conductive portion 12 onto the substrate. The second extension portion 232 is connected to the side of the second main body portion 231 near the third gate signal line Gate3. The second main body portion 231 forms the second electrode of the storage capacitor C. The second main body portion 231 has an opening M through which a portion of the second conductive portion 12 can be exposed. Thus, the exposed second conductive portion 12 can be connected to the first extension portion 412 in the first conductive portion 41 through a via.

[0069] [Corrected according to Rule 91, 20.10.2023] The second addition portion 232 can be connected to the third bridging portion 53 of the fourth conductive layer 5 via a via, so that the second addition portion 232 is connected to the third node N3 through the third bridging portion 53, thereby connecting the second terminal of the storage capacitor C to the third node N3. In an exemplary embodiment, the conductor structure forming the third node N3 in the active layer 3 can be located on the side of the third active portion 33 away from the fifth active portion 35, and correspondingly, the second addition portion 232 can be located on the side of the second main body portion 231 away from the first enable signal line EM.

[0070] [Corrected according to Rule 91, 20.10.2023] Furthermore, as shown in FIG11, the second conductive layer 2 may also include a first gate line Gate1', a second gate line Gate2', a third gate line Gate3', and a second enable signal line EM'. The second enable signal line EM', the first gate line Gate1', and the second gate line Gate2' are located on one side of the third conductive portion 23 in the second direction Y, and the third gate line Gate3' is located on the other side of the third conductive portion 23 in the second direction Y. The orthographic projections of the first gate line Gate1', the second gate line Gate2', the third gate line Gate3', and the second enable signal line EM' on the substrate can all extend along the first direction X, and the second enable signal line EM', the first gate line Gate1', and the second gate line Gate2' are sequentially spaced apart in the second direction Y along a direction away from the third conductive portion 23.

[0071] [Corrected according to Rule 91 20.10.2023] The first gate line Gate1' is provided corresponding to the first gate signal line Gate1 of the third conductive layer 4. The orthographic projection of the first gate line Gate1' on the substrate can overlap with the orthographic projection of the first gate signal line Gate1 on the substrate and cover the orthographic projection of the first active part 31 on the substrate, so that part of the structure of the first gate line Gate1' can be used to form the bottom gate of the first transistor T1.

[0072] [Corrected according to Rule 91 20.10.2023] The second gate line Gate2' is provided correspondingly to the second gate signal line Gate2. The orthographic projection of the second gate line Gate2' onto the substrate overlaps with the orthographic projection of the second gate signal line Gate2 onto the substrate and covers the orthographic projection of the second active part 32 onto the substrate. Thus, a portion of the structure of the second gate line Gate2' can be used to form the bottom gate of the second transistor T2.

[0073] [Corrected according to Rule 91 20.10.2023] The third gate line Gate3' is provided correspondingly to the third gate signal line Gate3. The orthographic projection of the third gate line Gate3' onto the substrate overlaps with the orthographic projection of the third gate signal line Gate3 onto the substrate and covers the orthographic projection of the fourth active part 34 onto the substrate. Thus, a portion of the structure of the third gate line Gate3' can be used to form the bottom gate of the fourth transistor T4.

[0074] [Corrected according to Rule 91 20.10.2023] The second enable signal line EM' is provided corresponding to the first enable signal line EM. The orthographic projection of the second enable signal line EM' onto the substrate overlaps with the orthographic projection of the first enable signal line EM onto the substrate and covers the orthographic projection of the fifth active part 35 onto the substrate. Thus, a portion of the structure of the second enable signal line EM' can be used to form the bottom gate of the fifth transistor T5.

[0075] [Corrected according to Rule 91, 20.10.2023] As shown in Figures 6 and 7, in an exemplary embodiment, the active layer 3 may further include a first active portion 31, a second active portion 32, and a fourth active portion 34. The first active portion 31 forms the channel region of the first transistor T1, the second active portion 32 forms the channel region of the second transistor T2, and the fourth transistor T4 forms the channel region of the fourth transistor T4. The fourth active portion 34 and the fifth active portion 35 are located at both ends of the third active portion 33, respectively, to connect to both ends of the driving transistor T3.

[0076] [Corrected according to Rule 91, 20.10.2023] As shown in FIG7, the active layer 3 may further include an eleventh active portion 311 to an eighteenth active portion 318. The eleventh active portion 311 is connected to one side of the first active portion 31 and is used to form the first electrode of the first transistor T1. The orthographic projection of the eleventh active portion 311 on the substrate can extend along the first direction X to below the data signal line Vdata, so as to connect with the data signal line Vdata through a via, thereby connecting the first electrode of the first transistor T1 to the data signal terminal Data. The twelfth active portion 312 is connected to the other side of the first active portion 31 and is used to form the second electrode of the first transistor T1. The orthographic projection of the twelfth active portion 312 on the substrate can extend along the second direction Y to the position of the first node N1, thereby connecting the first bridging portion 51 of the fourth conductive layer 5 through a via, so as to connect the second electrode of the first transistor T1 to the first node N1.

[0077] [Corrected according to Rule 91, 20.10.2023] The thirteenth active portion 313 and the fourteenth active portion 314 are respectively connected to both sides of the second active portion 32. The thirteenth active portion 313 can be used to form the first electrode of the second transistor T2, and the fourteenth active portion 314 can be used to form the second electrode of the second transistor T2. The structure after the thirteenth active portion 313, the second active portion 32 and the fourteenth active portion 314 are connected can extend along the second direction Y. The fourteenth active portion 314 is located on the side of the second active portion 32 closer to the third active portion 33, and correspondingly, the thirteenth active portion 313 is located on the side of the second active portion 32 away from the third active portion 33. The thirteenth active portion 313 can be connected to the second bridging portion 52 of the fourth conductive layer 5 through a via, so that the second initial signal line Vinit2 connected to the third conductive layer 4 can be connected through the second bridging portion 52, thereby connecting the first electrode of the second transistor T2 to the second initial signal terminal Vinit2. The fourteenth active part 314 can be connected to the first bridging part 51 of the fourth conductive layer 5 through a via, so as to connect the second terminal of the second transistor T2 to the first node N1 through the first bridging part 51.

[0078] [Corrected according to Rule 91, 20.10.2023] The eighteenth active part 318 is connected between the fourth active part 34 and the third active part 33, and is used to form the second electrode and the third node N3 of the fourth transistor T4. The seventeenth active part 317 is connected to the side of the fourth active part 34 away from the third active part 33, and is used to form the first electrode of the fourth transistor T4. The seventeenth active part 317 can be connected to the fourth bridging part 54 of the fourth conductive layer 5 through a via, so that the first electrode of the fourth transistor T4 can be connected to the first initial signal terminal Vinit1 through the fourth bridging part 54.

[0079] [Corrected according to Rule 91 20.10.2023] As shown in FIG8, in an exemplary embodiment, the third conductive layer 4 may further include a first gate signal line Gate1 to a third gate signal line Gate3, a first initial signal line Vinit1, and a second initial signal line Vinit2. Each of the above signal lines may extend along the first direction X. The first enable signal line EM, the first gate signal line Gate1, the second gate signal line Gate2, and the second initial signal line Vinit2 are located on one side of the third conductive portion 23 in the second direction Y and are distributed sequentially at intervals in the second direction Y in a direction away from the third conductive portion 23. The third gate signal and the first initial signal line Vinit1 are located on the other side of the third conductive portion 23 in the second direction Y and are distributed at intervals in the second direction Y in a direction away from the third conductive portion 23.

[0080] [Corrected according to Rule 91 20.10.2023] The first gate signal line Gate1 can be used to provide the first gate signal terminal Gate1 in FIG1. ​​The orthographic projection of the first gate signal line Gate1 onto the substrate covers the orthographic projection of the first active portion 31 onto the substrate, and a portion of the structure of the first gate signal line Gate1 is used to form the top gate of the first transistor T1.

[0081] [Corrected according to Rule 91 20.10.2023] The second gate signal line Gate2 can be used to provide the second gate signal terminal Gate2 in FIG1. ​​The orthographic projection of the second gate signal line Gate2 onto the substrate covers the orthographic projection of the second active portion 32 onto the substrate, and a portion of the structure of the second gate signal line Gate2 is used to form the top gate of the second transistor T2.

[0082] [Corrected according to Rule 91 20.10.2023] The third gate signal line Gate3 can be used to provide the third gate signal terminal Gate3 in FIG1. ​​The orthographic projection of the third gate signal line Gate3 onto the substrate covers the orthographic projection of the fourth active part 34 onto the substrate, and a portion of the structure of the third gate signal line Gate3 is used to form the top gate of the fourth transistor T4.

[0083] [Corrected according to Rule 91, 20.10.2023] The first initial signal line Vinit1 can be used to provide the first initial signal terminal Vinit1 in FIG1. ​​The first initial signal line Vinit1 can be connected to the fourth bridging portion 54 of the fourth conductive layer 5 via a via, so as to connect to the first terminal of the fourth transistor T4 through the fourth bridging portion 54. The second initial signal line Vinit2 can be used to provide the second initial signal terminal Vinit2 in FIG1. ​​The second initial signal line Vinit2 can be connected to the second bridging portion 52 of the fourth conductive layer 5 via a via, so as to connect to the first terminal of the second transistor T2 through the second bridging portion 52.

[0084] [Corrected according to Rule 91 20.10.2023] As shown in FIG9, in an exemplary embodiment, the fourth conductive layer 5 may include, in addition to the first power line Vdd, a first bridging portion 51 to a fourth bridging portion 54. The first bridging portion 51 may be used to form the first node N1 in FIG1. ​​The first bridging portion 51 may include a first sub-bridging portion 511 and a second sub-bridging portion 512. The first sub-bridging portion 511 may be bent to connect the fourteenth active portion 314 and the twelfth active portion 312 through vias, that is, to connect the second electrode of the second transistor T2 and the second electrode of the first transistor T1, respectively. The second sub-bridge portion 512 can extend along the second direction Y. One end of the second sub-bridge portion 512 is connected to the first sub-bridge portion 511, and the other end can be connected to the first addition portion 412 through a via to connect to the gate of the driving transistor T3. Thus, the second terminal of the first transistor T1 and the second terminal of the second transistor T2 are connected to the gate of the driving transistor T3 through the first sub-bridge portion 511 and the second sub-bridge portion 512.

[0085] [Corrected according to Rule 91 20.10.2023] The orthogonal projection of the second bridging portion 52 onto the substrate can extend along the second direction Y, so as to connect the thirteenth active portion 313 and the second initial signal line Vinit2 respectively through vias in the second direction Y, so as to connect the first terminal of the second transistor T2 to the second initial signal terminal Vinit2.

[0086] [Corrected according to Rule 91 20.10.2023] The orthogonal projection of the third bridging portion 53 onto the substrate can extend along the first direction X, so as to connect the second addition portion 232 and the eighteenth active portion 318 respectively through vias in the first direction X, so as to connect the second terminal of the fourth transistor T4 and the second terminal of the storage capacitor C to the third node N3.

[0087] [Corrected according to Rule 91 20.10.2023] The orthogonal projection of the fourth bridging portion 54 onto the substrate can extend along the second direction Y, so as to connect the seventeenth active portion 317 and the first initial signal line Vinit1 respectively through vias in the second direction Y, thereby connecting the first terminal of the fourth transistor T4 to the first initial signal terminal Vinit1.

[0088] [Corrected according to Rule 91, 20.10.2023] Furthermore, as shown in FIG9, the fourth conductive layer 5 may also include a data signal line Vdata. The orthogonal projection of the data signal line Vdata onto the substrate may extend along the second direction Y. The data signal line Vdata may be used to provide the data signal terminal Data in FIG1. ​​The data signal line Vdata may be connected to the eleventh active part 311 through a via to connect to the first terminal of the first transistor T1. As shown in FIG6, in an exemplary embodiment, in a repeating unit, the data signal line Vdata and the first power supply line Vdd may be located on opposite sides. In other words, in the same repeating unit, other structures of the pixel driving circuit are located between the data signal line Vdata and the first power supply line Vdd.

[0089] [Corrected according to Rule 91, 20.10.2023] As shown in FIG6, in the plurality of pixel driving circuits in the display panel of this disclosure, one pixel driving circuit can constitute a repeating unit. In another exemplary embodiment of this disclosure, two pixel driving circuits can also constitute a repeating unit. For example, FIG12 is a structural layout diagram of a display panel according to another embodiment of this disclosure. As shown in FIG12, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 that are adjacently distributed in the row direction X. The first pixel driving circuit P1 and the second pixel driving circuit P2 can be arranged in a mirror symmetrical manner. The first pixel driving circuit P1 and the second pixel driving circuit P2 can form a repeating unit Q. The display panel may include a plurality of repeating units Q that are arrayed in the row direction X and the column direction Y. In two adjacent repeating units Q in the row direction, the first pixel driving circuit P1 in one repeating unit Q is arranged adjacent to the second pixel driving circuit P2 in the adjacent repeating unit Q, and the second pixel driving circuit P2 in one repeating unit Q is arranged adjacent to the first pixel driving circuit P1 in the other repeating unit Q.

[0090] [Corrected according to Rule 91, 20.10.2023] As shown in Figure 12, in a repeating unit Q, the first pixel driving circuit P1 and the second pixel driving circuit P2 are arranged in a mirror-symmetric manner, and the first power line Vdd in the first pixel driving circuit P1 and the first power line Vdd in the second pixel driving circuit P2 can be connected as a whole. In two adjacent repeating units Q in the row direction, the first power line Vdd in the first pixel driving circuit P1 is not connected to the first power line Vdd in the second pixel driving circuit P2 in the adjacent repeating unit Q. In addition, as shown in Figure 12, in the same repeating unit Q, the data signal line Data in the first pixel driving circuit P1 and the data signal line Data in the second pixel driving circuit P2 are not connected, and the two data signal lines Data are distributed on both sides of the two first power lines Vdd.

[0091] [Corrected according to Rule 91, 20.10.2023] Figure 13 is a cross-sectional view along the AA direction in Figure 6. As shown in Figure 13, the display panel may further include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, and a passivation layer 76. The substrate 71, buffer layer 72, first conductive layer 1, first insulating layer 73, second conductive layer 2, second insulating layer 74, active layer 3, third insulating layer 75, third conductive layer 4, first dielectric layer 76, fourth conductive layer 5, and first planarization layer 77 are sequentially stacked. The first insulating layer 73, second insulating layer 74, and third insulating layer 75 may be silicon oxide layers, the first dielectric layer 75 may be a silicon nitride layer, and the buffer layer 72 may be made of silicon oxide, silicon nitride, etc. The substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer sequentially stacked. The barrier layer may be an inorganic material. The materials of the first conductive layer 1, the second conductive layer 2, and the third conductive layer 4 can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The material of the fourth conductive layer 5 can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof, or a titanium / aluminum / titanium stack thereof.

[0092] [Revised according to Rule 91, 20.10.2023] This disclosure also provides a display device that may include the display panel described in any embodiment of this disclosure.

[0093] [Revised according to Rule 91, October 2023] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0094] [Corrected on October 20, 2023, according to Rule 91]

[0095] [Corrected on October 20, 2023, according to Rule 91]

[0096] [Corrected on October 20, 2023, according to Rule 91]

[0097] [Corrected on October 20, 2023, according to Rule 91]

[0098] [Corrected on October 20, 2023, according to Rule 91]

[0099] [Corrected on October 20, 2023, according to Rule 91]

[0100] [Corrected on October 20, 2023, according to Rule 91]

[0101] [Corrected on October 20, 2023, according to Rule 91]

[0102] [Corrected on October 20, 2023, according to Rule 91]

[0103] [Corrected on October 20, 2023, according to Rule 91]

[0104] [Corrected on October 20, 2023, according to Rule 91]

[0105] [Corrected on October 20, 2023, according to Rule 91]

[0106] [Corrected on October 20, 2023, according to Rule 91]

[0107] [Corrected on October 20, 2023, according to Rule 91]

[0108] [Corrected on October 20, 2023, according to Rule 91]

[0109] [Corrected on October 20, 2023, according to Rule 91]

[0110] [Corrected on October 20, 2023, according to Rule 91]

[0111] [Corrected on October 20, 2023, according to Rule 91]

Claims

1. A pixel driving circuit, wherein, The pixel driving circuit comprises: a driving circuit connected to the first node, the second node and the third node, the driving circuit being configured to provide a driving current using a voltage difference between the second node and the third node in response to a voltage signal of the first node; a first control circuit connected to the second node, a first power supply terminal and an enable signal terminal, the first control circuit being configured to transmit a voltage signal of the first power supply terminal to the second node in response to a signal of the enable signal terminal.

2. The pixel driving circuit according to claim 1, wherein The on level of the driving circuit and the on level of the first control circuit are of the same polarity.

3. The pixel driving circuit of claim 1, wherein the driving circuit comprises: a driving transistor having a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode connected to the first node, the driving transistor being configured to provide a driving current using a voltage difference between the second node and the third node in response to a voltage signal of the first node; the first control circuit comprises: a fifth transistor having a first electrode connected to the second node, a second electrode connected to the first power supply terminal, and a gate electrode connected to the enable signal terminal, the fifth transistor being configured to transmit a voltage signal of the first power supply terminal to the second node in response to a signal of the enable signal terminal.

4. The pixel driving circuit of claim 3, wherein, The driving transistor and the fifth transistor are both N-type transistors.

5. The pixel driving circuit of claim 1, wherein, The pixel driving circuit further comprises: a first reset circuit connected to the third node, a third gate signal terminal and a first initial signal terminal, the first reset circuit being configured to transmit a signal of the first initial signal terminal to the third node in response to a signal of the third gate signal terminal; a second reset circuit connected to the first node, a second initial signal terminal and a second gate signal terminal, the second reset circuit being configured to transmit a signal of the second initial signal terminal to the first node in response to a signal of the second gate signal terminal; a data writing circuit connected to the first node, a first gate signal terminal and a data signal terminal, the data writing circuit being configured to transmit a signal of the data signal terminal to the first node in response to a signal of the first gate signal terminal; a coupling circuit connected between the first node and the third node.

6. The pixel driving circuit of claim 5, wherein the first reset circuit comprises: a fourth transistor having a first electrode connected to the first initial signal terminal, a second electrode connected to the third node, and a gate electrode connected to the third gate signal terminal, the fourth transistor being configured to transmit a signal of the first initial signal terminal to the third node in response to a signal of the third gate signal terminal; the second reset circuit comprises: a second transistor having a first electrode connected to the second initial signal terminal, a second electrode connected to the first node, and a gate electrode connected to the second gate signal terminal, the second transistor being configured to transmit a signal of the second initial signal terminal to the first node in response to a signal of the second gate signal terminal; the data writing circuit comprises: a first transistor having a first electrode connected to the data signal terminal, a second electrode connected to the first node, and a gate electrode connected to the first gate signal terminal, the first transistor being configured to transmit a signal of the data signal terminal to the first node in response to a signal of the first gate signal terminal. ​ The coupling circuit comprises: The storage capacitor has a first pole connected to the first node and a second pole connected to the third node.

7. The pixel driving circuit of claim 6, wherein, The fourth transistor, the second transistor and the first transistor are all N-type transistors.

8. A pixel driving circuit driving method, wherein, The method for driving the pixel driving circuit of any one of claims 1-7 comprises: In the light-emitting stage, a preset duty ratio of the on level signal is provided to the enable signal end to control the preset time length of the first control circuit, and the signal of the first power supply end is transmitted to the second node by the first control circuit, and the driving circuit is controlled to provide the driving current by the voltage difference between the second node and the third node.

9. A pixel driving circuit driving method, wherein, The method for driving the pixel driving circuit of claim 5 comprises: In the initialization stage, the signal of the first initial signal end is transmitted to the third node by the first reset circuit, and the signal of the second initial signal end is transmitted to the first node by the second reset circuit; In the data writing stage, the signal of the data signal end is transmitted to the first node by the data writing circuit; In the light-emitting stage, the first control circuit is controlled to be turned on for a preset time length, and the signal of the first power supply end is transmitted to the second node by the first control circuit, and the driving circuit is controlled to provide the driving current by the voltage difference between the second node and the third node.

10. A display panel, wherein, The display panel comprises a plurality of pixel driving circuits of any one of claims 1-7, and the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction. The first pole of the driving transistor is connected to the second node. The pixel driving circuit is used for driving the light-emitting unit to emit light. The display panel further comprises: a substrate; an active layer located on one side of the substrate, the active layer comprising: a third active part extending along the second direction in the orthographic projection of the substrate, the third active part being used for forming a channel region of a driving transistor; a fifth active part located on one side of the third active part and used for forming a channel region of the fifth transistor; a fifteenth active part connected between the third active part and the fifth active part and used for forming a first pole of the driving transistor and a first pole of the fifth transistor; a sixteenth active part connected to one side of the fifth active part away from the fifteenth active part and used for forming a second pole of the fifth transistor; a third conductive layer located on a side of the active layer away from the substrate, the third conductive layer comprising: a first conductive part corresponding to the third active part, the first conductive part covering the third active part in the orthographic projection of the substrate, the first conductive part being used for forming a gate of the driving transistor; a first enable signal line extending along the first direction in the orthographic projection of the substrate and covering the fifth active part in the orthographic projection of the substrate, and part of the structure of the first enable signal line being used for forming a top gate of the fifth transistor; A fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the fourth conductive layer comprises The fourth conductive layer comprises: A first power line extends along the second direction in the orthogonal projection of the substrate and intersects the sixteenth active part in the orthogonal projection of the substrate, and the first power line is connected to the corresponding position of the sixteenth active part through a via hole.

11. The display panel of claim 10, wherein, The pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor is connected to a first initial signal terminal, a second electrode is connected to a third node, and a gate electrode is connected to a third gate signal terminal; and a second electrode of the driving transistor is connected to the third node. The active layer further comprises: A fourth active part is located on a side of the third active part away from the fifth active part, and is used for forming a channel region of the fourth transistor; An eighteenth active part is connected between the fourth active part and the third active part, and is used for forming a second electrode of the fourth transistor and a second electrode of the driving transistor; A seventeenth active part is connected on a side of the fourth active part away from the eighteenth active part, and is used for forming a first electrode of the fourth transistor; The third conductive layer further comprises: A third gate signal line extends along the first direction in the orthogonal projection of the substrate and covers the fourth active part in the orthogonal projection of the substrate, and part of the structure of the third gate signal line is used for forming a top gate of the fourth transistor; A first initial signal line extends along the first direction in the orthogonal projection of the substrate and is located on a side of the third gate signal in the orthogonal projection of the substrate away from the third active part in the orthogonal projection of the substrate; The fourth conductive layer further comprises: A fourth bridge part extends along the second direction in the orthogonal projection of the substrate, and the fourth bridge part is connected to the first initial signal line and the seventeenth active part through a via hole respectively.

12. The display panel of claim 11, wherein, The pixel driving circuit further comprises a second transistor, a first electrode of the second transistor is connected to a second initial signal line, a second electrode is connected to a first node, and a gate electrode is connected to a second gate signal line; and a gate electrode of the driving transistor is connected to the first node; The active layer further comprises: A second active part extends along the second direction in the orthogonal projection of the substrate, and the second active part is used for forming a channel region of the second transistor; A thirteenth active part is connected on a side of the second active part away from the third active part, and is used for forming a first electrode of the second transistor; A fourteenth active part is connected on a side of the second active part close to the third active part, and is used for forming a second electrode of the second transistor; The third conductive layer further comprises: A second gate signal line extends along the first direction in the orthogonal projection of the substrate and is located on a side of the first enable signal line in the orthogonal projection of the substrate away from the third active part in the orthogonal projection of the substrate, and the second gate signal line covers the second active part in the orthogonal projection of the substrate, and part of the structure of the second gate signal line is used for forming a top gate of the second transistor; A second initial signal line, in a projection of the substrate substrate along the first direction, the second initial signal line is located on the side of the second gate signal line away from the first enable signal line; The fourth conductive layer further includes: A first bridge portion connecting the fourteenth active portion and the first conductive portion through a via hole to connect the second electrode of the second transistor to the gate electrode of the driving transistor; A second bridge portion connecting the thirteenth active portion and the second initial signal line through a via hole to connect the first electrode of the second transistor to the second initial signal line.

13. The display panel of claim 12, wherein, The pixel driving circuit further includes a first transistor, the first electrode of the first transistor is connected to a data signal end, the second electrode is connected to a first node, and the gate electrode is connected to a first gate signal line; The active layer further includes: A first active portion for forming a channel region of the first transistor; An eleventh active portion connected to one side of the first active portion for forming a first electrode of the first transistor; A twelfth active portion connected to the other side of the first active portion for forming a second electrode of the first transistor, and the twelfth active portion is connected to the first bridge portion through a via hole; The third conductive layer further includes: A first gate signal line extending along the first direction in a projection of the substrate substrate and covering the first active portion in the projection of the substrate substrate, and the first gate signal line is located between the second gate signal line and the first enable signal line; The fourth conductive layer further includes: A data signal line extending along the second direction in a projection of the substrate substrate and located on the side of the third active portion in the projection of the substrate substrate away from the first power supply line in the projection of the substrate substrate, and the data signal line is connected to the eleventh active portion through a via hole.

14. The display panel of claim 11, wherein, The pixel driving circuit further includes a storage capacitor, the first electrode of the storage capacitor is connected to the first node, and the second electrode is connected to the third node; The first conductive portion includes a first main portion and a first additional portion, the first main portion extends along the second direction in a projection of the substrate substrate and covers the third active portion in the projection of the substrate substrate, and the first additional portion is connected to the side of the first main portion away from the first power supply line, and the first additional portion extends along the first direction in the projection of the substrate substrate; The display panel further includes: A first conductive layer between the substrate substrate and the active layer, the first conductive layer includes: A second conductive portion corresponding to the first conductive portion, the second conductive portion is used for forming the first electrode of the storage capacitor and is connected to the first additional portion through a via hole; A second conductive layer between the first conductive layer and the active layer, the second conductive layer includes: A third conductive part for forming a second electrode of the storage capacitor, the third conductive part comprising a second main part and a second additional part, the second main part extending along the second direction in the orthographic projection of the substrate and partially overlapping the second conductive part in the orthographic projection of the substrate, and the second additional part being located between the orthographic projection of the second main part and the orthographic projection of the third gate signal line in the orthographic projection of the substrate; The fourth conductive layer further comprises: A third bridge part extending along the first direction in the orthographic projection of the substrate, the third bridge part connecting the second additional part and the eighteenth active part through vias, respectively; The second main part has an opening for exposing part of the second conductive part, the first additional part is located within the orthographic projection of the opening in the orthographic projection of the substrate, and the part of the second conductive part facing the opening is connected to the first additional part through a via.

15. The display panel of claim 13, wherein, The second conductive layer further comprises: A first gate line extending along the first direction in the orthographic projection of the substrate and partially overlapping the first gate signal line in the orthographic projection of the substrate, the first gate line covering the orthographic projection of the first active part in the orthographic projection of the substrate, and part of the structure of the first gate line being used to form a bottom gate of the first transistor; A second gate line extending along the first direction in the orthographic projection of the substrate and partially overlapping the second gate signal line in the orthographic projection of the substrate, the second gate line covering the orthographic projection of the second active part in the orthographic projection of the substrate, and part of the structure of the second gate line being used to form a bottom gate of the second transistor; A third gate line extending along the first direction in the orthographic projection of the substrate and partially overlapping the third gate signal line in the orthographic projection of the substrate, the third gate line covering the orthographic projection of the fourth active part in the orthographic projection of the substrate, and part of the structure of the third gate line being used to form a bottom gate of the fourth transistor.

16. The display panel of claim 10, wherein, The first direction is a row direction, and the second direction is a column direction; The display panel comprises a plurality of repeating units distributed along the row and column directions, each repeating unit comprising two pixel drive circuits adjacent in the row direction, and each column of pixel drive circuits is provided with a first power line; In the same repeating unit, the two first power lines are connected.

17. The display panel of claim 16, wherein, In the same repeating unit, the two pixel drive circuits adjacent in the row direction are mirror images of each other.

18. A display device, wherein, The display panel of any one of claims 10-17.

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