Array substrate, display panel, display apparatus, and mask

Abstract

An array substrate. The array substrate (110) has a display area (AA), a fan-out area (BB1) and a binding area (BB2). The array substrate (110) comprises a base (11), a plurality of connecting leads (30) and a flat layer (40), wherein the flat layer (40) is located on one side of the plurality of connecting leads (30) that is away from the base (11), and comprises a first pattern area (401), which is located in the fan-out area (BB1); the first pattern area (401) is provided with a plurality of first recessed portions (41); an orthographic projection of at least one first recessed portion (41) on the base (11) overlaps with an orthographic projection of at least one connecting lead (30) on the base (11); and there is a spacing between the first recessed portion (41) and the connecting lead (30) in a direction perpendicular to the base (11).

Description

Array substrate, display panel, display device and mask Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a display device, and a mask plate. Background Art

[0002] Liquid crystal displays (LCDs) are widely used due to their low power consumption, miniaturization, and thinness. They are used in various fields, including mobile phones, flat-panel displays, automotive displays, televisions, and public displays.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate comprises a display area, a fan-out area, and a binding area. The array substrate includes a substrate, a plurality of connecting leads, and a planar layer. The planar layer is located on a side of the connecting leads away from the substrate and includes a first pattern area located in the fan-out area. The first pattern area is provided with a plurality of first recesses, wherein the orthographic projection of at least one first recess on the substrate overlaps the orthographic projection of at least one connecting lead on the substrate, and a gap is formed between the first recess and the connecting lead in a direction perpendicular to the substrate.

[0005] In some embodiments, along a direction perpendicular to the substrate, a ratio of a depth of the first recessed portion to a thickness of the planar layer is 0.25 to 0.65.

[0006] In some embodiments, the first recess includes a first bottom wall, and along a direction perpendicular to the substrate, a distance between the first bottom wall and the connecting lead is greater than or equal to 1 μm.

[0007] In some embodiments, the first recess further includes a first sidewall, and a variation in a tangent slope of the first sidewall is less than or equal to 0.1.

[0008] In some embodiments, the first pattern area further includes a connecting portion, the connecting portion being located in gaps between the plurality of first recesses and connecting the plurality of first recesses, wherein an angle between a surface of the connecting portion away from the substrate and the first sidewall is 125° to 160°.

[0009] In some embodiments, an angle between a surface of the connecting portion away from the substrate and the first sidewall is 150° to 155°.

[0010] In some embodiments, the array substrate further comprises a plurality of binding pins. The plurality of binding pins are disposed in the binding region, and each binding pin is electrically connected to at least one connecting lead. Along a first direction, a distance between outer edges of two first recessed portions furthest apart is greater than a distance between outer edges of two binding pins furthest apart in the binding region. The first direction is parallel to an extension direction of a boundary between the display region and the fan-out region.

[0011] In some embodiments, the plurality of first recessed portions are arranged in a plurality of rows, the plurality of rows of first recessed portions are spaced apart along a second direction, any two adjacent rows of first recessed portions are staggered along the first direction, and the second direction is parallel to an arrangement direction of the display area and the fan-out area.

[0012] In some embodiments, the planar layer further comprises a groove, the groove being located in the fan-out area and further away from the display area than the first pattern area. The array substrate comprises a first side and a second side opposite to each other in a first direction, the groove extending from the first side to the second side.

[0013] In some embodiments, an orthographic projection of the groove on the substrate partially overlaps an orthographic projection of at least one connecting lead on the substrate. A ratio of a depth of the groove to a thickness of the planar layer along a direction perpendicular to the substrate is 0.25 to 0.65.

[0014] In some embodiments, the trench includes a second bottom wall, and along a direction perpendicular to the substrate, a distance between the second bottom wall and the connecting lead is greater than or equal to 1 μm.

[0015] In some embodiments, the depth of the groove is greater than the depth of the first recess.

[0016] In some embodiments, a boundary of the first pattern area close to the binding area is a broken line, and the groove extends along an extension direction of the first pattern area away from the boundary of the display area.

[0017] In some embodiments, the distance between the first pattern area and the display area is 100 μm to 200 μm. And / or the distance between the first pattern area and the groove is 5 μm to 50 μm. And / or the distance between the groove and the binding area is 5 μm to 50 μm.

[0018] In some embodiments, the fan-out region includes a first routing region. In the first routing region, the width of the connecting leads is 1.5 μm to 1.9 μm. The spacing between two adjacent connecting leads is 1.6 μm to 2.0 μm. The orthographic projection of the first recess on the substrate overlaps with the orthographic projection of at least two of the connecting leads on the substrate.

[0019] In some embodiments, the first pattern area further includes a plurality of second recessed portions, wherein the orthographic projections of the second recessed portions on the substrate do not overlap with the orthographic projections of the connecting leads on the substrate, and the depth of the second recessed portions is greater than the depth of the first recessed portions.

[0020] In some embodiments, a distance between a boundary of the display area close to the binding area and a boundary of the binding area away from the display area is less than or equal to 2.4 mm.

[0021] In some embodiments, the array substrate further comprises an alignment film, which is located on a side of the planar layer away from the substrate and at least partially located within the display area.

[0022] In another aspect, a display panel is provided, comprising the array substrate described in any one of the above embodiments, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

[0023] In another aspect, a display device is provided. The display device includes the aforementioned display panel, a flexible circuit board, and a driver chip. The flexible circuit board is bonded to the array substrate of the display panel and at least partially bent toward the back side of the array substrate. The driver chip is disposed on the array substrate and located between the grooves of the flexible circuit board and the array substrate.

[0024] In another aspect, another display device is provided. The display device includes the aforementioned display panel, a chip-on-film (COF), and a driver chip. The COF is bonded to the array substrate of the display panel and at least partially bent to the back side of the array substrate. The driver chip is disposed on the COF and located on the back side of the array substrate.

[0025] On the other hand, a mask plate is provided. The mask plate is used to prepare the array substrate described in any of the above embodiments. The mask plate includes a second pattern area. The second pattern area includes a plurality of first opening areas, each of which is configured to form a first recessed portion. The first opening area includes a first shading pattern and a plurality of first through holes arranged at intervals, the boundary of the first shading pattern enclosing the plurality of first through holes, the light transmittance of the shading pattern is 0%, and the light transmittance of the first through holes is 100%. The interval between two adjacent first through holes is less than or equal to a first threshold, and the maximum size of each first through hole is less than or equal to the first threshold. The first threshold is 1 / 2 of the resolution size of the exposure machine used.

[0026] In some embodiments, the first opening region is rectangular in shape, and the side length of the first opening region is greater than or equal to 10 μm. Furthermore, the spacing between two adjacent first opening regions is greater than or equal to 5 μm. Furthermore, within each first opening region, the spacing between two adjacent first through-holes is between 1.0 μm and 1.5 μm. Furthermore, the opening shape of the first through-hole is square, and the side length of the first through-hole is between 1.0 μm and 1.5 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is another structural diagram of a display device according to some embodiments;

[0030] FIG3A is a diagram showing a connection structure between a driving chip and an array substrate according to some embodiments;

[0031] FIG3B is another connection structure diagram of a driving chip and an array substrate according to some embodiments;

[0032] FIG4 is a structural diagram of an array substrate according to some embodiments;

[0033] FIG5 is a cross-sectional view taken along section line A1-A1 in FIG4;

[0034] FIG6 is a partial enlarged view of the B1 area in FIG4 ;

[0035] FIG7A is a cross-sectional view taken along section lines C1-C1 and C2-C2 in FIG4;

[0036] FIG7B is a graph showing the surface tension of an alignment liquid on a flat layer according to some embodiments;

[0037] FIG8 is a schematic diagram of an alignment liquid flowing on a planar layer according to some embodiments;

[0038] FIG9 is a structural diagram of a groove formed on a flat layer in the related art;

[0039] FIG10 is another structural diagram of an array substrate according to some embodiments;

[0040] FIG11 is a partial enlarged view of the B2 area in FIG4 ;

[0041] FIG12 is a cross-sectional view taken along section line EE in FIG11;

[0042] FIG13 is a cross-sectional view taken along section lines C3-C3 and C2-C2 in FIG4;

[0043] FIG14 is a structural diagram of a mask according to some embodiments;

[0044] FIG15A is a partial enlarged view of the G area in FIG14 ;

[0045] FIG15B is another partial enlarged view of the G area in FIG14 ;

[0046] FIG16 is a partial enlarged view of the H area in FIG14 . DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] Some embodiments of the present disclosure provide a display device 1000. Referring to FIG1 , the display device 1000 may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. For example, the display device 1000 may be a television, a laptop computer, a tablet computer, a mobile phone, an electronic photo, an electronic billboard or signboard, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any other product or component with a display function. For example, as shown in FIG1 , the display device 1000 may be, for example, a mobile phone.

[0059] 2 , the display device 1000 may include a display panel 100 (LCD panel), a backlight assembly 200, and a glass cover 300. The glass cover 300 is disposed on the light-emitting side of the display panel 100 to protect the display panel 100.

[0060] As shown in FIG2 , the display panel 100 may include at least an array substrate 110, a color filter substrate 120 (full name: Color Filter), and a liquid crystal layer 130 disposed between the array substrate 110 and the color filter substrate 120. The color filter substrate 120 may also be referred to as a cell-matching substrate. The array substrate 110 and the color filter substrate 120 are disposed opposite each other. The display panel 100 may further include a sealant (not shown in the figure). The sealant is disposed along the circumferential edges of the array substrate 110 and the color filter substrate 120 to seal the array substrate 110 and the color filter substrate 120 to form a liquid crystal cell. The liquid crystal layer 130 is disposed within the liquid crystal cell.

[0061] The backlight assembly 200 is used to provide a light source for the display panel 100. The backlight assembly 200 can be an edge-type backlight assembly or a direct-type backlight assembly. In the embodiment of the present disclosure, as shown in Figure 2, the backlight assembly 200 is described as an edge-type backlight assembly. The backlight assembly 200 may include a backlight source 210, a light guide plate 220, and a reflective sheet 230. The backlight source 210 is arranged on one side of the light guide plate 220, and the reflective sheet 230 is arranged on the side of the light guide plate 220 away from the display panel 100, and is used to reflect the light emitted from the light guide plate 220 to the reflective sheet 230, thereby improving the light extraction efficiency of the display panel 100.

[0062] It is understood that the backlight assembly 200 may also include other structures, which are not specifically limited in the embodiments of the present disclosure. For example, the backlight assembly 200 may also include a diffusion sheet and / or a light-enhancing film located on a side of the light guide plate 220 away from the reflective sheet 230, and these are not further described here.

[0063] In some embodiments, as shown in FIG3A , the display device 1000 may further include a driver chip 400. The driver chip 400 may be directly bonded to the array substrate 110 (on the bonding area BB2 ), i.e., the driver chip 400 may utilize a COG (Chip On Glass) bonding solution. This improves the compatibility of the display device 1000 with the display panel 100 and reduces the cost of the display device 1000 . For example, the display device 1000 may further include a flexible printed circuit (FPC) 500 . The flexible printed circuit 500 may be used to connect the bonding area BB2 to a printed circuit board (PCB) or a motherboard or other control components.

[0064] In other embodiments, as shown in FIG3B , the display device 1000 may further include a chip-on-film (COF) 600. The driver chip 400 may also be encapsulated within the COF 600, and the driver chip 400 is folded along the COF 600 to the back side of the array substrate 110. This means that the driver chip 400 utilizes a COF bonding solution. This helps reduce the bezel width of the array substrate 110, thereby enabling the display device 1000 to achieve a narrow bezel.

[0065] In the following embodiments of the present disclosure, the driver chip 400 shown in FIG3A is directly bonded to the array substrate 110. It is understood that the following embodiments can also be applied to the display device 1000 in which the driver chip 400 is encapsulated in the chip-on-film 600.

[0066] Referring to FIG. 4 , which is a partially enlarged view of the fan-out area and the binding area of ​​the array substrate, the array substrate 110 may include a display area AA and a peripheral area BB surrounding the display area AA, wherein only a portion of the peripheral area BB is shown in FIG. The peripheral area BB includes a fan-out area BB1 and a binding area BB2 located on one side of the display area AA. In the embodiment of the present disclosure, the extension direction of the boundary between the display area AA and the fan-out area BB1 (the horizontal direction in FIG. 4 ) is taken as the first direction X, and the arrangement direction of the display area AA, the fan-out area BB1, and the binding area BB2 (the vertical direction in FIG. 4 ) is taken as the second direction Y. The first direction X and the second direction intersect with each other. Exemplarily, the first direction X and the second direction Y are perpendicular to each other. That is, the display area AA, the fan-out area BB1, and the binding area BB2 are arranged in sequence along the second direction Y, and along the second direction Y, the binding area BB2 is farther away from the display area AA than the fan-out area BB1.

[0067] In particular, the binding area BB2 is provided with a first pin area 410 for binding the driver chip 400 and a second pin area 510 for binding the flexible circuit board 500. In some embodiments, a test pin area 420 and a ground contact 430 may also be provided in the binding area BB2. For example, after the display array substrate 110 is prepared, the test pin area 420 can be connected to a test circuit (a circuit structure independent of the array substrate 110) to test whether the array substrate 110 can operate normally. In other words, the test pin area 420 is used to detect whether the array substrate 110 is qualified. In addition, after the subsequent module process of the array substrate (after assembly to form a display panel and a display device), the test pin area 420 may not be bound or connected to any device. The material of the ground contact 430 can be a conductive material (such as silver), and the ground contact 430 is used for grounding, thereby reducing the risk of the array substrate 110 being damaged by static electricity.

[0068] The first pin area 410, the second pin area 510, and the test pin area 420 are each provided with a plurality of binding pins 31. The binding pins 31, which may also be referred to as pins, gold fingers, etc., are conductive structures provided within the binding area BB1 for electrical connection to external devices. For example, the binding pins 31 within the first pin area 410 can be used for binding and connecting to the driver chip 400, and the binding pins 31 within the second pin area 510 can be used for binding and connecting to the flexible circuit board 500. The binding pins 31 within the test pin area 420, also referred to as test pins, are used to connect to the test circuit during the array substrate inspection process. After the array substrate is assembled to form a display panel and display device, the binding pins 31 within the test pin area 420 may not be connected to any device or circuit. In other words, the binding pins 31 refer to all pins provided within the binding area BB1, rather than pins within one or more specific areas. Of course, the binding area BB1 may also include areas provided with binding pins for connection to other devices, but this is not specifically limited in the embodiments of the present disclosure.

[0069] It is understood that in the embodiments of the present disclosure, the fan-out area BB1 refers to the partial area between the display area AA and the binding area BB2; the boundary between the fan-out area BB1 and the binding area BB2 can be a line connecting the ends of the multiple binding pins 31 close to the display area AA, and extending to the opposite sides of the array substrate 110. In addition, the fan-out area BB1 can be understood as an area for setting the connecting leads 30 and is not connected to or in contact with external devices (such as the driver chip 400). The binding area BB2 refers to an area for binding or setting external devices (such as the driver chip 400, the flexible circuit board 500, etc.).

[0070] Referring to Figures 4 and 5, Figure 5 is a cross-sectional structural diagram of a thin film transistor, a portion of the first recess, a groove, and a binding area. The array substrate 110 may include a substrate 11 and a circuit structure 20 disposed on the substrate 11. The substrate 11 may include a substrate 111, a light-shielding pattern 112 disposed on the substrate, and a buffer layer 113 disposed on the light-shielding pattern 112. The substrate 111 may be, for example, a glass substrate, the light-shielding pattern 112 is used to shield part of the circuit structure 20 (for example, shielding the semiconductor layer of the thin film transistor), and the buffer layer 113 may flatten the upper surface of the substrate 11 and buffer the film layer formed on the substrate 11. The circuit structure 20 may include, for example, a pixel circuit 21 located in the display area AA and a gate drive circuit 22 located in the peripheral area.

[0071] Referring to FIG5 , the array substrate 110 includes a thin film transistor (TFT) 12, a planar layer 40, a common electrode 13, a pixel electrode 14, and an insulating layer 15 located between the common electrode 13 and the pixel electrode 14, disposed on a substrate 11. The thin film transistor 12 includes a semiconductor layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124. The array substrate 110 may further include a gate insulating layer located between the semiconductor layer 121 and the gate electrode 122, and an interlayer insulating layer located between the gate electrode 122 and the source electrode 123 (drain electrode 124), etc., which will not be described in detail here. The planar layer 40 is disposed above the film layer where the source electrode 123 and the drain electrode 124 are located, and a via (through hole) is provided on the planar layer 40, through which the pixel electrode 14 can be electrically connected to the drain electrode 124 of the thin film transistor. The pixel circuit 21 and the gate driving circuit 22 may each include a plurality of thin film transistors 12 . The embodiments of the present disclosure do not specifically limit the pixel circuit 21 and the gate driving circuit 22 .

[0072] As shown in Figure 4 , the array substrate 110 also includes a plurality of connecting leads 30. Figure 4 only schematically illustrates a few connecting leads 30 and should not be construed as limiting the location, quantity, or arrangement of the connecting leads 30. The connecting leads 30 are disposed on the substrate 11 and within the fan-out area BB1. The connecting leads 30 can be disposed on the same layer as the source electrode 123 and the drain electrode 124. That is, the connecting leads 30, the source electrode 123, and the drain electrode 124 can be a film layer having a specific pattern formed using the same film formation process.

[0073] In the embodiment of the present disclosure, the plurality of connecting leads 30 being located in the fan-out area BB1 can be understood as at least a portion of the plurality of connecting leads 30 being located in the fan-out area BB1. For example, the connecting leads 30 can extend from the gate drive circuit 22 of the peripheral area BB, through the fan-out area BB1 and to the binding area BB2, or can extend from the display area AA through the fan-out area BB1 and to the binding area BB2. The plurality of connecting leads 30 can be used to connect the gate drive circuit 22 and the binding pins 31 (also referred to as gold fingers, pads, etc.) in the binding area BB2. The plurality of connecting leads 30 can be used, for example, to transmit start signals, clock signals, data signals, etc., and the embodiments of the present disclosure do not specifically limit this.

[0074] As shown in FIG5 , the array substrate 110 may further include a first conductive block 33 located in the fan-out region and a second conductive block 34 located in the binding region. The first conductive block 33 and the second conductive block 34 may be made of the same material as the gate 122 of the thin film transistor 12 and be disposed in the same layer.

[0075] The first conductive block 33 can extend along the arrangement direction (e.g., the first direction) of the plurality of connecting leads 30. The first conductive block 33 is used to connect at least two connecting leads for transmitting the same signal. A plurality of connecting leads 30 are provided in the fan-out area BB1. The arrangement density of the connecting leads 30 is relatively high, and non-adjacent connecting leads 30 can be connected through the first conductive block 33. For example, an interlayer insulating layer 125 is further provided between the first conductive block 33 and the connecting leads 30. The connecting leads 30 that need to be electrically connected to the first conductive block 33 can pass through the interlayer insulating layer 125 through vias (not shown in the figure) to be electrically connected to the first conductive block 33. In this way, the first conductive block 33 can be effectively prevented from contacting other connecting leads (connecting leads that do not need to be electrically connected), thereby reducing the risk of signal crosstalk between different connecting leads 30.

[0076] The second conductive block 34 is used to electrically connect to the binding pins 31 of the first pin area and / or the second pin area to reduce the contact resistance between the driver chip, the flexible circuit board 500, and the binding pins 31. For example, the second conductive block 34 is disposed on the side of the binding pin 31 closest to the substrate, and the second conductive block 34 is in direct contact with the binding pin 31. In other words, no interlayer insulating layer 125 is provided between the second conductive block 34 and the binding pin 31. This helps increase the contact area between the second conductive block 34 and the binding pin 31, reduces the contact resistance between the second conductive block 34 and the binding pin 31, and facilitates signal transmission between the binding pin 31 and the driver chip and the flexible circuit board, thereby reducing energy consumption.

[0077] It is understood that the binding area BB2 has a large space, providing ample room for the design of the binding pins 31. Furthermore, the spacing between the binding pins 31 is large, eliminating the risk of signal crosstalk and short circuits. Therefore, the interlayer insulating layer 125 on the side of the binding pins 31 closest to the substrate 11 can be completely removed, allowing the second conductive blocks 34 to be directly positioned on the binding pins 31. Furthermore, the patterning of the interlayer insulating layer 125 in the binding area BB2 is simpler, which helps reduce the difficulty of manufacturing the display panel.

[0078] In some embodiments, as shown in FIG5 , one or more layers of third conductive blocks 32 may be further provided on the surface of the binding pins 31 away from the substrate 11. Similar to the second conductive blocks 34, the third conductive blocks 32 can reduce the contact resistance between the driver chip and the flexible circuit board 500 and the binding pins 31, thereby reducing the power consumption of the display panel. A detailed description thereof will not be repeated here.

[0079] Exemplarily, the array substrate 110 may further include a third conductive block 32 disposed on the binding pin 31 . The third conductive block 32 may be made of the same material and disposed on the same layer as the common electrode 13 , or the third conductive block 32 may be made of the same material and disposed on the same layer as the pixel electrode 14 .

[0080] In some embodiments, as shown in FIG2 , the array substrate 110 further includes an alignment film 140. The alignment film 140 can be disposed on the side of the planar layer 40 of the array substrate away from the substrate 110, that is, on the side of the array substrate 110 relatively close to the liquid crystal layer 130. The color filter substrate 120 also includes an alignment film 140. The alignment film 140 of the color filter substrate 120 is disposed on the color filter substrate 120 and is located on the side close to the liquid crystal layer 130. The alignment film 140 is used to control the alignment direction of the liquid crystal molecules in the liquid crystal layer 130. Specifically, the alignment film 140 can be used to control the alignment direction of the liquid crystal molecules when not subjected to an electric field. It can also be understood that the alignment film 140 is used to limit the pretilt angle of the liquid crystal molecules.

[0081] During the process of applying an alignment liquid (a solution used to form an alignment film) to the array substrate 110 to form the alignment film, the alignment liquid will flow along the surface of the array substrate. It is necessary to prevent the alignment liquid from flowing into the bonding area (bonding pins) and affecting the electrical connection between the bonding area and other components (such as the driver chip and FPC) to ensure the reliability of the array substrate.

[0082] However, in the related art, with the development of narrow bezels of display panels, the spacing between the display area and the binding area (the width of the fan-out area) is getting smaller and smaller, the setting density of the connecting leads in the fan-out area is getting larger and larger, the width of the connecting leads (the dimension perpendicular to the extension direction of the connecting leads) is getting smaller and smaller, and the spacing between the connecting leads is also getting smaller and smaller. For example, the line width of the connecting leads is less than 2μm or less than 2.5μm, and the spacing between adjacent connecting leads is less than 2μm or less than 2.5μm. Based on this, the space for setting grooves on the flat layer is getting smaller and smaller. In particular, in the related art, when the grooves are only set in the spacing between the connecting leads, there is insufficient space for setting grooves on the flat layer, resulting in an increasing risk of the alignment liquid flowing to the binding area.

[0083] To address the above technical issues, reduce the risk of alignment liquid flowing to the binding area BB2 of the array substrate 110, and improve the reliability of the array substrate 110 in the (narrow-frame) display panel 100, the display panel 100 provided in an embodiment of the present disclosure, as shown in FIG4 , comprises a planarization layer 40 including a first pattern area 401 located within the fan-out area BB1.

[0084] Referring to FIG5 , the first pattern area 401 is provided with a plurality of first recesses 41 , and along a direction perpendicular to the substrate 11 , the first recesses 41 are spaced apart from the connecting wires 30 . Referring to FIG6 , in the orthographic projection onto the substrate 11 , at least one first recess 41 partially overlaps with at least one connecting lead 30 . In other words, the first recess 41 is provided on the side of the connecting lead 30 away from the substrate 11 , and the first recess 41 does not need to avoid the connecting lead 30 , which is beneficial to increasing the setting area of ​​the first recess 41 in the fan-out area BB1 , increasing the number of the first recess 41 , and increasing the opening area of ​​the first recess 41 , thereby increasing the area ratio of the first recess 41 , improving the ability of the fan-out area BB1 to absorb and accommodate the alignment liquid, and reducing the risk of the alignment liquid flowing to the binding area. At the same time, it is also beneficial to reduce the width of the fan-out area BB1 , thereby reducing the border width of the display panel 100 .

[0085] As shown in Figure 5, along the direction perpendicular to the substrate 11, the first recessed portion 41 is spaced apart from the connecting wire 30, which can prevent the first recessed portion 41 from exposing the connecting wire 30, thereby protecting the connecting wire and reducing the risk of exposing and damaging the connecting wire 30 during the subsequent preparation process of the display panel 100.

[0086] It is understandable that in FIG6 , the projection relationship between the first recessed portion 41 and the connecting lead 30 is merely an example, and not a limitation of the present application. In the orthographic projection onto the substrate 11, at least one first recessed portion 41 partially overlaps with at least one connecting lead 30, and each first recessed portion 41 may partially overlap with at least one connecting lead 30. For example, each first recessed portion 41 partially overlaps with one or two or more connecting leads 30, and the number of connecting leads 30 overlapping with different first recessed portions 41 may be the same or different. For example, in an area where the connecting leads 30 are densely arranged, each first recessed portion 41 overlaps with two connecting leads 30, and in an area where the connecting leads 30 are densely and sparsely arranged, the first recessed portion 41 partially overlaps with one connecting lead 30.

[0087] In the orthographic projection onto the substrate 11, at least one first recess 41 partially overlaps with at least one connecting lead 30. Alternatively, part of the first recess 41 partially overlaps with at least one connecting lead 30, and part of the first recess 41 does not overlap with the connecting lead 30 (is separated from each other). The first recess 41 partially overlaps with at least one connecting lead 30, as described above, and will not be repeated here. Part of the first recess 41 does not overlap with the connecting lead 30. For example, in an area where the connecting leads 30 are densely and sparsely arranged, part of the first recess 41 is located between two adjacent connecting leads 30, or in an area of ​​the fan-out area where no connecting leads 30 are provided, part of the first recess 41 does not overlap with the connecting lead 30.

[0088] Based on the above, in the embodiment of the present disclosure, the first recessed portion 41 can be understood as each groove having approximately the same opening size and depth along a direction perpendicular to the substrate 11 (the third direction Z). In other words, the multiple first recessed portions 41 have the same or approximately the same structure and size except for their different positions. In particular, due to the uniformity and precision errors of the manufacturing process, there may be certain deviations in the structure and size of the multiple first recessed portions 41 formed. For example, the deviation range of the multiple first recessed portions 41 is less than or equal to 5%, or the deviation range is less than or equal to 10%. The embodiment of the present disclosure does not specifically limit this.

[0089] In some embodiments, the fan-out area BB1 includes a first routing area 402 and a second routing area (not shown in the figure), and the arrangement density of the connecting leads 30 in the first routing area 402 is greater than the arrangement density of the connecting leads in the second routing area. For example, the first routing area 402 can be an area in the fan-out area close to the first pin area 410, the test pin area 420, and the second pin area 510; the second routing area can be an area on both sides of the fan-out area along the first direction X, or other areas. The embodiments of the present disclosure do not specifically limit the specific arrangement method and arrangement area of ​​the connecting leads 30 in the fan-out area.

[0090] Referring to Figure 6, in the first routing area 402, the width of the connecting lead 30 is 1.5μm to 1.9μm. Exemplarily, the width of the connecting lead is 1.5μm, 1.7μm or 1.9μm. The embodiments of the present disclosure will not list them one by one. Among them, the width of the connecting lead 30 refers to the dimension perpendicular to the extension direction of the connecting lead 30 at any position of the connecting lead 30, and can also be understood as the minimum spacing between the two opposite sides of the connecting lead 30. The spacing between two adjacent connecting leads 30 is 1.6μm to 2.0μm. Exemplarily, the spacing between two adjacent connecting leads 30 can be 1.6μm, 1.8μm or 2.0μm. In this way, it is conducive to further reducing the width of the fan-out area BB1 along the second direction X, thereby realizing the narrow frame of the display panel 100. In the first routing area, the orthographic projection of the first recessed portion 41 on the substrate 11 overlaps with the orthographic projections of at least two connecting leads 30 on the substrate 11, which is beneficial to increasing the size of the first recessed portion 41, increasing the area ratio of the first recessed portion 41 in the first pattern area 401, and increasing the ability of the first recessed portion 41 to absorb and accommodate the alignment liquid.

[0091] In some embodiments, as shown in FIG4 , the distance D1 between the display area AA adjacent to the binding area BB2 and the binding area BB2 distal to the display area AA is less than or equal to 2.4 mm. Thus, the array substrate 110 can be used to manufacture a display panel 100 with an extremely narrow bezel, facilitating a narrow bezel for the display device 1000.

[0092] For example, the distance D1 between the boundary of the display area AA near the binding area BB2 and the boundary of the binding area BB2 away from the display area AA is 2.37 mm. Furthermore, along the second direction Y, the distance between the second pin area 510 and the boundary of the binding area BB2 away from the display area AA can be 0.07 mm; the width of the second pin area 510 can be 0.3 mm; the distance between the second pin area 510 and the first pin area 410 can be 0.2 mm; the width of the first pin area 410 can be 0.95 mm; and the distance between the display area AA and the first pin area 410 can be 0.85 mm.

[0093] In some embodiments, referring to Figures 5 and 7A , along a direction perpendicular to the substrate (third direction Z), the ratio of the depth H1 of the first recessed portion 41 to the thickness H2 of the planar layer 40 is 0.25 to 0.65, i.e., H1 / H2 is in the range of 0.25 to 0.65. In this way, the first recessed portion 41 can both absorb and accommodate the alignment liquid and protect the connecting lead 30 on the side of the first recessed portion 41 closest to the substrate 11. For example, the ratio of the depth H1 of the first recessed portion 41 to the thickness H2 of the planar layer 40 can be 0.25, 0.4, 0.55, or 0.65, etc., which are not listed in detail in the embodiments of the present disclosure.

[0094] It is understood that the thickness H2 of the planar layer 40 in different areas may vary. For example, the thickness of the portion of the planar layer 40 located in the display area AA may differ from the thickness of the portion located in the fan-out area BB1. The thickness of the portion of the planar layer 40 in contact with the connecting lead 3 may also differ from the thickness of the portion of the planar layer 40 in contact with the interlayer insulating layer 125. Based on this, in the embodiment of the present disclosure, the ratio of the depth H1 of the first recess 41 to the thickness H2 of the planar layer 40 can be understood as the ratio of the depth H1 of the first recess 41 to the thickness of the portion of the planar layer 40 in the area where the first recess 41 is located.

[0095] For example, the thickness H2 of the portion of the planar layer 40 located in the fan-out area BB1 may be 2.3 μm to 2.5 μm, and the depth H1 of the first recessed portion 41 may be 1.0 μm to 1.5 μm. For example, the thickness of the portion of the planar layer 40 located in the fan-out area BB1 may be 2.3 μm, 2.4 μm, or 2.5 μm. The depth H1 of the first recessed portion 41 may be 1.0 μm, 1.3 μm, or 1.5 μm, which are not listed in detail in the embodiments of the present disclosure.

[0096] In some embodiments, referring to Figures 5 and 7A, Figure 7A is a cross-sectional structural diagram of a first recessed portion 41 and a portion of the groove. The first recessed portion 41 includes a first bottom wall 411. Along the direction perpendicular to the substrate 11 (the third direction Z), the interval between the first bottom wall 411 and the connecting lead 30 is D2, and D2 is greater than or equal to 1 μm. In other words, the thickness of the flat layer 40 on the upper side of the connecting lead 30 is greater than or equal to 1 μm. In this way, it is beneficial to improve the flatness of the first bottom wall 411 of the first recessed portion 41, and ensure that the flat layer 40 can protect the connecting lead 30 below, thereby reducing the risk of exposing the connecting lead 30 during the subsequent preparation process of the display panel 100.

[0097] In some embodiments, referring again to FIG. 7A , the first recessed portion 41 further includes a first sidewall 412, and the variation in the tangent slope of the first sidewall 412 is less than or equal to 0.1. In other words, the first sidewall 412 of the first recessed portion 41 is a substantially straight slope. Thus, a sharp (compared to a circular angle) obtuse angle α is formed at the top end (the end away from the substrate 11) of the first sidewall 412 with the upper surface of the planar layer 40 (the surface of the unpatterned region away from the substrate 11).

[0098] The tangent slope of the first sidewall 412 refers to the slope of a tangent line of the first sidewall 412, measured from the position where it contacts the first bottom wall 411 to various positions on the upper surface of the planar layer 40, compared to the plane of the substrate, in a cross section perpendicular to the substrate 11 and passing through the first recessed portion 41. Furthermore, to clearly identify the starting and ending positions of the first sidewall 412, that is, to clarify the range of the first sidewall, the sidewall within a certain depth range of the first recessed portion 41 can be defined as the first sidewall. For example, the sidewall corresponding to the portion from 10% to 90% of the depth H1 of the first recessed portion 41 is the first sidewall 412. The embodiments of the present application do not specifically limit the range of the depth H1 of the first recessed portion 41 to which the first sidewall 412 corresponds. For example, the first sidewall 412 may also correspond to the portion from 5% to 95% or from 20% to 80% of the depth H1 of the first recessed portion 41. Based on this, the change in the tangent slope of the first side wall 412 is less than or equal to 0.1, which may mean that the change in the tangent slope of the first side wall 412 in the section of the depth H1 of the first recessed portion 41 from 10% to 90% is less than or equal to 0.1, that is, the difference between the maximum and minimum values ​​of the tangent slope of the first side wall 412 in the section of the depth H1 of the first recessed portion 41 from 10% to 90% is less than or equal to 0.1.

[0099] Referring to Figures 8 and 9 , compared to a smooth arc angle, the top of the first sidewall 412 forms a sharp obtuse angle α with the upper surface of the flat layer 40. This reduces the contact area between the alignment liquid 1 and the solid phase (flat layer 40) as it flows into the first recess 41 (flowing from right to left), enhancing the cohesion of the alignment liquid 1 and making it less likely to flow into the first recess 41. Simultaneously, the contact area between the alignment liquid 1 and the gas phase (air) increases, allowing the air to support the alignment liquid 1. The suspended alignment liquid is supported by the gas phase below, making it more difficult for the alignment liquid 1 to flow into the first recess 41. In other words, the first recess 41 enhances its blocking effect on the alignment liquid 1, which helps reduce the flow velocity of the alignment liquid 1 and, in turn, further minimizes the flow distance (overflow distance) of the alignment liquid 1. Based on the increased blocking effect of the first recessed portion 41 on the alignment liquid 1, while ensuring that the alignment liquid 1 does not flow into the binding area, the number of first recessed portions 41 can be reduced and / or the size of a single first recessed portion 41 can be reduced, that is, the space occupied by the first recessed portion 41 is reduced, which is beneficial for the display panel 100 to achieve a narrow frame.

[0100] In related art, as shown in Figure 9, the sidewalls of the grooves are formed to form a rounded (smooth) arc angle with the upper surface of the planar layer. This allows the alignment liquid to flow into the grooves, creating a larger contact area with the planar layer. This reduces the agglomeration effect of the alignment liquid, making it easier for the alignment liquid to flow into the grooves. Furthermore, when the alignment liquid flows at a high rate, it can easily overflow from the grooves along the sidewalls, hindering the grooves from absorbing and retaining the alignment liquid.

[0101] Compared with the prior art, in the present application, the top of the first side wall 412 forms a sharp obtuse angle α with the upper surface of the flat layer 40, which can enhance the blocking effect of the first recessed portion 41 on the alignment liquid 1 and reduce the flow distance of the alignment liquid 1, which is beneficial for the display panel 100 to achieve a narrow frame.

[0102] In some embodiments, referring to Figures 5 and 7A, the first pattern area 401 further includes a connecting portion 43, which is located within the gaps between the multiple first recesses 41 and connects the multiple first recesses 41. The connecting portion 43 can also be understood as the portion of the first pattern area BB1 that has not been patterned (the portion without grooves, pits, holes, or other features). The angle α between the surface of the connecting portion 43 away from the substrate 11 and the first sidewall 412 is 125° to 160°. In other words, the inclination angle of the first sidewall 412 (the acute angle formed by the first sidewall 412 and a plane parallel to the substrate 11) is 20° to 55°. This helps increase the size of the space formed by the first recesses 41, thereby increasing the ability of the first recesses 41 to absorb and accommodate the alignment liquid, enhancing the first recesses 41's blocking effect on the alignment liquid, and reducing the distance the alignment liquid flows along the array substrate 110. For example, the angle α between the surface of the connection portion 43 away from the substrate 11 and the first sidewall 412 may be 125°, 150°, or 160°, etc., which will not be described in detail in the embodiments of the present disclosure.

[0103] In some embodiments, the angle α between the surface of the connection portion 43 away from the substrate 11 and the first sidewall 412 of the first recessed portion 41 is 150° to 155°. In other words, the inclination angle of the first sidewall 412 is 25° to 30°. Thus, the smaller the angle α between the surface of the connection portion 43 away from the substrate 11 and the first sidewall 412, the easier it is to manufacture the first recessed portion 41, thereby reducing the manufacturing cost of the array substrate 110. For example, the angle α between the surface of the connection portion 43 away from the substrate 11 and the first sidewall 412 can be 150°, 152°, or 155°, etc., which are not listed in detail in the embodiments of the present disclosure.

[0104] Referring to Figure 7B , the applicants of the present disclosure also verified the surface tension of the alignment liquid on the planar layer 40 when the angle α between the surface of the connection portion 43 facing away from the substrate 11 and the first sidewall 412 of the first recessed portion 41 is 160° (the first sidewall 412 has a 20° inclination angle), 150° (the first sidewall 412 has a 30° inclination angle), and 125° (the first sidewall 412 has a 55° inclination angle). Figure 7B shows multiple test points selected sequentially along the second direction Y and away from the display area AA on the portion of the planar layer 40 located in the fan-out area BB1. Any test point can be selected as needed. It has been verified that the first recessed portion 41 effectively blocks the alignment liquid when the angle α between the surface of the connection portion 43 facing away from the substrate 11 and the first sidewall 412 is between 125° and 160°.

[0105] As shown in FIG7B , when the angle α between the surface of the connecting portion 43 away from the substrate 11 and the first sidewall 412 is 125°, the alignment liquid has a larger surface tension on the flat layer 40, and the first recessed portion 41 has the strongest barrier effect on the alignment liquid. Alternatively, when the angle α is 150° or 160°, the alignment liquid has a surface tension of 1.05N on the flat layer 40. However, at the angle α of 150°, the stress of the alignment liquid on the flat layer 40 is maintained longer, thus providing a better barrier effect. For example, to balance the difficulty of preparing the first recessed portion 41 and the impedance effect of the first recessed portion 41 on the alignment liquid, the angle α between the surface of the connecting portion 43 away from the substrate 11 and the first sidewall 412 can be set to 140°, 150°, or 155°, etc. The embodiments of the present disclosure are not listed one by one.

[0106] In some embodiments, referring to FIG. 10 , along the first direction X, the distance D3 between the outer edges of the two furthest-distance first recesses 41 is greater than the distance D4 between the outer edges of the two furthest-distance binding pins 31 in the binding area BB2. Specifically, the distance between the outer edges of the two furthest-distance binding pins 31 in the binding area BB2 may be the distance between the outer edges of the two binding pins 31 located in the two test pin areas 420 away from the first pin area 410. The first direction X and the second direction Y intersect, and illustratively, the first direction X and the second direction Y are perpendicular to each other. That is, along the second direction Y, a first recess 41 is provided at each position opposite the binding pin 31. This improves the first recess 41's ability to absorb and accommodate alignment liquid, prevents alignment liquid from passing through the fan-out area BB1 from both sides without passing through the first recess 41, and reduces the risk of alignment liquid flowing into the binding area BB2. For example, referring to FIG. 10 , the distance between the two furthest-distance binding pins 31 in the binding area BB2 may be the distance between the outer edges of the two test pin areas 420.

[0107] In some embodiments, as shown in FIG10 , a plurality of first recessed portions 41 are arranged in a plurality of rows, and the plurality of rows of first recessed portions 41 are spaced apart along the second direction Y. Any two adjacent rows of first recessed portions 41 are staggered along the first direction X. In this way, the plurality of rows of first recessed portions 41 can play a multi-channel absorption role for the alignment liquid, thereby reducing the flow distance of the alignment liquid. Moreover, the first recessed portions 41 can be provided at each position of the fan-out area BB1 along the first direction X, thereby preventing the alignment liquid from directly passing through the fan-out area BB1 through the gaps between the first recessed portions 41, thereby improving the absorption effect of the alignment liquid by the plurality of first recessed portions 41. Among them, FIG10 only exemplarily shows a portion of the three rows of first recessed portions 41, and a plurality of first recessed portions 41 can be evenly provided in the first pattern area 401.

[0108] In some embodiments, referring to FIG. 4 , the planar layer 40 further includes a groove 42 . The groove 42 is located in the fan-out area BB1 and is further away from the display area AA than the first pattern area 401 . The array substrate 110 includes a first side 1101 and a second side 1102 that are opposite to each other in the first direction X, and the groove 42 extends from the first side 1101 to the second side 1102 . In other words, along the first direction X, the two ends of the groove 42 are flush with the boundaries of the array substrate 110 , the groove 42 is continuously arranged, and runs through the fan-out area along the length of the first direction X. In this way, no matter where the alignment liquid flows out of the first pattern area 401 from, it can flow into the groove 42, so that the groove 42 plays the role of intercepting the alignment liquid and improves the ability of the groove 42 to accommodate the alignment liquid.

[0109] In some embodiments, the orthographic projection of the groove 42 on the substrate 11 partially overlaps the orthographic projection of at least one connecting lead 30 on the substrate. In other words, by providing the groove 42 on the side of the connecting lead 30 away from the substrate 11, the groove 42 does not need to avoid the connecting lead 30. This helps to increase the area of ​​the groove 42 within the fan-out area BB1, allowing the groove 42 to penetrate the fan-out area BB1 along the first direction, thereby improving the groove 42's ability to absorb and accommodate the alignment liquid.

[0110] Along a direction perpendicular to the substrate (third direction Z), the ratio of the depth H3 of the groove 42 to the thickness H2 of the planar layer 40 is 0.25 to 0.65, i.e., H3 / H2 is in the range of 0.25 to 0.65. This allows the groove 42 to both absorb and accommodate the alignment liquid and protect the connecting leads 30 on the side of the groove 42 closest to the substrate 11. For example, the ratio of the depth H3 of the groove 42 to the thickness H2 of the planar layer 40 can be 0.25, 0.35, 0.5, or 0.65, etc., which are not listed in detail in the embodiments of the present disclosure.

[0111] For example, the thickness H2 of the portion of the planar layer 40 located in the fan-out region BB1 can be 2.3 μm to 2.5 μm, and the depth H3 of the trench 42 can be 1.0 μm to 1.5 μm. For example, the thickness of the portion of the planar layer 40 located in the fan-out region BB1 can be 2.3 μm, 2.4 μm, or 2.5 μm. The depth H1 of the first recessed portion 41 can be 1.0 μm, 1.3 μm, or 1.5 μm, which are not listed in detail in the embodiments of the present disclosure.

[0112] Referring to FIG. 7A , the trench 42 includes a second bottom wall 421. The distance between the second bottom wall 421 and the connecting lead 30 is greater than or equal to 1 μm, along a direction perpendicular to the substrate 11. The distance between the second bottom wall 421 and the connecting lead 30 is D5, which is greater than or equal to 1 μm. This improves the flatness of the second bottom wall 421 of the trench 42 and ensures that the flattening layer 40 protects the connecting lead 30 below, reducing the risk of exposing the connecting lead 30 during subsequent fabrication of the display panel 100.

[0113] In some embodiments, referring to FIG7A , the depth H3 of the groove 42 is greater than the depth H1 of the first recess 41. That is, the spacing D5 between the second bottom wall 421 of the groove 42 and the connecting lead 30 is smaller than the spacing D2 between the first bottom wall 411 of the first recess 41 and the connecting lead 30. In the embodiment of the present disclosure, a first recess 41 and a groove 42 of different depths are formed in the flat layer 40. This is conducive to further increasing the volume of the groove 42, thereby improving the ability of the groove 42 to absorb and accommodate the alignment liquid. The groove 42 serves as the last barrier to intercept the alignment liquid. A deeper groove is conducive to improving the ability of the groove 42 to absorb and accommodate the alignment liquid, further improving the ability of the fan-out area BB1 to absorb and accommodate the alignment liquid, and reducing the risk of the alignment liquid flowing to the binding area.

[0114] Exemplarily, the distance D2 between the first bottom wall 411 of the first recess 41 and the connection lead 30 is 1.5 μm, 1.6 μm or 1.7 μm, etc., and the distance D5 between the second bottom wall 421 of the groove 42 and the connection lead 30 is 1.0 μm, 1.1 μm or 1.2 μm, etc.

[0115] In some embodiments, referring again to FIG. 10 , the boundary between the fan-out area BB1 and the binding area BB2 is a broken line. The boundary shape of the first pattern area 401 can be contoured to the boundary between the fan-out area BB1 and the binding area BB2. This helps maximize the area of ​​the first pattern area 401, providing a greater number of first recesses 41 and improving the first recesses' 41's ability to absorb and accommodate the alignment liquid.

[0116] When the boundary between the fan-out area BB1 and the binding area BB2 is a zigzag line, the boundary of the first pattern area 401 near the binding area BB2 is also a zigzag line. The groove 42 extends along the boundary of the first pattern area 401 near the binding area BB2, that is, the extension direction of the groove 42 is also a zigzag line.

[0117] For example, as shown in FIG10 , the groove 42 includes a plurality of first sub-segments 422 and a plurality of second sub-segments 423 that are alternately connected in sequence. The first sub-segments 422 extend along the second direction Y, and the second sub-segments 423 extend along the first direction X. The groove 42 is terminated at both ends by the second sub-segments 423. The interval D6 between the first sub-segment 422 and the first pattern area 401 is substantially equal to the interval D7 between the second sub-segment 423 and the first pattern area 401.

[0118] In some embodiments, referring to FIG. 10 , the spacing D8 between the first pattern area 401 and the display area AA along the second direction Y is 100 μm to 200 μm. This facilitates visual identification (e.g., via a camera) of whether the formed alignment film extends beyond the boundaries of the display area AA, thereby facilitating determination of whether the alignment film meets fabrication requirements. For example, the spacing D8 between the first pattern area 401 and the display area AA can be 100 μm, 130 μm, 185 μm, or 200 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0119] The spacing D6 between the first pattern area 401 and the groove 42 is 5 μm to 50 μm. This helps separate the groove 42 from the first recessed portion 41, preventing the first recessed portion 41 from communicating with the groove 42. This improves the ability of the first recessed portion 41 and the groove 42 to store the alignment liquid, allowing the first recessed portion 41 and the groove 42 to independently absorb and hold the alignment liquid. For example, the spacing D6 between the first pattern area 401 and the groove 42 can be 5 μm, 20 μm, 45 μm, or 50 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0120] As shown in Figure 10, the gap D9 between the groove 42 and the bonding area BB2 is 5μm to 50μm. This prevents the groove 42 from connecting to other openings in the bonding area BB2 (such as those used to bond the driver chip and FPC). It also increases the safety buffer distance of the bonding area BB2. Even if a small amount of alignment liquid flows out of the groove 42 due to excessive flow rate, it will not flow further into the bonding area BB2.

[0121] In some embodiments, referring to Figures 11 and 12, the first pattern area 401 further includes a plurality of second recesses 44, the orthographic projections of the second recesses 44 on the substrate 11 not overlapping with the orthographic projections of the connecting leads 30 on the substrate 11. In other words, the second recesses 44 can be provided in areas of the first pattern area 401 where no connecting leads 30 are provided. There are no connecting leads 30 on the side of the second recesses 44 close to the substrate 11. Therefore, there is no need to worry about the second recesses 44 exposing the connecting leads 30 on the lower side. Based on this, the depth H4 of the second recesses 44 is greater than the depth H1 of the first recesses 41. This is beneficial for increasing the volume of the second recesses 44 (compared to the first recesses 41) and improving the ability of the second recesses 44 to absorb and accommodate the alignment liquid.

[0122] For example, as shown in FIG12 , the second recessed portion 44 includes a third bottom wall 441. A distance D10 between the third bottom wall 441 of the second recessed portion 44 and the surface of the planar layer 40 close to the substrate 11 can be less than or equal to 1 μm. In other words, the thickness of the planar layer 40 at the bottom of the second recessed portion 44 is less than 1 μm. For example, the distance D10 between the third bottom wall 441 of the second recessed portion 44 and the surface of the planar layer 40 close to the substrate 11 can be 0.2 μm, 0.5 μm, 0.8 μm, or 1 μm.

[0123] It is understood that, when the depth H3 of the groove 42 is also greater than the depth H1 of the first recessed portion 41, the depth H4 of the second recessed portion 44 may be equal to or different from the depth H3 of the groove 42. For example, as shown in FIG13 , the depth H4 of the second recessed portion 44 is greater than the depth H3 of the groove 42.

[0124] As can be seen from the above embodiment, the planar layer 40 includes through holes of varying depths, a groove 42, a first recess 41, and a second recess 44. When using a conventional half-tone mask to prepare the planar layer 40, multiple regions with different transmittances need to be provided. The preparation of a half-tone mask is expensive and difficult.

[0125] In order to solve the above technical problems, referring to FIG. 14 , other embodiments of the present disclosure further provide a mask plate 2000 for preparing the array substrate 110 described in any of the above embodiments, specifically for preparing the planar layer 40 described in any of the above embodiments.

[0126] It can be understood that the preparation process of the flat layer 40 includes coating, exposure and development. Coating refers to the preparation of a continuous entire layer of the initial flat layer, and the surface of the initial flat layer away from the substrate is roughly flat. Exposure refers to the use of an exposure machine to allow the laser to pass through the mask plate 2000 to irradiate the initial flat layer, so that part of the initial flat layer is subjected to light treatment. Development is to spray the developer on the initial flat layer after exposure, and the solubility of the part of the initial flat layer that is exposed to light and the part that is not exposed to light in the developer is inconsistent, thereby removing part of the initial flat layer and exposing part of the initial flat layer to form a flat layer. In the embodiment of the present disclosure, the part of the flat layer that is exposed to light that can be removed during the development process is described as an example. Among them, according to the difference in the degree of light exposure in the initial flat layer, patterns of different depths (such as grooves, first recessed portions, second recessed portions and through holes, etc.) can be formed in the initial flat layer.

[0127] Referring to FIG. 14 , a mask 2000 provided in an embodiment of the present disclosure includes a second pattern area 2100. The second pattern area 2100 may, for example, correspond to the first pattern area of ​​the planar layer and be used to form a portion of the first pattern area in the planar layer. The second pattern area 2100 includes a plurality of first opening areas 2110, each of which is configured to form a first recess. Referring to FIG. 15A , the first opening area 2110 includes a first light-shielding pattern 2111 and a plurality of first through-holes 2112 spaced apart. The boundaries of the first light-shielding pattern 2111 enclose the plurality of first through-holes 2112. The light transmittance of the light-shielding pattern 2111 is 0%, while the light transmittance of the first through-holes 2112 is 100%. The interval L1 between two adjacent first through-holes 2112 is less than or equal to a first threshold value M, and the maximum dimension L2 of each first through-hole 2112 is less than or equal to the first threshold value M. The first threshold value M is 1 / 2 of the resolution dimension of the exposure machine used in the process of preparing the planar layer 40.

[0128] It is understood that the opening of the first through hole 2112 is generally a regular shape, which helps reduce the difficulty of processing the mask plate 2000 and reduces the cost of the mask plate 2000. The maximum dimension L2 of the first through hole 2112 refers to the diameter or side length of the first through hole 2112. For example, when the opening (boundary shape) of the first through hole 2112 is rectangular, the maximum dimension of the first through hole 2112 is the side length of the first through hole 2112. When the opening of the first through hole 2112 is circular, the maximum dimension of the first through hole 2112 is the diameter of the first through hole 2112.

[0129] When the maximum dimension L2 of the first through-hole 2112 is greater than the resolution of the exposure machine, light (exposure energy) can fully pass through the first through-hole 2112 and reach the glass substrate, thereby fully acting on the initial flat layer and ultimately forming a through-hole in the initial flat layer. When the opening of the first through-hole 2112 is smaller than the resolution of the exposure machine (for example, less than 1 / 2 of the exposure machine resolution), the exposure energy will primarily rely on diffraction to pass through the first through-hole 2112. In other words, the exposure energy can only partially pass through the first through-hole 2112 and thus only act at a certain depth on the surface of the initial flat layer, ultimately forming a groove of a certain depth in the initial flat layer. Based on this, the same effect as a halftone mask can be achieved.

[0130] In the embodiment of the present disclosure, the spacing L1 between two adjacent first through-holes 2112 and the maximum dimension of each first through-hole 2112 are both less than or equal to the first threshold value M. Thus, the first aperture region 2110 can form an effect similar to that of a half-tone mask. The maximum dimension L2 of the first through-hole 2112 is less than or equal to the first threshold value, thereby preventing light from directly passing through the first through-hole 2112 and irradiating the initial flat layer, allowing light to pass through the first through-hole 2112 primarily by diffraction. The spacing L1 between two adjacent first through-holes 2112 is less than or equal to the first threshold value, thereby preventing the problem of unevenness on the first bottom wall of the first recessed portion due to excessive spacing between the two first through-holes 2112. This improves the flatness of the first bottom wall of the first recessed portion.

[0131] In some embodiments, the light energy passing through the first opening region 2110, and thus the depth of the formed first recessed portion, can be controlled by controlling the area of ​​the first opening region 2110, the area ratio of the first through-holes 2112 in the first opening region 2110, and the area of ​​each first through-hole 2112. Based on this, different opening regions 2110 can be provided in different areas of the mask, thereby forming patterns of varying areas and depths on the planar layer.

[0132] Moreover, since the light transmittance of the first through hole 2112 is 100%, there is no area with a gradual change in light transmittance between the first through hole 2112 and the connecting pattern 2111, and between the first through hole 2112 and the area around the first opening area 2110. Therefore, the slope change of the tangent of the side wall of the first recessed portion formed on the flat layer through the first opening area 2110 can be less than 0.1, that is, the side wall of the first recessed portion can be a straight slope surface. Refer to the above text. This is conducive to enhancing the blocking effect of the first recessed portion on the alignment liquid and reducing the overflow distance of the alignment liquid.

[0133] In some embodiments, referring to FIG. 15A , the plurality of first through-holes 2112 included in each first opening region 2110 are arranged in multiple rows and columns. In other words, the plurality of first through-holes 2112 are evenly spaced. Each column includes a plurality of first through-holes 2112 spaced apart along a second direction Y; each row includes a plurality of first through-holes spaced apart along a first direction X. The second direction Y intersects the first direction X, for example, the first direction X and the second direction Y are perpendicular.

[0134] For example, the spacing between two adjacent first through holes 2112 in each row is equal, the spacing between two adjacent first through holes 2112 in each column is equal, and the spacing between two adjacent first through holes 2112 in each row is equal to the spacing between two adjacent first through holes 2112 in each column. This helps improve the uniformity of light illumination at different locations on the initial flat layer corresponding to the first opening area 2110, thereby improving the flatness of the first bottom wall of the formed first recessed portion.

[0135] In some embodiments, when a deeper groove is required, referring to FIG. 15B , a second through hole 2113 may be provided between each of two adjacent rows and columns of four first through holes 2112. The size of the second through hole 2113 is smaller than that of the first through hole 2112. The second through hole 2113 can increase the amount of light passing through the first opening area 2110, thereby increasing the depth of the ultimately formed first recessed portion. For example, in a case where both a first recessed portion and a second recessed portion are included on a flat layer, the first recessed portion may be formed using the first opening area as shown in FIG. 15A , and the second recessed portion may be formed using the first opening area as shown in FIG. 15B .

[0136] Alternatively, the purpose of increasing the depth of the second recessed portion can be achieved by increasing the area of ​​the first opening region 2110. For example, the mask plate 2000 can also include a second opening region, where the first opening region is used to form the first recessed portion, and the second opening region is used to form the second recessed portion, and the area of ​​the second opening region is larger than the area of ​​the first opening region. Alternatively, the second opening region includes multiple third through holes, and the area proportion of the third through holes in the second opening region is larger than the area proportion of the first through holes (and the second through holes) in the first opening region.

[0137] In some embodiments, referring to Figures 14 and 15A, the shape of the first opening area 2110 is rectangular, such as a rectangle or a square. In the drawings of the present application, the shape of the first opening area 2110 is a square as an example. The side length L4 of the first opening area 2110 is greater than or equal to 10 μm, which can increase the number of first through holes 2112 (and second through holes) in the first opening area 2110, so that the first opening area 2110 as a whole forms an effect similar to semi-transmittance. For example, the side length L4 of the first opening area 2110 can be any value such as 10 μm, 15 μm, 18.5 μm, 22 μm, etc., and the embodiments of the present disclosure will not be listed one by one.

[0138] The spacing L5 between two adjacent first opening areas 2110 is greater than or equal to 5 μm. This allows a connection pattern of a certain width to be formed between two adjacent first recesses on the planar layer, ensuring a certain spacing between the two adjacent first recesses. For example, the spacing L5 between two adjacent first opening areas 2110 can be 5 μm, 8 μm, 9.5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0139] As shown in FIG15A , within each first opening region 2110, the spacing L1 between two adjacent first through holes 2112 is 1.0 μm to 1.5 μm, which facilitates forming a flat first bottom wall at the bottom of the first recess. For example, the spacing L1 between two adjacent first through holes 2112 is 1.0 μm, 1.3 μm, or 1.5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0140] In some embodiments, the opening shape of the first through hole 2112 (the shape surrounded by the boundary) is a square, and the side length of the first through hole 2112 is 1.0μm to 1.5μm. If the side length of the first through hole is less than 1.0μm, the difficulty of preparing the first through hole 2112 will be significantly increased, thereby increasing the preparation cost of the mask plate 2000. If the side length of the first through hole 2112 is greater than 1.5μm, more light will pass through the first through hole 2112, and it will be easy to form an uneven first bottom wall at the bottom of the first recessed portion. Based on the above reasons, in the embodiment of the present disclosure, the side length of the first through hole 2112 is between 1.0μm and 1.5μm. For example, the side length of the first through hole 2112 can be 1.0μm, 1.25μm or 1.5μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0141] In some embodiments, as shown in FIG14 , the mask plate 2000 further includes a third pattern area 2200, which is configured to form a groove of the array substrate (flat layer). As shown in FIG16 , the third pattern area 2200 may include a plurality of third through holes 2210 spaced apart along a first direction X. Along the second direction Y, the size of the third through holes 2210 is larger than the size of the first through holes 2112. Thus, the size of the formed groove along the second direction X is larger than the size of the first recessed portion along the second direction. The interval L3 between two adjacent third through holes 2210 along the first direction X is less than or equal to the first threshold value M, which helps to improve the flatness of the second bottom wall of the formed groove.

[0142] In some embodiments, as shown in FIG16 , when the mask plate 2000 includes a third pattern area 2200 and the third pattern area 2200 includes a plurality of third through holes 2210, the spacing between two adjacent third through holes 2210 may also be 1.0 μm to 1.5 μm. This helps reduce the manufacturing cost of the mask plate 2000 while forming a flat second bottom wall at the bottom of the trench. For example, the spacing between two adjacent third through holes 2210 may be 1.0 μm, 1.35 μm, or 1.5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0143] For example, the opening shape of the third through hole 2210 may be a rectangle, each third through hole 2210 extends along the second direction Y, and the plurality of third through holes 2210 are arranged at intervals along the first direction X.

[0144] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate having a display area, a fan-out area and a binding area; the array substrate comprises: substrate; A plurality of connecting leads are arranged on one side of the substrate and located in the fan-out area; The flat layer is located on a side of the multiple connecting leads away from the substrate, and includes a first pattern area located in the fan-out area; the first pattern area is provided with a plurality of first recessed portions, and the orthographic projection of at least one first recessed portion on the substrate overlaps with the orthographic projection of at least one connecting lead on the substrate, and along a direction perpendicular to the substrate, the first recessed portion is spaced from the connecting lead.

2. The array substrate according to claim 1, wherein: Along a direction perpendicular to the substrate, a ratio of a depth of the first recessed portion to a thickness of the planar layer is 0.25 to 0.

65.

3. The array substrate according to claim 1 or 2, wherein: The first recessed portion includes a first bottom wall, the first bottom wall is close to the substrate, and along a direction perpendicular to the substrate, a distance between the first bottom wall and the connecting lead is greater than or equal to 1 μm.

4. The array substrate according to claim 3, wherein: The first recessed portion further includes a first side wall, and a variation of a tangent slope of the first side wall is less than or equal to 0.

1.

5. The array substrate according to claim 4, wherein: The first pattern area further includes a connecting portion, the connecting portion is located between the plurality of first recessed portions and connects the plurality of first recessed portions; An angle between a surface of the connecting portion away from the substrate and the first side wall is 125° to 160°.

6. The array substrate according to claim 5, wherein: An angle between a surface of the connecting portion away from the substrate and the first side wall is 150° to 155°.

7. The array substrate according to any one of claims 1 to 6, further comprising: A plurality of binding pins are arranged in the binding area, and each binding pin is electrically connected to at least one connecting lead; Among them, along the first direction, the distance between the outer boundaries of the two farthest first recessed portions is greater than the distance between the outer boundaries of the two farthest binding pins in the binding area; the first direction is parallel to the extension direction of the boundary between the display area and the fan-out area.

8. The array substrate according to any one of claims 1 to 7, wherein: The plurality of first recessed portions are arranged in a plurality of rows, and the plurality of rows of first recessed portions are arranged at intervals along the second direction; any two adjacent rows of the first recessed portions are staggered along the first direction; and the second direction is parallel to an arrangement direction of the display area and the fan-out area.

9. The array substrate according to any one of claims 1 to 8, wherein: The planar layer also includes a groove, which is located in the fan-out area and is farther away from the display area than the first pattern area; the array substrate includes a first side edge and a second side edge opposite to each other in a first direction, and the groove extends from the first side edge to the second side edge.

10. The array substrate according to claim 9, wherein: The orthographic projection of the groove on the substrate partially overlaps with the orthographic projection of at least one connecting lead on the substrate; Along a direction perpendicular to the substrate, a ratio of the depth of the groove to the thickness of the planar layer is 0.25 to 0.

65.

11. The array substrate according to claim 9 or 10, wherein: The groove includes a second bottom wall. Along a direction perpendicular to the substrate, a distance between the second bottom wall and the connecting lead is greater than or equal to 1 μm.

12. The array substrate according to any one of claims 9 to 11, wherein: Along a direction perpendicular to the substrate, a depth of the trench is greater than a depth of the first recessed portion.

13. The array substrate according to any one of claims 9 to 12, wherein: The boundary of the first pattern area close to the binding area is a broken line; The groove extends along an extension direction of the first pattern area away from a boundary of the display area.

14. The array substrate according to any one of claims 9 to 13, wherein: The interval between the first pattern area and the display area is 100 μm to 200 μm; and / or, The interval between the first pattern area and the groove is 5 μm to 50 μm; and / or, The interval between the groove and the binding area is 5 μm to 50 μm.

15. The array substrate according to any one of claims 1 to 14, wherein: The fan-out area includes a first routing area; in the first routing area, the width of the connecting lead is 1.5μm to 1.9μm; the interval between two adjacent connecting leads is 1.6μm to 2.0μm, and the orthographic projection of the first recessed portion on the substrate overlaps with the orthographic projection of at least two connecting leads on the substrate.

16. The array substrate according to any one of claims 1 to 15, wherein: The first pattern area further includes a plurality of second recessed portions, the orthographic projections of the second recessed portions on the substrate do not overlap with the orthographic projections of the connecting leads on the substrate; and the depth of the second recessed portions is greater than the depth of the first recessed portions.

17. The array substrate according to any one of claims 1 to 16, wherein: The interval between a boundary of the display area close to the binding area and a boundary of the binding area far from the display area is less than or equal to 2.4 mm.

18. The array substrate according to any one of claims 1 to 16, further comprising: The alignment film is located on a side of the planar layer away from the substrate and is at least partially located in the display area.

19. A display panel, comprising: The array substrate according to any one of claims 1 to 18; A color filter substrate, arranged opposite to the array substrate; The liquid crystal layer is arranged between the array substrate and the color filter substrate.

20. A display device, comprising: The display panel as claimed in claim 19; A flexible circuit board, bound to the array substrate of the display panel and at least partially bent to the back side of the array substrate; The driving chip is arranged on the array substrate and located between the flexible circuit board and the groove of the array substrate.

21. A display device, comprising: The display panel as claimed in claim 19; A chip-on-film is bound to the array substrate of the display panel and is at least partially bent to the back side of the array substrate; The driving chip is arranged on the chip-on-film and is located on the back side of the array substrate.

22. A mask plate for preparing the array substrate according to any one of claims 1 to 18, comprising: The second pattern area includes a plurality of first opening areas, each of which is configured to form a first recessed portion; the first opening area includes a first light shielding pattern and a plurality of first through holes arranged at intervals, the boundaries of the first light shielding pattern enclose the plurality of first through holes, the light transmittance of the light shielding pattern is 0%, and the light transmittance of the first through holes is 100%; The interval between two adjacent first through holes is less than or equal to a first threshold, and the maximum size of each first through hole is less than or equal to the first threshold; the first threshold is 1 / 2 of the resolution of the exposure machine used.

23. The mask plate according to claim 22, wherein: The shape of the first opening area is rectangular, and the side length of the first opening area is greater than or equal to 10 μm; and / or, The interval between two adjacent first opening areas is greater than or equal to 5 μm; and / or, In each first opening area, the interval between two adjacent first through holes is 1.0 μm to 1.5 μm; and / or, The opening shape of the first through hole is a square, and the side length of the first through hole is 1.0 μm to 1.5 μm.

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