Super-lattice castellated field effect transistor (slcfet) switch system
The SLCFET switch system addresses the limitations of SLCFETs in handling high power and high frequency RF signals by using a series stack of SLCFETs, gate resistors, and balancing resistors to achieve low-loss and linear signal propagation.
WO2025064041A1 Publication Date: 2025-03-27NORTHROP GRUMMAN SYSTEMS CORP
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Patent Information
- Application Number
- PCT/US2024/038189
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-22
- Filing Date
- 2024-07-16
- Publication Date
- 2025-03-27
AI Technical Summary
Technical Problem
SLCFETs face limitations in handling high power and high frequency RF signals due to power requirements, signal losses, and non-linearities in existing switching device designs.
Method used
A SLCFET switch system is designed with a series stack of SLCFETs, gate resistors, and balancing resistors to provide a propagation path for RF signals, equalize drain-gate and gate-source voltages, and minimize losses and non-linearities.
Benefits of technology
The system achieves low-loss and linear propagation of high-frequency and high-power RF signals by balancing voltages and compensating for current imbalances, thereby enhancing the operational characteristics of SLCFETs.
✦ Generated by Eureka AI based on patent content.
Abstract
One example includes a super-lattice castellated field effect transistor (SLCFET) system. The system includes a plurality of SLCFETs arranged in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RF) signal between the first port and the second port in response to activation of the SLCFETs. The system also includes a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port to which an activation signal is provided to concurrently activate the SLCFETs. The system further includes a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when activated.
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