Low-latency code fetching from memory
By determining the type of read command based on the contiguity of read operations and utilizing direct memory array or cache reads, the system reduces code fetch latency and power consumption in small computing devices, addressing the high latency issues in NOR flash memory.
WO2025071760A1 Publication Date: 2025-04-03QUALCOMM INC
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Patent Information
- Application Number
- PCT/US2024/040602
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-28
- Filing Date
- 2024-08-01
- Publication Date
- 2025-04-03
AI Technical Summary
Technical Problem
Code fetch latency from NOR flash memory in small computing devices, such as IoT devices, is high due to the protocol used by the NOR flash controller, which affects the performance and efficiency of these devices.
Method used
The implementation of a system that determines the type of read command (legacy or continued-read) based on whether the next read operation is contiguous with the previous one, allowing for data to be read directly from the memory array or from a cache, thereby reducing latency.
Benefits of technology
This approach reduces code fetch latency and power consumption by optimizing read operations, especially in scenarios where read operations are contiguous, thereby enhancing the performance and efficiency of small computing devices.
✦ Generated by Eureka AI based on patent content.
Abstract
A memory device responds to two types of read commands. When the memory device receives a first type of read command, the memory device reads data from a memory array beginning at an address indicated in association with the received read command. When the memory device receives a second type of read command, the memory device begins reading data from a cache in the memory device. Data that is read from the memory array is also stored in the cache.
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