Display panel and manufacturing method therefor, and display apparatus

Abstract

The present disclosure relates to a display panel. The display panel comprises a pixel definition portion, which comprises at least two layers of definition sub-portions that are sequentially stacked in a direction away from a driving backplane, wherein two first blocking electrodes, which are discontinuously distributed, are provided between at least two layers of adjacent definition sub-portions; and a light-emitting layer group between the two first blocking electrodes is broken down or heated by means of applying an alternating current to the two first blocking electrodes, such that the conductivity of the light-emitting layer group located on the pixel definition portion becomes poor, and cannot serve as a channel for carrier migration, thereby avoiding the crosstalk light emission of adjacent light-emitting devices. Further provided in the present disclosure are a manufacturing method for the display panel, and a display apparatus comprising the display panel.

Description

Display panel, manufacturing method thereof, and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311594995.4 filed on November 27, 2023, entitled “Display panel, manufacturing method thereof, and display device”, and the entire contents of the Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0004] OLED (Organic Light Emitting Diode) display panels have been widely used in various display devices. The display panels separate adjacent light-emitting devices by providing pixel defining portions.

[0005] The width of the pixel definition portion becomes narrower as the size of the light-emitting device becomes smaller. When the width of the pixel definition portion is equivalent to the thickness of the light-emitting device, when one light-emitting device is lit, its light-emitting area will expand to the adjacent light-emitting device, causing the display quality to deteriorate.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a manufacturing method thereof, and a display device.

[0009] According to one aspect of the present disclosure, a display panel is provided, comprising a driving backplane, a plurality of pixel electrodes, a pixel definition layer, a light-emitting layer group and a common electrode, wherein the plurality of pixel electrodes are arranged at intervals on one side of the driving backplane; the pixel definition layer is arranged on a side of the plurality of pixel electrodes away from the driving backplane, the pixel definition layer is provided with pixel openings exposing the pixel electrodes, a pixel definition portion is provided between two adjacent pixel openings, the pixel definition portion comprises at least two layers of sub-definition portions stacked in sequence in a direction away from the driving backplane, two first blocking electrodes are provided at intervals between at least two adjacent layers of sub-definition portions; the light-emitting layer group is arranged on a side of the pixel electrode away from the driving backplane, the light-emitting layer group extends to a side of the pixel definition layer away from the driving backplane; the common electrode is arranged on a side of the light-emitting layer group away from the driving backplane.

[0010] In one embodiment of the present disclosure, a partition groove is provided between adjacent pixel electrodes, and two first blocking electrodes are respectively provided on both sides of the partition groove.

[0011] In one embodiment of the present disclosure, one end of the first blocking electrode close to the pixel opening is retracted relative to one end of each layer sub-defining portion close to the pixel opening.

[0012] In one embodiment of the present disclosure, an orthographic projection of the first blocking electrode on the driving backplane does not overlap with an orthographic projection of the pixel electrode on the driving backplane.

[0013] In one embodiment of the present disclosure, the display panel further includes a second blocking electrode disposed in the partition groove, wherein the orthographic projection of the second blocking electrode on the driving backplane does not overlap with the orthographic projection of the first blocking electrode on the driving backplane.

[0014] In one embodiment of the present disclosure, there are multiple second blocking electrodes, and the multiple second blocking electrodes are evenly arranged between the two first blocking electrodes.

[0015] In one embodiment of the present disclosure, the partition groove includes a first groove section and a second groove section which are sequentially away from the drive back plate, the orthographic projection of the second groove section on the drive back plate is located within the orthographic projection of the first groove section on the drive back plate, and the area of ​​the orthographic projection of the second groove section on the drive back plate is smaller than the area of ​​the orthographic projection of the first groove section on the drive back plate.

[0016] In one embodiment of the present disclosure, the pixel definition portion includes a first sub-definition portion, a second sub-definition portion and a third sub-definition portion arranged in sequence along a direction away from the driving backplane, and two first blocking electrodes are arranged between the second sub-definition portion and the third sub-definition portion.

[0017] In one embodiment of the present disclosure, the first slot segment includes a first through hole passing through the second sub-defining portion, and the second slot segment includes a second through hole passing through the third sub-defining portion and a third through hole provided between the two first blocking electrodes.

[0018] In one embodiment of the present disclosure, the display panel further includes an encapsulation layer, which is disposed on a side of the common electrode away from the driving backplane.

[0019] In one embodiment of the present disclosure, the display panel further includes a first control electrode, which is disposed on a side of the encapsulation layer away from the driving backplane, and the orthographic projection of the first control electrode on the driving backplane is located within the orthographic projection of the pixel definition portion on the driving backplane.

[0020] In one embodiment of the present disclosure, the first control electrode includes two sub-first control electrodes, which are respectively arranged on both sides of the partition groove, and the orthographic projection of the sub-first control electrode on the driving backplane overlaps with the orthographic projection of the pixel electrode on the driving backplane.

[0021] In one embodiment of the present disclosure, the orthographic projections of the two sub-first control electrodes on the driving backplane overlap with the orthographic projections of the two first blocking electrodes on the driving backplane respectively.

[0022] In one embodiment of the present disclosure, the light-emitting layer group includes a plurality of functional layer groups, and a second control electrode is provided between at least two adjacent functional layer groups.

[0023] In one embodiment of the present disclosure, the second control electrode includes two sub-second control electrodes, which are respectively arranged on both sides of the partition groove, and the orthographic projection of the sub-second control electrode on the driving backplane overlaps with the orthographic projection of the sub-first control electrode on the driving backplane.

[0024] According to another aspect of the present disclosure, a method for manufacturing a display panel is provided, the method comprising:

[0025] Provide driver backplane;

[0026] A plurality of pixel electrodes are formed at intervals on one side of the driving backplane;

[0027] At least two layers of sub-definition parts are sequentially stacked on the pixel electrode in a direction away from the driving backplane, and two first blocking electrodes are spaced apart between two adjacent layers of sub-definition parts, and a pixel opening for exposing the pixel electrode is formed between two adjacent pixel definition parts;

[0028] A light-emitting layer group is formed on a side of the pixel electrode in the pixel opening away from the driving backplane, and the light-emitting layer group extends to a side of the pixel definition portion away from the driving backplane;

[0029] applying an alternating current to the two first blocking electrodes to break down or heat the light-emitting layer group between the two first blocking electrodes, so that the conductivity of the light-emitting layer group located on the pixel defining portion deteriorates;

[0030] A common electrode is formed on a side of the light emitting layer group away from the driving backplane.

[0031] According to yet another aspect of the present disclosure, a display device is provided, comprising the display panel provided in any one aspect of the present disclosure.

[0032] The display panel disclosed herein includes a pixel definition portion, at least two layers of sub-definition portions stacked in sequence along a direction away from a driving backplane, and two first blocking electrodes intermittently distributed are provided between at least two adjacent sub-definition portions. By applying alternating current to the two first blocking electrodes, the light-emitting layer group between the two first blocking electrodes is broken down or heated, so that the conductivity of the light-emitting layer group located on the pixel definition portion deteriorates and can no longer serve as a channel for carrier migration, thereby avoiding crosstalk illumination of adjacent light-emitting devices.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0035] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when crosstalk occurs between two adjacent sub-pixels.

[0036] 2 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when a first blocking electrode is disposed between the second sub-defining portion and the third sub-defining portion, and the thickness of the polarizing layer is greater than the thickness of the protective adhesive.

[0037] FIG3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when two first blocking electrodes are disposed on both sides of a partition groove.

[0038] FIG4 is another cross-sectional schematic diagram of the display panel according to an embodiment of the present disclosure when two first blocking electrodes are disposed on both sides of the partition groove.

[0039] FIG5 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the edge of the first groove segment is retracted relative to the edge of the second groove segment.

[0040] FIG6 is a schematic cross-sectional view of the display panel according to the embodiment of the present disclosure when corresponding voltages are applied to two first blocking electrodes.

[0041] 7 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when one end of the first blocking electrode close to the pixel opening is retracted relative to one end of each layer sub-defining portion close to the pixel opening.

[0042] 8 is a schematic cross-sectional view of the display panel according to an embodiment of the present disclosure when the orthographic projection of the first blocking electrode on the driving backplane does not overlap with the orthographic projection of the pixel electrode on the driving backplane.

[0043] FIG9 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when a second blocking electrode is disposed in the partition groove.

[0044] FIG10 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when two second blocking electrodes are disposed in the partition groove.

[0045] FIG11 is a schematic cross-sectional view of the display panel according to an embodiment of the present disclosure when a first control electrode is provided on a side of the encapsulation layer away from the driving backplane.

[0046] FIG12 is a schematic diagram showing the distribution of electrons in the light-emitting layer group according to an embodiment of the present disclosure under a first control electric field formed by direct current.

[0047] FIG13 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the first control electrode includes two sub-first control electrodes.

[0048] FIG14 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the second control electrode includes two sub-second control electrodes.

[0049] FIG15 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0051] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0052] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0053] As shown in Figure 1, OLED (Organic Light Emitting Diode) display panels have been widely used in various display devices. The OLED display panel includes a pixel definition layer (PDL), which is provided with a pixel opening 2101 exposing a pixel electrode 221. The pixel definition portion 21 is located between two adjacent pixel openings 2101. Different light-emitting devices 22 are separated by the pixel definition portion 21, but the light-emitting layer group 223 and the common electrode 222 are connected across the pixel definition portion 21 on adjacent pixel electrodes 221.

[0054] The width of the pixel definition portion 21 becomes narrower as the size of the light-emitting device 22 becomes smaller. When the width of the pixel definition portion 21 is equivalent to the thickness of the light-emitting device 22, the lateral transmission distance of the carriers is not much different from the longitudinal transmission distance. Under the action of the electric field between the pixel electrode 221 of one light-emitting device 22 and the common electrode 222 area of ​​another light-emitting device 22, the carriers are transmitted obliquely, forming an oblique light-emitting path. In this case, when a light-emitting device 22 is lit, the light-emitting area of ​​the light-emitting device 22 will expand onto the pixel definition portion, and even onto the adjacent light-emitting device 22, causing crosstalk between the two adjacent sub-pixels, affecting the display quality. It should be noted that the horizontal direction refers to the direction parallel to the display surface, and the vertical direction refers to the thickness direction of the display panel.

[0055] Based on this, embodiments of the present disclosure provide a display panel that can prevent color crosstalk between different sub-pixels. As shown in Figures 2 to 12, the display panel includes a driving backplane 1, a plurality of pixel electrodes 221, a pixel definition layer, a light-emitting layer group 223, and a common electrode 222. The plurality of pixel electrodes 221 are spaced apart on one side of the driving backplane 1. The pixel definition layer is disposed on a side of the plurality of pixel electrodes 221 away from the driving backplane 1. The pixel definition layer is provided with pixel openings 2101 that expose the pixel electrodes 221. A pixel definition portion 21 is formed between two adjacent pixel openings 2101. The pixel definition portion 21 includes at least two layers of sub-definition portions stacked sequentially in a direction away from the driving backplane 1. Two first blocking electrodes 31 are spaced apart between at least two adjacent layers of sub-definition portions. The light-emitting layer group 223 is disposed on a side of the pixel electrodes 221 away from the driving backplane 1, extending to the side of the pixel definition layer away from the driving backplane 1. The common electrode 222 is disposed on a side of the light-emitting layer group 223 away from the driving backplane 1.

[0056] The pixel definition portion 21 comprises at least two layers of sub-definition portions stacked in sequence in a direction away from the driving backplane 1, and two first blocking electrodes 31 are intermittently distributed between at least two adjacent sub-definition portions. By applying alternating current to the two first blocking electrodes 31, the light-emitting layer group 223 between the two first blocking electrodes 31 is broken down or heated, so that the conductivity of the light-emitting layer group 223 located on the pixel definition portion 21 deteriorates and can no longer serve as a channel for carrier migration, thereby avoiding crosstalk illumination of adjacent light-emitting devices 22.

[0057] The display panel involved in the present disclosure is described in detail below with reference to specific embodiments.

[0058] As shown in Figures 2 to 4, the display panel includes a pixel layer 2, which may include a plurality of light-emitting devices 22. The light-emitting devices 22 may include a pixel electrode 221, a common electrode 222, and a light-emitting layer group 223. The pixel electrode 221 may be an anode of the light-emitting device 22, and the common electrode 222 may be a cathode of the light-emitting device 22. The pixel electrodes 221 of different light-emitting devices 22 are disconnected and insulated from each other in a plane, and the pixel electrodes 221 of all light-emitting devices 22 constitute a first conductive layer. The common electrodes 222 of different light-emitting devices 22 are an integrated structure, that is, the common electrodes 222 of different light-emitting devices 22 are a continuous and smooth structure formed by the same conductive material layer, and the common electrodes 222 of all light-emitting devices 22 constitute a second conductive layer, and there is no interface between different regions in the second conductive layer. The light-emitting layer group 223 is arranged between the first conductive layer and the second conductive layer.

[0059] One of the pixel electrode 221 and the common electrode 222 is a reflective electrode, and the other is a semi-transparent and semi-reflective electrode. Regardless of whether the pixel electrode 221 is set as a transparent electrode or a semi-transparent electrode, or the common electrode 222 is set as a transparent electrode or a semi-transparent electrode, light is emitted from the transparent electrode or the semi-transparent electrode. It can be understood that one of the first conductive layer and the second conductive layer is reflective, and the other is semi-transparent or translucent. For example, the pixel electrode 221 and the common electrode 222 in the first light-emitting device 2201 form a microcavity, which can make the distance from each light-emitting material layer 2231 to the reflective layer and the wavelength of the light emitted by the light-emitting material layer 2231 satisfy 2Δ=mλ (m=1, 2, 3, ...), where Δ is the optical path, and the optical path is equal to the refractive index of the medium multiplied by the distance the light propagates in the medium multiplied by the refractive index of the medium, so that the emitted light and the reflected light resonate in the microcavity, thereby improving the purity of the light emission and further improving the color gamut and light brightness of the display panel.

[0060] Exemplarily, the first conductive layer is a high work function material, for example, also having high reflectivity, such as a stacked structure of Ti / Al / Ti / Mo, wherein metallic titanium can serve as a buffer layer to improve interlayer adhesion, Al serves as a highly reflective material, and Mo serves as a high work function material that directly contacts the organic functional layer to improve carrier injection capability.

[0061] Exemplarily, the material of the second conductive layer is a conductive material with low work function and high transmittance, for example, it can be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., or it can be a transparent nano-conductive material such as carbon nanotubes, graphene, nano silver wires, etc.

[0062] The display panel also includes a driving backplane 1, which includes a base substrate 10 and a driving circuit layer 100. For the sake of clarity, FIG4 only shows the first sub-pixel area and the second sub-pixel area adjacent to the pixel layer 2, and for each sub-pixel area, only the light-emitting element and the transistor 11 directly connected to the light-emitting element in the driving circuit layer 100 are shown. For example, the transistor 11 can be a driving transistor configured to control the magnitude of the current driving the light-emitting element to emit light. For example, the transistor 11 can also be a light-emitting control transistor for controlling whether the current driving the light-emitting element to emit light flows. The embodiments of the present disclosure are not limited to this.

[0063] As shown in FIG4 , the driving backplane 1 includes a base substrate 10, a first conductive layer, an organic functional layer, and a second conductive layer disposed on the base substrate 10. The organic functional layer includes a carrier injection layer 229. The first conductive layer includes a pixel electrode 221 of a first light-emitting device 2201 and a pixel electrode 221 of a second light-emitting device 2202, which are insulated from each other and located in a first sub-pixel region and a second sub-pixel region, respectively. The pixel electrodes 221 of the first light-emitting device 2201 and the pixel electrodes 221 of the second light-emitting device 2202 are disconnected from each other. The second conductive layer includes a common electrode 222 of the first light-emitting device 2201 and a common electrode 222 of the second light-emitting device 2202, which are connected to each other and located in the first sub-pixel region and the second sub-pixel region, respectively.

[0064] The display panel provided in the embodiments of the present disclosure uses a silicon substrate as the base substrate 10. The driving circuit layer 100 can be integrated on the silicon substrate to form a driving backplane 1. In this case, the silicon-based circuit can achieve higher precision. The first and second light-emitting elements are formed on the driving backplane 1. The driving backplane 1 includes the base substrate 10 and the driving circuit layer 100 formed on the base substrate 10. The silicon substrate is, for example, single crystal silicon or high-purity silicon.

[0065] The driving circuit layer 100 is formed on the base substrate 10 through a semiconductor process. For example, an active layer 112 (i.e., a semiconductor layer), a first source electrode 113, and a drain electrode 114 of the transistor 11 are formed in the base substrate 10 through a doping process. An insulating layer 15 is formed through a silicon oxidation process, and multiple third conductive layers 16 are formed through a sputtering process. The semiconductor layer of the transistor 11 (such as the active layer in FIG. 4 ) is located within the base substrate 10 or is part of the base substrate 10.

[0066] The first light-emitting device 2201 is electrically connected to the first transistor 12, and the second light-emitting device 2202 is electrically connected to the second transistor 13. The embodiments of the present disclosure do not limit the specific types of the first transistor 12 and the second transistor 13. The following is an exemplary description of the first transistor 12, which also applies to the second transistor 13 and is therefore not repeated here.

[0067] The pixel electrode 221 of the first light-emitting element is formed on the surface of the driving backplane 1 and is electrically connected to the first source electrode 113 of the first transistor 12 through a contact hole 14 filled with a conductive material (e.g., tungsten) and the multiple conductive layers. FIG4 exemplarily shows one insulating layer 15 and two third conductive layers 16, but the embodiments of the present disclosure do not limit the number of insulating layers 15 and conductive layers.

[0068] For example, the first transistor 12 includes a gate 111, a gate insulating layer 115, an active layer 112, a first source 113, and a drain 114. The embodiments of the present disclosure do not limit the type, material, and structure of the first transistor 12. For example, it can be a top-gate type, a bottom-gate type, etc. The active layer 112 of the first transistor 12 can be an inorganic semiconductor material such as microcrystalline silicon, amorphous silicon, polycrystalline silicon (low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), an oxide semiconductor (such as IGZO), or an organic material such as PBTTT, PDBT-co-TT, PDQT, PDVT-10, dinaphtho-dithiophene (DNTT), or pentacene. For example, the first transistor 12 can be N-type or P-type.

[0069] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin film transistors, field effect transistors or other switching devices with the same characteristics. Some embodiments of the present disclosure are described by taking a field effect transistor (such as a MOS field effect transistor) formed in a silicon substrate as an example. In this example, the silicon substrate is doped (p-type doping or n-type doping) to form an active layer of the transistor, that is, the active layer of the transistor is located in the silicon substrate, or the active layer of the transistor is part of the silicon substrate. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, for example, one of the poles can be directly described as the first source 113 and the other pole as the drain 114.

[0070] Some embodiments of the present disclosure are described by taking a field effect transistor (such as a MOS field effect transistor) formed in a silicon substrate as an example. In this example, the silicon substrate is doped (p-type doping or n-type doping) to form an active layer 112 of the transistor, that is, the active layer 112 of the transistor is located in the silicon substrate, or the active layer 112 of the transistor is part of the silicon substrate. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, for example, one of the poles can be directly described as the first source 113 and the other pole as the drain 114.

[0071] The topmost conductive layer in the driving backplane 1 can be reflective, for example, a stacked structure of titanium / titanium nitride / aluminum. For example, the conductive layer includes a plurality of sub-layers arranged at intervals, which are respectively arranged in one-to-one correspondence with the plurality of pixel electrodes 221 included in the first conductive layer. In the top emission structure, the conductive layer can be set as a reflective layer to reflect the light emitted by the light-emitting element to improve the light extraction efficiency. For example, the orthographic projection of each electrode in the first conductive layer on the base substrate 10 falls within the orthographic projection of the portion of the conductive layer corresponding to the electrode on the base substrate 10. In this case, the first conductive layer can adopt a transparent conductive oxide material with a high work function, such as ITO, IZO, IGZO, AZO, etc.

[0072] The first light-emitting device 2201 is disposed in the first sub-pixel region, and the second light-emitting device 2202 is disposed in the second sub-pixel region. Both the first light-emitting device 2201 and the second light-emitting device 2202 include a light-emitting layer group 223, as well as a pixel electrode 221 and a common electrode 222 facing the light-emitting layer group 223. For example, the first light-emitting device 2201 and the second light-emitting device 2202 may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), etc. The present disclosure does not limit the type of light-emitting element. For example, the light-emitting layer group 223 may be a small molecule organic material or a polymer organic material.

[0073] For example, the first light-emitting device 2201 and the second light-emitting device 2202 are top-emitting structures, and the pixel electrode 221 and the common electrode 222 are reflective. For example, the pixel electrode 221 includes a first pixel electrode layer 2211, and a material with high work function and high reflectivity serves as the first pixel electrode layer 2211, such as a stacked structure of Ti / Al / Ti / Mo, wherein metallic titanium can serve as a buffer layer to improve the adhesion between the layers, Al serves as a highly reflective material, and Mo serves as a high work function material that directly contacts the organic functional layer to improve the carrier injection capability. Accordingly, the second conductive layer serves as a cathode, for example, the second conductive layer can be a transparent conductive material or a stacked structure of a transparent conductive material and a metal material. For example, the second conductive layer can be a transparent metal oxide conductive material, such as indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), etc., or can be a transparent nano-conductive material such as carbon nanotubes, graphene, and nano silver wires.

[0074] In order to better ensure the setting accuracy of the sub-pixels, a pixel definition layer is provided on the side of the pixel electrode 221 away from the base substrate 10. The pixel definition layer is provided with a pixel opening 2101 that exposes the pixel electrode. The position and size of each sub-pixel are defined by the pixel opening 2101 to better control the accuracy of each sub-pixel. Different light-emitting devices are controlled to emit light by the driving circuit layer 100, so that the pixel layer 2 realizes the function of image display. Specifically, the source can be connected to the pixel electrode 221 of the light-emitting device, and the light-emitting device can be driven to emit light by applying a signal to the pixel electrode 221. The specific light-emitting principle will not be described in detail here. At least some of the light-emitting devices can adopt any of the above-mentioned stacked electroluminescent devices, and their structure and materials have been described in detail, so they will not be repeated here.

[0075] Between two adjacent pixel openings 2101 is a pixel defining portion 21. The pixel defining portion 21 includes a first sub-defining portion 211, a second sub-defining portion 212, and a third sub-defining portion 213, which are sequentially arranged in a direction away from the substrate 10. The first sub-defining portion 211, the second sub-defining portion 212, and the third sub-defining portion 213 have a relatively large dielectric constant and may be made of silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide. The materials of the first sub-defining portion 211, the second sub-defining portion 212, and the third sub-defining portion 213 may be different. For example, the second sub-defining portion 212 and the third sub-defining portion 213 may be made of silicon oxide, while the first sub-defining portion 211 may be made of silicon nitride. Two first blocking electrodes 31 are provided between the second sub-defining portion 212 and the third sub-defining portion 213. The two first blocking electrodes 31 are spaced apart along the first direction to form a blocking circuit. In order to ensure the flatness of the pixel defining portion 21 , a filling portion 23 is provided between the two pixel electrodes 221 to ensure the flatness of the first sub-defining portion 211 .

[0076] A light-emitting layer group 223 is provided on the side of the pixel electrode away from the driving backplane 1. The light-emitting layer group 223 extends from the side of the pixel definition portion 21 to the side of the pixel definition portion 21 away from the driving backplane 1. A common electrode 222 is formed on the side of the light-emitting layer group 223 away from the driving backplane 1. Alternating current is applied to the two first blocking electrodes 31 of the blocking circuit, breaking down or heating the light-emitting layer group 223 on the pixel definition portion 21. This degrades the conductivity of the light-emitting layer group 223 located on the pixel definition portion 21, making it unable to serve as a channel for carrier migration. Carriers injected from the pixel electrode 221 of a light-emitting device cannot migrate laterally across the pixel definition portion 21 to the common electrode region of another adjacent light-emitting device, thereby preventing crosstalk between adjacent light-emitting devices.

[0077] To enhance the blocking effect on the light-emitting layer group 223, a partitioning groove 2102 can be provided between adjacent pixel electrodes, with two first blocking electrodes 31 positioned on either side of the partitioning groove 2102. This allows the light-emitting layer group 223 to enter between the two first blocking electrodes 31, effectively breaking down or heating the light-emitting layer group 223 on the pixel definition portion 21. Furthermore, the light-emitting layer group 223 is disconnected within the partitioning groove 2102, reducing the probability of carrier transmission within the light-emitting layer group 223 on the pixel definition portion 21.

[0078] The partitioning groove 2102 may include a first groove section 2103 and a second groove section 2104, which are sequentially spaced away from the driver backplane 1. The first groove section 2103 may include a first through hole extending through the second sub-defining portion 212. The second groove section 2104 may include a second through hole extending through the third sub-defining portion 213 and a third through hole disposed between the two first blocking electrodes. The first through hole, the second through hole, and the third through hole may be formed separately after forming the first sub-defining portion 211, the second sub-defining portion 212, the first blocking electrode layer, and the third sub-defining portion 213 in a sequentially stacked manner. This method is easier to form the partitioning groove than forming the first sub-defining portion 211, the second sub-defining portion 212, and the first blocking electrode on both sides of the partitioning groove separately.

[0079] As shown in Figures 2 to 4, the orthographic projection of the second slot segment 2104 on the drive backplane 1 overlaps with the orthographic projection of the first slot segment 2103 on the drive backplane 1, and the area of ​​the orthographic projection of the second slot segment 2104 on the drive backplane 1 can be equal to the area of ​​the orthographic projection of the first slot segment 2103 on the drive backplane 1. As shown in Figures 5 and 6, in order to improve the partitioning effect of the partition slot 2102, the edge of the first slot segment 2103 can be set to be retracted relative to the edge of the second slot segment 2104, that is, the orthographic projection of the second slot segment 2104 on the drive backplane 1 is located within the orthographic projection of the first slot segment 2103 on the drive backplane 1, and the area of ​​the orthographic projection of the second slot segment 2104 on the drive backplane 1 is smaller than the area of ​​the orthographic projection of the first slot segment 2103 on the drive backplane 1.

[0080] As shown in Figure 7, because the distance between the two first blocking electrodes 31 is small, carriers generated by the pixel electrode 221 of one light-emitting device 22 are transmitted along the side of the light-emitting layer group 223 to the first blocking electrode 31 closer to it, then to the other first blocking electrode 31 farther from the pixel electrode 221, and then to the common electrode region of the other light-emitting device 22, forming a new leakage path, causing the other light-emitting device 22 to emit light. To prevent carriers from being transmitted laterally through the two first blocking electrodes 31, which could cause crosstalk between two adjacent sub-pixels, the end of the first blocking electrode 31 near the pixel opening 2101 is retracted relative to the ends of the first sub-defining portion 211, the second sub-defining portion 212, and the third sub-defining portion 213 near the pixel opening 2101. This allows the third sub-defining portion 213 to cover the end of the first blocking electrode 31 near the pixel opening 2101, preventing carriers generated by the pixel electrode 221 from being transmitted along the side of the light-emitting layer group 223 to the first blocking electrode 31 closer to it.

[0081] As shown in Figure 8, in order to further enhance the isolation effect between the first blocking electrode 31 and the pixel electrode 221, the retraction distance of the end of the first blocking electrode 31 close to the pixel opening 2101 is increased relative to the end of the first sub-definition portion 211, the second sub-definition portion 212 and the third sub-definition portion 213 close to the pixel opening 2101, and the orthographic projection of the first blocking electrode 31 on the base substrate 10 does not overlap with the orthographic projection of the pixel electrode 221 on the base substrate 10, thereby preventing carriers from being transmitted from the overlapping area between the pixel electrode 221 and the first blocking electrode 31, and completely blocking the carrier transmission path between the pixel electrode 221 and the first blocking electrode 31.

[0082] As shown in FIG9 , the display panel may further include a second blocking electrode 32 disposed within the partition groove 2102 . The orthographic projection of the second blocking electrode 32 on the driving backplane 1 does not overlap with the orthographic projection of the first blocking electrode 31 on the driving backplane 1 . The two first blocking electrodes 31 can each form a blocking circuit with the second blocking electrode 32 . The two blocking circuits are connected in parallel to form a total circuit. Applying alternating current to the total circuit reduces the distance between the two blocking electrodes in the blocking circuit, increases the strength of the blocking electric field, and thereby enhances the effect of breaking down or heating the light-emitting layer group 223 on the pixel defining portion 21 .

[0083] As shown in FIG10 , there are multiple second blocking electrodes 32, each of which is evenly spaced between the two first blocking electrodes 31. In this embodiment, there are two second blocking electrodes 32. One second blocking electrode 32 can form a blocking circuit with one first blocking electrode 31, and another second blocking electrode 32 can form another blocking circuit with another first blocking electrode 31. Alternating current can be applied to each of the two blocking circuits, further reducing the distance between the two blocking electrodes in the blocking circuit, increasing the strength of the blocking electric field, and enhancing the effect of breaking down or heating the light-emitting layer group 223 on the pixel defining portion 21.

[0084] As shown in Figure 11, the light-emitting layer group 223 within the pixel opening 2101 forms the normal light-emitting area 202. However, the light-emitting layer groups 223 located on both sides of the partition groove 2102 may also form light leakage areas 201. The provision of a blocking circuit can block the transmission of carriers from the light-emitting layer group 223 within the partition groove 2102 of the pixel definition portion 21. The display panel also includes an encapsulation layer 5, which is disposed on the side of the common electrode 222 away from the driving backplane 1. A first control electrode 41 is disposed on the side of the encapsulation layer 5 away from the driving backplane 1. The orthographic projection of the first control electrode 41 on the driving backplane 1 is located within the orthographic projection of the pixel definition portion 21 on the driving backplane 1. The material of the first control electrode 41 can be metal, conductive oxide, or conductive polymer.

[0085] A corresponding voltage is applied to the first control electrode 41, forming a first control electric field between the first control electrode 41 and the pixel electrode. The direction and strength of the first control electric field control the lateral conduction characteristics of the light-emitting layer group 223 between the first control electrode 41 and the pixel electrode, thereby preventing carrier migration toward the light leakage region 201 and controlling the emission of light from the light leakage region 201. Even if the light leakage region 201 cannot be completely prevented from emitting light, differential control of the light leakage region 201 of different light-emitting devices can compensate for inconsistent light emission intensity in the light leakage region 201 caused by differences in the overlap area between the pixel electrode and the pixel defining portion 21, as well as differences in the edge morphology of the pixel defining portion 21, thereby improving display uniformity.

[0086] As shown in Figure 12, under the action of the first control electric field, the electrons are distributed in area a in Figure 12, and do not exceed the positive projection area of ​​the pixel electrode of the light-emitting device on the first control electrode 41, blocking the migration of electrons along the x-direction. For different carrier concentrations and carrier types, electric fields of corresponding directions and intensities are applied to adjust the control area of ​​the first control electric field to control the lateral migration characteristics of the carriers. The stronger the first control electric field from the pixel electrode to the first control electrode 41, the stronger the control ability for electrons. Conversely, the stronger the first control electric field from the first control electrode 41 to the pixel electrode, the stronger the control ability for holes.

[0087] As shown in FIG13 , the first control electrode 41 includes two sub-first control electrodes 411, which are respectively disposed on either side of the partition groove 2102. The orthographic projections of the sub-first control electrodes 411 on the driver backplane 1 overlap with the orthographic projections of the pixel electrodes on the driver backplane 1. By overlapping the two sub-first control electrodes 411 with the two pixel electrodes, two sub-first control electric fields are formed, which control the light leakage regions 201 of different light-emitting devices separately. This prevents the portion of the first control electrode 41 located between the two pixel electrodes from forming a control region, which could cause carriers to migrate to the light leakage region 201 of another light-emitting device.

[0088] The orthographic projection of the sub-first control electrode 411 on the driving backplane 1 overlaps with the orthographic projection of the first blocking electrode 31 on the driving backplane 1. A second control electric field can be formed between the sub-first control electrode 411 and the first blocking electrode 31. The distance between the sub-first control electrode 411 and the first blocking electrode 31 is smaller than the distance between the sub-first control electrode 411 and the pixel electrode. Therefore, the intensity of the second control electric field is greater than that of the first control electric field, and the ability to control the lateral migration characteristics of carriers is also stronger.

[0089] As shown in Figure 14, the light-emitting layer group 223 includes multiple functional layer groups, wherein a second control electrode 42 is disposed between two adjacent functional layer groups. Similar to the arrangement of the first control electrode 41, the second control electrode 42 includes two sub-second control electrodes 421, one disposed on either side of the partition groove 2102. The orthographic projections of the sub-second control electrodes 421 on the driver backplane 1 overlap with the orthographic projections of the sub-first control electrode 411 on the driver backplane 1. When the light-emitting layer group 223 includes a large number of functional layer groups, a second control electrode 42 can be disposed between each two functional layer groups. A third control electric field can be formed between the sub-second control electrode 421 and the sub-first control electrode 411, and another third control electric field can be formed between the sub-second control electrode 421 and the first blocking electrode 31. These two third control electric fields can be used to perform differentiated electric field modulation on the functional layer groups in the light-emitting layer group 223.

[0090] The present disclosure also provides a method for manufacturing a display panel. As shown in FIG15 , the method includes:

[0091] Step S10, providing a driving backplane;

[0092] Step S20, forming a plurality of pixel electrodes at intervals on one side of the driving backplane;

[0093] Step S30, forming at least two layers of sub-definition portions stacked sequentially on the pixel electrode in a direction away from the driving backplane, and two first blocking electrodes spaced apart between two adjacent layers of sub-definition portions, and forming a pixel opening between two adjacent pixel definition portions to expose the pixel electrode;

[0094] Step S40, forming a light-emitting layer group on a side of the pixel electrode in the pixel opening away from the driving backplane, and extending the light-emitting layer group to a side of the pixel definition portion away from the driving backplane;

[0095] Step S50, applying alternating current to the two first blocking electrodes to break down or heat the light-emitting layer group between the two first blocking electrodes, so that the conductivity of the light-emitting layer group located on the pixel defining portion deteriorates;

[0096] Step S60: forming a common electrode on a side of the light-emitting layer group away from the driving backplane.

[0097] The beneficial effects of this manufacturing method can be referenced to those of the display panel and will not be further elaborated here. After depositing the light-emitting layer group, an alternating current is applied to the two first blocking electrodes 31, breaking down or heating the light-emitting layer group between the two first blocking electrodes 31. This degrades the conductivity of the light-emitting layer group located above the pixel defining portion 21, thereby blocking the path for carrier migration during the display panel manufacturing process. Compared to processing the light-emitting layer group between the two first blocking electrodes 31 after the display panel is manufactured, this method eliminates the need for a secondary process, making it more convenient and efficient.

[0098] The present disclosure also provides a display device, which may include any of the display modules mentioned above. The structure and beneficial effects of the display device can be referred to the display module and will not be described in detail here.

[0099] It should be noted that, in addition to the display module, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0100] The display device can be a traditional electronic device, such as a mobile phone, a watch, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as VR glasses, which are not listed here one by one.

[0101] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein: include: Driver backplane; A plurality of pixel electrodes are arranged at intervals on one side of the driving backplane; A pixel definition layer is provided on a side of the plurality of pixel electrodes away from the driving backplane, the pixel definition layer is provided with a pixel opening exposing the pixel electrode, a pixel definition portion is provided between two adjacent pixel openings, the pixel definition portion includes at least two layers of sub-definition portions stacked in sequence in a direction away from the driving backplane, and two first blocking electrodes are provided between at least two adjacent layers of sub-definition portions. A light-emitting layer group is disposed on a side of the pixel electrode away from the driving backplane, and the light-emitting layer group extends to a side of the pixel definition layer away from the driving backplane; The common electrode is arranged on a side of the light emitting layer group away from the driving backplane.

2. The display panel according to claim 1, wherein: A partition groove is provided between adjacent pixel electrodes, and two first blocking electrodes are respectively provided on both sides of the partition groove.

3. The display panel according to claim 1 or 2, wherein: One end of the first blocking electrode close to the pixel opening is retracted relative to one end of each layer of the sub-definition portion close to the pixel opening.

4. The display panel according to claim 3, wherein: The orthographic projection of the first blocking electrode on the driving backplane does not overlap with the orthographic projection of the pixel electrode on the driving backplane.

5. The display panel according to claim 2, wherein: The display panel further includes a second blocking electrode, which is disposed in the partition groove, and an orthographic projection of the second blocking electrode on the driving backplane does not overlap with an orthographic projection of the first blocking electrode on the driving backplane.

6. The display panel according to claim 5, wherein: There are multiple second blocking electrodes, and the multiple second blocking electrodes are evenly arranged between two first blocking electrodes.

7. The display panel according to claim 2, wherein: The partition groove includes a first groove section and a second groove section which are successively away from the driving back plate, the orthographic projection of the second groove section on the driving back plate is located within the orthographic projection of the first groove section on the driving back plate, and the area of ​​the orthographic projection of the second groove section on the driving back plate is smaller than the area of ​​the orthographic projection of the first groove section on the driving back plate.

8. The display panel according to claim 7, wherein: The pixel defining portion includes a first sub-defining portion, a second sub-defining portion and a third sub-defining portion which are sequentially arranged in a direction away from the driving backplane, and the two first blocking electrodes are arranged between the second sub-defining portion and the third sub-defining portion.

9. The display panel according to claim 8, wherein: The first slot segment includes a first through hole penetrating the second sub-defining portion, and the second slot segment includes a second through hole penetrating the third sub-defining portion and a third through hole disposed between the two first blocking electrodes.

10. The display panel according to claim 2, wherein: The display panel further comprises an encapsulation layer, and the encapsulation layer is arranged on a side of the common electrode away from the driving backplane.

11. The display panel according to claim 10, wherein: The display panel further includes a first control electrode, which is disposed on a side of the encapsulation layer away from the driving backplane, and an orthographic projection of the first control electrode on the driving backplane is located within an orthographic projection of the pixel definition portion on the driving backplane.

12. The display panel according to claim 11, wherein: The first control electrode includes two sub-first control electrodes, which are respectively arranged on both sides of the partition groove, and the orthographic projection of the sub-first control electrode on the driving backplane overlaps with the orthographic projection of the pixel electrode on the driving backplane.

13. The display panel according to claim 12, wherein: The orthographic projections of the two sub-first control electrodes on the driving backplane overlap with the orthographic projections of the two first blocking electrodes on the driving backplane respectively.

14. The display panel according to claim 12, wherein: The light-emitting layer group includes a plurality of functional layer groups, and a second control electrode is disposed between at least two adjacent functional layer groups.

15. The display panel according to claim 14, wherein: The second control electrode includes two sub-second control electrodes, which are respectively arranged on both sides of the partition groove, and the orthographic projection of the sub-second control electrode on the driving backplane overlaps with the orthographic projection of the sub-first control electrode on the driving backplane.

16. A method for manufacturing a display panel, wherein: The method comprises: Provide drive backplane; A plurality of pixel electrodes are formed at intervals on one side of the driving backplane; At least two layers of sub-definition parts are sequentially stacked on the pixel electrode in a direction away from the driving backplane, and two first blocking electrodes are spaced apart between two adjacent layers of sub-definition parts, and a pixel opening exposing the pixel electrode is formed between two adjacent pixel definition parts; A light-emitting layer group is formed on a side of the pixel electrode in the pixel opening away from the driving backplane, and the light-emitting layer group extends to a side of the pixel definition portion away from the driving backplane; Applying alternating current to the two first blocking electrodes to break down or heat the light-emitting layer group between the two first blocking electrodes, so that the conductivity of the light-emitting layer group located on the pixel definition portion becomes poor; A common electrode is formed on a side of the light emitting layer group away from the driving backplane.

17. A display device, wherein: A display panel comprising any one of claims 1 to 15.

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