Power conversion device

Abstract

This power conversion device comprises: a delta connection cascade-type three-phase MMC power converter; and a control device (3) for controlling the power converter. In the control device (3), a phase voltage balance control unit (30) calculates an arm current command value (Iuv*, Ivw*, Iwu*) of each arm and a circulating current command value (Iz*) so that the difference between a representative value of voltage of a power storage element included in each arm and a representative value of voltage of power storage elements included in all arms becomes small. A reverse phase current command value calculation unit (40) calculates reverse phase current command values (Idn*, Iqn*) on the basis of the arm current command values and the circulating current command value. The phase voltage balance control unit (30) is configured to limit the magnitude of the arm current command values and the circulating current command value.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] A modular multilevel converter (MMC), in which multiple unit converters (hereinafter referred to as "converter cells") are cascaded, is known as a large-capacity power conversion device installed in a power system. The MMC has multiple arms, each configured with multiple cascaded converter cells and a series-connected reactor. A three-phase delta-connected cascade converter used as a reactive power compensator has three delta-connected arms and is connected in parallel to an AC power system via a reactor or a transformer.

[0003] Since MMCs have capacitors in each converter cell, voltage variations between capacitors can cause imbalances in the capacitor voltages between phases. When the capacitor voltages between phases become unbalanced, there is a concern that the control characteristics of the MMC may deteriorate due to unintended circulating currents, etc. Therefore, phase balance control of capacitor voltages to suppress this imbalance is important.

[0004] A particular problem with MMC-configured delta-connection reactive power compensators occurs when unbalanced voltages occur in a three-phase power system. For example, if the impedance of the transmission and distribution network is unbalanced in three phases or if a single-phase load is connected to the load, the three-phase voltage at the interconnection point becomes unbalanced. Furthermore, if a system fault occurs, such as a one-phase earth fault, a two-phase earth fault, or a line-to-line short circuit, an even larger unbalanced voltage occurs. Even when the system voltage becomes unbalanced, an MMC-configured delta-connection reactive power compensator is required to maintain its most basic function as a reactive power compensator—outputting positive-sequence reactive current. Therefore, to ensure continuous operation, the capacitor voltage of each converter cell must be maintained constant.

[0005] Japanese Patent No. 6147363 (Patent Document 1) discloses a method for suppressing imbalance in capacitor voltages between phases due to system unbalance by using circulating current and negative-phase current.

[0006] Patent No. 6147363

[0007] The problem with the technology disclosed in the above-mentioned Japanese Patent No. 6147363 (Patent Document 1) is that increasing the circulating current to suppress imbalance in the capacitor voltages between the phases increases the arm current, which results in an increase in the capacity of the power converter.

[0008] The present disclosure has been made in consideration of the above-mentioned problems, and one of its objectives is to provide a power conversion device with an MMC configuration that can eliminate imbalances in capacitor voltages between phases while suppressing increases in arm currents.

[0009] According to one embodiment, the power conversion apparatus includes a power converter connected to a three-phase AC system and a control device for controlling the power converter. The power converter includes three delta-connected arms, each including a plurality of cascaded converter cells. Each of the converter cells includes an input / output terminal pair, a bridge circuit including a plurality of semiconductor switching elements, and a storage element connected to the input / output terminal pair via the bridge circuit. The control device includes a phase voltage balance control unit, a negative-sequence current command value calculation unit, an output current control unit, a circulating current control unit, a voltage command value calculation unit, and a gate signal generation unit. The phase voltage balance control unit calculates a valve branch current command value and a circulating current command value for each arm so as to minimize a difference between a representative value of the voltage of the storage element included in each arm and a representative value of the voltages of the storage elements included in all arms. The negative-sequence current command value calculation unit calculates a negative-sequence current command value based on the valve branch current command value and the circulating current command value. The output current control unit calculates a voltage command value for controlling the output current of the power converter based on the negative-sequence current command value and the positive-sequence current command value. The power conversion device includes a circulating current control unit that calculates, based on the circulating current command value, a zero-phase-sequence voltage command value for controlling the circulating current based on the detected value of the arm current of each arm. The voltage command value calculation unit calculates, based on the voltage command value and the zero-phase-sequence voltage command value, an output voltage command value to be output to each arm. The gate signal generation unit generates, based on the output voltage command value, a gate signal for controlling on / off of each semiconductor switching element included in each converter cell of each arm. The phase voltage balance control unit is configured to limit the magnitudes of the arm current command value and the circulating current command value, and the magnitude of the negative-phase-sequence current command value calculated by the negative-phase-sequence current command value calculation unit increases according to the amount by which the magnitudes of the arm current command value and circulating current command value of any arm are limited.

[0010] According to the above embodiment, while the increase in the valve branch current is suppressed by limiting the magnitudes of the valve branch current command value and the circulating current command value, the magnitude of the negative-phase current command value increases in accordance with the amount by which the magnitudes of the valve branch current command value and the circulating current command value are limited, so that the imbalance in the capacitor voltages between the phases can be eliminated.

[0011] 1 is a schematic configuration diagram of a power conversion device according to embodiment 1. FIG. 2 is a circuit diagram showing the configuration of a full-bridge type converter cell. FIG. 3 is a circuit diagram showing the configuration of a half-bridge type converter cell. FIG. 4 is a block diagram showing the schematic configuration of the control device of FIG. 1. FIG. 5 is a block diagram showing an example of the configuration of a phase voltage balance control unit of FIG. 4. FIG. 6 is a block diagram showing an example of the configuration of a negative-sequence current command value calculation unit of FIG. 4. FIG. 7 is a block diagram showing an example of the configuration of a circulating current control unit of FIG. 4. FIG. 8 is a block diagram showing an example of the configuration of a DC voltage control unit of FIG. 4. FIG. 9 is a block diagram showing an example of the configuration of an output current control unit of FIG. 4. FIG. 10 is a block diagram showing an example of the configuration of a phase voltage balance control unit included in the control device in a power conversion device according to embodiment 2. FIG. 11 is a diagram showing an example of arm currents of a power converter under unbalanced system voltage conditions when negative-sequence current control is not performed. FIG. 12 is a diagram showing an example of the difference in maximum arm current depending on whether or not negative-sequence current control is performed.

[0012] Each embodiment will be described in detail below with reference to the drawings. The same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

[0013] First Embodiment [Key Points of First Embodiment] In the control device 3 of the power conversion device 1 of the first embodiment, a limiter 34 is provided at the output of the controller 33 of the phase voltage balance control unit 30. This limits the magnitudes of the valve branch current command value and the circulating current command value, thereby making it possible to suppress an increase in the valve branch current. On the other hand, the magnitude of the negative-phase sequence current command value increases in accordance with the amount by which the magnitudes of the valve branch current command value and the circulating current command value of any one of the valve branches are limited, so that the phase voltage balance control function can be maintained.

[0014] 1 is a schematic configuration diagram of a power conversion device 1 according to embodiment 1. The power conversion device 1 includes a delta-connected cascade three-phase MMC power converter 2 and its control device 3. The power converter 2 is also referred to as a STATCOM (Static Synchronous Compensator).

[0015] The power converter 2 includes a transformer 4 and three-phase AC lines UL, VL, and WL. Primary windings of the transformer 4 are connected to U-phase, V-phase, and W-phase transmission lines of an AC power system 9, respectively. Secondary windings of the transformer 4 are connected to first terminals of the AC lines UL, VL, and WL, respectively.

[0016] The power converter 2 functions as a reactive power compensator that injects or absorbs reactive power into the AC power system 9 via the transformer 4. Specifically, when the three-phase AC voltage (hereinafter also referred to as "system voltage") of the AC power system 9 decreases, the power converter 2 injects reactive power into the AC power system 9 so as to increase the system voltage. On the other hand, when the system voltage increases, the power converter 2 absorbs reactive power from the AC power system 9 so as to decrease the system voltage. In other words, the power converter 2 can compensate for reactive power by injecting or absorbing a current that is orthogonal to the system voltage into the AC power system 9.

[0017] The power converter 2 further includes arms A1 to A3. The arm A1 is connected between a second terminal of the U-phase AC line UL and a second terminal of the V-phase AC line VL. The arm A2 is connected between a second terminal of the V-phase AC line VL and a second terminal of the W-phase AC line WL. The arm A3 is connected between a second terminal of the W-phase AC line WL and a second terminal of the U-phase AC line UL. That is, the arms A1 to A3 are connected in a delta connection.

[0018] Note that arms A1 to A3 may be connected in a star connection. In this case, arm A1 is connected between a second terminal of U-phase AC line UL and the common neutral point. Arm A2 is connected between a second terminal of V-phase AC line VL and the common neutral point. Arm A3 is connected between a second terminal of W-phase AC line WL and the common neutral point.

[0019] Each of the arms A1 to A3 has a reactor L (L1 to L3) and n (n is an integer of 2 or more) converter cells 5. Therefore, the power converter 2 has a total of 3n converter cells 5. The n converter cells 5 are connected in series with each other. The reactor L is connected in series with the n converter cells 5 in each arm (A1 to A3) to suppress circulating current flowing in the delta connection.

[0020] Each of the plurality of converter cells 5 performs bidirectional power conversion in accordance with a control signal from the control device 3. An example of the configuration of the converter cell 5 will be described later with reference to FIGS.

[0021] The power conversion device 1 further includes a branch current detector 10 disposed in each branch (A1 to A3), and an AC current detector 11 and an AC voltage detector 12 disposed in the AC power system 9.

[0022] The valve branch current detection unit 10a detects the valve branch current Iuv flowing in the valve branch A1, the valve branch current detection unit 10b detects the valve branch current Ivw flowing in the valve branch A2, and the valve branch current detection unit 10c detects the valve branch current Iwu flowing in the valve branch A3. The AC current detection unit 11 detects the U-phase AC current Iu, the V-phase AC current Iv, and the W-phase AC current Iw of the AC power system 9. That is, the AC current detection unit 11 detects the output current from the power converter 2 to the power conversion device 1. The AC voltage detection unit 12 detects the U-phase AC voltage Vu, the V-phase AC voltage Vv, and the W-phase AC voltage Vw of the AC power system 9. Signals representing these detected currents and voltages are input to the control device 3.

[0023] In FIG. 1, the UV-phase voltage applied to arm A1 is represented by Vuv, the VW-phase voltage applied to arm A2 is represented by Vvw, and the WU-phase voltage applied to arm A3 is represented by Vwu.

[0024] [Configuration Example of Converter Cell 5] Hereinafter, a configuration example of the converter cell 5 will be described with reference to Fig. 2 and Fig. 3. Fig. 2 shows a configuration example of a full-bridge type, and Fig. 3 shows a configuration example of a half-bridge type. The configuration of the converter cell 5 may be a configuration other than that shown in Figs. 2 and 3.

[0025] Fig. 2 is a circuit diagram showing the configuration of a full-bridge converter cell 5. The converter cell 5 in Fig. 2 includes a first series body formed by connecting two semiconductor switching elements Q1 and Q2 in series, a second series body formed by connecting two semiconductor switching elements Q3 and Q4 in series, rectifying elements D1, D2, D3, and D4 (typically diodes), a storage element 17 (typically a capacitor), a voltage detector 18, input / output terminals 16a and 16b, and a driver 19.

[0026] The first series body, the second series body, and the storage element 17 are connected in parallel between the positive electrode line PL and the negative electrode line NL. The rectifying elements D1 and D2 are connected in anti-parallel (i.e., in parallel and in the reverse bias direction) with the semiconductor switching elements Q1 and Q2, respectively. The rectifying elements D3 and D4 are connected in anti-parallel with the semiconductor switching elements Q3 and Q4, respectively. The semiconductor switching elements Q1, Q2, Q3, and Q4 and the rectifying elements D1, D2, D3, and D4 form a full-bridge circuit 15F. The voltage detector 18 detects the voltage Vdccell (also referred to as the capacitor voltage Vdccell) across the storage element 17.

[0027] The midpoints of semiconductor switching elements Q1 and Q2 are connected to input / output terminal 16a. Similarly, the midpoints of semiconductor switching elements Q3 and Q4 are connected to input / output terminal 16b. Therefore, power storage element 17 is connected to input / output terminals 16a and 16b via full-bridge circuit 15F. Converter cell 5 outputs the voltage Vdccell, −Vdccell, or zero voltage of power storage element 17 as output voltage Vcell between input / output terminals 16a and 16b through the switching operations of semiconductor switching elements Q1, Q2, Q3, and Q4.

[0028] Driver 19 is connected to positive electrode line PL and negative electrode line NL, and operates by the voltage of storage element 17. Driver 19 controls the switching of semiconductor switching elements Q1, Q2, Q3, and Q4 by outputting a gate signal Ga to the control electrode G of each of semiconductor switching elements Q1, Q2, Q3, and Q4.

[0029] Fig. 3 is a circuit diagram showing the configuration of a half-bridge type converter cell 5. The converter cell 5 in Fig. 3 includes a series body formed by connecting two semiconductor switching elements Q1 and Q2 in series, rectifying elements D1 and D2, a storage element 17, a voltage detector 18, and input / output terminals 16a and 16b.

[0030] Rectifier elements D1 and D2 are connected in anti-parallel to semiconductor switching elements Q1 and Q2. A series connection of semiconductor switching elements Q1 and Q2 and power storage element 17 are connected in parallel between positive electrode line PL and negative electrode line NL. Voltage detector 18 detects voltage Vdccell across power storage element 17.

[0031] A half-bridge circuit 15H is formed by the series connection of semiconductor switching elements Q1 and Q2 and rectifying elements D1 and D2. Both terminals of semiconductor switching element Q2 are connected to input / output terminals 16a and 16b, respectively. Therefore, a storage element 17 is connected to the input / output terminals 16a and 16b via the half-bridge circuit 15H.

[0032] The converter cell 5 outputs the voltage Vdccell of the storage element 17 or zero voltage between the input / output terminals 16a and 16b through the switching operations of the semiconductor switching elements Q1 and Q2. When the semiconductor switching element Q1 is on and the semiconductor switching element Q2 is off, the converter cell 5 outputs the voltage Vdccell of the storage element 17. When the semiconductor switching element Q1 is off and the semiconductor switching element Q2 is on, the converter cell 5 outputs zero voltage.

[0033] Both terminals of the semiconductor switching element Q1 may be connected to the input / output terminals 16a and 16b, respectively. In this case, the converter cell 5 outputs the voltage Vdccell of the storage element 17 and zero voltage from the input / output terminals 16a and 16b by the on / off operation of the semiconductor switching elements Q1 and Q2.

[0034] Driver 19 is connected to positive electrode line PL and negative electrode line NL, and operates by the voltage of storage element 17. Driver 19 controls the switching of semiconductor switching elements Q1 and Q2 by outputting a gate signal Ga to the control electrode G of each of semiconductor switching elements Q1 and Q2.

[0035] 2 and 3, the semiconductor switching elements Q1, Q2, Q3, and Q4 are configured by self-extinguishing semiconductor switching elements such as insulated gate bipolar transistors (IGBTs) and gate commutated turn-off thyristors (GCTs).

[0036] In the following description, when referring to semiconductor switching elements collectively or any one of them, they will be referred to as semiconductor switching element Q. When referring to rectifying elements collectively or any one of them, they will be referred to as rectifying element D.

[0037] As shown in Fig. 1, the converter cells 5 are cascaded. Therefore, in each of Fig. 2 and Fig. 3, the input / output terminal 16a is connected to the input / output terminal 16b of one adjacent converter cell 5 or the second terminal of one corresponding AC line. The input / output terminal 16b is connected to the input / output terminal 16a of the other adjacent converter cell 5 or the second terminal of the other corresponding AC line.

[0038] [General Configuration of Control Device] Fig. 4 is a block diagram showing a general configuration of the control device 3 of Fig. 1. As shown in Fig. 4, the control device 3 includes a DC voltage control unit 20, a phase voltage balance control unit 30, a negative-phase-sequence current command value calculation unit 40, an output current control unit 50, a circulating current control unit 60, a voltage command value calculation unit 70, and a gate signal generation unit 80. The configurations and operations of these components will be described in more detail below.

[0039] The control device 3 can be configured based on at least one computer including at least one central processing unit (CPU) that operates according to a program and at least one memory. Alternatively, at least a part of the control device 3 can be configured using a programmable logic device (PLD) such as a field programmable gate array (FPGA) and / or a dedicated circuit such as an application specific integrated circuit (ASIC).

[0040] [Phase voltage balance control unit 30] The phasors of arm currents Iuv, Ivw, and Iwu flowing through arms A1, A2, and A3 of the three-phase delta-connection MMC power converter are expressed as the positive-phase component Ip of the output current, the negative-phase component In of the output current, and the circulating current I ０ In the following formula (1), j represents the imaginary unit, e represents the base of the natural logarithm, and θ ０ represents the phase of the circulating current.

[0041]

[0042] As shown in FIG. 4, the phase voltage balance control unit 30 controls the converter arm current command value Iuv ＊ , Ivw ＊ , Iwu ＊ and the circulating current command value Iz ＊ The negative sequence current command value calculation unit 40 calculates the arm current command value Iuv calculated by the phase voltage balance control unit 30. ＊ , Ivw ＊ , Iwu ＊ and the circulating current command value Iz ＊ Using the negative-phase current command value Idn ＊ , Iqn ＊ Calculate the following.

[0043] 5 is a block diagram showing an example of the configuration of the phase voltage balance control unit 30 shown in FIG. 4. The phase voltage balance control unit 30 receives the value of the capacitor voltage Vdccell detected by the voltage detector 18 of each converter cell 5, and calculates an arm current command value Iuv for balancing the capacitor voltages Vdccell of all converter cells 5. ＊ , Ivw ＊ , Iwu ＊ and the circulating current command value Iz ＊ Output.

[0044] 5, the phase voltage balance control unit 30 includes a voltage representative value calculation unit 31, a subtractor 32, a controller 33, a limiter 34, a multiplier 35, an adder 36, a constant multiplier 37, and a filter 38. Of these components, the subtractor 32, the controller 33, the limiter 34, the multiplier 35, and the filter 38 are provided corresponding to the voltage or current of each arm. When distinguishing between the arms, a, b, and c are added to the end of the reference numerals to correspond to arms A1, A2, and A3, respectively.

[0045] The voltage representative value calculation unit 31 receives the value of the capacitor voltage Vdccell detected in each converter cell 5. Based on the detected values ​​of these capacitor voltages Vdccell, the voltage representative value calculation unit 31 calculates a representative value Vph of the capacitor voltages Vdccell of all converter cells 5. ＊ , a representative value Vdcuv of the capacitor voltage Vdccell of the converter cells 5 constituting arm A1, a representative value Vdcvw of the capacitor voltage Vdccell of the converter cells 5 constituting arm A2, and a representative value Vdcwu of the capacitor voltage Vdccell of the converter cells 5 constituting arm A3 are calculated. The representative value of the capacitor voltage Vdccell may be an average value, a median value, a maximum value, a minimum value, or the like, and is not particularly limited as long as it reflects the magnitude of the capacitor voltage Vdccell of the corresponding converter cell 5.

[0046] The representative values ​​Vdcuv, Vdcvw, and Vdcwu of the capacitor voltages for each arm oscillate at a frequency of 2f, where f is the fundamental frequency of the power system. Each of the filters 38a, 38b, and 38c removes the 2f AC component from the representative value Vdcuv, Vdcvw, or Vdcwu of the capacitor voltage for the corresponding arm, thereby outputting only the DC component.

[0047] Each of the subtractors 32a, 32b, and 32c calculates a representative value Vph of the total capacitor voltage Vdccell. ＊ The error ΔVuv, ΔVvw, or ΔVwu is calculated by subtracting the representative value Vdcuv, Vdcvw, or Vdcwu of the capacitor voltage of the corresponding arm from the error ΔVuv, ΔVvw, or ΔVwu.

[0048] Each of the controllers 33a, 33b, and 33c executes a feedback calculation to bring the corresponding error ΔVuv, ΔVvw, or ΔVwu closer to 0. Specifically, the controller 33 may be configured as a proportional controller, or as a PI (proportional-integral) controller that adds the results of a proportional calculation (P) and an integral calculation (I), or as some other controller.

[0049] Each of the limiters 34a, 34b, and 34c limits the output of the corresponding controller 33a, 33b, or 33c to within a range between an upper limit and a lower limit. That is, each limiter 34 changes the output value of the corresponding controller 33 to the upper limit value and outputs it when the output of the corresponding controller 33 exceeds the upper limit value, changes the output value to the lower limit value and outputs it when the output of the corresponding controller 33 exceeds the lower limit value, and outputs the output value as is when the output of the corresponding controller 33 is between the upper limit and the lower limit value. When the system voltage is unbalanced, the circulating current command value Iz output from the phase voltage balance control unit 30 ＊ Since the magnitude of the circulating current command value Iz ＊ A limiter 34 is provided to reduce the magnitude of .

[0050] The upper and lower limit values ​​of the limiter 34 may be determined, for example, according to the rated value of the arm current so that the arm current flowing through the converter cell 5 does not become an overcurrent. Alternatively, the upper and lower limit values ​​may be set in advance in the form of a table according to the values ​​of the positive and negative sequence voltages of the power system (i.e., the degree of voltage imbalance) so that the output current of the power converter does not exceed the current capacity.

[0051] The multiplier 35a multiplies the output of the corresponding limiter 34a by the voltage Vuv of the arm A1 to obtain a UV-phase arm current command value Iuv flowing through the arm A1. ＊ Similarly, the multiplier 35b multiplies the output of the corresponding limiter 34b by the voltage Vvw of the arm A2 to calculate a VW-phase arm current command value Ivw flowing through the arm A2. ＊ The multiplier 35c multiplies the output of the corresponding limiter 34c by the voltage Vwu of the arm A3 to calculate a WU-phase arm current command value Iwu ＊ Calculate the following.

[0052] The adder 36 calculates the arm current command value Iuv ＊ , Ivw ＊ , Iwu ＊ The constant multiplier 37 multiplies the result of the addition by the adder 36 by one-third to obtain the circulating current command value Iz ＊ The limiter 34 calculates the arm current command value Iuv ＊ , Ivw ＊ , Iwu ＊ When any of the values ​​is limited, the circulating current command value Iz ＊ The value of is also limited.

[0053] When the limiter 34 is not provided to the output of the controller 33 of the phase voltage balance control unit 30, the circulating current command value Iz ＊ As a result, the arm current increases. By limiting the output of the controller 33 of the phase voltage balance control unit 30 using the limiter 34, the circulating current command value Iz ＊The compensation for the phase voltage balance control limited by the limiter 34 is calculated by the negative-sequence current command value In ＊ That is, the circulating current command value Iz is reflected by the upper and lower limit values ​​of the limiter 34. ＊ and the negative-phase current command value In ＊ (i.e., Iz for arm current) ＊ and In ＊ The proportion of

[0054] [Negative-phase-sequence current command value calculation unit 40] Fig. 6 is a block diagram showing an example of the configuration of the negative-phase-sequence current command value calculation unit 40 shown in Fig. 4. The negative-phase-sequence current command value calculation unit 40 calculates the arm current command value Iuv calculated by the phase voltage balance control unit 30. ＊ , Ivw ＊ , Iwu ＊ and the circulating current command value Iz ＊ From the negative-phase current command value In ＊ The negative-phase current command value In ＊ is the negative-phase reactive current command value Idn ＊ and the negative-phase active current command value Iqn ＊ It is composed of:

[0055] As shown in FIG. 6, the negative-phase sequence current command value calculation unit 40 includes subtractors 41a, 41b, 41c, 41d, and 41e, a three-phase / two-phase coordinate conversion unit 42, and filters 43a and 43b.

[0056] The subtractor 41a subtracts the UV-phase arm current command value Iuv output from the phase voltage balance control unit 30. ＊ from the circulating current command value Iz ＊ is subtracted to obtain the difference value ΔIuv ＊ By calculating the UV-phase arm current command value Iuv ＊ Similarly, the subtractor 41b extracts the positive and negative sequence components included in the VW phase arm current command value Ivw ＊ from the circulating current command value Iz ＊ The difference value ΔIvw is obtained by subtracting ＊ By calculating the VW phase arm current command value Ivw ＊The subtractor 41c extracts the positive and negative sequence components included in the WU phase arm current command value Iwu output from the phase voltage balance control unit 30. ＊ from the circulating current command value Iz ＊ The difference value ΔIwu is obtained by subtracting ＊ By calculating the WU phase arm current command value Iwu ＊ The positive and negative sequence components contained in the signal are extracted.

[0057] The three-phase / two-phase coordinate conversion unit 42 converts the extracted positive and negative phase components (i.e., the difference value ΔIuv ＊ , ΔIvw ＊ , ΔIwu ＊ ) is converted from three-phase to two-phase in the positive phase coordinate system. ＊ , ΔIvw ＊ , ΔIwu ＊ is converted from UVW coordinates to αβ coordinates in three-phase / two-phase, and further converted from αβ coordinates to positive phase dq coordinates using the reference phase θ.

[0058] Here, the reference phase θ is a phase θ synchronized with the system voltage, and is extracted from the detected values ​​of the system voltages Vu, Vv, and Vw by a PLL circuit (phase-locked loop) (not shown). The transformation matrices for the three-phase / two-phase transformation and the rotational coordinate transformation are the same as the transformation matrices in equations (3A) and (3B) described below.

[0059] The filter 43a extracts the positive-phase-sequence component from the output (q-axis component) of the three-phase / two-phase coordinate converter 42. The filter 43b extracts the positive-phase-sequence component from the output (d-axis component) of the three-phase / two-phase coordinate converter 42. Specifically, each of the filters 43a and 43b is configured to remove the negative-phase-sequence component from the input value to the filter and extract the positive-phase-sequence component. In the positive-phase-sequence coordinate system, the positive-phase-sequence component is a DC component, and the negative-phase-sequence component is a frequency component (2f) twice the fundamental frequency (f) of the power system. Therefore, the filters 43a and 43b use a first-order lag, a 2f moving average, a 2f notch filter, or the like.

[0060] The subtractor 41d subtracts the output (positive sequence component) of the filter 43a from the q-axis components (positive sequence component and negative sequence component) output from the three-phase / two-phase coordinate converter 42, thereby obtaining the negative sequence active current command value Iqn ＊ Similarly, the subtractor 41e subtracts the output (positive sequence component) of the filter 43a from the d-axis components (positive sequence component and negative sequence component) output from the three-phase / two-phase coordinate converter 42 to generate the negative sequence reactive current command value Idn ＊ Generate.

[0061] When the output of any of the controllers 33a, 33b, and 33c of the phase voltage balance control unit 30 is limited by the corresponding limiter 34, the arm current command value and the circulating current command value Iz of the limited phase are ＊ In this case, the difference values ​​ΔIuv output from the subtractors 41a, 41b, and 41c of the negative-phase-sequence current command value calculation unit 40 are ＊ , ΔIvw ＊ , ΔIwu ＊ , the difference value of the phase in which the output is not limited becomes large, and as a result, the negative-phase current command value In ＊ (Idn ＊ , Iqn ＊ That is, the circulating current command value Iz ＊ and the negative-phase current command value In ＊ (i.e., Iz for arm current) ＊ and In ＊ The proportion of

[0062] [Circulating current control unit 60] Fig. 7 is a block diagram showing an example of the configuration of circulating current control unit 60 of Fig. 4. Referring to Fig. 7, circulating current control unit 60 includes an adder 63, a constant multiplier 64, a subtractor 62, and a controller 61.

[0063] The adder 63 adds the valve branch currents Iuv, Ivw, and Iwu detected by the valve branch current detection unit 10. The constant multiplier 64 multiplies the addition result of the adder 63 by one-third to calculate the circulating current Iz flowing through the power converter 2.

[0064] The subtractor 62 calculates the circulating current command value Iz＊ The controller 61 calculates the deviation ΔIz between the circulating current Iz and the circulating current command value Iz. ＊ , and executes a feedback control calculation to make the zero-phase voltage command value vz ＊ The controller 84 may be a PI controller or other controllers.

[0065] [DC voltage control unit 20] Fig. 8 is a block diagram showing an example of the configuration of the DC voltage control unit 20 of Fig. 4. Referring to Fig. 8, the DC voltage control unit 20 includes a DC voltage representative value calculation unit 21, a subtractor 22, and a controller 23. The DC voltage control unit 20 calculates the capacitor voltages Vdccell of all (3n in this case) converter cells 5 detected by the voltage detector 18 for each converter cell 5, and the DC total voltage command value vdc ＊ is entered.

[0066] The DC voltage representative value calculation unit 21 calculates a voltage representative value vdc that represents all the capacitor voltages Vdccell from the capacitor voltages Vdccell of all the converter cells 5. The voltage representative value vdc may be the average value, median value, maximum value, or minimum value of at least some of the capacitor voltages Vdccell, and is not particularly limited as long as it reflects the magnitude of the capacitor voltages Vdccell of all the converter cells 5.

[0067] The subtractor 22 calculates the DC total voltage command value vdc ＊ The deviation Δvdc between the DC total voltage command value vdc and the voltage representative value vdc is calculated. ＊ is set to 1 [pu]. In order to make this deviation Δvdc zero, that is, to change the voltage representative value vdc to the DC total voltage command value vdc ＊ , and executes a feedback control calculation to make the positive-phase active current command value Iq ＊ The controller 23 may be a PI controller or another controller.

[0068] [Output Current Control Unit 50] Fig. 9 is a block diagram showing an example of the configuration of output current control unit 50 in Fig. 4. Referring to Fig. 9, output current control unit 50 includes a reference voltage calculation unit 51, a three-phase / two-phase coordinate conversion unit 55b, and adders 53c and 53d.

[0069] The reference voltage calculation unit 51 includes a three-phase / two-phase coordinate conversion unit 55a, adders 53a and 53b, subtractors 54a and 54b, and a controller 52. As shown in FIG. 9, the reference voltage calculation unit 51 includes a positive-phase reactive current command value Id ＊ and the positive-phase active current command value Iq calculated by the DC voltage control unit 20. ＊ and the negative-phase-sequence reactive current command value Idn calculated by the negative-phase-sequence current command value calculation unit 40. ＊ and the negative-phase active current command value Iqn ＊ and the U-phase AC current Iu, V-phase AC current Iv, and W-phase AC current Iw, which are output currents of the power converter 2 detected by the AC current detection unit 11, are input.

[0070] The adder 53a calculates the positive-phase reactive current command value Id as shown in the following equation (2A). ＊ and the negative-phase reactive current command value Idn ＊ By adding these, the reactive current command value Id2 is obtained. ＊ The adder 53b calculates the positive-phase active current command value Iq as shown in the following equation (2B). ＊ and the negative-phase active current command value Iqn ＊ By adding these, the active current command value Iq2 ＊ Calculate the following.

[0071]

[0072] The three-phase / two-phase coordinate converter 55a calculates a positive-phase reactive current Id and a positive-phase active current Iq by performing three-phase / two-phase conversion on the output currents Iu, Iv, and Iw detected by the AC current detector 11 in a positive-phase coordinate system. More specifically, the three-phase / two-phase coordinate converter 55a performs three-phase / two-phase conversion on the output currents Iu, Iv, and Iw from the UVW coordinates to the output currents Iα and Iβ in the αβ coordinates in accordance with the following equation (3A). The three-phase / two-phase coordinate converter 55a further performs rotational coordinate conversion on the output currents Iα and Iβ in the αβ coordinates to the positive-phase currents Id and Iq in the positive-phase dq coordinates in accordance with the following equation (3B) using a reference phase θ. Here, the reference phase θ is a phase θ synchronized with the system voltage.

[0073]

[0074] The subtractor 54a subtracts the reactive current command value Id2 output from the adder 53a. ＊ The subtractor 54b calculates the deviation ΔId between the active current command value Iq2 output from the adder 53b and the positive-sequence reactive current Id output from the three-phase / two-phase coordinate converter 55a. ＊ and the positive-phase active current Iq output from the three-phase / two-phase coordinate converter 55a.

[0075] In order to make the deviations ΔId and ΔIq zero, that is, to make the positive-sequence reactive current Id and the positive-sequence active current Iq equal to the reactive current command value Id2 ＊ and active current command value Iq2 ＊ , and a feedback control calculation is performed to make the DC total voltage command value Vdc ＊ The controller 52 performs a feedback control calculation to cause the positive and negative phase reference voltages vdref and vqref to follow the reference voltages vdref and vqref, where vdref is a reactive component of the positive and negative phase reference voltages, and vqref is an active component of the positive and negative phase reference voltages. The controller 52 may be a PI controller or another controller.

[0076] Meanwhile, the three-phase / two-phase coordinate converter 55b generates positive-phase voltages (positive-phase reactive voltage Vdff and positive-phase active voltage Vqff) by three-phase / two-phase conversion of the U-phase AC voltage Vu, V-phase AC voltage Vv, and W-phase AC voltage Vw of the power grid in a positive-phase coordinate system. More specifically, the three-phase / two-phase coordinate converter 55b performs three-phase / two-phase conversion of the grid voltages U-phase AC voltage Vu, V-phase AC voltage Vv, and W-phase AC voltage Vw from the UVW coordinate to the grid voltages Vα and Vβ in the αβ coordinate. The three-phase / two-phase coordinate converter 55b further performs rotational coordinate conversion from the grid voltages Vα and Vβ in the αβ coordinate to the positive-phase voltages Vdff and Vqff in the positive-phase dq coordinate using a reference phase θ. Here, the reference phase θ is a phase θ synchronized with the grid voltage.

[0077] The adder 53c adds the positive-phase reactive voltage Vdff calculated by the three-phase / two-phase coordinate conversion unit 55b in a feedforward manner to the positive-phase / negative-phase reference voltage vdref on the d-axis, which is the output of the controller 52, to obtain the reactive voltage command value vd ＊ The adder 53c adds the positive-phase active voltage Vqff calculated by the three-phase / two-phase coordinate conversion unit 55b to the positive-phase / negative-phase reference voltage vqref on the q axis, which is the output of the controller 52, in a feedforward manner, to calculate the active voltage command value vq ＊ Here, the voltage command value vd on the d axis is calculated. ＊ and the voltage command value vq on the q axis ＊ Each of the signals includes both positive and negative sequence components.

[0078] [Voltage command value calculation unit 70] Referring again to FIG. 4, the voltage command value calculation unit 70 calculates the voltage command value vd on the d axis output from the output current control unit 50. ＊ and the voltage command value vq on the q axis ＊ By performing two-phase / three-phase conversion on the U-phase, V-phase, and W-phase AC voltage command values ​​vu ＊ , vv ＊ , vw ＊ The two-phase / three-phase conversion can be configured as an inverse conversion of the three-phase / two-phase conversion. That is, the voltage command value calculation unit 70 converts the dq coordinates into the αβ coordinates, and then converts the αβ coordinates into the three-phase coordinates.

[0079] Furthermore, the voltage command value calculation unit 70 calculates the AC voltage command value vu＊ , vv ＊ , vw ＊ The zero-phase voltage command value vz output from the circulating current control unit 60 to each of ＊ By adding these, the output voltage command values ​​Vuo of the U phase, V phase, and W phase are obtained. ＊ , Vvo ＊ , Vwo ＊ Calculate the following.

[0080] [Gate Signal Generator 80] Referring to FIG. 4, gate signal generator 80 generates output voltage command values ​​Vuo for U, V, and W phases output from voltage command value calculator 70. ＊ , Vvo ＊ , Vwo ＊ A gate signal Ga is generated for controlling the on / off of the semiconductor switching elements Q1 to Q4 of each converter cell 5 of each arm by PWM (Pulse Width Modulation) control according to the above. The gate signal Ga is input to the control electrode G of the semiconductor switching elements Q1 to Q4 of each converter cell 5 via the driver 19 of each converter cell 5. This determines the on / off of the semiconductor switching elements Q1 to Q4 of each converter cell 5.

[0081] As described above, according to the power conversion device 1 of the first embodiment, it is possible to appropriately determine the proportion of the circulating current and the negative-phase current that contribute to the phase voltage balance control while suppressing an increase in the valve branch current by limiting the magnitudes of the valve branch current command value and the circulating current command value output from the phase voltage balance control unit 30. This makes it possible to reduce the converter capacity and improve the operational continuity of the power conversion device in the event of a grid fault.

[0082] Second Embodiment [Key Points of Second Embodiment] In a power conversion device according to the second embodiment, a controller 33 included in a phase voltage balance control unit 30 is configured by a proportional-integral (PI) controller, and a limiter 34 is provided at the output of an integrator of the PI controller. This makes it possible to adjust the magnitudes of the valve branch current command value and the circulating current command value output from the phase voltage balance control unit 30, as in the case of the first embodiment. Furthermore, the magnitudes of the valve branch current command value and the circulating current command value can also be adjusted by the input / output characteristics of the PI controller (specifically, the proportional gain and the integral gain).

[0083] [Configuration of Phase Voltage Balance Control Unit] In power conversion device 1 of embodiment 2, the configuration of phase voltage balance control unit 30 included in control device 3 of Fig. 4 is different from that of embodiment 1. The other components included in control device 3 are the same as those in Fig. 4, and therefore description thereof will not be repeated.

[0084] FIG. 10 is a block diagram showing an example of the configuration of a phase voltage balance control unit 30 included in the control device 3 in the power conversion device 1 according to the second embodiment.

[0085] The phase voltage balance control unit 30 in Fig. 10 differs from the phase voltage balance control unit 30 in Fig. 5 in the configurations of the controllers 33a, 33b, and 33c and the limiters 34a, 34b, and 34c. In the phase voltage balance control unit 30 in Fig. 10, each controller 33 is configured as a PI controller and includes a corresponding limiter 34 therein.

[0086] Specifically, the controller 33a receives the UV-phase error ΔVuv from the corresponding subtractor 32a. The controller 33a includes a proportional unit 39a having a proportional gain Kp, an integrator 390a having an integral gain Ki, a limiter 34a, and an adder 36a.

[0087] The proportional unit 39a multiplies the error ΔVuv by Kp and outputs the result. The integrator 390a multiplies the error ΔVuv by Ki and integrates it. The limiter 34a limits the calculation result of the integrator 390a within a range between an upper limit and a lower limit. That is, if the output of the integrator 390a exceeds the upper limit, the limiter 34a changes the output value to the upper limit and outputs it. If the output of the integrator 390a exceeds the lower limit, the limiter 34a changes the output value to the lower limit and outputs it. If the output of the integrator 390a is between the upper limit and the lower limit, the limiter 34a outputs the output value as is. The adder 36a adds the calculation result of the proportional unit 39a and the output of the limiter 34a. The multiplier 35a receives the sum of the adder 36a as the output of the controller 33a and multiplies the output of the controller 33a by the voltage Vuv of the arm A1.

[0088] Similarly, the controller 33b, to which the VW-phase error ΔVvw is input from the corresponding subtractor 32b, includes a proportional unit 39b having a proportional gain Kp, an integrator 390b having an integral gain Ki, a limiter 34b, and an adder 36b. The proportional unit 39b multiplies the error ΔVvw by Kp and outputs the result. The integrator 390b integrates the error ΔVvw by Ki. The limiter 34b limits the calculation result of the integrator 390b within a range between upper and lower limits. The adder 36b adds the calculation result of the proportional unit 39b to the output of the limiter 34b and outputs the sum to the corresponding multiplier 35b as the output of the controller 33b. The multiplier 35b multiplies the output of the controller 33b by the voltage Vvw of the arm A2.

[0089] Similarly, the controller 33c, to which the WU-phase error ΔVwu is input from the corresponding subtractor 32c, includes a proportional unit 39c having a proportional gain Kp, an integrator 390c having an integral gain Ki, a limiter 34c, and an adder 36c. The proportional unit 39c multiplies the error ΔVwu by Kp and outputs the result. The integrator 390c integrates the error ΔVwu by Ki. The limiter 34c limits the calculation result of the integrator 390c within a range between upper and lower limits. The adder 36c adds the calculation result of the proportional unit 39c and the output of the limiter 34c, and outputs the sum to the corresponding multiplier 35c as the output of the controller 33c. The multiplier 35c multiplies the output of the controller 33c by the voltage Vwu of the arm A3.

[0090] Other points in FIG. 10 are the same as those in FIG. 5, so the same or corresponding parts are given the same reference numerals and description thereof will not be repeated.

[0091] [Effects of Second Embodiment] According to the power conversion device 1 of the second embodiment, each controller 33 of the phase voltage balance control unit 30 is configured as a PI controller, and a limiter 34 is arranged to limit the output of the integrator 390. As a result, the arm current command value and the circulating current command value Iz of any phase are adjusted according to the degree of imbalance in the system voltage. ＊ The compensation amount of the phase voltage balance control unit 30 limited by the limiter 34 is limited to the negative sequence current command value In ＊ (That is, the negative-phase active current command value Iqn ＊ and the negative-phase reactive current command value Idn ＊ ) and its magnitude increases. That is, the upper and lower limit values ​​of the limiter 34 are used to change the circulating current command value Iz ＊ and the negative-phase current command value In ＊ (i.e., the circulating current command value Iz ＊ and the negative-phase current command value In ＊ This makes it possible to limit the arm current flowing through the power converter 2, thereby reducing the converter capacity of the power converter 2. Furthermore, it is possible to improve the operational continuity of the power converter 2 in the event of a fault in the power grid.

[0092] The magnitudes of the valve branch current command value and the circulating current command value may be adjusted according to the input / output characteristics of the controller 33. For example, the input / output characteristics of the PI controller relate to the proportional gain, the integral gain, and the upper and lower limit values ​​of the limiter 34 that limits the output of the integrator 390.

[0093] Third Embodiment [Key Points of Third Embodiment] In the power conversion device 1 of the third embodiment, the upper and lower limit values ​​of the limiter 34 described in the first and second embodiments are adjusted to the minimum circulating current value determined according to the detected value of the grid voltage and the detected value of the output current of the power converter 2. The minimum circulating current value can be determined under the condition that the DC component of the voltage of the storage element 17 of each converter cell 5 does not fluctuate.

[0094] [Difference in Arm Current with and without Negative-Sequence Current Control] When the system voltage becomes unbalanced due to a power system fault, the arm current of the power conversion device increases. Negative-sequence current control is required to suppress the arm current. Below, we will explain the calculation results of the difference in arm current with and without negative-sequence current control.

[0095] FIG. 11 is a diagram showing an example of arm currents of a power converter under unbalanced system voltage conditions when negative-phase-sequence current control is not performed.

[0096] Specifically, the graph in Figure 11 shows the theoretical amplitude (pu) of the arm current of each phase (UV, VW, WU) relative to the phase of the negative-sequence voltage during steady-state operation when the positive-sequence voltage is ⅔ (pu) and the negative-sequence voltage is ⅓ (pu). The phase of the negative-sequence voltage on the horizontal axis represents a value when the phase of the positive-sequence voltage is set to the reference (0°). The positive-sequence reactive current of the output current is set to 1 (pu), and the negative-sequence current In shown in equation (1) of the first embodiment is set to 0 (pu) (i.e., no negative-sequence current control).

[0097] 11, it can be seen that the amplitude of the arm current varies depending on the phase of the negative-sequence current. When the phase of the negative-sequence voltage is in the range of 0° to 120°, the WU-phase arm current has the maximum amplitude, when the phase of the negative-sequence voltage is in the range of 120° to 240°, the UV-phase arm current has the maximum amplitude, and when the phase of the negative-sequence voltage is in the range of 240° to 360°, the VW-phase arm current has the maximum amplitude.

[0098] Fig. 12 is a diagram showing an example of the difference in maximum arm current depending on whether or not negative-sequence current control is performed. In Fig. 12, the dashed line graph shows the maximum arm current relative to the phase of the negative-sequence voltage when negative-sequence current control is not performed. Specifically, as in Fig. 11, the positive-sequence voltage is set to 2 / 3 [pu], the negative-sequence voltage is set to 1 / 3 [pu], the positive-sequence reactive current is set to 1 [pu], and the negative-sequence current In is set to 0 [pu]. Therefore, the maximum amplitude indicated by the dashed line in Fig. 12 is the same as in Fig. 11.

[0099] On the other hand, the solid line graph in Figure 12 shows the maximum valve branch current versus the phase of the negative-sequence voltage when negative-sequence current control is enabled. Specifically, the negative-sequence current In is set to 0.2 [pu], and the phase of the negative-sequence current In is controlled to be 90 degrees different from the phase of the negative-sequence voltage. As shown in Figure 12, the maximum valve branch current when negative-sequence current control is enabled is smaller than the maximum valve branch current when negative-sequence current control is disabled, demonstrating that the valve branch current can be suppressed by negative-sequence current control.

[0100] Here, the conditions under which the arm current decreases are shown based on the relational expression between the capacitor voltage and the arm current of each converter cell of the MMC.

[0101] In the MMC type power converter 2, the instantaneous value v of the capacitor voltage of each converter cell 5 ｄｃ and the instantaneous value of the capacitor current i ｄｃ The differential equation that expresses the relationship between the capacitance of the capacitor is ＳＭ and a differential operator p, it is expressed as the following equation (4).

[0102]

[0103] The instantaneous value of the AC output voltage of the UV-phase arm A1 is v ｕｖ The instantaneous value of the AC output current is i ｕｖ Let the number of converter cells 5 be N ＳＭ Considering the voltage balance between the series-connected converter cells 5 and assuming that there is no loss in conversion in the voltage source converter, the DC input power of each converter cell 5 and the AC output power of arm A1 must be balanced as shown in the following equation (5).

[0104]

[0105] Each converter cell 5 of the UV-phase arm A1 is supplied with a modulation index k ｕｖ By introducing the above equation, the AC voltage of each converter cell 5 of the UV-phase arm A1 can be expressed by the following equation (6).

[0106]

[0107] Substituting equations (5) and (6) into equation (4), the arm current i ｕｖ and modulation index k ｕｖThe differential equation of the capacitor is derived as shown in the following equation (7).

[0108]

[0109] Equivalent time constant T of a capacitor ｄｃ [s], normalized UV phase capacitor voltage v ｃＵＶ [pu], UV phase modulation index m ＵＶ [pu / peak], UV phase arm current i ＵＶ [pu / peak], system frequency ω ｓｙｓ [rad / s], DC capacitor voltage V ｃａｐ [V], rated capacity of power converter 2 (STATCOM) S ｒａｔｅ By using the line-to-line secondary voltage Vu [V], the differential equation (7) above can be converted into a differential equation for the system per unit as shown in the following equation (8A). ｄｃ [s] is given by the following equation (8B).

[0110]

[0111] Here, the normalized UV phase capacitor voltage v ｃＵＶ [pu], UV phase arm current i ＵＶ [pu / peak], UV phase modulation index m ＵＶ [pu / peak] is defined by the following equations (9A) to (9C), respectively.

[0112]

[0113] Differential equations can be similarly obtained for the VW phase and WU phase. Considering the fundamental wave components of the line voltage and arm current, the above equation (8A) holds for the average value of the DC capacitor voltage of the converter cell 5 in each arm. Therefore, the three-phase differential equation for the average value of the DC capacitor voltage in the arm is given by the following equation (10).

[0114]

[0115] Since the transformer 4 is Y-Δ connected, the UV phase of the power converter 2 corresponds to the U phase (also referred to as the A phase) of the AC power system 9, the VW phase of the power converter 2 corresponds to the V phase (also referred to as the B phase) of the AC power system 9, and the WU phase of the power converter 2 corresponds to the W phase (also referred to as the C phase) of the AC power system 9.

[0116]

[0117] When formula (10) is converted by the conversion formula of formula (11) (x represents v and i), the following formula (12) is obtained. ｃ０ represents the voltage of the zero-phase component, which corresponds to the three-phase average voltage of the capacitor voltage. ｃα , v ｃβ corresponds to the imbalance of the capacitor voltages between the phases (i.e., the fluctuation component relative to the three-phase average voltage).

[0118]

[0119] Here, to facilitate handling of the unbalanced components (i.e., positive and negative phases), signals on orthogonal stationary coordinates are expressed as complex signals. In orthogonal stationary coordinates, positive frequency components represent positive phase components, and negative frequency components represent negative phase components. Therefore, by handling them as complex signals, both components can be included in a single variable. Specifically, the unbalanced component of the capacitor voltage can be expressed by the following equation (13A), the unbalanced component of the arm current can be expressed by the following equation (13B), and the unbalanced component of the modulation index can be expressed by the following equation (13C).

[0120]

[0121] The discharge current associated with the unbalanced component of the DC voltage is given by v in equation (13A). ｃα and v ｃβ v in equation (12) ｃα and v ｃβ and transforming the equation using equations (13B) and (13C), the following equation (14) can be obtained: In the following equation (14), the complex conjugate is represented by a bar.

[0122]

[0123] [Conditions for circulating current necessary for balancing phase voltages] Below, the minimum value of circulating current necessary for balancing phase voltages is derived from the steady-state equation of the delta-connected STATCOM. Positive-sequence instantaneous voltage v ｐ (t) and the negative-phase instantaneous voltage v ｎ (t) is the voltage phasor V ｐ , V ｎ In the following equations, the angular frequency of the power system is expressed as ω ｓｙｓ Let's say.

[0124]

[0125] Similarly, the positive-sequence instantaneous current i in the steady state of the power system ｐ (t) and the negative-phase instantaneous current i ｎ (t) is the current phasor I ｐ , I ｎ The following equations (16A) and (16B) are obtained.

[0126]

[0127] In the phasor representation, the voltage v(t) and current i(t) in the Cartesian stationary coordinate system are expressed as the sum of the complex conjugates of the positive and negative sequence components, so the following equations (17A) and (17B) hold true. In the following equations, the complex conjugates are represented by bars.

[0128]

[0129] Circulating current i ０ Since (t) is a single-phase component and a real number, it is expressed by the following equation (18). In the following equation, the amplitude of the circulating current is I ０ The phase of the circulating current is θ ０ Let's say.

[0130]

[0131] The rated value of the capacitor voltage of each converter cell is V ｃ０ Let's say. V ｃ０ corresponds to the zero-phase component voltage. Also, the fundamental wave component of the modulation index m of each converter cell is expressed as m １ and the reactance of the transformer is X ｔ and the reactance per unit of the arm reactor Xａｒｍ The sum of ｓ Let [pu] be the differential operator, and p be the differential equation. The differential equation (19A) below holds for the output voltage v(t) and the output current i(t). Furthermore, the following equation (19B) can be obtained from the following equation (19A) and equations (17A) and (17B). Also, let m be the modulation index of the circulating current. ０ Then, m ０ is expressed by the following equation (19C).

[0132]

[0133] The first term in the brackets on the right side of the above equation (19B) corresponds to the positive-phase voltage output by the MMC-STATCOM power converter 2, and the second term in the brackets on the right side corresponds to the negative-phase voltage output by the MMC-STATCOM power converter 2. The result of dividing these voltages by the three-phase average voltage of the capacitor becomes the modulation signal.

[0134] Here, the condition under which the capacitor voltage of each converter cell does not fluctuate at least with respect to the DC component is when the discharge current related to the unbalanced component of the DC voltage becomes 0, and the above-mentioned equation (14) becomes 0, that is, the following equation (20A) is satisfied. Note that the left side of the following equation (20A) is obtained by multiplying equation (14) by -1. Here, the modulation index m includes a fundamental wave component and a harmonic component, and the fundamental wave component m expressed by equation (19B) １ Since the modulation index m in the following equation (20A) is large and dominant, the modulation index m in the above equation (19B) is １ Furthermore, in the following formula (20A), m ０ Substituting equation (19C) into i ０ Substitute equation (18) into and equation (17B) into i. １ and m ０ and currents i and i ０ Since the fundamental wave component is included in the multiplication of the modulation signal and the current, a DC component and positive and negative double frequency components are included. Therefore, by extracting and rearranging only the DC component, the following equation (20B) is obtained. In deriving the following equation (20B), X ｓ =X ａｒｍ +X ｔ The relationship was used.

[0135]

[0136] The first term in the curly brackets in the above equation (20B) corresponds to the power when a circulating current flows in the presence of a positive-phase voltage and a negative-phase voltage, and the second term in the curly brackets in the above equation (20B) corresponds to the power when an unbalanced voltage and an unbalanced current exist. Therefore, by balancing the power due to the negative-phase component and the power due to the circulating current, the imbalance of the DC capacitor voltage can be suppressed.

[0137] From the above equation (20B), the condition for the circulating current to make the fluctuation component of the capacitor voltage constant is derived as follows: ０ is given by the following equation (21A), and the magnitude of the circulating current I ０ is given by the following equation (21B). That is, the circulating current (equation (18)) required for phase balance control can be calculated by the following equations (21A) and (21B). Note that the following equation (21B) is obtained by converting the above equation (20B) into I ０ The following equation (21A) is the phase θ when the imaginary part of the following equation (21B) becomes 0. ０ is calculated as follows.

[0138]

[0139] The positive-sequence voltage phasor Vp and the negative-sequence voltage phasor Vn in the above equations (21A) and (21B) are the voltage phasors V of the U-phase, V-phase, and W-phase of the three-phase AC voltage based on the detected values ​​of the AC voltage detector 12 in FIG. ｕ , V ｖ , V ｗ In addition, the positive sequence current phasor I ｐ The negative-phase sequence current phasor In is the current phasor I of the output current of the U phase, V phase, and W phase based on the detection value of the AC current detection unit 11 in FIG. ｕ , I ｖ , I ｗ can be obtained from the following equation (22B): The operator a in the following equations (22A) and (22B) is expressed by the following equation (22C).

[0140]

[0141] Note that a phasor includes a magnitude and a phase. If the phase of the positive-sequence voltage phasor is set as the reference (0°), in equations (21A) and (21B), the phase and magnitude of the circulating current are determined by inputting the magnitude, phase, and magnitude of the positive-sequence voltage, the negative-sequence voltage, and the phase of the negative-sequence voltage of the power grid, and the magnitude, phase, and magnitude of the positive-sequence current, and the phase of the negative-sequence current, for the output current of power conversion device 1.

[0142] According to the above-mentioned formula (1), when the magnitude of the circulating current is reduced, the magnitude of the valve branch current is reduced, so the upper and lower limit values ​​of the limiter 34 are determined so as to obtain the minimum value of the valve branch current given by formulas (21A) and (21B). Specifically, the phase voltage balance control unit 30 in the first and second embodiments outputs the circulating current command value Iz ＊ The upper and lower limit values ​​of each limiter 34 are determined so that the magnitude of the circulating current I0 obtained by equation (21B) is equal to the magnitude of the circulating current I0.

[0143] The phase voltage balance control unit 30 may calculate the minimum value of the circulating current that satisfies (21A) and (21B) by sequentially performing calculations based on the system voltage detected by the AC voltage detection unit 12 and the output current of the power converter 2 detected by the AC current detection unit 11, and may determine the upper and lower limit values ​​of the limiter 34 based on the minimum value of the circulating current. However, this method requires a considerable amount of time for calculations.

[0144] Therefore, upper and lower limit values ​​of the limiter 34 that will provide the minimum circulating current value may be determined in advance according to various values ​​of the system voltage and the output current of the power converter 2, and may be stored in memory as a table showing the relationship between the system voltage and output current values ​​and the upper and lower limit values ​​of the limiter 34. In this case, the phase voltage balance control unit 30 refers to this table to determine the upper and lower limit values ​​of the limiter 34 that correspond to the detected values ​​of the system voltage and output power.

[0145] [Effects of Third Embodiment] According to the power conversion device 1 of the third embodiment, the upper and lower limit values ​​of the limiter 34 described in the first and second embodiments are made variable, and the upper and lower limit values ​​of the limiter 34 are adjusted so that the circulating current command value is equal to the minimum circulating current value determined in accordance with the detected value of the grid voltage and the detected value of the output current of the power converter 2. This makes it possible to reduce the magnitude of the arm current as much as possible while maintaining the phase voltage balance control function, thereby making it possible to reduce the capacity of the power converter 2 as much as possible and improve operational continuity in the event of a grid fault.

[0146] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0147] REFERENCE SIGNS LIST 1 power conversion device, 2 power converter, 3 control device, 4 transformer, 5 converter cell, 9 AC power system, 10 arm current detection unit, 11 AC current detection unit, 12 AC voltage detection unit, 15F full bridge circuit, 15H half bridge circuit, 16a, 16b input / output terminals, 17 storage element, 18 voltage detector, 19 driver, 20 DC voltage control unit, 21 DC voltage representative value calculation unit, 22, 32, 41, 54, 62 subtractor, 23, 33, 52, 61, 84 controller, 30 voltage balance control unit, 31 voltage representative value calculation unit, 34 limiter, 35 multiplier, 36, 53, 63 adder, 37, 64 constant multiplier, 38, 43 filter, 39 proportional unit, 40 negative-phase sequence current command value calculation unit, 42, 55 Three-phase / two-phase coordinate conversion unit, 50 output current control unit, 51 reference voltage calculation unit, 60 circulating current control unit, 70 voltage command value calculation unit, 80 gate signal generation unit, 390 integrator, A1, A2, A3 arms, D rectifier element, G control electrode, L reactor, NL negative electrode line, PL positive electrode line, Q semiconductor switching element, UL, VL, WL AC lines.

Claims

1. A power converter connected to a three-phase AC system; and a control device for controlling the power converter, wherein the power converter has three delta-connected arms each including a plurality of cascaded converter cells, each of the plurality of converter cells including: an input / output terminal pair; a bridge circuit including a plurality of semiconductor switching elements; and a storage element connected to the input / output terminal pair via the bridge circuit, wherein the control device comprises: a phase voltage balance control unit that calculates a branch current command value and a circulating current command value for each arm so that a difference between a representative value of a voltage of the storage element included in each arm and a representative value of voltages of the storage elements included in all arms becomes small; a negative-sequence current command value calculation unit that calculates a negative-sequence current command value based on the branch current command value and the circulating current command value; an output current control unit that calculates a voltage command value for controlling an output current of the power converter based on the negative-sequence current command value and the positive-sequence current command value; and a circulating current control unit that calculates a zero-sequence voltage command value for controlling a circulating current based on a detected value of the branch current of each arm, based on the circulating current command value. a voltage command value calculation unit that calculates an output voltage command value to be output to each arm based on the voltage command value and the zero-phase sequence voltage command value; and a gate signal generation unit that generates, based on the output voltage command value, a gate signal for controlling on / off of each semiconductor switching element included in each converter cell of each arm, wherein the phase voltage balance control unit is configured to limit magnitudes of the arm current command value and the circulating current command value, and the magnitude of the negative-phase sequence current command value calculated by the negative-phase sequence current command value calculation unit increases in accordance with an amount by which the magnitudes of the arm current command value and the circulating current command value of any arm are limited.

2. The power conversion device according to claim 1, wherein the phase voltage balance control section includes: a feedback controller to which the difference between a representative value of the voltage of the storage elements included in each arm and a representative value of the voltage of the storage elements included in all arms is input; and a limiter that limits the output of the controller to within a range between an upper limit value and a lower limit value.

3. The power conversion device according to claim 1, wherein the phase voltage balance control section includes a feedback controller to which a difference between a representative value of the voltage of the storage elements included in each arm and a representative value of the voltage of the storage elements included in all arms is input, and the magnitudes of the arm current command value and the circulating current command value are limited in accordance with the input / output characteristics of the controller.

4. The power conversion device according to claim 3, wherein the controller includes a limiter that limits the internal signal within a range of upper and lower limits.

5. The power conversion device according to claim 4, wherein the controller is a proportional-integral controller including a proportional unit and an integrator, and the limiter limits the output of the integrator.

6. The power conversion device according to any one of claims 2, 4, and 5, wherein a minimum circulating current value is determined in accordance with a detected value of the system voltage of the three-phase AC system and a detected value of the output current of the power converter, under the condition that the DC component of the voltage of the storage element of each converter cell does not fluctuate, and wherein the phase voltage balance control unit adjusts the upper limit value and the lower limit value of the limiter in accordance with the detected value of the system voltage of the three-phase AC system and the detected value of the output current of the power converter, so that the circulating current command value becomes equal to the minimum circulating current value.

7. Positive sequence voltage phasor V based on the detected value of the system voltage of the three-phase AC system ｐ and the negative-sequence voltage phasor V ｎ , a positive-sequence current phasor I based on the detected value of the output current of the power converter ｐ and negative sequence current phasor I ｎ , and a reactance X of a transformer provided between the three-phase AC system and the power converter. ｔ Using the phase of the circulating current θ ０ and the minimum value I of the circulating current magnitude ０ is given by the following equation: The power conversion device according to claim 6.

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